1 /**
2 ******************************************************************************
3 * @file stm32g0xx_hal_spi.c
4 * @author MCD Application Team
5 * @brief SPI HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2018 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 @verbatim
24 ==============================================================================
25 ##### How to use this driver #####
26 ==============================================================================
27 [..]
28 The SPI HAL driver can be used as follows:
29
30 (#) Declare a SPI_HandleTypeDef handle structure, for example:
31 SPI_HandleTypeDef hspi;
32
33 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
34 (##) Enable the SPIx interface clock
35 (##) SPI pins configuration
36 (+++) Enable the clock for the SPI GPIOs
37 (+++) Configure these SPI pins as alternate function push-pull
38 (##) NVIC configuration if you need to use interrupt process
39 (+++) Configure the SPIx interrupt priority
40 (+++) Enable the NVIC SPI IRQ handle
41 (##) DMA Configuration if you need to use DMA process
42 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
43 (+++) Enable the DMAx clock
44 (+++) Configure the DMA handle parameters
45 (+++) Configure the DMA Tx or Rx Stream/Channel
46 (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle
47 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
48
49 (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
50 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
51
52 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
53 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
54 by calling the customized HAL_SPI_MspInit() API.
55 [..]
56 Circular mode restriction:
57 (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
58 (##) Master 2Lines RxOnly
59 (##) Master 1Line Rx
60 (#) The CRC feature is not managed when the DMA circular mode is enabled
61 (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
62 the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
63 [..]
64 Master Receive mode restriction:
65 (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
66 bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
67 does not initiate a new transfer the following procedure has to be respected:
68 (##) HAL_SPI_DeInit()
69 (##) HAL_SPI_Init()
70 [..]
71 Callback registration:
72
73 (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
74 allows the user to configure dynamically the driver callbacks.
75 Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
76
77 Function HAL_SPI_RegisterCallback() allows to register following callbacks:
78 (++) TxCpltCallback : SPI Tx Completed callback
79 (++) RxCpltCallback : SPI Rx Completed callback
80 (++) TxRxCpltCallback : SPI TxRx Completed callback
81 (++) TxHalfCpltCallback : SPI Tx Half Completed callback
82 (++) RxHalfCpltCallback : SPI Rx Half Completed callback
83 (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
84 (++) ErrorCallback : SPI Error callback
85 (++) AbortCpltCallback : SPI Abort callback
86 (++) MspInitCallback : SPI Msp Init callback
87 (++) MspDeInitCallback : SPI Msp DeInit callback
88 This function takes as parameters the HAL peripheral handle, the Callback ID
89 and a pointer to the user callback function.
90
91
92 (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
93 weak function.
94 HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
95 and the Callback ID.
96 This function allows to reset following callbacks:
97 (++) TxCpltCallback : SPI Tx Completed callback
98 (++) RxCpltCallback : SPI Rx Completed callback
99 (++) TxRxCpltCallback : SPI TxRx Completed callback
100 (++) TxHalfCpltCallback : SPI Tx Half Completed callback
101 (++) RxHalfCpltCallback : SPI Rx Half Completed callback
102 (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
103 (++) ErrorCallback : SPI Error callback
104 (++) AbortCpltCallback : SPI Abort callback
105 (++) MspInitCallback : SPI Msp Init callback
106 (++) MspDeInitCallback : SPI Msp DeInit callback
107
108 [..]
109 By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
110 all callbacks are set to the corresponding weak functions:
111 examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
112 Exception done for MspInit and MspDeInit functions that are
113 reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
114 these callbacks are null (not registered beforehand).
115 If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
116 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
117
118 [..]
119 Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
120 Exception done MspInit/MspDeInit functions that can be registered/unregistered
121 in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
122 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
123 Then, the user first registers the MspInit/MspDeInit user callbacks
124 using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
125 or HAL_SPI_Init() function.
126
127 [..]
128 When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
129 not defined, the callback registering feature is not available
130 and weak (surcharged) callbacks are used.
131
132 [..]
133 Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
134 the following table resume the max SPI frequency reached with data size 8bits/16bits,
135 according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
136
137 @endverbatim
138
139 Additional table :
140
141 DataSize = SPI_DATASIZE_8BIT:
142 +----------------------------------------------------------------------------------------------+
143 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
144 | Process | Transfer mode |---------------------|----------------------|----------------------|
145 | | | Master | Slave | Master | Slave | Master | Slave |
146 |==============================================================================================|
147 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
148 | X |----------------|----------|----------|-----------|----------|-----------|----------|
149 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
150 | R |----------------|----------|----------|-----------|----------|-----------|----------|
151 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
152 |=========|================|==========|==========|===========|==========|===========|==========|
153 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
154 | |----------------|----------|----------|-----------|----------|-----------|----------|
155 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
156 | X |----------------|----------|----------|-----------|----------|-----------|----------|
157 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
158 |=========|================|==========|==========|===========|==========|===========|==========|
159 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
160 | |----------------|----------|----------|-----------|----------|-----------|----------|
161 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
162 | X |----------------|----------|----------|-----------|----------|-----------|----------|
163 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
164 +----------------------------------------------------------------------------------------------+
165
166 DataSize = SPI_DATASIZE_16BIT:
167 +----------------------------------------------------------------------------------------------+
168 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
169 | Process | Transfer mode |---------------------|----------------------|----------------------|
170 | | | Master | Slave | Master | Slave | Master | Slave |
171 |==============================================================================================|
172 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
173 | X |----------------|----------|----------|-----------|----------|-----------|----------|
174 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
175 | R |----------------|----------|----------|-----------|----------|-----------|----------|
176 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
177 |=========|================|==========|==========|===========|==========|===========|==========|
178 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
179 | |----------------|----------|----------|-----------|----------|-----------|----------|
180 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
181 | X |----------------|----------|----------|-----------|----------|-----------|----------|
182 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
183 |=========|================|==========|==========|===========|==========|===========|==========|
184 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
185 | |----------------|----------|----------|-----------|----------|-----------|----------|
186 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
187 | X |----------------|----------|----------|-----------|----------|-----------|----------|
188 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
189 +----------------------------------------------------------------------------------------------+
190 @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
191 SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
192 @note
193 (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
194 (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
195 (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
196
197 */
198
199 /* Includes ------------------------------------------------------------------*/
200 #include "stm32g0xx_hal.h"
201
202 /** @addtogroup STM32G0xx_HAL_Driver
203 * @{
204 */
205
206 /** @defgroup SPI SPI
207 * @brief SPI HAL module driver
208 * @{
209 */
210 #ifdef HAL_SPI_MODULE_ENABLED
211
212 /* Private typedef -----------------------------------------------------------*/
213 /* Private defines -----------------------------------------------------------*/
214 /** @defgroup SPI_Private_Constants SPI Private Constants
215 * @{
216 */
217 #define SPI_DEFAULT_TIMEOUT 100U
218 /**
219 * @}
220 */
221
222 /* Private macros ------------------------------------------------------------*/
223 /* Private variables ---------------------------------------------------------*/
224 /* Private function prototypes -----------------------------------------------*/
225 /** @defgroup SPI_Private_Functions SPI Private Functions
226 * @{
227 */
228 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
229 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
230 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
231 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
232 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
233 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
234 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
235 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
236 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
237 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
238 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
239 uint32_t Timeout, uint32_t Tickstart);
240 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
241 uint32_t Timeout, uint32_t Tickstart);
242 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
243 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
244 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
245 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
246 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
247 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
248 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
249 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
250 #if (USE_SPI_CRC != 0U)
251 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
252 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
253 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
254 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
255 #endif /* USE_SPI_CRC */
256 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
257 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
258 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
259 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
260 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
261 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
262 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
263 /**
264 * @}
265 */
266
267 /* Exported functions --------------------------------------------------------*/
268 /** @defgroup SPI_Exported_Functions SPI Exported Functions
269 * @{
270 */
271
272 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
273 * @brief Initialization and Configuration functions
274 *
275 @verbatim
276 ===============================================================================
277 ##### Initialization and de-initialization functions #####
278 ===============================================================================
279 [..] This subsection provides a set of functions allowing to initialize and
280 de-initialize the SPIx peripheral:
281
282 (+) User must implement HAL_SPI_MspInit() function in which he configures
283 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
284
285 (+) Call the function HAL_SPI_Init() to configure the selected device with
286 the selected configuration:
287 (++) Mode
288 (++) Direction
289 (++) Data Size
290 (++) Clock Polarity and Phase
291 (++) NSS Management
292 (++) BaudRate Prescaler
293 (++) FirstBit
294 (++) TIMode
295 (++) CRC Calculation
296 (++) CRC Polynomial if CRC enabled
297 (++) CRC Length, used only with Data8 and Data16
298 (++) FIFO reception threshold
299
300 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
301 of the selected SPIx peripheral.
302
303 @endverbatim
304 * @{
305 */
306
307 /**
308 * @brief Initialize the SPI according to the specified parameters
309 * in the SPI_InitTypeDef and initialize the associated handle.
310 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
311 * the configuration information for SPI module.
312 * @retval HAL status
313 */
HAL_SPI_Init(SPI_HandleTypeDef * hspi)314 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
315 {
316 uint32_t frxth;
317
318 /* Check the SPI handle allocation */
319 if (hspi == NULL)
320 {
321 return HAL_ERROR;
322 }
323
324 /* Check the parameters */
325 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
326 assert_param(IS_SPI_MODE(hspi->Init.Mode));
327 assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
328 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
329 assert_param(IS_SPI_NSS(hspi->Init.NSS));
330 assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
331 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
332 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
333 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
334 if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
335 {
336 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
337 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
338
339 if (hspi->Init.Mode == SPI_MODE_MASTER)
340 {
341 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
342 }
343 else
344 {
345 /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
346 hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
347 }
348 }
349 else
350 {
351 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
352
353 /* Force polarity and phase to TI protocaol requirements */
354 hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
355 hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
356 }
357 #if (USE_SPI_CRC != 0U)
358 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
359 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
360 {
361 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
362 assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
363 }
364 #else
365 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
366 #endif /* USE_SPI_CRC */
367
368 if (hspi->State == HAL_SPI_STATE_RESET)
369 {
370 /* Allocate lock resource and initialize it */
371 hspi->Lock = HAL_UNLOCKED;
372
373 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
374 /* Init the SPI Callback settings */
375 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
376 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
377 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
378 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
379 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
380 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
381 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
382 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
383
384 if (hspi->MspInitCallback == NULL)
385 {
386 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
387 }
388
389 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
390 hspi->MspInitCallback(hspi);
391 #else
392 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
393 HAL_SPI_MspInit(hspi);
394 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
395 }
396
397 hspi->State = HAL_SPI_STATE_BUSY;
398
399 /* Disable the selected SPI peripheral */
400 __HAL_SPI_DISABLE(hspi);
401
402 /* Align by default the rs fifo threshold on the data size */
403 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
404 {
405 frxth = SPI_RXFIFO_THRESHOLD_HF;
406 }
407 else
408 {
409 frxth = SPI_RXFIFO_THRESHOLD_QF;
410 }
411
412 /* CRC calculation is valid only for 16Bit and 8 Bit */
413 if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
414 {
415 /* CRC must be disabled */
416 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
417 }
418
419 /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
420 /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
421 Communication speed, First bit and CRC calculation state */
422 WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
423 (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) |
424 (hspi->Init.CLKPolarity & SPI_CR1_CPOL) |
425 (hspi->Init.CLKPhase & SPI_CR1_CPHA) |
426 (hspi->Init.NSS & SPI_CR1_SSM) |
427 (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
428 (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
429 (hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
430 #if (USE_SPI_CRC != 0U)
431 /*---------------------------- SPIx CRCL Configuration -------------------*/
432 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
433 {
434 /* Align the CRC Length on the data size */
435 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
436 {
437 /* CRC Length aligned on the data size : value set by default */
438 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
439 {
440 hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
441 }
442 else
443 {
444 hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
445 }
446 }
447
448 /* Configure : CRC Length */
449 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
450 {
451 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCL);
452 }
453 }
454 #endif /* USE_SPI_CRC */
455
456 /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
457 WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) |
458 (hspi->Init.TIMode & SPI_CR2_FRF) |
459 (hspi->Init.NSSPMode & SPI_CR2_NSSP) |
460 (hspi->Init.DataSize & SPI_CR2_DS_Msk) |
461 (frxth & SPI_CR2_FRXTH)));
462
463 #if (USE_SPI_CRC != 0U)
464 /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
465 /* Configure : CRC Polynomial */
466 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
467 {
468 WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk));
469 }
470 #endif /* USE_SPI_CRC */
471
472 #if defined(SPI_I2SCFGR_I2SMOD)
473 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
474 CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
475 #endif /* SPI_I2SCFGR_I2SMOD */
476
477 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
478 hspi->State = HAL_SPI_STATE_READY;
479
480 return HAL_OK;
481 }
482
483 /**
484 * @brief De-Initialize the SPI peripheral.
485 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
486 * the configuration information for SPI module.
487 * @retval HAL status
488 */
HAL_SPI_DeInit(SPI_HandleTypeDef * hspi)489 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
490 {
491 /* Check the SPI handle allocation */
492 if (hspi == NULL)
493 {
494 return HAL_ERROR;
495 }
496
497 /* Check SPI Instance parameter */
498 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
499
500 hspi->State = HAL_SPI_STATE_BUSY;
501
502 /* Disable the SPI Peripheral Clock */
503 __HAL_SPI_DISABLE(hspi);
504
505 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
506 if (hspi->MspDeInitCallback == NULL)
507 {
508 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
509 }
510
511 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
512 hspi->MspDeInitCallback(hspi);
513 #else
514 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
515 HAL_SPI_MspDeInit(hspi);
516 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
517
518 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
519 hspi->State = HAL_SPI_STATE_RESET;
520
521 /* Release Lock */
522 __HAL_UNLOCK(hspi);
523
524 return HAL_OK;
525 }
526
527 /**
528 * @brief Initialize the SPI MSP.
529 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
530 * the configuration information for SPI module.
531 * @retval None
532 */
HAL_SPI_MspInit(SPI_HandleTypeDef * hspi)533 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
534 {
535 /* Prevent unused argument(s) compilation warning */
536 UNUSED(hspi);
537
538 /* NOTE : This function should not be modified, when the callback is needed,
539 the HAL_SPI_MspInit should be implemented in the user file
540 */
541 }
542
543 /**
544 * @brief De-Initialize the SPI MSP.
545 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
546 * the configuration information for SPI module.
547 * @retval None
548 */
HAL_SPI_MspDeInit(SPI_HandleTypeDef * hspi)549 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
550 {
551 /* Prevent unused argument(s) compilation warning */
552 UNUSED(hspi);
553
554 /* NOTE : This function should not be modified, when the callback is needed,
555 the HAL_SPI_MspDeInit should be implemented in the user file
556 */
557 }
558
559 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
560 /**
561 * @brief Register a User SPI Callback
562 * To be used instead of the weak predefined callback
563 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
564 * the configuration information for the specified SPI.
565 * @param CallbackID ID of the callback to be registered
566 * @param pCallback pointer to the Callback function
567 * @retval HAL status
568 */
HAL_SPI_RegisterCallback(SPI_HandleTypeDef * hspi,HAL_SPI_CallbackIDTypeDef CallbackID,pSPI_CallbackTypeDef pCallback)569 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
570 pSPI_CallbackTypeDef pCallback)
571 {
572 HAL_StatusTypeDef status = HAL_OK;
573
574 if (pCallback == NULL)
575 {
576 /* Update the error code */
577 hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
578
579 return HAL_ERROR;
580 }
581 /* Process locked */
582 __HAL_LOCK(hspi);
583
584 if (HAL_SPI_STATE_READY == hspi->State)
585 {
586 switch (CallbackID)
587 {
588 case HAL_SPI_TX_COMPLETE_CB_ID :
589 hspi->TxCpltCallback = pCallback;
590 break;
591
592 case HAL_SPI_RX_COMPLETE_CB_ID :
593 hspi->RxCpltCallback = pCallback;
594 break;
595
596 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
597 hspi->TxRxCpltCallback = pCallback;
598 break;
599
600 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
601 hspi->TxHalfCpltCallback = pCallback;
602 break;
603
604 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
605 hspi->RxHalfCpltCallback = pCallback;
606 break;
607
608 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
609 hspi->TxRxHalfCpltCallback = pCallback;
610 break;
611
612 case HAL_SPI_ERROR_CB_ID :
613 hspi->ErrorCallback = pCallback;
614 break;
615
616 case HAL_SPI_ABORT_CB_ID :
617 hspi->AbortCpltCallback = pCallback;
618 break;
619
620 case HAL_SPI_MSPINIT_CB_ID :
621 hspi->MspInitCallback = pCallback;
622 break;
623
624 case HAL_SPI_MSPDEINIT_CB_ID :
625 hspi->MspDeInitCallback = pCallback;
626 break;
627
628 default :
629 /* Update the error code */
630 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
631
632 /* Return error status */
633 status = HAL_ERROR;
634 break;
635 }
636 }
637 else if (HAL_SPI_STATE_RESET == hspi->State)
638 {
639 switch (CallbackID)
640 {
641 case HAL_SPI_MSPINIT_CB_ID :
642 hspi->MspInitCallback = pCallback;
643 break;
644
645 case HAL_SPI_MSPDEINIT_CB_ID :
646 hspi->MspDeInitCallback = pCallback;
647 break;
648
649 default :
650 /* Update the error code */
651 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
652
653 /* Return error status */
654 status = HAL_ERROR;
655 break;
656 }
657 }
658 else
659 {
660 /* Update the error code */
661 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
662
663 /* Return error status */
664 status = HAL_ERROR;
665 }
666
667 /* Release Lock */
668 __HAL_UNLOCK(hspi);
669 return status;
670 }
671
672 /**
673 * @brief Unregister an SPI Callback
674 * SPI callback is redirected to the weak predefined callback
675 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
676 * the configuration information for the specified SPI.
677 * @param CallbackID ID of the callback to be unregistered
678 * @retval HAL status
679 */
HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef * hspi,HAL_SPI_CallbackIDTypeDef CallbackID)680 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
681 {
682 HAL_StatusTypeDef status = HAL_OK;
683
684 /* Process locked */
685 __HAL_LOCK(hspi);
686
687 if (HAL_SPI_STATE_READY == hspi->State)
688 {
689 switch (CallbackID)
690 {
691 case HAL_SPI_TX_COMPLETE_CB_ID :
692 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
693 break;
694
695 case HAL_SPI_RX_COMPLETE_CB_ID :
696 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
697 break;
698
699 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
700 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
701 break;
702
703 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
704 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
705 break;
706
707 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
708 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
709 break;
710
711 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
712 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
713 break;
714
715 case HAL_SPI_ERROR_CB_ID :
716 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
717 break;
718
719 case HAL_SPI_ABORT_CB_ID :
720 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
721 break;
722
723 case HAL_SPI_MSPINIT_CB_ID :
724 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
725 break;
726
727 case HAL_SPI_MSPDEINIT_CB_ID :
728 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
729 break;
730
731 default :
732 /* Update the error code */
733 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
734
735 /* Return error status */
736 status = HAL_ERROR;
737 break;
738 }
739 }
740 else if (HAL_SPI_STATE_RESET == hspi->State)
741 {
742 switch (CallbackID)
743 {
744 case HAL_SPI_MSPINIT_CB_ID :
745 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
746 break;
747
748 case HAL_SPI_MSPDEINIT_CB_ID :
749 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
750 break;
751
752 default :
753 /* Update the error code */
754 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
755
756 /* Return error status */
757 status = HAL_ERROR;
758 break;
759 }
760 }
761 else
762 {
763 /* Update the error code */
764 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
765
766 /* Return error status */
767 status = HAL_ERROR;
768 }
769
770 /* Release Lock */
771 __HAL_UNLOCK(hspi);
772 return status;
773 }
774 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
775 /**
776 * @}
777 */
778
779 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
780 * @brief Data transfers functions
781 *
782 @verbatim
783 ==============================================================================
784 ##### IO operation functions #####
785 ===============================================================================
786 [..]
787 This subsection provides a set of functions allowing to manage the SPI
788 data transfers.
789
790 [..] The SPI supports master and slave mode :
791
792 (#) There are two modes of transfer:
793 (++) Blocking mode: The communication is performed in polling mode.
794 The HAL status of all data processing is returned by the same function
795 after finishing transfer.
796 (++) No-Blocking mode: The communication is performed using Interrupts
797 or DMA, These APIs return the HAL status.
798 The end of the data processing will be indicated through the
799 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
800 using DMA mode.
801 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
802 will be executed respectively at the end of the transmit or Receive process
803 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
804
805 (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
806 exist for 1Line (simplex) and 2Lines (full duplex) modes.
807
808 @endverbatim
809 * @{
810 */
811
812 /**
813 * @brief Transmit an amount of data in blocking mode.
814 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
815 * the configuration information for SPI module.
816 * @param pData pointer to data buffer
817 * @param Size amount of data to be sent
818 * @param Timeout Timeout duration
819 * @retval HAL status
820 */
HAL_SPI_Transmit(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size,uint32_t Timeout)821 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
822 {
823 uint32_t tickstart;
824 HAL_StatusTypeDef errorcode = HAL_OK;
825 uint16_t initial_TxXferCount;
826
827 /* Check Direction parameter */
828 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
829
830 /* Process Locked */
831 __HAL_LOCK(hspi);
832
833 /* Init tickstart for timeout management*/
834 tickstart = HAL_GetTick();
835 initial_TxXferCount = Size;
836
837 if (hspi->State != HAL_SPI_STATE_READY)
838 {
839 errorcode = HAL_BUSY;
840 goto error;
841 }
842
843 if ((pData == NULL) || (Size == 0U))
844 {
845 errorcode = HAL_ERROR;
846 goto error;
847 }
848
849 /* Set the transaction information */
850 hspi->State = HAL_SPI_STATE_BUSY_TX;
851 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
852 hspi->pTxBuffPtr = (uint8_t *)pData;
853 hspi->TxXferSize = Size;
854 hspi->TxXferCount = Size;
855
856 /*Init field not used in handle to zero */
857 hspi->pRxBuffPtr = (uint8_t *)NULL;
858 hspi->RxXferSize = 0U;
859 hspi->RxXferCount = 0U;
860 hspi->TxISR = NULL;
861 hspi->RxISR = NULL;
862
863 /* Configure communication direction : 1Line */
864 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
865 {
866 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
867 __HAL_SPI_DISABLE(hspi);
868 SPI_1LINE_TX(hspi);
869 }
870
871 #if (USE_SPI_CRC != 0U)
872 /* Reset CRC Calculation */
873 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
874 {
875 SPI_RESET_CRC(hspi);
876 }
877 #endif /* USE_SPI_CRC */
878
879 /* Check if the SPI is already enabled */
880 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
881 {
882 /* Enable SPI peripheral */
883 __HAL_SPI_ENABLE(hspi);
884 }
885
886 /* Transmit data in 16 Bit mode */
887 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
888 {
889 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
890 {
891 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
892 hspi->pTxBuffPtr += sizeof(uint16_t);
893 hspi->TxXferCount--;
894 }
895 /* Transmit data in 16 Bit mode */
896 while (hspi->TxXferCount > 0U)
897 {
898 /* Wait until TXE flag is set to send data */
899 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
900 {
901 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
902 hspi->pTxBuffPtr += sizeof(uint16_t);
903 hspi->TxXferCount--;
904 }
905 else
906 {
907 /* Timeout management */
908 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
909 {
910 errorcode = HAL_TIMEOUT;
911 goto error;
912 }
913 }
914 }
915 }
916 /* Transmit data in 8 Bit mode */
917 else
918 {
919 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
920 {
921 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
922 hspi->pTxBuffPtr += sizeof(uint8_t);
923 hspi->TxXferCount--;
924 }
925 while (hspi->TxXferCount > 0U)
926 {
927 /* Wait until TXE flag is set to send data */
928 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
929 {
930 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
931 hspi->pTxBuffPtr += sizeof(uint8_t);
932 hspi->TxXferCount--;
933 }
934 else
935 {
936 /* Timeout management */
937 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
938 {
939 errorcode = HAL_TIMEOUT;
940 goto error;
941 }
942 }
943 }
944 }
945 #if (USE_SPI_CRC != 0U)
946 /* Enable CRC Transmission */
947 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
948 {
949 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
950 }
951 #endif /* USE_SPI_CRC */
952
953 /* Check the end of the transaction */
954 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
955 {
956 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
957 }
958
959 /* Clear overrun flag in 2 Lines communication mode because received is not read */
960 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
961 {
962 __HAL_SPI_CLEAR_OVRFLAG(hspi);
963 }
964
965 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
966 {
967 errorcode = HAL_ERROR;
968 }
969
970 error:
971 hspi->State = HAL_SPI_STATE_READY;
972 /* Process Unlocked */
973 __HAL_UNLOCK(hspi);
974 return errorcode;
975 }
976
977 /**
978 * @brief Receive an amount of data in blocking mode.
979 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
980 * the configuration information for SPI module.
981 * @param pData pointer to data buffer
982 * @param Size amount of data to be received
983 * @param Timeout Timeout duration
984 * @retval HAL status
985 */
HAL_SPI_Receive(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size,uint32_t Timeout)986 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
987 {
988 #if (USE_SPI_CRC != 0U)
989 __IO uint32_t tmpreg = 0U;
990 __IO uint8_t *ptmpreg8;
991 __IO uint8_t tmpreg8 = 0;
992 #endif /* USE_SPI_CRC */
993 uint32_t tickstart;
994 HAL_StatusTypeDef errorcode = HAL_OK;
995
996 if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
997 {
998 hspi->State = HAL_SPI_STATE_BUSY_RX;
999 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1000 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
1001 }
1002
1003 /* Process Locked */
1004 __HAL_LOCK(hspi);
1005
1006 /* Init tickstart for timeout management*/
1007 tickstart = HAL_GetTick();
1008
1009 if (hspi->State != HAL_SPI_STATE_READY)
1010 {
1011 errorcode = HAL_BUSY;
1012 goto error;
1013 }
1014
1015 if ((pData == NULL) || (Size == 0U))
1016 {
1017 errorcode = HAL_ERROR;
1018 goto error;
1019 }
1020
1021 /* Set the transaction information */
1022 hspi->State = HAL_SPI_STATE_BUSY_RX;
1023 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1024 hspi->pRxBuffPtr = (uint8_t *)pData;
1025 hspi->RxXferSize = Size;
1026 hspi->RxXferCount = Size;
1027
1028 /*Init field not used in handle to zero */
1029 hspi->pTxBuffPtr = (uint8_t *)NULL;
1030 hspi->TxXferSize = 0U;
1031 hspi->TxXferCount = 0U;
1032 hspi->RxISR = NULL;
1033 hspi->TxISR = NULL;
1034
1035 #if (USE_SPI_CRC != 0U)
1036 /* Reset CRC Calculation */
1037 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1038 {
1039 SPI_RESET_CRC(hspi);
1040 /* this is done to handle the CRCNEXT before the latest data */
1041 hspi->RxXferCount--;
1042 }
1043 #endif /* USE_SPI_CRC */
1044
1045 /* Set the Rx Fifo threshold */
1046 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1047 {
1048 /* Set RX Fifo threshold according the reception data length: 16bit */
1049 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1050 }
1051 else
1052 {
1053 /* Set RX Fifo threshold according the reception data length: 8bit */
1054 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1055 }
1056
1057 /* Configure communication direction: 1Line */
1058 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1059 {
1060 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1061 __HAL_SPI_DISABLE(hspi);
1062 SPI_1LINE_RX(hspi);
1063 }
1064
1065 /* Check if the SPI is already enabled */
1066 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1067 {
1068 /* Enable SPI peripheral */
1069 __HAL_SPI_ENABLE(hspi);
1070 }
1071
1072 /* Receive data in 8 Bit mode */
1073 if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
1074 {
1075 /* Transfer loop */
1076 while (hspi->RxXferCount > 0U)
1077 {
1078 /* Check the RXNE flag */
1079 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
1080 {
1081 /* read the received data */
1082 (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1083 hspi->pRxBuffPtr += sizeof(uint8_t);
1084 hspi->RxXferCount--;
1085 }
1086 else
1087 {
1088 /* Timeout management */
1089 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1090 {
1091 errorcode = HAL_TIMEOUT;
1092 goto error;
1093 }
1094 }
1095 }
1096 }
1097 else
1098 {
1099 /* Transfer loop */
1100 while (hspi->RxXferCount > 0U)
1101 {
1102 /* Check the RXNE flag */
1103 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
1104 {
1105 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1106 hspi->pRxBuffPtr += sizeof(uint16_t);
1107 hspi->RxXferCount--;
1108 }
1109 else
1110 {
1111 /* Timeout management */
1112 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1113 {
1114 errorcode = HAL_TIMEOUT;
1115 goto error;
1116 }
1117 }
1118 }
1119 }
1120
1121 #if (USE_SPI_CRC != 0U)
1122 /* Handle the CRC Transmission */
1123 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1124 {
1125 /* freeze the CRC before the latest data */
1126 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1127
1128 /* Read the latest data */
1129 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1130 {
1131 /* the latest data has not been received */
1132 errorcode = HAL_TIMEOUT;
1133 goto error;
1134 }
1135
1136 /* Receive last data in 16 Bit mode */
1137 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1138 {
1139 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1140 }
1141 /* Receive last data in 8 Bit mode */
1142 else
1143 {
1144 (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1145 }
1146
1147 /* Wait the CRC data */
1148 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1149 {
1150 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1151 errorcode = HAL_TIMEOUT;
1152 goto error;
1153 }
1154
1155 /* Read CRC to Flush DR and RXNE flag */
1156 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1157 {
1158 /* Read 16bit CRC */
1159 tmpreg = READ_REG(hspi->Instance->DR);
1160 /* To avoid GCC warning */
1161 UNUSED(tmpreg);
1162 }
1163 else
1164 {
1165 /* Initialize the 8bit temporary pointer */
1166 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
1167 /* Read 8bit CRC */
1168 tmpreg8 = *ptmpreg8;
1169 /* To avoid GCC warning */
1170 UNUSED(tmpreg8);
1171
1172 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1173 {
1174 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1175 {
1176 /* Error on the CRC reception */
1177 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1178 errorcode = HAL_TIMEOUT;
1179 goto error;
1180 }
1181 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
1182 tmpreg8 = *ptmpreg8;
1183 /* To avoid GCC warning */
1184 UNUSED(tmpreg8);
1185 }
1186 }
1187 }
1188 #endif /* USE_SPI_CRC */
1189
1190 /* Check the end of the transaction */
1191 if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1192 {
1193 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1194 }
1195
1196 #if (USE_SPI_CRC != 0U)
1197 /* Check if CRC error occurred */
1198 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1199 {
1200 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1201 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1202 }
1203 #endif /* USE_SPI_CRC */
1204
1205 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1206 {
1207 errorcode = HAL_ERROR;
1208 }
1209
1210 error :
1211 hspi->State = HAL_SPI_STATE_READY;
1212 __HAL_UNLOCK(hspi);
1213 return errorcode;
1214 }
1215
1216 /**
1217 * @brief Transmit and Receive an amount of data in blocking mode.
1218 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1219 * the configuration information for SPI module.
1220 * @param pTxData pointer to transmission data buffer
1221 * @param pRxData pointer to reception data buffer
1222 * @param Size amount of data to be sent and received
1223 * @param Timeout Timeout duration
1224 * @retval HAL status
1225 */
HAL_SPI_TransmitReceive(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size,uint32_t Timeout)1226 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
1227 uint32_t Timeout)
1228 {
1229 uint16_t initial_TxXferCount;
1230 uint32_t tmp_mode;
1231 HAL_SPI_StateTypeDef tmp_state;
1232 uint32_t tickstart;
1233 #if (USE_SPI_CRC != 0U)
1234 __IO uint32_t tmpreg = 0U;
1235 uint32_t spi_cr1;
1236 uint32_t spi_cr2;
1237 __IO uint8_t *ptmpreg8;
1238 __IO uint8_t tmpreg8 = 0;
1239 #endif /* USE_SPI_CRC */
1240
1241 /* Variable used to alternate Rx and Tx during transfer */
1242 uint32_t txallowed = 1U;
1243 HAL_StatusTypeDef errorcode = HAL_OK;
1244
1245 /* Check Direction parameter */
1246 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1247
1248 /* Process Locked */
1249 __HAL_LOCK(hspi);
1250
1251 /* Init tickstart for timeout management*/
1252 tickstart = HAL_GetTick();
1253
1254 /* Init temporary variables */
1255 tmp_state = hspi->State;
1256 tmp_mode = hspi->Init.Mode;
1257 initial_TxXferCount = Size;
1258 #if (USE_SPI_CRC != 0U)
1259 spi_cr1 = READ_REG(hspi->Instance->CR1);
1260 spi_cr2 = READ_REG(hspi->Instance->CR2);
1261 #endif /* USE_SPI_CRC */
1262
1263 if (!((tmp_state == HAL_SPI_STATE_READY) || \
1264 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1265 {
1266 errorcode = HAL_BUSY;
1267 goto error;
1268 }
1269
1270 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1271 {
1272 errorcode = HAL_ERROR;
1273 goto error;
1274 }
1275
1276 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1277 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1278 {
1279 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1280 }
1281
1282 /* Set the transaction information */
1283 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1284 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1285 hspi->RxXferCount = Size;
1286 hspi->RxXferSize = Size;
1287 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1288 hspi->TxXferCount = Size;
1289 hspi->TxXferSize = Size;
1290
1291 /*Init field not used in handle to zero */
1292 hspi->RxISR = NULL;
1293 hspi->TxISR = NULL;
1294
1295 #if (USE_SPI_CRC != 0U)
1296 /* Reset CRC Calculation */
1297 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1298 {
1299 SPI_RESET_CRC(hspi);
1300 }
1301 #endif /* USE_SPI_CRC */
1302
1303 /* Set the Rx Fifo threshold */
1304 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1305 {
1306 /* Set fiforxthreshold according the reception data length: 16bit */
1307 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1308 }
1309 else
1310 {
1311 /* Set fiforxthreshold according the reception data length: 8bit */
1312 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1313 }
1314
1315 /* Check if the SPI is already enabled */
1316 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1317 {
1318 /* Enable SPI peripheral */
1319 __HAL_SPI_ENABLE(hspi);
1320 }
1321
1322 /* Transmit and Receive data in 16 Bit mode */
1323 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1324 {
1325 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1326 {
1327 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1328 hspi->pTxBuffPtr += sizeof(uint16_t);
1329 hspi->TxXferCount--;
1330 }
1331 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1332 {
1333 /* Check TXE flag */
1334 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1335 {
1336 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1337 hspi->pTxBuffPtr += sizeof(uint16_t);
1338 hspi->TxXferCount--;
1339 /* Next Data is a reception (Rx). Tx not allowed */
1340 txallowed = 0U;
1341
1342 #if (USE_SPI_CRC != 0U)
1343 /* Enable CRC Transmission */
1344 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1345 {
1346 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
1347 if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
1348 {
1349 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
1350 }
1351 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1352 }
1353 #endif /* USE_SPI_CRC */
1354 }
1355
1356 /* Check RXNE flag */
1357 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1358 {
1359 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1360 hspi->pRxBuffPtr += sizeof(uint16_t);
1361 hspi->RxXferCount--;
1362 /* Next Data is a Transmission (Tx). Tx is allowed */
1363 txallowed = 1U;
1364 }
1365 if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
1366 {
1367 errorcode = HAL_TIMEOUT;
1368 goto error;
1369 }
1370 }
1371 }
1372 /* Transmit and Receive data in 8 Bit mode */
1373 else
1374 {
1375 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1376 {
1377 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
1378 hspi->pTxBuffPtr += sizeof(uint8_t);
1379 hspi->TxXferCount--;
1380 }
1381 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1382 {
1383 /* Check TXE flag */
1384 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1385 {
1386 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
1387 hspi->pTxBuffPtr++;
1388 hspi->TxXferCount--;
1389 /* Next Data is a reception (Rx). Tx not allowed */
1390 txallowed = 0U;
1391
1392 #if (USE_SPI_CRC != 0U)
1393 /* Enable CRC Transmission */
1394 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1395 {
1396 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
1397 if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
1398 {
1399 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
1400 }
1401 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1402 }
1403 #endif /* USE_SPI_CRC */
1404 }
1405
1406 /* Wait until RXNE flag is reset */
1407 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1408 {
1409 (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1410 hspi->pRxBuffPtr++;
1411 hspi->RxXferCount--;
1412 /* Next Data is a Transmission (Tx). Tx is allowed */
1413 txallowed = 1U;
1414 }
1415 if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
1416 {
1417 errorcode = HAL_TIMEOUT;
1418 goto error;
1419 }
1420 }
1421 }
1422
1423 #if (USE_SPI_CRC != 0U)
1424 /* Read CRC from DR to close CRC calculation process */
1425 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1426 {
1427 /* Wait until TXE flag */
1428 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1429 {
1430 /* Error on the CRC reception */
1431 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1432 errorcode = HAL_TIMEOUT;
1433 goto error;
1434 }
1435 /* Read CRC */
1436 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1437 {
1438 /* Read 16bit CRC */
1439 tmpreg = READ_REG(hspi->Instance->DR);
1440 /* To avoid GCC warning */
1441 UNUSED(tmpreg);
1442 }
1443 else
1444 {
1445 /* Initialize the 8bit temporary pointer */
1446 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
1447 /* Read 8bit CRC */
1448 tmpreg8 = *ptmpreg8;
1449 /* To avoid GCC warning */
1450 UNUSED(tmpreg8);
1451
1452 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
1453 {
1454 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1455 {
1456 /* Error on the CRC reception */
1457 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1458 errorcode = HAL_TIMEOUT;
1459 goto error;
1460 }
1461 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
1462 tmpreg8 = *ptmpreg8;
1463 /* To avoid GCC warning */
1464 UNUSED(tmpreg8);
1465 }
1466 }
1467 }
1468
1469 /* Check if CRC error occurred */
1470 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1471 {
1472 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1473 /* Clear CRC Flag */
1474 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1475
1476 errorcode = HAL_ERROR;
1477 }
1478 #endif /* USE_SPI_CRC */
1479
1480 /* Check the end of the transaction */
1481 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1482 {
1483 errorcode = HAL_ERROR;
1484 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1485 }
1486
1487 error :
1488 hspi->State = HAL_SPI_STATE_READY;
1489 __HAL_UNLOCK(hspi);
1490 return errorcode;
1491 }
1492
1493 /**
1494 * @brief Transmit an amount of data in non-blocking mode with Interrupt.
1495 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1496 * the configuration information for SPI module.
1497 * @param pData pointer to data buffer
1498 * @param Size amount of data to be sent
1499 * @retval HAL status
1500 */
HAL_SPI_Transmit_IT(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1501 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1502 {
1503 HAL_StatusTypeDef errorcode = HAL_OK;
1504
1505 /* Check Direction parameter */
1506 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1507
1508 /* Process Locked */
1509 __HAL_LOCK(hspi);
1510
1511 if ((pData == NULL) || (Size == 0U))
1512 {
1513 errorcode = HAL_ERROR;
1514 goto error;
1515 }
1516
1517 if (hspi->State != HAL_SPI_STATE_READY)
1518 {
1519 errorcode = HAL_BUSY;
1520 goto error;
1521 }
1522
1523 /* Set the transaction information */
1524 hspi->State = HAL_SPI_STATE_BUSY_TX;
1525 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1526 hspi->pTxBuffPtr = (uint8_t *)pData;
1527 hspi->TxXferSize = Size;
1528 hspi->TxXferCount = Size;
1529
1530 /* Init field not used in handle to zero */
1531 hspi->pRxBuffPtr = (uint8_t *)NULL;
1532 hspi->RxXferSize = 0U;
1533 hspi->RxXferCount = 0U;
1534 hspi->RxISR = NULL;
1535
1536 /* Set the function for IT treatment */
1537 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1538 {
1539 hspi->TxISR = SPI_TxISR_16BIT;
1540 }
1541 else
1542 {
1543 hspi->TxISR = SPI_TxISR_8BIT;
1544 }
1545
1546 /* Configure communication direction : 1Line */
1547 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1548 {
1549 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1550 __HAL_SPI_DISABLE(hspi);
1551 SPI_1LINE_TX(hspi);
1552 }
1553
1554 #if (USE_SPI_CRC != 0U)
1555 /* Reset CRC Calculation */
1556 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1557 {
1558 SPI_RESET_CRC(hspi);
1559 }
1560 #endif /* USE_SPI_CRC */
1561
1562 /* Enable TXE and ERR interrupt */
1563 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
1564
1565
1566 /* Check if the SPI is already enabled */
1567 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1568 {
1569 /* Enable SPI peripheral */
1570 __HAL_SPI_ENABLE(hspi);
1571 }
1572
1573 error :
1574 __HAL_UNLOCK(hspi);
1575 return errorcode;
1576 }
1577
1578 /**
1579 * @brief Receive an amount of data in non-blocking mode with Interrupt.
1580 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1581 * the configuration information for SPI module.
1582 * @param pData pointer to data buffer
1583 * @param Size amount of data to be sent
1584 * @retval HAL status
1585 */
HAL_SPI_Receive_IT(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1586 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1587 {
1588 HAL_StatusTypeDef errorcode = HAL_OK;
1589
1590 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1591 {
1592 hspi->State = HAL_SPI_STATE_BUSY_RX;
1593 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1594 return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
1595 }
1596
1597 /* Process Locked */
1598 __HAL_LOCK(hspi);
1599
1600 if (hspi->State != HAL_SPI_STATE_READY)
1601 {
1602 errorcode = HAL_BUSY;
1603 goto error;
1604 }
1605
1606 if ((pData == NULL) || (Size == 0U))
1607 {
1608 errorcode = HAL_ERROR;
1609 goto error;
1610 }
1611
1612 /* Set the transaction information */
1613 hspi->State = HAL_SPI_STATE_BUSY_RX;
1614 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1615 hspi->pRxBuffPtr = (uint8_t *)pData;
1616 hspi->RxXferSize = Size;
1617 hspi->RxXferCount = Size;
1618
1619 /* Init field not used in handle to zero */
1620 hspi->pTxBuffPtr = (uint8_t *)NULL;
1621 hspi->TxXferSize = 0U;
1622 hspi->TxXferCount = 0U;
1623 hspi->TxISR = NULL;
1624
1625 /* Check the data size to adapt Rx threshold and the set the function for IT treatment */
1626 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1627 {
1628 /* Set RX Fifo threshold according the reception data length: 16 bit */
1629 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1630 hspi->RxISR = SPI_RxISR_16BIT;
1631 }
1632 else
1633 {
1634 /* Set RX Fifo threshold according the reception data length: 8 bit */
1635 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1636 hspi->RxISR = SPI_RxISR_8BIT;
1637 }
1638
1639 /* Configure communication direction : 1Line */
1640 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1641 {
1642 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1643 __HAL_SPI_DISABLE(hspi);
1644 SPI_1LINE_RX(hspi);
1645 }
1646
1647 #if (USE_SPI_CRC != 0U)
1648 /* Reset CRC Calculation */
1649 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1650 {
1651 hspi->CRCSize = 1U;
1652 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1653 {
1654 hspi->CRCSize = 2U;
1655 }
1656 SPI_RESET_CRC(hspi);
1657 }
1658 else
1659 {
1660 hspi->CRCSize = 0U;
1661 }
1662 #endif /* USE_SPI_CRC */
1663
1664 /* Enable TXE and ERR interrupt */
1665 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
1666
1667 /* Note : The SPI must be enabled after unlocking current process
1668 to avoid the risk of SPI interrupt handle execution before current
1669 process unlock */
1670
1671 /* Check if the SPI is already enabled */
1672 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1673 {
1674 /* Enable SPI peripheral */
1675 __HAL_SPI_ENABLE(hspi);
1676 }
1677
1678 error :
1679 /* Process Unlocked */
1680 __HAL_UNLOCK(hspi);
1681 return errorcode;
1682 }
1683
1684 /**
1685 * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
1686 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1687 * the configuration information for SPI module.
1688 * @param pTxData pointer to transmission data buffer
1689 * @param pRxData pointer to reception data buffer
1690 * @param Size amount of data to be sent and received
1691 * @retval HAL status
1692 */
HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size)1693 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
1694 {
1695 uint32_t tmp_mode;
1696 HAL_SPI_StateTypeDef tmp_state;
1697 HAL_StatusTypeDef errorcode = HAL_OK;
1698
1699 /* Check Direction parameter */
1700 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1701
1702 /* Process locked */
1703 __HAL_LOCK(hspi);
1704
1705 /* Init temporary variables */
1706 tmp_state = hspi->State;
1707 tmp_mode = hspi->Init.Mode;
1708
1709 if (!((tmp_state == HAL_SPI_STATE_READY) || \
1710 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1711 {
1712 errorcode = HAL_BUSY;
1713 goto error;
1714 }
1715
1716 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1717 {
1718 errorcode = HAL_ERROR;
1719 goto error;
1720 }
1721
1722 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1723 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1724 {
1725 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1726 }
1727
1728 /* Set the transaction information */
1729 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1730 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1731 hspi->TxXferSize = Size;
1732 hspi->TxXferCount = Size;
1733 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1734 hspi->RxXferSize = Size;
1735 hspi->RxXferCount = Size;
1736
1737 /* Set the function for IT treatment */
1738 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1739 {
1740 hspi->RxISR = SPI_2linesRxISR_16BIT;
1741 hspi->TxISR = SPI_2linesTxISR_16BIT;
1742 }
1743 else
1744 {
1745 hspi->RxISR = SPI_2linesRxISR_8BIT;
1746 hspi->TxISR = SPI_2linesTxISR_8BIT;
1747 }
1748
1749 #if (USE_SPI_CRC != 0U)
1750 /* Reset CRC Calculation */
1751 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1752 {
1753 hspi->CRCSize = 1U;
1754 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1755 {
1756 hspi->CRCSize = 2U;
1757 }
1758 SPI_RESET_CRC(hspi);
1759 }
1760 else
1761 {
1762 hspi->CRCSize = 0U;
1763 }
1764 #endif /* USE_SPI_CRC */
1765
1766 /* Check if packing mode is enabled and if there is more than 2 data to receive */
1767 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U))
1768 {
1769 /* Set RX Fifo threshold according the reception data length: 16 bit */
1770 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1771 }
1772 else
1773 {
1774 /* Set RX Fifo threshold according the reception data length: 8 bit */
1775 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1776 }
1777
1778 /* Enable TXE, RXNE and ERR interrupt */
1779 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
1780
1781 /* Check if the SPI is already enabled */
1782 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1783 {
1784 /* Enable SPI peripheral */
1785 __HAL_SPI_ENABLE(hspi);
1786 }
1787
1788 error :
1789 /* Process Unlocked */
1790 __HAL_UNLOCK(hspi);
1791 return errorcode;
1792 }
1793
1794 /**
1795 * @brief Transmit an amount of data in non-blocking mode with DMA.
1796 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1797 * the configuration information for SPI module.
1798 * @param pData pointer to data buffer
1799 * @param Size amount of data to be sent
1800 * @retval HAL status
1801 */
HAL_SPI_Transmit_DMA(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1802 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1803 {
1804 HAL_StatusTypeDef errorcode = HAL_OK;
1805
1806 /* Check tx dma handle */
1807 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1808
1809 /* Check Direction parameter */
1810 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1811
1812 /* Process Locked */
1813 __HAL_LOCK(hspi);
1814
1815 if (hspi->State != HAL_SPI_STATE_READY)
1816 {
1817 errorcode = HAL_BUSY;
1818 goto error;
1819 }
1820
1821 if ((pData == NULL) || (Size == 0U))
1822 {
1823 errorcode = HAL_ERROR;
1824 goto error;
1825 }
1826
1827 /* Set the transaction information */
1828 hspi->State = HAL_SPI_STATE_BUSY_TX;
1829 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1830 hspi->pTxBuffPtr = (uint8_t *)pData;
1831 hspi->TxXferSize = Size;
1832 hspi->TxXferCount = Size;
1833
1834 /* Init field not used in handle to zero */
1835 hspi->pRxBuffPtr = (uint8_t *)NULL;
1836 hspi->TxISR = NULL;
1837 hspi->RxISR = NULL;
1838 hspi->RxXferSize = 0U;
1839 hspi->RxXferCount = 0U;
1840
1841 /* Configure communication direction : 1Line */
1842 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1843 {
1844 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1845 __HAL_SPI_DISABLE(hspi);
1846 SPI_1LINE_TX(hspi);
1847 }
1848
1849 #if (USE_SPI_CRC != 0U)
1850 /* Reset CRC Calculation */
1851 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1852 {
1853 SPI_RESET_CRC(hspi);
1854 }
1855 #endif /* USE_SPI_CRC */
1856
1857 /* Set the SPI TxDMA Half transfer complete callback */
1858 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
1859
1860 /* Set the SPI TxDMA transfer complete callback */
1861 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
1862
1863 /* Set the DMA error callback */
1864 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
1865
1866 /* Set the DMA AbortCpltCallback */
1867 hspi->hdmatx->XferAbortCallback = NULL;
1868
1869 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1870 /* Packing mode is enabled only if the DMA setting is HALWORD */
1871 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
1872 {
1873 /* Check the even/odd of the data size + crc if enabled */
1874 if ((hspi->TxXferCount & 0x1U) == 0U)
1875 {
1876 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1877 hspi->TxXferCount = (hspi->TxXferCount >> 1U);
1878 }
1879 else
1880 {
1881 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1882 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
1883 }
1884 }
1885
1886 /* Enable the Tx DMA Stream/Channel */
1887 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
1888 hspi->TxXferCount))
1889 {
1890 /* Update SPI error code */
1891 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
1892 errorcode = HAL_ERROR;
1893
1894 hspi->State = HAL_SPI_STATE_READY;
1895 goto error;
1896 }
1897
1898 /* Check if the SPI is already enabled */
1899 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1900 {
1901 /* Enable SPI peripheral */
1902 __HAL_SPI_ENABLE(hspi);
1903 }
1904
1905 /* Enable the SPI Error Interrupt Bit */
1906 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
1907
1908 /* Enable Tx DMA Request */
1909 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
1910
1911 error :
1912 /* Process Unlocked */
1913 __HAL_UNLOCK(hspi);
1914 return errorcode;
1915 }
1916
1917 /**
1918 * @brief Receive an amount of data in non-blocking mode with DMA.
1919 * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
1920 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1921 * the configuration information for SPI module.
1922 * @param pData pointer to data buffer
1923 * @note When the CRC feature is enabled the pData Length must be Size + 1.
1924 * @param Size amount of data to be sent
1925 * @retval HAL status
1926 */
HAL_SPI_Receive_DMA(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1927 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1928 {
1929 HAL_StatusTypeDef errorcode = HAL_OK;
1930
1931 /* Check rx dma handle */
1932 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
1933
1934 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1935 {
1936 hspi->State = HAL_SPI_STATE_BUSY_RX;
1937
1938 /* Check tx dma handle */
1939 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1940
1941 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1942 return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
1943 }
1944
1945 /* Process Locked */
1946 __HAL_LOCK(hspi);
1947
1948 if (hspi->State != HAL_SPI_STATE_READY)
1949 {
1950 errorcode = HAL_BUSY;
1951 goto error;
1952 }
1953
1954 if ((pData == NULL) || (Size == 0U))
1955 {
1956 errorcode = HAL_ERROR;
1957 goto error;
1958 }
1959
1960 /* Set the transaction information */
1961 hspi->State = HAL_SPI_STATE_BUSY_RX;
1962 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1963 hspi->pRxBuffPtr = (uint8_t *)pData;
1964 hspi->RxXferSize = Size;
1965 hspi->RxXferCount = Size;
1966
1967 /*Init field not used in handle to zero */
1968 hspi->RxISR = NULL;
1969 hspi->TxISR = NULL;
1970 hspi->TxXferSize = 0U;
1971 hspi->TxXferCount = 0U;
1972
1973 /* Configure communication direction : 1Line */
1974 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1975 {
1976 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1977 __HAL_SPI_DISABLE(hspi);
1978 SPI_1LINE_RX(hspi);
1979 }
1980
1981 #if (USE_SPI_CRC != 0U)
1982 /* Reset CRC Calculation */
1983 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1984 {
1985 SPI_RESET_CRC(hspi);
1986 }
1987 #endif /* USE_SPI_CRC */
1988
1989
1990 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
1991 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1992 {
1993 /* Set RX Fifo threshold according the reception data length: 16bit */
1994 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1995 }
1996 else
1997 {
1998 /* Set RX Fifo threshold according the reception data length: 8bit */
1999 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2000
2001 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2002 {
2003 /* Set RX Fifo threshold according the reception data length: 16bit */
2004 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2005
2006 if ((hspi->RxXferCount & 0x1U) == 0x0U)
2007 {
2008 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2009 hspi->RxXferCount = hspi->RxXferCount >> 1U;
2010 }
2011 else
2012 {
2013 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2014 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
2015 }
2016 }
2017 }
2018
2019 /* Set the SPI RxDMA Half transfer complete callback */
2020 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
2021
2022 /* Set the SPI Rx DMA transfer complete callback */
2023 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
2024
2025 /* Set the DMA error callback */
2026 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
2027
2028 /* Set the DMA AbortCpltCallback */
2029 hspi->hdmarx->XferAbortCallback = NULL;
2030
2031 /* Enable the Rx DMA Stream/Channel */
2032 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
2033 hspi->RxXferCount))
2034 {
2035 /* Update SPI error code */
2036 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2037 errorcode = HAL_ERROR;
2038
2039 hspi->State = HAL_SPI_STATE_READY;
2040 goto error;
2041 }
2042
2043 /* Check if the SPI is already enabled */
2044 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
2045 {
2046 /* Enable SPI peripheral */
2047 __HAL_SPI_ENABLE(hspi);
2048 }
2049
2050 /* Enable the SPI Error Interrupt Bit */
2051 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
2052
2053 /* Enable Rx DMA Request */
2054 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2055
2056 error:
2057 /* Process Unlocked */
2058 __HAL_UNLOCK(hspi);
2059 return errorcode;
2060 }
2061
2062 /**
2063 * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
2064 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2065 * the configuration information for SPI module.
2066 * @param pTxData pointer to transmission data buffer
2067 * @param pRxData pointer to reception data buffer
2068 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
2069 * @param Size amount of data to be sent
2070 * @retval HAL status
2071 */
HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size)2072 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
2073 uint16_t Size)
2074 {
2075 uint32_t tmp_mode;
2076 HAL_SPI_StateTypeDef tmp_state;
2077 HAL_StatusTypeDef errorcode = HAL_OK;
2078
2079 /* Check rx & tx dma handles */
2080 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
2081 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
2082
2083 /* Check Direction parameter */
2084 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
2085
2086 /* Process locked */
2087 __HAL_LOCK(hspi);
2088
2089 /* Init temporary variables */
2090 tmp_state = hspi->State;
2091 tmp_mode = hspi->Init.Mode;
2092
2093 if (!((tmp_state == HAL_SPI_STATE_READY) ||
2094 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
2095 {
2096 errorcode = HAL_BUSY;
2097 goto error;
2098 }
2099
2100 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
2101 {
2102 errorcode = HAL_ERROR;
2103 goto error;
2104 }
2105
2106 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
2107 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
2108 {
2109 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
2110 }
2111
2112 /* Set the transaction information */
2113 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2114 hspi->pTxBuffPtr = (uint8_t *)pTxData;
2115 hspi->TxXferSize = Size;
2116 hspi->TxXferCount = Size;
2117 hspi->pRxBuffPtr = (uint8_t *)pRxData;
2118 hspi->RxXferSize = Size;
2119 hspi->RxXferCount = Size;
2120
2121 /* Init field not used in handle to zero */
2122 hspi->RxISR = NULL;
2123 hspi->TxISR = NULL;
2124
2125 #if (USE_SPI_CRC != 0U)
2126 /* Reset CRC Calculation */
2127 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2128 {
2129 SPI_RESET_CRC(hspi);
2130 }
2131 #endif /* USE_SPI_CRC */
2132
2133 /* Reset the threshold bit */
2134 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
2135
2136 /* The packing mode management is enabled by the DMA settings according the spi data size */
2137 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
2138 {
2139 /* Set fiforxthreshold according the reception data length: 16bit */
2140 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2141 }
2142 else
2143 {
2144 /* Set RX Fifo threshold according the reception data length: 8bit */
2145 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2146
2147 if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2148 {
2149 if ((hspi->TxXferSize & 0x1U) == 0x0U)
2150 {
2151 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
2152 hspi->TxXferCount = hspi->TxXferCount >> 1U;
2153 }
2154 else
2155 {
2156 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
2157 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
2158 }
2159 }
2160
2161 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2162 {
2163 /* Set RX Fifo threshold according the reception data length: 16bit */
2164 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2165
2166 if ((hspi->RxXferCount & 0x1U) == 0x0U)
2167 {
2168 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2169 hspi->RxXferCount = hspi->RxXferCount >> 1U;
2170 }
2171 else
2172 {
2173 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2174 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
2175 }
2176 }
2177 }
2178
2179 /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
2180 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
2181 {
2182 /* Set the SPI Rx DMA Half transfer complete callback */
2183 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
2184 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
2185 }
2186 else
2187 {
2188 /* Set the SPI Tx/Rx DMA Half transfer complete callback */
2189 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
2190 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
2191 }
2192
2193 /* Set the DMA error callback */
2194 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
2195
2196 /* Set the DMA AbortCpltCallback */
2197 hspi->hdmarx->XferAbortCallback = NULL;
2198
2199 /* Enable the Rx DMA Stream/Channel */
2200 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
2201 hspi->RxXferCount))
2202 {
2203 /* Update SPI error code */
2204 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2205 errorcode = HAL_ERROR;
2206
2207 hspi->State = HAL_SPI_STATE_READY;
2208 goto error;
2209 }
2210
2211 /* Enable Rx DMA Request */
2212 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2213
2214 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
2215 is performed in DMA reception complete callback */
2216 hspi->hdmatx->XferHalfCpltCallback = NULL;
2217 hspi->hdmatx->XferCpltCallback = NULL;
2218 hspi->hdmatx->XferErrorCallback = NULL;
2219 hspi->hdmatx->XferAbortCallback = NULL;
2220
2221 /* Enable the Tx DMA Stream/Channel */
2222 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
2223 hspi->TxXferCount))
2224 {
2225 /* Update SPI error code */
2226 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2227 errorcode = HAL_ERROR;
2228
2229 hspi->State = HAL_SPI_STATE_READY;
2230 goto error;
2231 }
2232
2233 /* Check if the SPI is already enabled */
2234 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
2235 {
2236 /* Enable SPI peripheral */
2237 __HAL_SPI_ENABLE(hspi);
2238 }
2239 /* Enable the SPI Error Interrupt Bit */
2240 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
2241
2242 /* Enable Tx DMA Request */
2243 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
2244
2245 error :
2246 /* Process Unlocked */
2247 __HAL_UNLOCK(hspi);
2248 return errorcode;
2249 }
2250
2251 /**
2252 * @brief Abort ongoing transfer (blocking mode).
2253 * @param hspi SPI handle.
2254 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2255 * started in Interrupt or DMA mode.
2256 * This procedure performs following operations :
2257 * - Disable SPI Interrupts (depending of transfer direction)
2258 * - Disable the DMA transfer in the peripheral register (if enabled)
2259 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
2260 * - Set handle State to READY
2261 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
2262 * @retval HAL status
2263 */
HAL_SPI_Abort(SPI_HandleTypeDef * hspi)2264 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
2265 {
2266 HAL_StatusTypeDef errorcode;
2267 __IO uint32_t count;
2268 __IO uint32_t resetcount;
2269
2270 /* Initialized local variable */
2271 errorcode = HAL_OK;
2272 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2273 count = resetcount;
2274
2275 /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
2276 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
2277
2278 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
2279 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
2280 {
2281 hspi->TxISR = SPI_AbortTx_ISR;
2282 /* Wait HAL_SPI_STATE_ABORT state */
2283 do
2284 {
2285 if (count == 0U)
2286 {
2287 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2288 break;
2289 }
2290 count--;
2291 } while (hspi->State != HAL_SPI_STATE_ABORT);
2292 /* Reset Timeout Counter */
2293 count = resetcount;
2294 }
2295
2296 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
2297 {
2298 hspi->RxISR = SPI_AbortRx_ISR;
2299 /* Wait HAL_SPI_STATE_ABORT state */
2300 do
2301 {
2302 if (count == 0U)
2303 {
2304 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2305 break;
2306 }
2307 count--;
2308 } while (hspi->State != HAL_SPI_STATE_ABORT);
2309 /* Reset Timeout Counter */
2310 count = resetcount;
2311 }
2312
2313 /* Disable the SPI DMA Tx request if enabled */
2314 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2315 {
2316 /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
2317 if (hspi->hdmatx != NULL)
2318 {
2319 /* Set the SPI DMA Abort callback :
2320 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2321 hspi->hdmatx->XferAbortCallback = NULL;
2322
2323 /* Abort DMA Tx Handle linked to SPI Peripheral */
2324 if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
2325 {
2326 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2327 }
2328
2329 /* Disable Tx DMA Request */
2330 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
2331
2332 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2333 {
2334 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2335 }
2336
2337 /* Disable SPI Peripheral */
2338 __HAL_SPI_DISABLE(hspi);
2339
2340 /* Empty the FRLVL fifo */
2341 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2342 {
2343 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2344 }
2345 }
2346 }
2347
2348 /* Disable the SPI DMA Rx request if enabled */
2349 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2350 {
2351 /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
2352 if (hspi->hdmarx != NULL)
2353 {
2354 /* Set the SPI DMA Abort callback :
2355 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2356 hspi->hdmarx->XferAbortCallback = NULL;
2357
2358 /* Abort DMA Rx Handle linked to SPI Peripheral */
2359 if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
2360 {
2361 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2362 }
2363
2364 /* Disable peripheral */
2365 __HAL_SPI_DISABLE(hspi);
2366
2367 /* Control the BSY flag */
2368 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2369 {
2370 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2371 }
2372
2373 /* Empty the FRLVL fifo */
2374 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2375 {
2376 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2377 }
2378
2379 /* Disable Rx DMA Request */
2380 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
2381 }
2382 }
2383 /* Reset Tx and Rx transfer counters */
2384 hspi->RxXferCount = 0U;
2385 hspi->TxXferCount = 0U;
2386
2387 /* Check error during Abort procedure */
2388 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2389 {
2390 /* return HAL_Error in case of error during Abort procedure */
2391 errorcode = HAL_ERROR;
2392 }
2393 else
2394 {
2395 /* Reset errorCode */
2396 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2397 }
2398
2399 /* Clear the Error flags in the SR register */
2400 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2401 __HAL_SPI_CLEAR_FREFLAG(hspi);
2402
2403 /* Restore hspi->state to ready */
2404 hspi->State = HAL_SPI_STATE_READY;
2405
2406 return errorcode;
2407 }
2408
2409 /**
2410 * @brief Abort ongoing transfer (Interrupt mode).
2411 * @param hspi SPI handle.
2412 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2413 * started in Interrupt or DMA mode.
2414 * This procedure performs following operations :
2415 * - Disable SPI Interrupts (depending of transfer direction)
2416 * - Disable the DMA transfer in the peripheral register (if enabled)
2417 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
2418 * - Set handle State to READY
2419 * - At abort completion, call user abort complete callback
2420 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
2421 * considered as completed only when user abort complete callback is executed (not when exiting function).
2422 * @retval HAL status
2423 */
HAL_SPI_Abort_IT(SPI_HandleTypeDef * hspi)2424 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
2425 {
2426 HAL_StatusTypeDef errorcode;
2427 uint32_t abortcplt ;
2428 __IO uint32_t count;
2429 __IO uint32_t resetcount;
2430
2431 /* Initialized local variable */
2432 errorcode = HAL_OK;
2433 abortcplt = 1U;
2434 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2435 count = resetcount;
2436
2437 /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
2438 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
2439
2440 /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
2441 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
2442 {
2443 hspi->TxISR = SPI_AbortTx_ISR;
2444 /* Wait HAL_SPI_STATE_ABORT state */
2445 do
2446 {
2447 if (count == 0U)
2448 {
2449 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2450 break;
2451 }
2452 count--;
2453 } while (hspi->State != HAL_SPI_STATE_ABORT);
2454 /* Reset Timeout Counter */
2455 count = resetcount;
2456 }
2457
2458 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
2459 {
2460 hspi->RxISR = SPI_AbortRx_ISR;
2461 /* Wait HAL_SPI_STATE_ABORT state */
2462 do
2463 {
2464 if (count == 0U)
2465 {
2466 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2467 break;
2468 }
2469 count--;
2470 } while (hspi->State != HAL_SPI_STATE_ABORT);
2471 /* Reset Timeout Counter */
2472 count = resetcount;
2473 }
2474
2475 /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
2476 before any call to DMA Abort functions */
2477 /* DMA Tx Handle is valid */
2478 if (hspi->hdmatx != NULL)
2479 {
2480 /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
2481 Otherwise, set it to NULL */
2482 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2483 {
2484 hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
2485 }
2486 else
2487 {
2488 hspi->hdmatx->XferAbortCallback = NULL;
2489 }
2490 }
2491 /* DMA Rx Handle is valid */
2492 if (hspi->hdmarx != NULL)
2493 {
2494 /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
2495 Otherwise, set it to NULL */
2496 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2497 {
2498 hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
2499 }
2500 else
2501 {
2502 hspi->hdmarx->XferAbortCallback = NULL;
2503 }
2504 }
2505
2506 /* Disable the SPI DMA Tx request if enabled */
2507 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2508 {
2509 /* Abort the SPI DMA Tx Stream/Channel */
2510 if (hspi->hdmatx != NULL)
2511 {
2512 /* Abort DMA Tx Handle linked to SPI Peripheral */
2513 if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
2514 {
2515 hspi->hdmatx->XferAbortCallback = NULL;
2516 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2517 }
2518 else
2519 {
2520 abortcplt = 0U;
2521 }
2522 }
2523 }
2524 /* Disable the SPI DMA Rx request if enabled */
2525 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2526 {
2527 /* Abort the SPI DMA Rx Stream/Channel */
2528 if (hspi->hdmarx != NULL)
2529 {
2530 /* Abort DMA Rx Handle linked to SPI Peripheral */
2531 if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
2532 {
2533 hspi->hdmarx->XferAbortCallback = NULL;
2534 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2535 }
2536 else
2537 {
2538 abortcplt = 0U;
2539 }
2540 }
2541 }
2542
2543 if (abortcplt == 1U)
2544 {
2545 /* Reset Tx and Rx transfer counters */
2546 hspi->RxXferCount = 0U;
2547 hspi->TxXferCount = 0U;
2548
2549 /* Check error during Abort procedure */
2550 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2551 {
2552 /* return HAL_Error in case of error during Abort procedure */
2553 errorcode = HAL_ERROR;
2554 }
2555 else
2556 {
2557 /* Reset errorCode */
2558 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2559 }
2560
2561 /* Clear the Error flags in the SR register */
2562 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2563 __HAL_SPI_CLEAR_FREFLAG(hspi);
2564
2565 /* Restore hspi->State to Ready */
2566 hspi->State = HAL_SPI_STATE_READY;
2567
2568 /* As no DMA to be aborted, call directly user Abort complete callback */
2569 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2570 hspi->AbortCpltCallback(hspi);
2571 #else
2572 HAL_SPI_AbortCpltCallback(hspi);
2573 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2574 }
2575
2576 return errorcode;
2577 }
2578
2579 /**
2580 * @brief Pause the DMA Transfer.
2581 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2582 * the configuration information for the specified SPI module.
2583 * @retval HAL status
2584 */
HAL_SPI_DMAPause(SPI_HandleTypeDef * hspi)2585 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
2586 {
2587 /* Process Locked */
2588 __HAL_LOCK(hspi);
2589
2590 /* Disable the SPI DMA Tx & Rx requests */
2591 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2592
2593 /* Process Unlocked */
2594 __HAL_UNLOCK(hspi);
2595
2596 return HAL_OK;
2597 }
2598
2599 /**
2600 * @brief Resume the DMA Transfer.
2601 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2602 * the configuration information for the specified SPI module.
2603 * @retval HAL status
2604 */
HAL_SPI_DMAResume(SPI_HandleTypeDef * hspi)2605 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
2606 {
2607 /* Process Locked */
2608 __HAL_LOCK(hspi);
2609
2610 /* Enable the SPI DMA Tx & Rx requests */
2611 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2612
2613 /* Process Unlocked */
2614 __HAL_UNLOCK(hspi);
2615
2616 return HAL_OK;
2617 }
2618
2619 /**
2620 * @brief Stop the DMA Transfer.
2621 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2622 * the configuration information for the specified SPI module.
2623 * @retval HAL status
2624 */
HAL_SPI_DMAStop(SPI_HandleTypeDef * hspi)2625 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
2626 {
2627 HAL_StatusTypeDef errorcode = HAL_OK;
2628 /* The Lock is not implemented on this API to allow the user application
2629 to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
2630 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
2631 and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
2632 */
2633
2634 /* Abort the SPI DMA tx Stream/Channel */
2635 if (hspi->hdmatx != NULL)
2636 {
2637 if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
2638 {
2639 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2640 errorcode = HAL_ERROR;
2641 }
2642 }
2643 /* Abort the SPI DMA rx Stream/Channel */
2644 if (hspi->hdmarx != NULL)
2645 {
2646 if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
2647 {
2648 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2649 errorcode = HAL_ERROR;
2650 }
2651 }
2652
2653 /* Disable the SPI DMA Tx & Rx requests */
2654 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2655 hspi->State = HAL_SPI_STATE_READY;
2656 return errorcode;
2657 }
2658
2659 /**
2660 * @brief Handle SPI interrupt request.
2661 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2662 * the configuration information for the specified SPI module.
2663 * @retval None
2664 */
HAL_SPI_IRQHandler(SPI_HandleTypeDef * hspi)2665 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
2666 {
2667 uint32_t itsource = hspi->Instance->CR2;
2668 uint32_t itflag = hspi->Instance->SR;
2669
2670 /* SPI in mode Receiver ----------------------------------------------------*/
2671 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
2672 (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
2673 {
2674 hspi->RxISR(hspi);
2675 return;
2676 }
2677
2678 /* SPI in mode Transmitter -------------------------------------------------*/
2679 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
2680 {
2681 hspi->TxISR(hspi);
2682 return;
2683 }
2684
2685 /* SPI in Error Treatment --------------------------------------------------*/
2686 if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
2687 || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
2688 {
2689 /* SPI Overrun error interrupt occurred ----------------------------------*/
2690 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
2691 {
2692 if (hspi->State != HAL_SPI_STATE_BUSY_TX)
2693 {
2694 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
2695 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2696 }
2697 else
2698 {
2699 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2700 return;
2701 }
2702 }
2703
2704 /* SPI Mode Fault error interrupt occurred -------------------------------*/
2705 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
2706 {
2707 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
2708 __HAL_SPI_CLEAR_MODFFLAG(hspi);
2709 }
2710
2711 /* SPI Frame error interrupt occurred ------------------------------------*/
2712 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
2713 {
2714 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
2715 __HAL_SPI_CLEAR_FREFLAG(hspi);
2716 }
2717
2718 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2719 {
2720 /* Disable all interrupts */
2721 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
2722
2723 hspi->State = HAL_SPI_STATE_READY;
2724 /* Disable the SPI DMA requests if enabled */
2725 if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
2726 {
2727 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
2728
2729 /* Abort the SPI DMA Rx channel */
2730 if (hspi->hdmarx != NULL)
2731 {
2732 /* Set the SPI DMA Abort callback :
2733 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2734 hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
2735 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
2736 {
2737 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2738 }
2739 }
2740 /* Abort the SPI DMA Tx channel */
2741 if (hspi->hdmatx != NULL)
2742 {
2743 /* Set the SPI DMA Abort callback :
2744 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2745 hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
2746 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
2747 {
2748 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2749 }
2750 }
2751 }
2752 else
2753 {
2754 /* Call user error callback */
2755 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2756 hspi->ErrorCallback(hspi);
2757 #else
2758 HAL_SPI_ErrorCallback(hspi);
2759 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2760 }
2761 }
2762 return;
2763 }
2764 }
2765
2766 /**
2767 * @brief Tx Transfer completed callback.
2768 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2769 * the configuration information for SPI module.
2770 * @retval None
2771 */
HAL_SPI_TxCpltCallback(SPI_HandleTypeDef * hspi)2772 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
2773 {
2774 /* Prevent unused argument(s) compilation warning */
2775 UNUSED(hspi);
2776
2777 /* NOTE : This function should not be modified, when the callback is needed,
2778 the HAL_SPI_TxCpltCallback should be implemented in the user file
2779 */
2780 }
2781
2782 /**
2783 * @brief Rx Transfer completed callback.
2784 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2785 * the configuration information for SPI module.
2786 * @retval None
2787 */
HAL_SPI_RxCpltCallback(SPI_HandleTypeDef * hspi)2788 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
2789 {
2790 /* Prevent unused argument(s) compilation warning */
2791 UNUSED(hspi);
2792
2793 /* NOTE : This function should not be modified, when the callback is needed,
2794 the HAL_SPI_RxCpltCallback should be implemented in the user file
2795 */
2796 }
2797
2798 /**
2799 * @brief Tx and Rx Transfer completed callback.
2800 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2801 * the configuration information for SPI module.
2802 * @retval None
2803 */
HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef * hspi)2804 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
2805 {
2806 /* Prevent unused argument(s) compilation warning */
2807 UNUSED(hspi);
2808
2809 /* NOTE : This function should not be modified, when the callback is needed,
2810 the HAL_SPI_TxRxCpltCallback should be implemented in the user file
2811 */
2812 }
2813
2814 /**
2815 * @brief Tx Half Transfer completed callback.
2816 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2817 * the configuration information for SPI module.
2818 * @retval None
2819 */
HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef * hspi)2820 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2821 {
2822 /* Prevent unused argument(s) compilation warning */
2823 UNUSED(hspi);
2824
2825 /* NOTE : This function should not be modified, when the callback is needed,
2826 the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
2827 */
2828 }
2829
2830 /**
2831 * @brief Rx Half Transfer completed callback.
2832 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2833 * the configuration information for SPI module.
2834 * @retval None
2835 */
HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef * hspi)2836 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2837 {
2838 /* Prevent unused argument(s) compilation warning */
2839 UNUSED(hspi);
2840
2841 /* NOTE : This function should not be modified, when the callback is needed,
2842 the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
2843 */
2844 }
2845
2846 /**
2847 * @brief Tx and Rx Half Transfer callback.
2848 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2849 * the configuration information for SPI module.
2850 * @retval None
2851 */
HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef * hspi)2852 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2853 {
2854 /* Prevent unused argument(s) compilation warning */
2855 UNUSED(hspi);
2856
2857 /* NOTE : This function should not be modified, when the callback is needed,
2858 the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
2859 */
2860 }
2861
2862 /**
2863 * @brief SPI error callback.
2864 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2865 * the configuration information for SPI module.
2866 * @retval None
2867 */
HAL_SPI_ErrorCallback(SPI_HandleTypeDef * hspi)2868 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
2869 {
2870 /* Prevent unused argument(s) compilation warning */
2871 UNUSED(hspi);
2872
2873 /* NOTE : This function should not be modified, when the callback is needed,
2874 the HAL_SPI_ErrorCallback should be implemented in the user file
2875 */
2876 /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
2877 and user can use HAL_SPI_GetError() API to check the latest error occurred
2878 */
2879 }
2880
2881 /**
2882 * @brief SPI Abort Complete callback.
2883 * @param hspi SPI handle.
2884 * @retval None
2885 */
HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef * hspi)2886 __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
2887 {
2888 /* Prevent unused argument(s) compilation warning */
2889 UNUSED(hspi);
2890
2891 /* NOTE : This function should not be modified, when the callback is needed,
2892 the HAL_SPI_AbortCpltCallback can be implemented in the user file.
2893 */
2894 }
2895
2896 /**
2897 * @}
2898 */
2899
2900 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
2901 * @brief SPI control functions
2902 *
2903 @verbatim
2904 ===============================================================================
2905 ##### Peripheral State and Errors functions #####
2906 ===============================================================================
2907 [..]
2908 This subsection provides a set of functions allowing to control the SPI.
2909 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
2910 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
2911 @endverbatim
2912 * @{
2913 */
2914
2915 /**
2916 * @brief Return the SPI handle state.
2917 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2918 * the configuration information for SPI module.
2919 * @retval SPI state
2920 */
HAL_SPI_GetState(SPI_HandleTypeDef * hspi)2921 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
2922 {
2923 /* Return SPI handle state */
2924 return hspi->State;
2925 }
2926
2927 /**
2928 * @brief Return the SPI error code.
2929 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2930 * the configuration information for SPI module.
2931 * @retval SPI error code in bitmap format
2932 */
HAL_SPI_GetError(SPI_HandleTypeDef * hspi)2933 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
2934 {
2935 /* Return SPI ErrorCode */
2936 return hspi->ErrorCode;
2937 }
2938
2939 /**
2940 * @}
2941 */
2942
2943 /**
2944 * @}
2945 */
2946
2947 /** @addtogroup SPI_Private_Functions
2948 * @brief Private functions
2949 * @{
2950 */
2951
2952 /**
2953 * @brief DMA SPI transmit process complete callback.
2954 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2955 * the configuration information for the specified DMA module.
2956 * @retval None
2957 */
SPI_DMATransmitCplt(DMA_HandleTypeDef * hdma)2958 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
2959 {
2960 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2961 uint32_t tickstart;
2962
2963 /* Init tickstart for timeout management*/
2964 tickstart = HAL_GetTick();
2965
2966 /* DMA Normal Mode */
2967 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
2968 {
2969 /* Disable ERR interrupt */
2970 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
2971
2972 /* Disable Tx DMA Request */
2973 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
2974
2975 /* Check the end of the transaction */
2976 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
2977 {
2978 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
2979 }
2980
2981 /* Clear overrun flag in 2 Lines communication mode because received data is not read */
2982 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
2983 {
2984 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2985 }
2986
2987 hspi->TxXferCount = 0U;
2988 hspi->State = HAL_SPI_STATE_READY;
2989
2990 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2991 {
2992 /* Call user error callback */
2993 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2994 hspi->ErrorCallback(hspi);
2995 #else
2996 HAL_SPI_ErrorCallback(hspi);
2997 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2998 return;
2999 }
3000 }
3001 /* Call user Tx complete callback */
3002 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3003 hspi->TxCpltCallback(hspi);
3004 #else
3005 HAL_SPI_TxCpltCallback(hspi);
3006 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3007 }
3008
3009 /**
3010 * @brief DMA SPI receive process complete callback.
3011 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3012 * the configuration information for the specified DMA module.
3013 * @retval None
3014 */
SPI_DMAReceiveCplt(DMA_HandleTypeDef * hdma)3015 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
3016 {
3017 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3018 uint32_t tickstart;
3019 #if (USE_SPI_CRC != 0U)
3020 __IO uint32_t tmpreg = 0U;
3021 __IO uint8_t *ptmpreg8;
3022 __IO uint8_t tmpreg8 = 0;
3023 #endif /* USE_SPI_CRC */
3024
3025 /* Init tickstart for timeout management*/
3026 tickstart = HAL_GetTick();
3027
3028 /* DMA Normal Mode */
3029 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
3030 {
3031 /* Disable ERR interrupt */
3032 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3033
3034 #if (USE_SPI_CRC != 0U)
3035 /* CRC handling */
3036 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3037 {
3038 /* Wait until RXNE flag */
3039 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3040 {
3041 /* Error on the CRC reception */
3042 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3043 }
3044 /* Read CRC */
3045 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
3046 {
3047 /* Read 16bit CRC */
3048 tmpreg = READ_REG(hspi->Instance->DR);
3049 /* To avoid GCC warning */
3050 UNUSED(tmpreg);
3051 }
3052 else
3053 {
3054 /* Initialize the 8bit temporary pointer */
3055 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3056 /* Read 8bit CRC */
3057 tmpreg8 = *ptmpreg8;
3058 /* To avoid GCC warning */
3059 UNUSED(tmpreg8);
3060
3061 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
3062 {
3063 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3064 {
3065 /* Error on the CRC reception */
3066 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3067 }
3068 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
3069 tmpreg8 = *ptmpreg8;
3070 /* To avoid GCC warning */
3071 UNUSED(tmpreg8);
3072 }
3073 }
3074 }
3075 #endif /* USE_SPI_CRC */
3076
3077 /* Check if we are in Master RX 2 line mode */
3078 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
3079 {
3080 /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
3081 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3082 }
3083 else
3084 {
3085 /* Normal case */
3086 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
3087 }
3088
3089 /* Check the end of the transaction */
3090 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3091 {
3092 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
3093 }
3094
3095 hspi->RxXferCount = 0U;
3096 hspi->State = HAL_SPI_STATE_READY;
3097
3098 #if (USE_SPI_CRC != 0U)
3099 /* Check if CRC error occurred */
3100 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
3101 {
3102 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3103 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3104 }
3105 #endif /* USE_SPI_CRC */
3106
3107 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3108 {
3109 /* Call user error callback */
3110 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3111 hspi->ErrorCallback(hspi);
3112 #else
3113 HAL_SPI_ErrorCallback(hspi);
3114 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3115 return;
3116 }
3117 }
3118 /* Call user Rx complete callback */
3119 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3120 hspi->RxCpltCallback(hspi);
3121 #else
3122 HAL_SPI_RxCpltCallback(hspi);
3123 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3124 }
3125
3126 /**
3127 * @brief DMA SPI transmit receive process complete callback.
3128 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3129 * the configuration information for the specified DMA module.
3130 * @retval None
3131 */
SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef * hdma)3132 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
3133 {
3134 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3135 uint32_t tickstart;
3136 #if (USE_SPI_CRC != 0U)
3137 __IO uint32_t tmpreg = 0U;
3138 __IO uint8_t *ptmpreg8;
3139 __IO uint8_t tmpreg8 = 0;
3140 #endif /* USE_SPI_CRC */
3141
3142 /* Init tickstart for timeout management*/
3143 tickstart = HAL_GetTick();
3144
3145 /* DMA Normal Mode */
3146 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
3147 {
3148 /* Disable ERR interrupt */
3149 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3150
3151 #if (USE_SPI_CRC != 0U)
3152 /* CRC handling */
3153 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3154 {
3155 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
3156 {
3157 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
3158 tickstart) != HAL_OK)
3159 {
3160 /* Error on the CRC reception */
3161 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3162 }
3163 /* Initialize the 8bit temporary pointer */
3164 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3165 /* Read 8bit CRC */
3166 tmpreg8 = *ptmpreg8;
3167 /* To avoid GCC warning */
3168 UNUSED(tmpreg8);
3169 }
3170 else
3171 {
3172 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3173 {
3174 /* Error on the CRC reception */
3175 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3176 }
3177 /* Read CRC to Flush DR and RXNE flag */
3178 tmpreg = READ_REG(hspi->Instance->DR);
3179 /* To avoid GCC warning */
3180 UNUSED(tmpreg);
3181 }
3182 }
3183 #endif /* USE_SPI_CRC */
3184
3185 /* Check the end of the transaction */
3186 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3187 {
3188 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3189 }
3190
3191 /* Disable Rx/Tx DMA Request */
3192 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3193
3194 hspi->TxXferCount = 0U;
3195 hspi->RxXferCount = 0U;
3196 hspi->State = HAL_SPI_STATE_READY;
3197
3198 #if (USE_SPI_CRC != 0U)
3199 /* Check if CRC error occurred */
3200 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
3201 {
3202 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3203 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3204 }
3205 #endif /* USE_SPI_CRC */
3206
3207 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3208 {
3209 /* Call user error callback */
3210 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3211 hspi->ErrorCallback(hspi);
3212 #else
3213 HAL_SPI_ErrorCallback(hspi);
3214 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3215 return;
3216 }
3217 }
3218 /* Call user TxRx complete callback */
3219 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3220 hspi->TxRxCpltCallback(hspi);
3221 #else
3222 HAL_SPI_TxRxCpltCallback(hspi);
3223 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3224 }
3225
3226 /**
3227 * @brief DMA SPI half transmit process complete callback.
3228 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3229 * the configuration information for the specified DMA module.
3230 * @retval None
3231 */
SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef * hdma)3232 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
3233 {
3234 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3235
3236 /* Call user Tx half complete callback */
3237 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3238 hspi->TxHalfCpltCallback(hspi);
3239 #else
3240 HAL_SPI_TxHalfCpltCallback(hspi);
3241 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3242 }
3243
3244 /**
3245 * @brief DMA SPI half receive process complete callback
3246 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3247 * the configuration information for the specified DMA module.
3248 * @retval None
3249 */
SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef * hdma)3250 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
3251 {
3252 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3253
3254 /* Call user Rx half complete callback */
3255 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3256 hspi->RxHalfCpltCallback(hspi);
3257 #else
3258 HAL_SPI_RxHalfCpltCallback(hspi);
3259 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3260 }
3261
3262 /**
3263 * @brief DMA SPI half transmit receive process complete callback.
3264 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3265 * the configuration information for the specified DMA module.
3266 * @retval None
3267 */
SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef * hdma)3268 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
3269 {
3270 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3271
3272 /* Call user TxRx half complete callback */
3273 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3274 hspi->TxRxHalfCpltCallback(hspi);
3275 #else
3276 HAL_SPI_TxRxHalfCpltCallback(hspi);
3277 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3278 }
3279
3280 /**
3281 * @brief DMA SPI communication error callback.
3282 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3283 * the configuration information for the specified DMA module.
3284 * @retval None
3285 */
SPI_DMAError(DMA_HandleTypeDef * hdma)3286 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
3287 {
3288 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3289
3290 /* Stop the disable DMA transfer on SPI side */
3291 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3292
3293 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
3294 hspi->State = HAL_SPI_STATE_READY;
3295 /* Call user error callback */
3296 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3297 hspi->ErrorCallback(hspi);
3298 #else
3299 HAL_SPI_ErrorCallback(hspi);
3300 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3301 }
3302
3303 /**
3304 * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
3305 * (To be called at end of DMA Abort procedure following error occurrence).
3306 * @param hdma DMA handle.
3307 * @retval None
3308 */
SPI_DMAAbortOnError(DMA_HandleTypeDef * hdma)3309 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
3310 {
3311 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3312 hspi->RxXferCount = 0U;
3313 hspi->TxXferCount = 0U;
3314
3315 /* Call user error callback */
3316 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3317 hspi->ErrorCallback(hspi);
3318 #else
3319 HAL_SPI_ErrorCallback(hspi);
3320 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3321 }
3322
3323 /**
3324 * @brief DMA SPI Tx communication abort callback, when initiated by user
3325 * (To be called at end of DMA Tx Abort procedure following user abort request).
3326 * @note When this callback is executed, User Abort complete call back is called only if no
3327 * Abort still ongoing for Rx DMA Handle.
3328 * @param hdma DMA handle.
3329 * @retval None
3330 */
SPI_DMATxAbortCallback(DMA_HandleTypeDef * hdma)3331 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
3332 {
3333 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3334
3335 hspi->hdmatx->XferAbortCallback = NULL;
3336
3337 /* Disable Tx DMA Request */
3338 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
3339
3340 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3341 {
3342 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3343 }
3344
3345 /* Disable SPI Peripheral */
3346 __HAL_SPI_DISABLE(hspi);
3347
3348 /* Empty the FRLVL fifo */
3349 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3350 {
3351 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3352 }
3353
3354 /* Check if an Abort process is still ongoing */
3355 if (hspi->hdmarx != NULL)
3356 {
3357 if (hspi->hdmarx->XferAbortCallback != NULL)
3358 {
3359 return;
3360 }
3361 }
3362
3363 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3364 hspi->RxXferCount = 0U;
3365 hspi->TxXferCount = 0U;
3366
3367 /* Check no error during Abort procedure */
3368 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3369 {
3370 /* Reset errorCode */
3371 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3372 }
3373
3374 /* Clear the Error flags in the SR register */
3375 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3376 __HAL_SPI_CLEAR_FREFLAG(hspi);
3377
3378 /* Restore hspi->State to Ready */
3379 hspi->State = HAL_SPI_STATE_READY;
3380
3381 /* Call user Abort complete callback */
3382 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3383 hspi->AbortCpltCallback(hspi);
3384 #else
3385 HAL_SPI_AbortCpltCallback(hspi);
3386 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3387 }
3388
3389 /**
3390 * @brief DMA SPI Rx communication abort callback, when initiated by user
3391 * (To be called at end of DMA Rx Abort procedure following user abort request).
3392 * @note When this callback is executed, User Abort complete call back is called only if no
3393 * Abort still ongoing for Tx DMA Handle.
3394 * @param hdma DMA handle.
3395 * @retval None
3396 */
SPI_DMARxAbortCallback(DMA_HandleTypeDef * hdma)3397 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
3398 {
3399 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3400
3401 /* Disable SPI Peripheral */
3402 __HAL_SPI_DISABLE(hspi);
3403
3404 hspi->hdmarx->XferAbortCallback = NULL;
3405
3406 /* Disable Rx DMA Request */
3407 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
3408
3409 /* Control the BSY flag */
3410 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3411 {
3412 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3413 }
3414
3415 /* Empty the FRLVL fifo */
3416 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3417 {
3418 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3419 }
3420
3421 /* Check if an Abort process is still ongoing */
3422 if (hspi->hdmatx != NULL)
3423 {
3424 if (hspi->hdmatx->XferAbortCallback != NULL)
3425 {
3426 return;
3427 }
3428 }
3429
3430 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3431 hspi->RxXferCount = 0U;
3432 hspi->TxXferCount = 0U;
3433
3434 /* Check no error during Abort procedure */
3435 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3436 {
3437 /* Reset errorCode */
3438 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3439 }
3440
3441 /* Clear the Error flags in the SR register */
3442 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3443 __HAL_SPI_CLEAR_FREFLAG(hspi);
3444
3445 /* Restore hspi->State to Ready */
3446 hspi->State = HAL_SPI_STATE_READY;
3447
3448 /* Call user Abort complete callback */
3449 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3450 hspi->AbortCpltCallback(hspi);
3451 #else
3452 HAL_SPI_AbortCpltCallback(hspi);
3453 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3454 }
3455
3456 /**
3457 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3458 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3459 * the configuration information for SPI module.
3460 * @retval None
3461 */
SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3462 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3463 {
3464 /* Receive data in packing mode */
3465 if (hspi->RxXferCount > 1U)
3466 {
3467 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3468 hspi->pRxBuffPtr += sizeof(uint16_t);
3469 hspi->RxXferCount -= 2U;
3470 if (hspi->RxXferCount == 1U)
3471 {
3472 /* Set RX Fifo threshold according the reception data length: 8bit */
3473 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
3474 }
3475 }
3476 /* Receive data in 8 Bit mode */
3477 else
3478 {
3479 *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
3480 hspi->pRxBuffPtr++;
3481 hspi->RxXferCount--;
3482 }
3483
3484 /* Check end of the reception */
3485 if (hspi->RxXferCount == 0U)
3486 {
3487 #if (USE_SPI_CRC != 0U)
3488 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3489 {
3490 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
3491 hspi->RxISR = SPI_2linesRxISR_8BITCRC;
3492 return;
3493 }
3494 #endif /* USE_SPI_CRC */
3495
3496 /* Disable RXNE and ERR interrupt */
3497 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3498
3499 if (hspi->TxXferCount == 0U)
3500 {
3501 SPI_CloseRxTx_ISR(hspi);
3502 }
3503 }
3504 }
3505
3506 #if (USE_SPI_CRC != 0U)
3507 /**
3508 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3509 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3510 * the configuration information for SPI module.
3511 * @retval None
3512 */
SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef * hspi)3513 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3514 {
3515 __IO uint8_t *ptmpreg8;
3516 __IO uint8_t tmpreg8 = 0;
3517
3518 /* Initialize the 8bit temporary pointer */
3519 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3520 /* Read 8bit CRC to flush Data Register */
3521 tmpreg8 = *ptmpreg8;
3522 /* To avoid GCC warning */
3523 UNUSED(tmpreg8);
3524
3525 hspi->CRCSize--;
3526
3527 /* Check end of the reception */
3528 if (hspi->CRCSize == 0U)
3529 {
3530 /* Disable RXNE and ERR interrupt */
3531 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3532
3533 if (hspi->TxXferCount == 0U)
3534 {
3535 SPI_CloseRxTx_ISR(hspi);
3536 }
3537 }
3538 }
3539 #endif /* USE_SPI_CRC */
3540
3541 /**
3542 * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
3543 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3544 * the configuration information for SPI module.
3545 * @retval None
3546 */
SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3547 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3548 {
3549 /* Transmit data in packing Bit mode */
3550 if (hspi->TxXferCount >= 2U)
3551 {
3552 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3553 hspi->pTxBuffPtr += sizeof(uint16_t);
3554 hspi->TxXferCount -= 2U;
3555 }
3556 /* Transmit data in 8 Bit mode */
3557 else
3558 {
3559 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3560 hspi->pTxBuffPtr++;
3561 hspi->TxXferCount--;
3562 }
3563
3564 /* Check the end of the transmission */
3565 if (hspi->TxXferCount == 0U)
3566 {
3567 #if (USE_SPI_CRC != 0U)
3568 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3569 {
3570 /* Set CRC Next Bit to send CRC */
3571 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3572 /* Disable TXE interrupt */
3573 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3574 return;
3575 }
3576 #endif /* USE_SPI_CRC */
3577
3578 /* Disable TXE interrupt */
3579 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3580
3581 if (hspi->RxXferCount == 0U)
3582 {
3583 SPI_CloseRxTx_ISR(hspi);
3584 }
3585 }
3586 }
3587
3588 /**
3589 * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
3590 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3591 * the configuration information for SPI module.
3592 * @retval None
3593 */
SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3594 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3595 {
3596 /* Receive data in 16 Bit mode */
3597 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3598 hspi->pRxBuffPtr += sizeof(uint16_t);
3599 hspi->RxXferCount--;
3600
3601 if (hspi->RxXferCount == 0U)
3602 {
3603 #if (USE_SPI_CRC != 0U)
3604 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3605 {
3606 hspi->RxISR = SPI_2linesRxISR_16BITCRC;
3607 return;
3608 }
3609 #endif /* USE_SPI_CRC */
3610
3611 /* Disable RXNE interrupt */
3612 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3613
3614 if (hspi->TxXferCount == 0U)
3615 {
3616 SPI_CloseRxTx_ISR(hspi);
3617 }
3618 }
3619 }
3620
3621 #if (USE_SPI_CRC != 0U)
3622 /**
3623 * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
3624 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3625 * the configuration information for SPI module.
3626 * @retval None
3627 */
SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef * hspi)3628 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3629 {
3630 __IO uint32_t tmpreg = 0U;
3631
3632 /* Read 16bit CRC to flush Data Register */
3633 tmpreg = READ_REG(hspi->Instance->DR);
3634 /* To avoid GCC warning */
3635 UNUSED(tmpreg);
3636
3637 /* Disable RXNE interrupt */
3638 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3639
3640 SPI_CloseRxTx_ISR(hspi);
3641 }
3642 #endif /* USE_SPI_CRC */
3643
3644 /**
3645 * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
3646 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3647 * the configuration information for SPI module.
3648 * @retval None
3649 */
SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3650 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3651 {
3652 /* Transmit data in 16 Bit mode */
3653 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3654 hspi->pTxBuffPtr += sizeof(uint16_t);
3655 hspi->TxXferCount--;
3656
3657 /* Enable CRC Transmission */
3658 if (hspi->TxXferCount == 0U)
3659 {
3660 #if (USE_SPI_CRC != 0U)
3661 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3662 {
3663 /* Set CRC Next Bit to send CRC */
3664 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3665 /* Disable TXE interrupt */
3666 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3667 return;
3668 }
3669 #endif /* USE_SPI_CRC */
3670
3671 /* Disable TXE interrupt */
3672 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3673
3674 if (hspi->RxXferCount == 0U)
3675 {
3676 SPI_CloseRxTx_ISR(hspi);
3677 }
3678 }
3679 }
3680
3681 #if (USE_SPI_CRC != 0U)
3682 /**
3683 * @brief Manage the CRC 8-bit receive in Interrupt context.
3684 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3685 * the configuration information for SPI module.
3686 * @retval None
3687 */
SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef * hspi)3688 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3689 {
3690 __IO uint8_t *ptmpreg8;
3691 __IO uint8_t tmpreg8 = 0;
3692
3693 /* Initialize the 8bit temporary pointer */
3694 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3695 /* Read 8bit CRC to flush Data Register */
3696 tmpreg8 = *ptmpreg8;
3697 /* To avoid GCC warning */
3698 UNUSED(tmpreg8);
3699
3700 hspi->CRCSize--;
3701
3702 if (hspi->CRCSize == 0U)
3703 {
3704 SPI_CloseRx_ISR(hspi);
3705 }
3706 }
3707 #endif /* USE_SPI_CRC */
3708
3709 /**
3710 * @brief Manage the receive 8-bit in Interrupt context.
3711 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3712 * the configuration information for SPI module.
3713 * @retval None
3714 */
SPI_RxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3715 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3716 {
3717 *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
3718 hspi->pRxBuffPtr++;
3719 hspi->RxXferCount--;
3720
3721 #if (USE_SPI_CRC != 0U)
3722 /* Enable CRC Transmission */
3723 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3724 {
3725 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3726 }
3727 #endif /* USE_SPI_CRC */
3728
3729 if (hspi->RxXferCount == 0U)
3730 {
3731 #if (USE_SPI_CRC != 0U)
3732 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3733 {
3734 hspi->RxISR = SPI_RxISR_8BITCRC;
3735 return;
3736 }
3737 #endif /* USE_SPI_CRC */
3738 SPI_CloseRx_ISR(hspi);
3739 }
3740 }
3741
3742 #if (USE_SPI_CRC != 0U)
3743 /**
3744 * @brief Manage the CRC 16-bit receive in Interrupt context.
3745 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3746 * the configuration information for SPI module.
3747 * @retval None
3748 */
SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef * hspi)3749 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3750 {
3751 __IO uint32_t tmpreg = 0U;
3752
3753 /* Read 16bit CRC to flush Data Register */
3754 tmpreg = READ_REG(hspi->Instance->DR);
3755 /* To avoid GCC warning */
3756 UNUSED(tmpreg);
3757
3758 /* Disable RXNE and ERR interrupt */
3759 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3760
3761 SPI_CloseRx_ISR(hspi);
3762 }
3763 #endif /* USE_SPI_CRC */
3764
3765 /**
3766 * @brief Manage the 16-bit receive in Interrupt context.
3767 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3768 * the configuration information for SPI module.
3769 * @retval None
3770 */
SPI_RxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3771 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3772 {
3773 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3774 hspi->pRxBuffPtr += sizeof(uint16_t);
3775 hspi->RxXferCount--;
3776
3777 #if (USE_SPI_CRC != 0U)
3778 /* Enable CRC Transmission */
3779 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3780 {
3781 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3782 }
3783 #endif /* USE_SPI_CRC */
3784
3785 if (hspi->RxXferCount == 0U)
3786 {
3787 #if (USE_SPI_CRC != 0U)
3788 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3789 {
3790 hspi->RxISR = SPI_RxISR_16BITCRC;
3791 return;
3792 }
3793 #endif /* USE_SPI_CRC */
3794 SPI_CloseRx_ISR(hspi);
3795 }
3796 }
3797
3798 /**
3799 * @brief Handle the data 8-bit transmit in Interrupt mode.
3800 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3801 * the configuration information for SPI module.
3802 * @retval None
3803 */
SPI_TxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3804 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3805 {
3806 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3807 hspi->pTxBuffPtr++;
3808 hspi->TxXferCount--;
3809
3810 if (hspi->TxXferCount == 0U)
3811 {
3812 #if (USE_SPI_CRC != 0U)
3813 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3814 {
3815 /* Enable CRC Transmission */
3816 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3817 }
3818 #endif /* USE_SPI_CRC */
3819 SPI_CloseTx_ISR(hspi);
3820 }
3821 }
3822
3823 /**
3824 * @brief Handle the data 16-bit transmit in Interrupt mode.
3825 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3826 * the configuration information for SPI module.
3827 * @retval None
3828 */
SPI_TxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3829 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3830 {
3831 /* Transmit data in 16 Bit mode */
3832 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3833 hspi->pTxBuffPtr += sizeof(uint16_t);
3834 hspi->TxXferCount--;
3835
3836 if (hspi->TxXferCount == 0U)
3837 {
3838 #if (USE_SPI_CRC != 0U)
3839 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3840 {
3841 /* Enable CRC Transmission */
3842 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3843 }
3844 #endif /* USE_SPI_CRC */
3845 SPI_CloseTx_ISR(hspi);
3846 }
3847 }
3848
3849 /**
3850 * @brief Handle SPI Communication Timeout.
3851 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3852 * the configuration information for SPI module.
3853 * @param Flag SPI flag to check
3854 * @param State flag state to check
3855 * @param Timeout Timeout duration
3856 * @param Tickstart tick start value
3857 * @retval HAL status
3858 */
SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef * hspi,uint32_t Flag,FlagStatus State,uint32_t Timeout,uint32_t Tickstart)3859 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
3860 uint32_t Timeout, uint32_t Tickstart)
3861 {
3862 __IO uint32_t count;
3863 uint32_t tmp_timeout;
3864 uint32_t tmp_tickstart;
3865
3866 /* Adjust Timeout value in case of end of transfer */
3867 tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
3868 tmp_tickstart = HAL_GetTick();
3869
3870 /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
3871 count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
3872
3873 while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
3874 {
3875 if (Timeout != HAL_MAX_DELAY)
3876 {
3877 if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
3878 {
3879 /* Disable the SPI and reset the CRC: the CRC value should be cleared
3880 on both master and slave sides in order to resynchronize the master
3881 and slave for their respective CRC calculation */
3882
3883 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
3884 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
3885
3886 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3887 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3888 {
3889 /* Disable SPI peripheral */
3890 __HAL_SPI_DISABLE(hspi);
3891 }
3892
3893 /* Reset CRC Calculation */
3894 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3895 {
3896 SPI_RESET_CRC(hspi);
3897 }
3898
3899 hspi->State = HAL_SPI_STATE_READY;
3900
3901 /* Process Unlocked */
3902 __HAL_UNLOCK(hspi);
3903
3904 return HAL_TIMEOUT;
3905 }
3906 /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
3907 if (count == 0U)
3908 {
3909 tmp_timeout = 0U;
3910 }
3911 count--;
3912 }
3913 }
3914
3915 return HAL_OK;
3916 }
3917
3918 /**
3919 * @brief Handle SPI FIFO Communication Timeout.
3920 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3921 * the configuration information for SPI module.
3922 * @param Fifo Fifo to check
3923 * @param State Fifo state to check
3924 * @param Timeout Timeout duration
3925 * @param Tickstart tick start value
3926 * @retval HAL status
3927 */
SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef * hspi,uint32_t Fifo,uint32_t State,uint32_t Timeout,uint32_t Tickstart)3928 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
3929 uint32_t Timeout, uint32_t Tickstart)
3930 {
3931 __IO uint32_t count;
3932 uint32_t tmp_timeout;
3933 uint32_t tmp_tickstart;
3934 __IO uint8_t *ptmpreg8;
3935 __IO uint8_t tmpreg8 = 0;
3936
3937 /* Adjust Timeout value in case of end of transfer */
3938 tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
3939 tmp_tickstart = HAL_GetTick();
3940
3941 /* Initialize the 8bit temporary pointer */
3942 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3943
3944 /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
3945 count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U);
3946
3947 while ((hspi->Instance->SR & Fifo) != State)
3948 {
3949 if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
3950 {
3951 /* Flush Data Register by a blank read */
3952 tmpreg8 = *ptmpreg8;
3953 /* To avoid GCC warning */
3954 UNUSED(tmpreg8);
3955 }
3956
3957 if (Timeout != HAL_MAX_DELAY)
3958 {
3959 if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
3960 {
3961 /* Disable the SPI and reset the CRC: the CRC value should be cleared
3962 on both master and slave sides in order to resynchronize the master
3963 and slave for their respective CRC calculation */
3964
3965 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
3966 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
3967
3968 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3969 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3970 {
3971 /* Disable SPI peripheral */
3972 __HAL_SPI_DISABLE(hspi);
3973 }
3974
3975 /* Reset CRC Calculation */
3976 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3977 {
3978 SPI_RESET_CRC(hspi);
3979 }
3980
3981 hspi->State = HAL_SPI_STATE_READY;
3982
3983 /* Process Unlocked */
3984 __HAL_UNLOCK(hspi);
3985
3986 return HAL_TIMEOUT;
3987 }
3988 /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
3989 if (count == 0U)
3990 {
3991 tmp_timeout = 0U;
3992 }
3993 count--;
3994 }
3995 }
3996
3997 return HAL_OK;
3998 }
3999
4000 /**
4001 * @brief Handle the check of the RX transaction complete.
4002 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4003 * the configuration information for SPI module.
4004 * @param Timeout Timeout duration
4005 * @param Tickstart tick start value
4006 * @retval HAL status
4007 */
SPI_EndRxTransaction(SPI_HandleTypeDef * hspi,uint32_t Timeout,uint32_t Tickstart)4008 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
4009 {
4010 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
4011 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
4012 {
4013 /* Disable SPI peripheral */
4014 __HAL_SPI_DISABLE(hspi);
4015 }
4016
4017 /* Control the BSY flag */
4018 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
4019 {
4020 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4021 return HAL_TIMEOUT;
4022 }
4023
4024 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
4025 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
4026 {
4027 /* Empty the FRLVL fifo */
4028 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
4029 {
4030 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4031 return HAL_TIMEOUT;
4032 }
4033 }
4034 return HAL_OK;
4035 }
4036
4037 /**
4038 * @brief Handle the check of the RXTX or TX transaction complete.
4039 * @param hspi SPI handle
4040 * @param Timeout Timeout duration
4041 * @param Tickstart tick start value
4042 * @retval HAL status
4043 */
SPI_EndRxTxTransaction(SPI_HandleTypeDef * hspi,uint32_t Timeout,uint32_t Tickstart)4044 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
4045 {
4046 /* Control if the TX fifo is empty */
4047 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
4048 {
4049 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4050 return HAL_TIMEOUT;
4051 }
4052
4053 /* Control the BSY flag */
4054 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
4055 {
4056 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4057 return HAL_TIMEOUT;
4058 }
4059
4060 /* Control if the RX fifo is empty */
4061 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
4062 {
4063 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4064 return HAL_TIMEOUT;
4065 }
4066
4067 return HAL_OK;
4068 }
4069
4070 /**
4071 * @brief Handle the end of the RXTX transaction.
4072 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4073 * the configuration information for SPI module.
4074 * @retval None
4075 */
SPI_CloseRxTx_ISR(SPI_HandleTypeDef * hspi)4076 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
4077 {
4078 uint32_t tickstart;
4079
4080 /* Init tickstart for timeout management */
4081 tickstart = HAL_GetTick();
4082
4083 /* Disable ERR interrupt */
4084 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
4085
4086 /* Check the end of the transaction */
4087 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
4088 {
4089 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4090 }
4091
4092 #if (USE_SPI_CRC != 0U)
4093 /* Check if CRC error occurred */
4094 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
4095 {
4096 hspi->State = HAL_SPI_STATE_READY;
4097 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
4098 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
4099 /* Call user error callback */
4100 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4101 hspi->ErrorCallback(hspi);
4102 #else
4103 HAL_SPI_ErrorCallback(hspi);
4104 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4105 }
4106 else
4107 {
4108 #endif /* USE_SPI_CRC */
4109 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
4110 {
4111 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
4112 {
4113 hspi->State = HAL_SPI_STATE_READY;
4114 /* Call user Rx complete callback */
4115 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4116 hspi->RxCpltCallback(hspi);
4117 #else
4118 HAL_SPI_RxCpltCallback(hspi);
4119 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4120 }
4121 else
4122 {
4123 hspi->State = HAL_SPI_STATE_READY;
4124 /* Call user TxRx complete callback */
4125 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4126 hspi->TxRxCpltCallback(hspi);
4127 #else
4128 HAL_SPI_TxRxCpltCallback(hspi);
4129 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4130 }
4131 }
4132 else
4133 {
4134 hspi->State = HAL_SPI_STATE_READY;
4135 /* Call user error callback */
4136 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4137 hspi->ErrorCallback(hspi);
4138 #else
4139 HAL_SPI_ErrorCallback(hspi);
4140 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4141 }
4142 #if (USE_SPI_CRC != 0U)
4143 }
4144 #endif /* USE_SPI_CRC */
4145 }
4146
4147 /**
4148 * @brief Handle the end of the RX transaction.
4149 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4150 * the configuration information for SPI module.
4151 * @retval None
4152 */
SPI_CloseRx_ISR(SPI_HandleTypeDef * hspi)4153 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
4154 {
4155 /* Disable RXNE and ERR interrupt */
4156 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
4157
4158 /* Check the end of the transaction */
4159 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4160 {
4161 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4162 }
4163 hspi->State = HAL_SPI_STATE_READY;
4164
4165 #if (USE_SPI_CRC != 0U)
4166 /* Check if CRC error occurred */
4167 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
4168 {
4169 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
4170 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
4171 /* Call user error callback */
4172 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4173 hspi->ErrorCallback(hspi);
4174 #else
4175 HAL_SPI_ErrorCallback(hspi);
4176 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4177 }
4178 else
4179 {
4180 #endif /* USE_SPI_CRC */
4181 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
4182 {
4183 /* Call user Rx complete callback */
4184 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4185 hspi->RxCpltCallback(hspi);
4186 #else
4187 HAL_SPI_RxCpltCallback(hspi);
4188 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4189 }
4190 else
4191 {
4192 /* Call user error callback */
4193 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4194 hspi->ErrorCallback(hspi);
4195 #else
4196 HAL_SPI_ErrorCallback(hspi);
4197 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4198 }
4199 #if (USE_SPI_CRC != 0U)
4200 }
4201 #endif /* USE_SPI_CRC */
4202 }
4203
4204 /**
4205 * @brief Handle the end of the TX transaction.
4206 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4207 * the configuration information for SPI module.
4208 * @retval None
4209 */
SPI_CloseTx_ISR(SPI_HandleTypeDef * hspi)4210 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
4211 {
4212 uint32_t tickstart;
4213
4214 /* Init tickstart for timeout management*/
4215 tickstart = HAL_GetTick();
4216
4217 /* Disable TXE and ERR interrupt */
4218 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
4219
4220 /* Check the end of the transaction */
4221 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
4222 {
4223 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4224 }
4225
4226 /* Clear overrun flag in 2 Lines communication mode because received is not read */
4227 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
4228 {
4229 __HAL_SPI_CLEAR_OVRFLAG(hspi);
4230 }
4231
4232 hspi->State = HAL_SPI_STATE_READY;
4233 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
4234 {
4235 /* Call user error callback */
4236 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4237 hspi->ErrorCallback(hspi);
4238 #else
4239 HAL_SPI_ErrorCallback(hspi);
4240 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4241 }
4242 else
4243 {
4244 /* Call user Rx complete callback */
4245 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4246 hspi->TxCpltCallback(hspi);
4247 #else
4248 HAL_SPI_TxCpltCallback(hspi);
4249 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4250 }
4251 }
4252
4253 /**
4254 * @brief Handle abort a Rx transaction.
4255 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4256 * the configuration information for SPI module.
4257 * @retval None
4258 */
SPI_AbortRx_ISR(SPI_HandleTypeDef * hspi)4259 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
4260 {
4261 __IO uint32_t count;
4262
4263 /* Disable SPI Peripheral */
4264 __HAL_SPI_DISABLE(hspi);
4265
4266 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
4267
4268 /* Disable RXNEIE interrupt */
4269 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
4270
4271 /* Check RXNEIE is disabled */
4272 do
4273 {
4274 if (count == 0U)
4275 {
4276 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4277 break;
4278 }
4279 count--;
4280 } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
4281
4282 /* Control the BSY flag */
4283 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4284 {
4285 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4286 }
4287
4288 /* Empty the FRLVL fifo */
4289 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4290 {
4291 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4292 }
4293
4294 hspi->State = HAL_SPI_STATE_ABORT;
4295 }
4296
4297 /**
4298 * @brief Handle abort a Tx or Rx/Tx transaction.
4299 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4300 * the configuration information for SPI module.
4301 * @retval None
4302 */
SPI_AbortTx_ISR(SPI_HandleTypeDef * hspi)4303 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
4304 {
4305 __IO uint32_t count;
4306
4307 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
4308
4309 /* Disable TXEIE interrupt */
4310 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
4311
4312 /* Check TXEIE is disabled */
4313 do
4314 {
4315 if (count == 0U)
4316 {
4317 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4318 break;
4319 }
4320 count--;
4321 } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
4322
4323 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4324 {
4325 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4326 }
4327
4328 /* Disable SPI Peripheral */
4329 __HAL_SPI_DISABLE(hspi);
4330
4331 /* Empty the FRLVL fifo */
4332 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4333 {
4334 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4335 }
4336
4337 /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */
4338 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
4339 {
4340 /* Disable RXNEIE interrupt */
4341 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
4342
4343 /* Check RXNEIE is disabled */
4344 do
4345 {
4346 if (count == 0U)
4347 {
4348 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4349 break;
4350 }
4351 count--;
4352 } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
4353
4354 /* Control the BSY flag */
4355 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4356 {
4357 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4358 }
4359
4360 /* Empty the FRLVL fifo */
4361 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4362 {
4363 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4364 }
4365 }
4366 hspi->State = HAL_SPI_STATE_ABORT;
4367 }
4368
4369 /**
4370 * @}
4371 */
4372
4373 #endif /* HAL_SPI_MODULE_ENABLED */
4374
4375 /**
4376 * @}
4377 */
4378
4379 /**
4380 * @}
4381 */
4382
4383
