1 /**
2 ******************************************************************************
3 * @file stm32g0xx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2018 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32G0xx_LL_PWR_H
21 #define STM32G0xx_LL_PWR_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32g0xx.h"
29
30 /** @addtogroup STM32G0xx_LL_Driver
31 * @{
32 */
33
34 #if defined(PWR)
35
36 /** @defgroup PWR_LL PWR
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44
45 /* Private macros ------------------------------------------------------------*/
46
47 /* Exported types ------------------------------------------------------------*/
48 /* Exported constants --------------------------------------------------------*/
49 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
50 * @{
51 */
52
53 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
54 * @brief Flags defines which can be used with LL_PWR_WriteReg function
55 * @{
56 */
57 #define LL_PWR_SCR_CSBF PWR_SCR_CSBF
58 #define LL_PWR_SCR_CWUF PWR_SCR_CWUF
59 #define LL_PWR_SCR_CWUF6 PWR_SCR_CWUF6
60 #define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5
61 #define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4
62 #if defined(PWR_CR3_EWUP3)
63 #define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3
64 #endif /* PWR_CR3_EWUP3 */
65 #define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2
66 #define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1
67 /**
68 * @}
69 */
70
71 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
72 * @brief Flags defines which can be used with LL_PWR_ReadReg function
73 * @{
74 */
75 #define LL_PWR_SR1_WUFI PWR_SR1_WUFI
76 #define LL_PWR_SR1_SBF PWR_SR1_SBF
77 #define LL_PWR_SR1_WUF6 PWR_SR1_WUF6
78 #define LL_PWR_SR1_WUF5 PWR_SR1_WUF5
79 #define LL_PWR_SR1_WUF4 PWR_SR1_WUF4
80 #if defined(PWR_CR3_EWUP3)
81 #define LL_PWR_SR1_WUF3 PWR_SR1_WUF3
82 #endif /* PWR_CR3_EWUP3 */
83 #define LL_PWR_SR1_WUF2 PWR_SR1_WUF2
84 #define LL_PWR_SR1_WUF1 PWR_SR1_WUF1
85 #if defined(PWR_SR2_PVDO)
86 #define LL_PWR_SR2_PVDO PWR_SR2_PVDO
87 #endif /* PWR_SR2_PVDO */
88 #define LL_PWR_SR2_VOSF PWR_SR2_VOSF
89 #define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF
90 #define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS
91 /**
92 * @}
93 */
94
95 /** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE
96 * @{
97 */
98 #define LL_PWR_REGU_VOLTAGE_SCALE1 PWR_CR1_VOS_0
99 #define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_CR1_VOS_1
100 /**
101 * @}
102 */
103
104 /** @defgroup PWR_LL_EC_MODE_PWR MODE PWR
105 * @{
106 */
107 #define LL_PWR_MODE_STOP0 (0x00000000UL)
108 #define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_0)
109 #define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_1|PWR_CR1_LPMS_0)
110 #if defined (PWR_CR1_LPMS_2)
111 #define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_2)
112 #endif /* PWR_CR1_LPMS_2 */
113 /**
114 * @}
115 */
116
117 #if defined(PWR_CR2_PVDE)
118 /** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL
119 * @{
120 */
121 #define LL_PWR_PVDLLEVEL_0 0x000000000u /* VPVD0 > 2.05 V */
122 #define LL_PWR_PVDLLEVEL_1 (PWR_CR2_PVDFT_0) /* VPVD0 > 2.2 V */
123 #define LL_PWR_PVDLLEVEL_2 (PWR_CR2_PVDFT_1) /* VPVD1 > 2.36 V */
124 #define LL_PWR_PVDLLEVEL_3 (PWR_CR2_PVDFT_1 | PWR_CR2_PVDFT_0) /* VPVD2 > 2.52 V */
125 #define LL_PWR_PVDLLEVEL_4 (PWR_CR2_PVDFT_2) /* VPVD3 > 2.64 V */
126 #define LL_PWR_PVDLLEVEL_5 (PWR_CR2_PVDFT_2 | PWR_CR2_PVDFT_0) /* VPVD4 > 2.81 V */
127 #define LL_PWR_PVDLLEVEL_6 (PWR_CR2_PVDFT_2 | PWR_CR2_PVDFT_1) /* VPVD5 > 2.91 V */
128
129 #define LL_PWR_PVDHLEVEL_0 0x00000000u /* VPDD0 > 2.15 V */
130 #define LL_PWR_PVDHLEVEL_1 (PWR_CR2_PVDRT_0) /* VPVD1 > 2.3 V */
131 #define LL_PWR_PVDHLEVEL_2 (PWR_CR2_PVDRT_1) /* VPVD1 > 2.46 V */
132 #define LL_PWR_PVDHLEVEL_3 (PWR_CR2_PVDRT_1 | PWR_CR2_PVDRT_0) /* VPVD2 > 2.62 V */
133 #define LL_PWR_PVDHLEVEL_4 (PWR_CR2_PVDRT_2) /* VPVD3 > 2.74 V */
134 #define LL_PWR_PVDHLEVEL_5 (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_0) /* VPVD4 > 2.91 V */
135 #define LL_PWR_PVDHLEVEL_6 (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_1) /* VPVD5 > 3.01 V */
136 #define LL_PWR_PVDHLEVEL_7 (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_1 | PWR_CR2_PVDRT_0) /* External input analog voltage (Compare internally to VREFINT) */
137 /**
138 * @}
139 */
140 #endif /* PWR_CR2_PVDE */
141
142 #if defined(PWR_PVM_SUPPORT)
143 /** @defgroup PWR_LL_EC_PVM_IP PVM_IP
144 * @{
145 */
146 #define LL_PWR_PVM_USB PWR_CR2_PVMEN_USB /*!< Peripheral Voltage Monitoring enable for USB peripheral: Enable to keep the USB peripheral voltage monitoring under control (power domain Vddio2) */
147 /**
148 * @}
149 */
150 #endif /* PWR_PVM_SUPPORT */
151
152 /** @defgroup PWR_LL_EC_WAKEUP WAKEUP
153 * @{
154 */
155 #define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)
156 #define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)
157 #if defined(PWR_CR3_EWUP3)
158 #define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)
159 #endif /* PWR_CR3_EWUP3 */
160 #define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4)
161 #if defined(PWR_CR3_EWUP5)
162 #define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5)
163 #endif /* PWR_CR3_EWUP5 */
164 #define LL_PWR_WAKEUP_PIN6 (PWR_CR3_EWUP6)
165 /**
166 * @}
167 */
168
169 /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR
170 * @{
171 */
172 #define LL_PWR_BATTCHARG_RESISTOR_5K 0x000000000u
173 #define LL_PWR_BATTCHARG_RESISTOR_1_5K (PWR_CR4_VBRS)
174 /**
175 * @}
176 */
177
178 /** @defgroup PWR_LL_EC_GPIO GPIO
179 * @{
180 */
181 #define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
182 #define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
183 #define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
184 #define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
185 #if defined(GPIOE)
186 #define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))
187 #endif /* GPIOE */
188 #define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF)))
189 /**
190 * @}
191 */
192
193 /** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT
194 * @{
195 */
196 #define LL_PWR_GPIO_BIT_0 0x00000001u
197 #define LL_PWR_GPIO_BIT_1 0x00000002u
198 #define LL_PWR_GPIO_BIT_2 0x00000004u
199 #define LL_PWR_GPIO_BIT_3 0x00000008u
200 #define LL_PWR_GPIO_BIT_4 0x00000010u
201 #define LL_PWR_GPIO_BIT_5 0x00000020u
202 #define LL_PWR_GPIO_BIT_6 0x00000040u
203 #define LL_PWR_GPIO_BIT_7 0x00000080u
204 #define LL_PWR_GPIO_BIT_8 0x00000100u
205 #define LL_PWR_GPIO_BIT_9 0x00000200u
206 #define LL_PWR_GPIO_BIT_10 0x00000400u
207 #define LL_PWR_GPIO_BIT_11 0x00000800u
208 #define LL_PWR_GPIO_BIT_12 0x00001000u
209 #define LL_PWR_GPIO_BIT_13 0x00002000u
210 #define LL_PWR_GPIO_BIT_14 0x00004000u
211 #define LL_PWR_GPIO_BIT_15 0x00008000u
212 /**
213 * @}
214 */
215
216 /**
217 * @}
218 */
219
220 /* Exported macro ------------------------------------------------------------*/
221 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
222 * @{
223 */
224
225 /** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros
226 * @{
227 */
228
229 /**
230 * @brief Write a value in PWR register
231 * @param __REG__ Register to be written
232 * @param __VALUE__ Value to be written in the register
233 * @retval None
234 */
235 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
236
237 /**
238 * @brief Read a value in PWR register
239 * @param __REG__ Register to be read
240 * @retval Register value
241 */
242 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
243 /**
244 * @}
245 */
246
247 /**
248 * @}
249 */
250
251
252 /* Exported functions --------------------------------------------------------*/
253 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
254 * @{
255 */
256
257 /** @defgroup PWR_LL_EF_Configuration Configuration
258 * @{
259 */
260 /**
261 * @brief Set the main internal regulator output voltage
262 * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling
263 * @param VoltageScaling This parameter can be one of the following values:
264 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
265 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
266 * @retval None
267 */
LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)268 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
269 {
270 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
271 }
272
273 /**
274 * @brief Get the main internal regulator output voltage
275 * @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling
276 * @retval Returned value can be one of the following values:
277 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
278 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
279 */
LL_PWR_GetRegulVoltageScaling(void)280 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
281 {
282 return (READ_BIT(PWR->CR1, PWR_CR1_VOS));
283 }
284
285 /**
286 * @brief Switch the regulator from main mode to low-power mode
287 * @rmtoll CR1 LPR LL_PWR_EnableLowPowerRunMode
288 * @retval None
289 */
LL_PWR_EnableLowPowerRunMode(void)290 __STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void)
291 {
292 SET_BIT(PWR->CR1, PWR_CR1_LPR);
293 }
294
295 /**
296 * @brief Switch the regulator from low-power mode to main mode
297 * @rmtoll CR1 LPR LL_PWR_DisableLowPowerRunMode
298 * @retval None
299 */
LL_PWR_DisableLowPowerRunMode(void)300 __STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void)
301 {
302 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
303 }
304
305 /**
306 * @brief Check if the regulator is in low-power mode
307 * @rmtoll CR1 LPR LL_PWR_IsEnabledLowPowerRunMode
308 * @retval State of bit (1 or 0).
309 */
LL_PWR_IsEnabledLowPowerRunMode(void)310 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
311 {
312 return ((READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)) ? 1UL : 0UL);
313 }
314
315 /**
316 * @brief Switch from run main mode to run low-power mode.
317 * @rmtoll CR1 LPR LL_PWR_EnterLowPowerRunMode
318 * @retval None
319 */
LL_PWR_EnterLowPowerRunMode(void)320 __STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)
321 {
322 LL_PWR_EnableLowPowerRunMode();
323 }
324
325 /**
326 * @brief Switch from run main mode to low-power mode.
327 * @rmtoll CR1 LPR LL_PWR_ExitLowPowerRunMode
328 * @retval None
329 */
LL_PWR_ExitLowPowerRunMode(void)330 __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)
331 {
332 LL_PWR_DisableLowPowerRunMode();
333 }
334
335 /**
336 * @brief Enable access to the backup domain
337 * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess
338 * @retval None
339 */
LL_PWR_EnableBkUpAccess(void)340 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
341 {
342 SET_BIT(PWR->CR1, PWR_CR1_DBP);
343 }
344
345 /**
346 * @brief Disable access to the backup domain
347 * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess
348 * @retval None
349 */
LL_PWR_DisableBkUpAccess(void)350 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
351 {
352 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
353 }
354
355 /**
356 * @brief Check if the backup domain is enabled
357 * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess
358 * @retval State of bit (1 or 0).
359 */
LL_PWR_IsEnabledBkUpAccess(void)360 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
361 {
362 return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL);
363 }
364
365 /**
366 * @brief Enable Flash Power-down mode during low power sleep mode
367 * @rmtoll CR1 CFIPD_SLP LL_PWR_EnableFlashPowerDownInLPSleep
368 * @retval None
369 */
LL_PWR_EnableFlashPowerDownInLPSleep(void)370 __STATIC_INLINE void LL_PWR_EnableFlashPowerDownInLPSleep(void)
371 {
372 SET_BIT(PWR->CR1, PWR_CR1_FPD_LPSLP);
373 }
374
375 /**
376 * @brief Disable Flash Power-down mode during Low power sleep mode
377 * @rmtoll CR1 CFIPD_SLP LL_PWR_DisableFlashPowerDownInLPSleep
378 * @retval None
379 */
LL_PWR_DisableFlashPowerDownInLPSleep(void)380 __STATIC_INLINE void LL_PWR_DisableFlashPowerDownInLPSleep(void)
381 {
382 CLEAR_BIT(PWR->CR1, PWR_CR1_FPD_LPSLP);
383 }
384
385 /**
386 * @brief Check if flash power-down mode during low power sleep mode domain is enabled
387 * @rmtoll CR1 CFIPD_SLP LL_PWR_IsEnableFlashPowerDownInLPSleep
388 * @retval State of bit (1 or 0).
389 */
LL_PWR_IsEnableFlashPowerDownInLPSleep(void)390 __STATIC_INLINE uint32_t LL_PWR_IsEnableFlashPowerDownInLPSleep(void)
391 {
392 return ((READ_BIT(PWR->CR1, PWR_CR1_FPD_LPSLP) == (PWR_CR1_FPD_LPSLP)) ? 1UL : 0UL);
393 }
394
395 /**
396 * @brief Enable Flash Power-down mode during low power run mode
397 * @rmtoll CR1 CFIPD_RUN LL_PWR_EnableFlashPowerDownInLPRun
398 * @retval None
399 */
LL_PWR_EnableFlashPowerDownInLPRun(void)400 __STATIC_INLINE void LL_PWR_EnableFlashPowerDownInLPRun(void)
401 {
402 SET_BIT(PWR->CR1, PWR_CR1_FPD_LPRUN);
403 }
404
405 /**
406 * @brief Disable Flash Power-down mode during Low power run mode
407 * @rmtoll CR1 CFIPD_RUN LL_PWR_DisableFlashPowerDownInLPRun
408 * @retval None
409 */
LL_PWR_DisableFlashPowerDownInLPRun(void)410 __STATIC_INLINE void LL_PWR_DisableFlashPowerDownInLPRun(void)
411 {
412 CLEAR_BIT(PWR->CR1, PWR_CR1_FPD_LPRUN);
413 }
414
415 /**
416 * @brief Check if flash power-down mode during low power run mode domain is enabled
417 * @rmtoll CR1 CFIPD_RUN LL_PWR_IsEnableFlashPowerDownInLPRun
418 * @retval State of bit (1 or 0).
419 */
LL_PWR_IsEnableFlashPowerDownInLPRun(void)420 __STATIC_INLINE uint32_t LL_PWR_IsEnableFlashPowerDownInLPRun(void)
421 {
422 return ((READ_BIT(PWR->CR1, PWR_CR1_FPD_LPRUN) == (PWR_CR1_FPD_LPRUN)) ? 1UL : 0UL);
423 }
424
425 /**
426 * @brief Enable Flash Power-down mode during stop mode
427 * @rmtoll CR1 CFIPD_STOP LL_PWR_EnableFlashPowerDownInStop
428 * @retval None
429 */
LL_PWR_EnableFlashPowerDownInStop(void)430 __STATIC_INLINE void LL_PWR_EnableFlashPowerDownInStop(void)
431 {
432 SET_BIT(PWR->CR1, PWR_CR1_FPD_STOP);
433 }
434
435 /**
436 * @brief Disable Flash Power-down mode during stop mode
437 * @rmtoll CR1 CFIPD_STOP LL_PWR_DisableFlashPowerDownInStop
438 * @retval None
439 */
LL_PWR_DisableFlashPowerDownInStop(void)440 __STATIC_INLINE void LL_PWR_DisableFlashPowerDownInStop(void)
441 {
442 CLEAR_BIT(PWR->CR1, PWR_CR1_FPD_STOP);
443 }
444
445 /**
446 * @brief Check if flash power-down mode during stop mode domain is enabled
447 * @rmtoll CR1 CFIPD_STOP LL_PWR_IsEnableFlashPowerDownInStop
448 * @retval State of bit (1 or 0).
449 */
LL_PWR_IsEnableFlashPowerDownInStop(void)450 __STATIC_INLINE uint32_t LL_PWR_IsEnableFlashPowerDownInStop(void)
451 {
452 return ((READ_BIT(PWR->CR1, PWR_CR1_FPD_STOP) == (PWR_CR1_FPD_STOP)) ? 1UL : 0UL);
453 }
454
455 #if defined(STM32G0C1xx) || defined(STM32G0B1xx)
456 /**
457 * @brief Enable VDDIO2 supply
458 * @rmtoll CR2 IOSV LL_PWR_EnableVddIO2
459 * @retval None
460 */
LL_PWR_EnableVddIO2(void)461 __STATIC_INLINE void LL_PWR_EnableVddIO2(void)
462 {
463 SET_BIT(PWR->CR2, PWR_CR2_IOSV);
464 }
465
466 /**
467 * @brief Disable VDDIO2 supply
468 * @rmtoll CR2 IOSV LL_PWR_DisableVddIO2
469 * @retval None
470 */
LL_PWR_DisableVddIO2(void)471 __STATIC_INLINE void LL_PWR_DisableVddIO2(void)
472 {
473 CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
474 }
475
476 /**
477 * @brief Check if VDDIO2 supply is enabled
478 * @rmtoll CR2 IOSV LL_PWR_IsEnabledVddIO2
479 * @retval State of bit (1 or 0).
480 */
LL_PWR_IsEnabledVddIO2(void)481 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void)
482 {
483 return ((READ_BIT(PWR->CR2, PWR_CR2_IOSV) == (PWR_CR2_IOSV)) ? 1UL : 0UL);
484 }
485
486 /**
487 * @brief Enable VDDUSB supply
488 * @rmtoll CR2 USV LL_PWR_EnableVddUSB
489 * @retval None
490 */
LL_PWR_EnableVddUSB(void)491 __STATIC_INLINE void LL_PWR_EnableVddUSB(void)
492 {
493 SET_BIT(PWR->CR2, PWR_CR2_USV);
494 }
495
496 /**
497 * @brief Disable VDDUSB supply
498 * @rmtoll CR2 USV LL_PWR_DisableVddUSB
499 * @retval None
500 */
LL_PWR_DisableVddUSB(void)501 __STATIC_INLINE void LL_PWR_DisableVddUSB(void)
502 {
503 CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
504 }
505
506 /**
507 * @brief Check if VDDUSB supply is enabled
508 * @rmtoll CR2 USV LL_PWR_IsEnabledVddUSB
509 * @retval State of bit (1 or 0).
510 */
LL_PWR_IsEnabledVddUSB(void)511 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void)
512 {
513 return ((READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)) ? 1UL : 0UL);
514 }
515 #endif /* STM32G0C1xx || STM32G0B1xx */
516
517 #if defined (PWR_PVM_SUPPORT)
518 /**
519 * @brief Enable the Power Voltage Monitoring on a peripheral
520 * @rmtoll CR2 PVMUSB LL_PWR_EnablePVM
521 * @param PeriphVoltage This parameter can be one of the following values:
522 * @arg @ref LL_PWR_PVM_USB (*)
523 *
524 * (*) value not defined in all devices
525 * @retval None
526 */
LL_PWR_EnablePVM(uint32_t PeriphVoltage)527 __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage)
528 {
529 SET_BIT(PWR->CR2, PeriphVoltage);
530 }
531
532 /**
533 * @brief Disable the Power Voltage Monitoring on a peripheral
534 * @rmtoll CR2 PVMUSB LL_PWR_DisablePVM
535 * @param PeriphVoltage This parameter can be one of the following values:
536 * @arg @ref LL_PWR_PVM_USB (*)
537 *
538 * (*) value not defined in all devices
539 * @retval None
540 */
LL_PWR_DisablePVM(uint32_t PeriphVoltage)541 __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage)
542 {
543 CLEAR_BIT(PWR->CR2, PeriphVoltage);
544 }
545
546 /**
547 * @brief Check if Power Voltage Monitoring is enabled on a peripheral
548 * @rmtoll CR2 PVMUSB LL_PWR_IsEnabledPVM
549 * @param PeriphVoltage This parameter can be one of the following values:
550 * @arg @ref LL_PWR_PVM_USB (*)
551 *
552 * (*) value not defined in all devices
553 * @retval State of bit (1 or 0).
554 */
LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)555 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)
556 {
557 return ((READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)) ? 1UL : 0UL);
558 }
559 #endif /* PWR_PVM_SUPPORT */
560
561 /**
562 * @brief Set Low-Power mode
563 * @rmtoll CR1 LPMS LL_PWR_SetPowerMode
564 * @param LowPowerMode This parameter can be one of the following values:
565 * @arg @ref LL_PWR_MODE_STOP0
566 * @arg @ref LL_PWR_MODE_STOP1
567 * @arg @ref LL_PWR_MODE_STANDBY
568 * @arg @ref LL_PWR_MODE_SHUTDOWN
569 * @retval None
570 */
LL_PWR_SetPowerMode(uint32_t LowPowerMode)571 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
572 {
573 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);
574 }
575
576 /**
577 * @brief Get Low-Power mode
578 * @rmtoll CR1 LPMS LL_PWR_GetPowerMode
579 * @retval Returned value can be one of the following values:
580 * @arg @ref LL_PWR_MODE_STOP0
581 * @arg @ref LL_PWR_MODE_STOP1
582 * @arg @ref LL_PWR_MODE_STANDBY
583 * @arg @ref LL_PWR_MODE_SHUTDOWN
584 */
LL_PWR_GetPowerMode(void)585 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
586 {
587 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS));
588 }
589
590 #if defined (PWR_CR2_PVDE)
591 /**
592 * @brief Configure the high voltage threshold detected by the Power Voltage Detector
593 * @rmtoll CR2 PLS LL_PWR_SetPVDHighLevel
594 * @param PVDHighLevel This parameter can be one of the following values:
595 * @arg @ref LL_PWR_PVDHLEVEL_0
596 * @arg @ref LL_PWR_PVDHLEVEL_1
597 * @arg @ref LL_PWR_PVDHLEVEL_2
598 * @arg @ref LL_PWR_PVDHLEVEL_3
599 * @arg @ref LL_PWR_PVDHLEVEL_4
600 * @arg @ref LL_PWR_PVDHLEVEL_5
601 * @arg @ref LL_PWR_PVDHLEVEL_6
602 * @arg @ref LL_PWR_PVDHLEVEL_7
603 * @retval None
604 */
LL_PWR_SetPVDHighLevel(uint32_t PVDHighLevel)605 __STATIC_INLINE void LL_PWR_SetPVDHighLevel(uint32_t PVDHighLevel)
606 {
607 MODIFY_REG(PWR->CR2, PWR_CR2_PVDRT, PVDHighLevel);
608 }
609
610 /**
611 * @brief Get the voltage threshold detection
612 * @rmtoll CR2 PLS LL_PWR_GetPVDHighLevel
613 * @retval Returned value can be one of the following values:
614 * @arg @ref LL_PWR_PVDHLEVEL_0
615 * @arg @ref LL_PWR_PVDHLEVEL_1
616 * @arg @ref LL_PWR_PVDHLEVEL_2
617 * @arg @ref LL_PWR_PVDHLEVEL_3
618 * @arg @ref LL_PWR_PVDHLEVEL_4
619 * @arg @ref LL_PWR_PVDHLEVEL_5
620 * @arg @ref LL_PWR_PVDHLEVEL_6
621 * @arg @ref LL_PWR_PVDHLEVEL_7
622 */
LL_PWR_GetPVDHighLevel(void)623 __STATIC_INLINE uint32_t LL_PWR_GetPVDHighLevel(void)
624 {
625 return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PVDRT));
626 }
627 /**
628 * @brief Configure the low voltage threshold detected by the Power Voltage Detector
629 * @rmtoll CR2 PLS LL_PWR_SetPVDLowLevel
630 * @param PVDLowLevel This parameter can be one of the following values:
631 * @arg @ref LL_PWR_PVDLLEVEL_0
632 * @arg @ref LL_PWR_PVDLLEVEL_1
633 * @arg @ref LL_PWR_PVDLLEVEL_2
634 * @arg @ref LL_PWR_PVDLLEVEL_3
635 * @arg @ref LL_PWR_PVDLLEVEL_4
636 * @arg @ref LL_PWR_PVDLLEVEL_5
637 * @arg @ref LL_PWR_PVDLLEVEL_6
638 * @retval None
639 */
LL_PWR_SetPVDLowLevel(uint32_t PVDLowLevel)640 __STATIC_INLINE void LL_PWR_SetPVDLowLevel(uint32_t PVDLowLevel)
641 {
642 MODIFY_REG(PWR->CR2, PWR_CR2_PVDFT, PVDLowLevel);
643 }
644
645 /**
646 * @brief Get the low voltage threshold detection
647 * @rmtoll CR2 PLS LL_PWR_GetPVDLowLevel
648 * @retval Returned value can be one of the following values:
649 * @arg @ref LL_PWR_PVDLLEVEL_0
650 * @arg @ref LL_PWR_PVDLLEVEL_1
651 * @arg @ref LL_PWR_PVDLLEVEL_2
652 * @arg @ref LL_PWR_PVDLLEVEL_3
653 * @arg @ref LL_PWR_PVDLLEVEL_4
654 * @arg @ref LL_PWR_PVDLLEVEL_5
655 * @arg @ref LL_PWR_PVDLLEVEL_6
656 */
LL_PWR_GetPVDLowLevel(void)657 __STATIC_INLINE uint32_t LL_PWR_GetPVDLowLevel(void)
658 {
659 return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PVDFT));
660 }
661
662 /**
663 * @brief Enable Power Voltage Detector
664 * @rmtoll CR2 PVDE LL_PWR_EnablePVD
665 * @retval None
666 */
LL_PWR_EnablePVD(void)667 __STATIC_INLINE void LL_PWR_EnablePVD(void)
668 {
669 SET_BIT(PWR->CR2, PWR_CR2_PVDE);
670 }
671
672 /**
673 * @brief Disable Power Voltage Detector
674 * @rmtoll CR2 PVDE LL_PWR_DisablePVD
675 * @retval None
676 */
LL_PWR_DisablePVD(void)677 __STATIC_INLINE void LL_PWR_DisablePVD(void)
678 {
679 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
680 }
681
682 /**
683 * @brief Check if Power Voltage Detector is enabled
684 * @rmtoll CR2 PVDE LL_PWR_IsEnabledPVD
685 * @retval State of bit (1 or 0).
686 */
LL_PWR_IsEnabledPVD(void)687 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
688 {
689 return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL);
690 }
691 #endif /* PWR_CR2_PVDE */
692
693 /**
694 * @brief Enable Internal Wake-up line
695 * @rmtoll CR3 EIWF LL_PWR_EnableInternWU
696 * @retval None
697 */
LL_PWR_EnableInternWU(void)698 __STATIC_INLINE void LL_PWR_EnableInternWU(void)
699 {
700 SET_BIT(PWR->CR3, PWR_CR3_EIWUL);
701 }
702
703 /**
704 * @brief Disable Internal Wake-up line
705 * @rmtoll CR3 EIWF LL_PWR_DisableInternWU
706 * @retval None
707 */
LL_PWR_DisableInternWU(void)708 __STATIC_INLINE void LL_PWR_DisableInternWU(void)
709 {
710 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL);
711 }
712
713 /**
714 * @brief Check if Internal Wake-up line is enabled
715 * @rmtoll CR3 EIWF LL_PWR_IsEnabledInternWU
716 * @retval State of bit (1 or 0).
717 */
LL_PWR_IsEnabledInternWU(void)718 __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void)
719 {
720 return ((READ_BIT(PWR->CR3, PWR_CR3_EIWUL) == (PWR_CR3_EIWUL)) ? 1UL : 0UL);
721 }
722
723 /**
724 * @brief Enable pull-up and pull-down configuration
725 * @rmtoll CR3 APC LL_PWR_EnablePUPDCfg
726 * @retval None
727 */
LL_PWR_EnablePUPDCfg(void)728 __STATIC_INLINE void LL_PWR_EnablePUPDCfg(void)
729 {
730 SET_BIT(PWR->CR3, PWR_CR3_APC);
731 }
732
733 /**
734 * @brief Disable pull-up and pull-down configuration
735 * @rmtoll CR3 APC LL_PWR_DisablePUPDCfg
736 * @retval None
737 */
LL_PWR_DisablePUPDCfg(void)738 __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void)
739 {
740 CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
741 }
742
743 /**
744 * @brief Check if pull-up and pull-down configuration is enabled
745 * @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg
746 * @retval State of bit (1 or 0).
747 */
LL_PWR_IsEnabledPUPDCfg(void)748 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void)
749 {
750 return ((READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)) ? 1UL : 0UL);
751 }
752
753 #if defined(PWR_CR3_RRS)
754 /**
755 * @brief Enable SRAM content retention in Standby mode
756 * @rmtoll CR3 RRS LL_PWR_EnableSRAMRetention
757 * @retval None
758 */
LL_PWR_EnableSRAMRetention(void)759 __STATIC_INLINE void LL_PWR_EnableSRAMRetention(void)
760 {
761 SET_BIT(PWR->CR3, PWR_CR3_RRS);
762 }
763
764 /**
765 * @brief Disable SRAM content retention in Standby mode
766 * @rmtoll CR3 RRS LL_PWR_DisableSRAMRetention
767 * @retval None
768 */
LL_PWR_DisableSRAMRetention(void)769 __STATIC_INLINE void LL_PWR_DisableSRAMRetention(void)
770 {
771 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
772 }
773
774 /**
775 * @brief Check if SRAM content retention in Standby mode is enabled
776 * @rmtoll CR3 RRS LL_PWR_IsEnabledSRAMRetention
777 * @retval State of bit (1 or 0).
778 */
LL_PWR_IsEnabledSRAMRetention(void)779 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAMRetention(void)
780 {
781 return ((READ_BIT(PWR->CR3, PWR_CR3_RRS) == (PWR_CR3_RRS)) ? 1UL : 0UL);
782 }
783 #endif /* PWR_CR3_RRS */
784
785 #if defined(PWR_CR3_ENB_ULP)
786 /**
787 * @brief Enable sampling mode of LPMMU reset block
788 * @rmtoll CR3 ENB_ULP LL_PWR_EnableLPMUResetSamplingMode
789 * @retval None
790 */
LL_PWR_EnableLPMUResetSamplingMode(void)791 __STATIC_INLINE void LL_PWR_EnableLPMUResetSamplingMode(void)
792 {
793 SET_BIT(PWR->CR3, PWR_CR3_ENB_ULP);
794 }
795
796 /**
797 * @brief Disable sampling mode of LPMMU reset block
798 * @rmtoll CR3 ENB_ULP LL_PWR_DisableLPMUResetSamplingMode
799 * @retval None
800 */
LL_PWR_DisableLPMUResetSamplingMode(void)801 __STATIC_INLINE void LL_PWR_DisableLPMUResetSamplingMode(void)
802 {
803 CLEAR_BIT(PWR->CR3, PWR_CR3_ENB_ULP);
804 }
805
806 /**
807 * @brief Check if sampling mode of LPMMU reset block
808 * @rmtoll CR3 ENB_ULP LL_PWR_IsEnableLPMUResetSamplingMode
809 * @retval State of bit (1 or 0).
810 */
LL_PWR_IsEnableLPMUResetSamplingMode(void)811 __STATIC_INLINE uint32_t LL_PWR_IsEnableLPMUResetSamplingMode(void)
812 {
813 return ((READ_BIT(PWR->CR3, PWR_CR3_ENB_ULP) == (PWR_CR3_ENB_ULP)) ? 1UL : 0UL);
814 }
815 #endif /* PWR_CR3_ENB_ULP */
816
817 /**
818 * @brief Enable the WakeUp PINx functionality
819 * @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n
820 * CR3 EWUP2 LL_PWR_EnableWakeUpPin\n
821 * CR3 EWUP3 LL_PWR_EnableWakeUpPin\n
822 * CR3 EWUP4 LL_PWR_EnableWakeUpPin\n
823 * CR3 EWUP5 LL_PWR_EnableWakeUpPin\n
824 * CR3 EWUP6 LL_PWR_EnableWakeUpPin
825 * @param WakeUpPin This parameter can be one of the following values:
826 * @arg @ref LL_PWR_WAKEUP_PIN1
827 * @arg @ref LL_PWR_WAKEUP_PIN2
828 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
829 * @arg @ref LL_PWR_WAKEUP_PIN4
830 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
831 * @arg @ref LL_PWR_WAKEUP_PIN6
832 * @retval None
833 * @note (*) availability depends on devices
834 */
LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)835 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
836 {
837 SET_BIT(PWR->CR3, WakeUpPin);
838 }
839
840 /**
841 * @brief Disable the WakeUp PINx functionality
842 * @rmtoll CR3 EWUP1 LL_PWR_DisableWakeUpPin\n
843 * CR3 EWUP2 LL_PWR_DisableWakeUpPin\n
844 * CR3 EWUP3 LL_PWR_DisableWakeUpPin\n
845 * CR3 EWUP4 LL_PWR_DisableWakeUpPin\n
846 * CR3 EWUP5 LL_PWR_DisableWakeUpPin\n
847 * CR3 EWUP6 LL_PWR_DisableWakeUpPin
848 * @param WakeUpPin This parameter can be one of the following values:
849 * @arg @ref LL_PWR_WAKEUP_PIN1
850 * @arg @ref LL_PWR_WAKEUP_PIN2
851 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
852 * @arg @ref LL_PWR_WAKEUP_PIN4
853 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
854 * @arg @ref LL_PWR_WAKEUP_PIN6
855 * @retval None
856 * @note (*) availability depends on devices
857 */
LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)858 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
859 {
860 CLEAR_BIT(PWR->CR3, WakeUpPin);
861 }
862
863 /**
864 * @brief Check if the WakeUp PINx functionality is enabled
865 * @rmtoll CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin\n
866 * CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin\n
867 * CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin\n
868 * CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin\n
869 * CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin\n
870 * CR3 EWUP6 LL_PWR_IsEnabledWakeUpPin
871 * @param WakeUpPin This parameter can be one of the following values:
872 * @arg @ref LL_PWR_WAKEUP_PIN1
873 * @arg @ref LL_PWR_WAKEUP_PIN2
874 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
875 * @arg @ref LL_PWR_WAKEUP_PIN4
876 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
877 * @arg @ref LL_PWR_WAKEUP_PIN6
878 * @retval State of bit (1 or 0).
879 * @note (*) availability depends on devices
880 */
LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)881 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
882 {
883 return ((READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
884 }
885
886 /**
887 * @brief Set the resistor impedance
888 * @rmtoll CR4 VBRS LL_PWR_SetBattChargResistor
889 * @param Resistor This parameter can be one of the following values:
890 * @arg @ref LL_PWR_BATTCHARG_RESISTOR_5K
891 * @arg @ref LL_PWR_BATTCHARG_RESISTOR_1_5K
892 * @retval None
893 */
LL_PWR_SetBattChargResistor(uint32_t Resistor)894 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
895 {
896 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor);
897 }
898
899 /**
900 * @brief Get the resistor impedance
901 * @rmtoll CR4 VBRS LL_PWR_GetBattChargResistor
902 * @retval Returned value can be one of the following values:
903 * @arg @ref LL_PWR_BATTCHARG_RESISTOR_5K
904 * @arg @ref LL_PWR_BATTCHARG_RESISTOR_1_5K
905 */
LL_PWR_GetBattChargResistor(void)906 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
907 {
908 return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS));
909 }
910
911 /**
912 * @brief Enable battery charging
913 * @rmtoll CR4 VBE LL_PWR_EnableBatteryCharging
914 * @retval None
915 */
LL_PWR_EnableBatteryCharging(void)916 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
917 {
918 SET_BIT(PWR->CR4, PWR_CR4_VBE);
919 }
920
921 /**
922 * @brief Disable battery charging
923 * @rmtoll CR4 VBE LL_PWR_DisableBatteryCharging
924 * @retval None
925 */
LL_PWR_DisableBatteryCharging(void)926 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
927 {
928 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
929 }
930
931 /**
932 * @brief Check if battery charging is enabled
933 * @rmtoll CR4 VBE LL_PWR_IsEnabledBatteryCharging
934 * @retval State of bit (1 or 0).
935 */
LL_PWR_IsEnabledBatteryCharging(void)936 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
937 {
938 return ((READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)) ? 1UL : 0UL);
939 }
940
941 /**
942 * @brief Set the Wake-Up pin polarity low for the event detection
943 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow\n
944 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow\n
945 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow\n
946 * CR4 WP4 LL_PWR_SetWakeUpPinPolarityLow\n
947 * CR4 WP5 LL_PWR_SetWakeUpPinPolarityLow\n
948 * CR4 WP6 LL_PWR_SetWakeUpPinPolarityLow
949 * @param WakeUpPin This parameter can be one of the following values:
950 * @arg @ref LL_PWR_WAKEUP_PIN1
951 * @arg @ref LL_PWR_WAKEUP_PIN2
952 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
953 * @arg @ref LL_PWR_WAKEUP_PIN4
954 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
955 * @arg @ref LL_PWR_WAKEUP_PIN6
956 * @retval None
957 * @note (*) availability depends on devices
958 */
LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)959 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
960 {
961 SET_BIT(PWR->CR4, WakeUpPin);
962 }
963
964 /**
965 * @brief Set the Wake-Up pin polarity high for the event detection
966 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh\n
967 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh\n
968 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh\n
969 * CR4 WP4 LL_PWR_SetWakeUpPinPolarityHigh\n
970 * CR4 WP5 LL_PWR_SetWakeUpPinPolarityHigh\n
971 * CR4 WP6 LL_PWR_SetWakeUpPinPolarityHigh
972 * @param WakeUpPin This parameter can be one of the following values:
973 * @arg @ref LL_PWR_WAKEUP_PIN1
974 * @arg @ref LL_PWR_WAKEUP_PIN2
975 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
976 * @arg @ref LL_PWR_WAKEUP_PIN4
977 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
978 * @arg @ref LL_PWR_WAKEUP_PIN6
979 * @note (*) availability depends on devices
980 * @retval None
981 */
LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)982 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
983 {
984 CLEAR_BIT(PWR->CR4, WakeUpPin);
985 }
986
987 /**
988 * @brief Get the Wake-Up pin polarity for the event detection
989 * @rmtoll CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow\n
990 * CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow\n
991 * CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow\n
992 * CR4 WP4 LL_PWR_IsWakeUpPinPolarityLow\n
993 * CR4 WP5 LL_PWR_IsWakeUpPinPolarityLow\n
994 * CR4 WP6 LL_PWR_IsWakeUpPinPolarityLow
995 * @param WakeUpPin This parameter can be one of the following values:
996 * @arg @ref LL_PWR_WAKEUP_PIN1
997 * @arg @ref LL_PWR_WAKEUP_PIN2
998 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
999 * @arg @ref LL_PWR_WAKEUP_PIN4
1000 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1001 * @arg @ref LL_PWR_WAKEUP_PIN6
1002 * @note (*) availability depends on devices
1003 * @retval State of bit (1 or 0).
1004 */
LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)1005 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
1006 {
1007 return ((READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
1008 }
1009
1010 /**
1011 * @brief Enable GPIO pull-up state in Standby and Shutdown modes
1012 * @rmtoll PUCRA PU0-15 LL_PWR_EnableGPIOPullUp\n
1013 * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n
1014 * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n
1015 * PUCRD PU0-15 LL_PWR_EnableGPIOPullUp\n
1016 * PUCRE PU0-15 LL_PWR_EnableGPIOPullUp\n
1017 * PUCRF PU0-13 LL_PWR_EnableGPIOPullUp
1018 * @param GPIO This parameter can be one of the following values:
1019 * @arg @ref LL_PWR_GPIO_A
1020 * @arg @ref LL_PWR_GPIO_B
1021 * @arg @ref LL_PWR_GPIO_C
1022 * @arg @ref LL_PWR_GPIO_D
1023 * @arg @ref LL_PWR_GPIO_E (*)
1024 * @arg @ref LL_PWR_GPIO_F
1025 * @param GPIONumber This parameter can be one of the following values:
1026 * @arg @ref LL_PWR_GPIO_BIT_0
1027 * @arg @ref LL_PWR_GPIO_BIT_1
1028 * @arg @ref LL_PWR_GPIO_BIT_2
1029 * @arg @ref LL_PWR_GPIO_BIT_3
1030 * @arg @ref LL_PWR_GPIO_BIT_4
1031 * @arg @ref LL_PWR_GPIO_BIT_5
1032 * @arg @ref LL_PWR_GPIO_BIT_6
1033 * @arg @ref LL_PWR_GPIO_BIT_7
1034 * @arg @ref LL_PWR_GPIO_BIT_8
1035 * @arg @ref LL_PWR_GPIO_BIT_9
1036 * @arg @ref LL_PWR_GPIO_BIT_10
1037 * @arg @ref LL_PWR_GPIO_BIT_11
1038 * @arg @ref LL_PWR_GPIO_BIT_12
1039 * @arg @ref LL_PWR_GPIO_BIT_13
1040 * @arg @ref LL_PWR_GPIO_BIT_14
1041 * @arg @ref LL_PWR_GPIO_BIT_15
1042 * @retval None
1043 */
LL_PWR_EnableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1044 __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1045 {
1046 SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
1047 }
1048
1049 /**
1050 * @brief Disable GPIO pull-up state in Standby and Shutdown modes
1051 * @rmtoll PUCRA PU0-15 LL_PWR_DisableGPIOPullUp\n
1052 * PUCRB PU0-15 LL_PWR_DisableGPIOPullUp\n
1053 * PUCRC PU0-15 LL_PWR_DisableGPIOPullUp\n
1054 * PUCRD PU0-15 LL_PWR_DisableGPIOPullUp\n
1055 * PUCRE PU0-15 LL_PWR_DisableGPIOPullUp\n
1056 * PUCRF PU0-13 LL_PWR_DisableGPIOPullUp
1057 * @param GPIO This parameter can be one of the following values:
1058 * @arg @ref LL_PWR_GPIO_A
1059 * @arg @ref LL_PWR_GPIO_B
1060 * @arg @ref LL_PWR_GPIO_C
1061 * @arg @ref LL_PWR_GPIO_D
1062 * @arg @ref LL_PWR_GPIO_E (*)
1063 * @arg @ref LL_PWR_GPIO_F
1064 * @param GPIONumber This parameter can be one of the following values:
1065 * @arg @ref LL_PWR_GPIO_BIT_0
1066 * @arg @ref LL_PWR_GPIO_BIT_1
1067 * @arg @ref LL_PWR_GPIO_BIT_2
1068 * @arg @ref LL_PWR_GPIO_BIT_3
1069 * @arg @ref LL_PWR_GPIO_BIT_4
1070 * @arg @ref LL_PWR_GPIO_BIT_5
1071 * @arg @ref LL_PWR_GPIO_BIT_6
1072 * @arg @ref LL_PWR_GPIO_BIT_7
1073 * @arg @ref LL_PWR_GPIO_BIT_8
1074 * @arg @ref LL_PWR_GPIO_BIT_9
1075 * @arg @ref LL_PWR_GPIO_BIT_10
1076 * @arg @ref LL_PWR_GPIO_BIT_11
1077 * @arg @ref LL_PWR_GPIO_BIT_12
1078 * @arg @ref LL_PWR_GPIO_BIT_13
1079 * @arg @ref LL_PWR_GPIO_BIT_14
1080 * @arg @ref LL_PWR_GPIO_BIT_15
1081 * @retval None
1082 */
LL_PWR_DisableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1083 __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1084 {
1085 CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
1086 }
1087
1088 /**
1089 * @brief Check if GPIO pull-up state is enabled
1090 * @rmtoll PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1091 * PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1092 * PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1093 * PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1094 * PUCRE PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1095 * PUCRF PU0-13 LL_PWR_IsEnabledGPIOPullUp
1096 * @param GPIO This parameter can be one of the following values:
1097 * @arg @ref LL_PWR_GPIO_A
1098 * @arg @ref LL_PWR_GPIO_B
1099 * @arg @ref LL_PWR_GPIO_C
1100 * @arg @ref LL_PWR_GPIO_D
1101 * @arg @ref LL_PWR_GPIO_E (*)
1102 * @arg @ref LL_PWR_GPIO_F
1103 * @param GPIONumber This parameter can be one of the following values:
1104 * @arg @ref LL_PWR_GPIO_BIT_0
1105 * @arg @ref LL_PWR_GPIO_BIT_1
1106 * @arg @ref LL_PWR_GPIO_BIT_2
1107 * @arg @ref LL_PWR_GPIO_BIT_3
1108 * @arg @ref LL_PWR_GPIO_BIT_4
1109 * @arg @ref LL_PWR_GPIO_BIT_5
1110 * @arg @ref LL_PWR_GPIO_BIT_6
1111 * @arg @ref LL_PWR_GPIO_BIT_7
1112 * @arg @ref LL_PWR_GPIO_BIT_8
1113 * @arg @ref LL_PWR_GPIO_BIT_9
1114 * @arg @ref LL_PWR_GPIO_BIT_10
1115 * @arg @ref LL_PWR_GPIO_BIT_11
1116 * @arg @ref LL_PWR_GPIO_BIT_12
1117 * @arg @ref LL_PWR_GPIO_BIT_13
1118 * @arg @ref LL_PWR_GPIO_BIT_14
1119 * @arg @ref LL_PWR_GPIO_BIT_15
1120 * @retval State of bit (1 or 0).
1121 */
LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1122 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1123 {
1124 return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
1125 }
1126
1127 /**
1128 * @brief Enable GPIO pull-down state in Standby and Shutdown modes
1129 * @rmtoll PDCRA PD0-15 LL_PWR_EnableGPIOPullDown\n
1130 * PDCRB PD0-15 LL_PWR_EnableGPIOPullDown\n
1131 * PDCRC PD0-15 LL_PWR_EnableGPIOPullDown\n
1132 * PDCRD PD0-15 LL_PWR_EnableGPIOPullDown\n
1133 * PDCRE PD0-15 LL_PWR_EnableGPIOPullDown\n
1134 * PDCRF PD0-13 LL_PWR_EnableGPIOPullDown
1135 * @param GPIO This parameter can be one of the following values:
1136 * @arg @ref LL_PWR_GPIO_A
1137 * @arg @ref LL_PWR_GPIO_B
1138 * @arg @ref LL_PWR_GPIO_C
1139 * @arg @ref LL_PWR_GPIO_D
1140 * @arg @ref LL_PWR_GPIO_E (*)
1141 * @arg @ref LL_PWR_GPIO_F
1142 * @param GPIONumber This parameter can be one of the following values:
1143 * @arg @ref LL_PWR_GPIO_BIT_0
1144 * @arg @ref LL_PWR_GPIO_BIT_1
1145 * @arg @ref LL_PWR_GPIO_BIT_2
1146 * @arg @ref LL_PWR_GPIO_BIT_3
1147 * @arg @ref LL_PWR_GPIO_BIT_4
1148 * @arg @ref LL_PWR_GPIO_BIT_5
1149 * @arg @ref LL_PWR_GPIO_BIT_6
1150 * @arg @ref LL_PWR_GPIO_BIT_7
1151 * @arg @ref LL_PWR_GPIO_BIT_8
1152 * @arg @ref LL_PWR_GPIO_BIT_9
1153 * @arg @ref LL_PWR_GPIO_BIT_10
1154 * @arg @ref LL_PWR_GPIO_BIT_11
1155 * @arg @ref LL_PWR_GPIO_BIT_12
1156 * @arg @ref LL_PWR_GPIO_BIT_13
1157 * @arg @ref LL_PWR_GPIO_BIT_14
1158 * @arg @ref LL_PWR_GPIO_BIT_15
1159 * @retval None
1160 */
LL_PWR_EnableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1161 __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1162 {
1163 SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
1164 }
1165
1166 /**
1167 * @brief Disable GPIO pull-down state in Standby and Shutdown modes
1168 * @rmtoll PDCRA PD0-15 LL_PWR_DisableGPIOPullDown\n
1169 * PDCRB PD0-15 LL_PWR_DisableGPIOPullDown\n
1170 * PDCRC PD0-15 LL_PWR_DisableGPIOPullDown\n
1171 * PDCRD PD0-15 LL_PWR_DisableGPIOPullDown\n
1172 * PDCRE PD0-15 LL_PWR_DisableGPIOPullDown\n
1173 * PDCRF PD0-13 LL_PWR_DisableGPIOPullDown
1174 * @param GPIO This parameter can be one of the following values:
1175 * @arg @ref LL_PWR_GPIO_A
1176 * @arg @ref LL_PWR_GPIO_B
1177 * @arg @ref LL_PWR_GPIO_C
1178 * @arg @ref LL_PWR_GPIO_D
1179 * @arg @ref LL_PWR_GPIO_E (*)
1180 * @arg @ref LL_PWR_GPIO_F
1181 * @param GPIONumber This parameter can be one of the following values:
1182 * @arg @ref LL_PWR_GPIO_BIT_0
1183 * @arg @ref LL_PWR_GPIO_BIT_1
1184 * @arg @ref LL_PWR_GPIO_BIT_2
1185 * @arg @ref LL_PWR_GPIO_BIT_3
1186 * @arg @ref LL_PWR_GPIO_BIT_4
1187 * @arg @ref LL_PWR_GPIO_BIT_5
1188 * @arg @ref LL_PWR_GPIO_BIT_6
1189 * @arg @ref LL_PWR_GPIO_BIT_7
1190 * @arg @ref LL_PWR_GPIO_BIT_8
1191 * @arg @ref LL_PWR_GPIO_BIT_9
1192 * @arg @ref LL_PWR_GPIO_BIT_10
1193 * @arg @ref LL_PWR_GPIO_BIT_11
1194 * @arg @ref LL_PWR_GPIO_BIT_12
1195 * @arg @ref LL_PWR_GPIO_BIT_13
1196 * @arg @ref LL_PWR_GPIO_BIT_14
1197 * @arg @ref LL_PWR_GPIO_BIT_15
1198 * @retval None
1199 */
LL_PWR_DisableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1200 __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1201 {
1202 CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
1203 }
1204
1205 /**
1206 * @brief Check if GPIO pull-down state is enabled
1207 * @rmtoll PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1208 * PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1209 * PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1210 * PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1211 * PDCRE PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1212 * PDCRF PD0-13 LL_PWR_IsEnabledGPIOPullDown
1213 * @param GPIO This parameter can be one of the following values:
1214 * @arg @ref LL_PWR_GPIO_A
1215 * @arg @ref LL_PWR_GPIO_B
1216 * @arg @ref LL_PWR_GPIO_C
1217 * @arg @ref LL_PWR_GPIO_D
1218 * @arg @ref LL_PWR_GPIO_E (*)
1219 * @arg @ref LL_PWR_GPIO_F
1220 * @param GPIONumber This parameter can be one of the following values:
1221 * @arg @ref LL_PWR_GPIO_BIT_0
1222 * @arg @ref LL_PWR_GPIO_BIT_1
1223 * @arg @ref LL_PWR_GPIO_BIT_2
1224 * @arg @ref LL_PWR_GPIO_BIT_3
1225 * @arg @ref LL_PWR_GPIO_BIT_4
1226 * @arg @ref LL_PWR_GPIO_BIT_5
1227 * @arg @ref LL_PWR_GPIO_BIT_6
1228 * @arg @ref LL_PWR_GPIO_BIT_7
1229 * @arg @ref LL_PWR_GPIO_BIT_8
1230 * @arg @ref LL_PWR_GPIO_BIT_9
1231 * @arg @ref LL_PWR_GPIO_BIT_10
1232 * @arg @ref LL_PWR_GPIO_BIT_11
1233 * @arg @ref LL_PWR_GPIO_BIT_12
1234 * @arg @ref LL_PWR_GPIO_BIT_13
1235 * @arg @ref LL_PWR_GPIO_BIT_14
1236 * @arg @ref LL_PWR_GPIO_BIT_15
1237 * @retval State of bit (1 or 0).
1238 */
LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1239 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1240 {
1241 return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
1242 }
1243
1244 /**
1245 * @}
1246 */
1247
1248 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
1249 * @{
1250 */
1251
1252 /**
1253 * @brief Get Internal Wake-up line Flag
1254 * @rmtoll SR1 WUFI LL_PWR_IsActiveFlag_InternWU
1255 * @retval State of bit (1 or 0).
1256 */
LL_PWR_IsActiveFlag_InternWU(void)1257 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void)
1258 {
1259 return ((READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)) ? 1UL : 0UL);
1260 }
1261
1262 /**
1263 * @brief Get Stand-By Flag
1264 * @rmtoll SR1 SBF LL_PWR_IsActiveFlag_SB
1265 * @retval State of bit (1 or 0).
1266 */
LL_PWR_IsActiveFlag_SB(void)1267 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
1268 {
1269 return ((READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF)) ? 1UL : 0UL);
1270 }
1271
1272 /**
1273 * @brief Get Wake-up Flag 6
1274 * @rmtoll SR1 WUF6 LL_PWR_IsActiveFlag_WU6
1275 * @retval State of bit (1 or 0).
1276 */
LL_PWR_IsActiveFlag_WU6(void)1277 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
1278 {
1279 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF6) == (PWR_SR1_WUF6)) ? 1UL : 0UL);
1280 }
1281
1282 #if defined(PWR_CR3_EWUP5)
1283 /**
1284 * @brief Get Wake-up Flag 5
1285 * @rmtoll SR1 WUF5 LL_PWR_IsActiveFlag_WU5
1286 * @retval State of bit (1 or 0).
1287 */
LL_PWR_IsActiveFlag_WU5(void)1288 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
1289 {
1290 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)) ? 1UL : 0UL);
1291 }
1292 #endif /* PWR_CR3_EWUP5 */
1293
1294 /**
1295 * @brief Get Wake-up Flag 4
1296 * @rmtoll SR1 WUF4 LL_PWR_IsActiveFlag_WU4
1297 * @retval State of bit (1 or 0).
1298 */
LL_PWR_IsActiveFlag_WU4(void)1299 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
1300 {
1301 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)) ? 1UL : 0UL);
1302 }
1303
1304 #if defined(PWR_CR3_EWUP3)
1305 /**
1306 * @brief Get Wake-up Flag 3
1307 * @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3
1308 * @retval State of bit (1 or 0).
1309 */
LL_PWR_IsActiveFlag_WU3(void)1310 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
1311 {
1312 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL);
1313 }
1314 #endif /* PWR_CR3_EWUP3 */
1315
1316 /**
1317 * @brief Get Wake-up Flag 2
1318 * @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2
1319 * @retval State of bit (1 or 0).
1320 */
LL_PWR_IsActiveFlag_WU2(void)1321 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
1322 {
1323 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL);
1324 }
1325
1326 /**
1327 * @brief Get Wake-up Flag 1
1328 * @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1
1329 * @retval State of bit (1 or 0).
1330 */
LL_PWR_IsActiveFlag_WU1(void)1331 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
1332 {
1333 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)) ? 1UL : 0UL);
1334 }
1335
1336 /**
1337 * @brief Clear Stand-By Flag
1338 * @rmtoll SCR CSBF LL_PWR_ClearFlag_SB
1339 * @retval None
1340 */
LL_PWR_ClearFlag_SB(void)1341 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
1342 {
1343 WRITE_REG(PWR->SCR, PWR_SCR_CSBF);
1344 }
1345
1346 /**
1347 * @brief Clear Wake-up Flags
1348 * @rmtoll SCR CWUF LL_PWR_ClearFlag_WU
1349 * @retval None
1350 */
LL_PWR_ClearFlag_WU(void)1351 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
1352 {
1353 WRITE_REG(PWR->SCR, PWR_SCR_CWUF);
1354 }
1355
1356 /**
1357 * @brief Clear Wake-up Flag 6
1358 * @rmtoll SCR CWUF6 LL_PWR_ClearFlag_WU6
1359 * @retval None
1360 */
LL_PWR_ClearFlag_WU6(void)1361 __STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
1362 {
1363 WRITE_REG(PWR->SCR, PWR_SCR_CWUF6);
1364 }
1365
1366 #if defined(PWR_CR3_EWUP5)
1367 /**
1368 * @brief Clear Wake-up Flag 5
1369 * @rmtoll SCR CWUF5 LL_PWR_ClearFlag_WU5
1370 * @retval None
1371 */
LL_PWR_ClearFlag_WU5(void)1372 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
1373 {
1374 WRITE_REG(PWR->SCR, PWR_SCR_CWUF5);
1375 }
1376 #endif /* PWR_CR3_EWUP5 */
1377
1378 /**
1379 * @brief Clear Wake-up Flag 4
1380 * @rmtoll SCR CWUF4 LL_PWR_ClearFlag_WU4
1381 * @retval None
1382 */
LL_PWR_ClearFlag_WU4(void)1383 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
1384 {
1385 WRITE_REG(PWR->SCR, PWR_SCR_CWUF4);
1386 }
1387
1388 #if defined(PWR_CR3_EWUP3)
1389 /**
1390 * @brief Clear Wake-up Flag 3
1391 * @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3
1392 * @retval None
1393 */
LL_PWR_ClearFlag_WU3(void)1394 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
1395 {
1396 WRITE_REG(PWR->SCR, PWR_SCR_CWUF3);
1397 }
1398 #endif /* PWR_CR3_EWUP3 */
1399
1400 /**
1401 * @brief Clear Wake-up Flag 2
1402 * @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2
1403 * @retval None
1404 */
LL_PWR_ClearFlag_WU2(void)1405 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
1406 {
1407 WRITE_REG(PWR->SCR, PWR_SCR_CWUF2);
1408 }
1409
1410 /**
1411 * @brief Clear Wake-up Flag 1
1412 * @rmtoll SCR CWUF1 LL_PWR_ClearFlag_WU1
1413 * @retval None
1414 */
LL_PWR_ClearFlag_WU1(void)1415 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
1416 {
1417 WRITE_REG(PWR->SCR, PWR_SCR_CWUF1);
1418 }
1419
1420 #if defined (PWR_PVM_SUPPORT)
1421 /**
1422 * @brief Indicate whether VDD voltage is below or above the selected PVD
1423 * threshold
1424 * @rmtoll SR2 PVDMO_USB LL_PWR_IsActiveFlag_PVMOUSB
1425 * @retval State of bit (1 or 0).
1426 */
LL_PWR_IsActiveFlag_PVMOUSB(void)1427 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMOUSB(void)
1428 {
1429 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO_USB) == (PWR_SR2_PVMO_USB)) ? 1UL : 0UL);
1430 }
1431 #endif /* PWR_PVM_SUPPORT */
1432
1433 #if defined(PWR_SR2_PVDO)
1434 /**
1435 * @brief Indicate whether VDD voltage is below or above the selected PVD
1436 * threshold
1437 * @rmtoll SR2 PVDO LL_PWR_IsActiveFlag_PVDO
1438 * @retval State of bit (1 or 0).
1439 */
LL_PWR_IsActiveFlag_PVDO(void)1440 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
1441 {
1442 return ((READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)) ? 1UL : 0UL);
1443 }
1444 #endif /* PWR_SR2_PVDO */
1445
1446 /**
1447 * @brief Indicate whether the regulator is ready in the selected voltage
1448 * range or if its output voltage is still changing to the required
1449 * voltage level
1450 * @note: Take care, return value "0" means the regulator is ready.
1451 * Return value "1" means the output voltage range is still changing.
1452 * @rmtoll SR2 VOSF LL_PWR_IsActiveFlag_VOS
1453 * @retval State of bit (1 or 0).
1454 */
LL_PWR_IsActiveFlag_VOS(void)1455 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
1456 {
1457 return ((READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)) ? 1UL : 0UL);
1458 }
1459
1460 /**
1461 * @brief Indicate whether the regulator is ready in main mode or is in
1462 * low-power mode
1463 * @note: Take care, return value "0" means regulator is ready in main mode
1464 * Return value "1" means regulator is in low-power mode (LPR)
1465 * @rmtoll SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF
1466 * @retval State of bit (1 or 0).
1467 */
LL_PWR_IsActiveFlag_REGLPF(void)1468 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
1469 {
1470 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)) ? 1UL : 0UL);
1471 }
1472
1473 /**
1474 * @brief Indicate whether or not the low-power regulator is ready
1475 * @rmtoll SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS
1476 * @retval State of bit (1 or 0).
1477 */
LL_PWR_IsActiveFlag_REGLPS(void)1478 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void)
1479 {
1480 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)) ? 1UL : 0UL);
1481 }
1482
1483 /**
1484 * @brief Indicate whether or not the flash is ready to be accessed
1485 * @rmtoll SR2 FLASH_RDY LL_PWR_IsActiveFlag_FLASH_RDY
1486 * @retval State of bit (1 or 0).
1487 */
LL_PWR_IsActiveFlag_FLASH_RDY(void)1488 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_FLASH_RDY(void)
1489 {
1490 return ((READ_BIT(PWR->SR2, PWR_SR2_FLASH_RDY) == (PWR_SR2_FLASH_RDY)) ? 1UL : 0UL);
1491 }
1492
1493
1494 /**
1495 * @}
1496 */
1497
1498 #if defined(USE_FULL_LL_DRIVER)
1499 /** @defgroup PWR_LL_EF_Init De-initialization function
1500 * @{
1501 */
1502 ErrorStatus LL_PWR_DeInit(void);
1503 /**
1504 * @}
1505 */
1506 #endif /* USE_FULL_LL_DRIVER */
1507
1508 /**
1509 * @}
1510 */
1511
1512 /**
1513 * @}
1514 */
1515
1516 #endif /* defined(PWR) */
1517
1518 /**
1519 * @}
1520 */
1521
1522 #ifdef __cplusplus
1523 }
1524 #endif
1525
1526 #endif /* STM32G0xx_LL_PWR_H */
1527
