1 /**
2 ******************************************************************************
3 * @file stm32g0xx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2018 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32G0xx_LL_DMA_H
21 #define STM32G0xx_LL_DMA_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32g0xx.h"
29 #include "stm32g0xx_ll_dmamux.h"
30
31 /** @addtogroup STM32G0xx_LL_Driver
32 * @{
33 */
34
35 #if defined (DMA1) || defined (DMA2)
36
37 /** @defgroup DMA_LL DMA
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
44 * @{
45 */
46 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
47 static const uint8_t CHANNEL_OFFSET_TAB[] =
48 {
49 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
50 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
51 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
52 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
53 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
54 #if defined(DMA1_Channel6_BASE)
55 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
56 #endif /* DMA1_Channel6_BASE */
57 #if defined(DMA1_Channel7_BASE)
58 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE),
59 #endif /* DMA1_Channel7_BASE */
60 };
61 /**
62 * @}
63 */
64
65 /* Private constants ---------------------------------------------------------*/
66 /* Private macros ------------------------------------------------------------*/
67
68 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
69 * @{
70 */
71 /**
72 * @brief Helper macro to convert DMA Instance DMAx into DMAMUX channel
73 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
74 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
75 * @param __DMA_INSTANCE__ DMAx
76 * @retval Channel_Offset (LL_DMA_CHANNEL_7 or 0).
77 */
78 #define __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \
79 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0 : LL_DMA_CHANNEL_7)
80 /**
81 * @}
82 */
83 /* Exported types ------------------------------------------------------------*/
84 #if defined(USE_FULL_LL_DRIVER)
85 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
86 * @{
87 */
88 typedef struct
89 {
90 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
91 or as Source base address in case of memory to memory transfer direction.
92
93 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
94
95 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
96 or as Destination base address in case of memory to memory transfer direction.
97
98 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
99
100 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
101 from memory to memory or from peripheral to memory.
102 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
103
104 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
105
106 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
107 This parameter can be a value of @ref DMA_LL_EC_MODE
108 @note: The circular buffer mode cannot be used if the memory to memory
109 data transfer direction is configured on the selected Channel
110
111 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
112
113 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
114 is incremented or not.
115 This parameter can be a value of @ref DMA_LL_EC_PERIPH
116
117 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
118
119 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
120 is incremented or not.
121 This parameter can be a value of @ref DMA_LL_EC_MEMORY
122
123 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
124
125 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
126 in case of memory to memory transfer direction.
127 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
128
129 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
130
131 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
132 in case of memory to memory transfer direction.
133 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
134
135 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
136
137 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
138 The data unit is equal to the source buffer configuration set in PeripheralSize
139 or MemorySize parameters depending in the transfer direction.
140 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
141
142 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
143
144 uint32_t PeriphRequest; /*!< Specifies the peripheral request.
145 This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
146
147 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
148
149 uint32_t Priority; /*!< Specifies the channel priority level.
150 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
151
152 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
153
154 } LL_DMA_InitTypeDef;
155 /**
156 * @}
157 */
158 #endif /*USE_FULL_LL_DRIVER*/
159
160 /* Exported constants --------------------------------------------------------*/
161 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
162 * @{
163 */
164 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
165 * @brief Flags defines which can be used with LL_DMA_WriteReg function
166 * @{
167 */
168 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
169 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
170 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
171 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
172 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
173 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
174 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
175 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
176 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
177 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
178 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
179 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
180 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
181 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
182 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
183 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
184 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
185 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
186 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
187 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
188 #if defined(DMA1_Channel6)
189 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
190 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
191 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
192 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
193 #endif /* DMA1_Channel6 */
194 #if defined(DMA1_Channel7)
195 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
196 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
197 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
198 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
199 #endif /* DMA1_Channel7 */
200 /**
201 * @}
202 */
203
204 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
205 * @brief Flags defines which can be used with LL_DMA_ReadReg function
206 * @{
207 */
208 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
209 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
210 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
211 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
212 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
213 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
214 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
215 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
216 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
217 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
218 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
219 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
220 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
221 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
222 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
223 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
224 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
225 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
226 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
227 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
228 #if defined(DMA1_Channel6)
229 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
230 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
231 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
232 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
233 #endif /* DMA1_Channel6 */
234 #if defined(DMA1_Channel7)
235 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
236 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
237 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
238 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
239 #endif /* DMA1_Channel7 */
240 /**
241 * @}
242 */
243
244 /** @defgroup DMA_LL_EC_IT IT Defines
245 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
246 * @{
247 */
248 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
249 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
250 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
251 /**
252 * @}
253 */
254
255 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
256 * @{
257 */
258 #define LL_DMA_CHANNEL_1 0x00000000U /*!< DMA Channel 1 */
259 #define LL_DMA_CHANNEL_2 0x00000001U /*!< DMA Channel 2 */
260 #define LL_DMA_CHANNEL_3 0x00000002U /*!< DMA Channel 3 */
261 #define LL_DMA_CHANNEL_4 0x00000003U /*!< DMA Channel 4 */
262 #define LL_DMA_CHANNEL_5 0x00000004U /*!< DMA Channel 5 */
263 #if defined(DMA1_Channel6)
264 #define LL_DMA_CHANNEL_6 0x00000005U /*!< DMA Channel 6 */
265 #endif /* DMA1_Channel6 */
266 #if defined(DMA1_Channel7)
267 #define LL_DMA_CHANNEL_7 0x00000006U /*!< DMA Channel 7 */
268 #endif /* DMA1_Channel7 */
269 #if defined(USE_FULL_LL_DRIVER)
270 #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
271 #endif /*USE_FULL_LL_DRIVER*/
272 /**
273 * @}
274 */
275
276 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
277 * @{
278 */
279 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
280 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
281 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
282 /**
283 * @}
284 */
285
286 /** @defgroup DMA_LL_EC_MODE Transfer mode
287 * @{
288 */
289 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
290 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
291 /**
292 * @}
293 */
294
295 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
296 * @{
297 */
298 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
299 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
300 /**
301 * @}
302 */
303
304 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
305 * @{
306 */
307 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
308 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
309 /**
310 * @}
311 */
312
313 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
314 * @{
315 */
316 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
317 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
318 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
319 /**
320 * @}
321 */
322
323 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
324 * @{
325 */
326 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
327 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
328 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
329 /**
330 * @}
331 */
332
333 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
334 * @{
335 */
336 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
337 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
338 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
339 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
340 /**
341 * @}
342 */
343
344 /**
345 * @}
346 */
347
348 /* Exported macro ------------------------------------------------------------*/
349 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
350 * @{
351 */
352
353 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
354 * @{
355 */
356 /**
357 * @brief Write a value in DMA register
358 * @param __INSTANCE__ DMA Instance
359 * @param __REG__ Register to be written
360 * @param __VALUE__ Value to be written in the register
361 * @retval None
362 */
363 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
364
365 /**
366 * @brief Read a value in DMA register
367 * @param __INSTANCE__ DMA Instance
368 * @param __REG__ Register to be read
369 * @retval Register value
370 */
371 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
372 /**
373 * @}
374 */
375
376 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
377 * @{
378 */
379 /**
380 * @brief Convert DMAx_Channely into DMAx
381 * @param __CHANNEL_INSTANCE__ DMAx_Channely
382 * @retval DMAx
383 */
384 #if defined(DMA2)
385 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
386 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
387 #else /* DMA1 */
388 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
389 #endif /* DMA2 */
390
391 /**
392 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
393 * @param __CHANNEL_INSTANCE__ DMAx_Channely
394 * @retval LL_DMA_CHANNEL_y
395 */
396 #if defined(DMA2)
397 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
398 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
399 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
400 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
401 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
402 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
403 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
404 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
405 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
406 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
407 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
408 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
409 LL_DMA_CHANNEL_7)
410 #else /* DMA1 */
411 #if defined(DMA1_Channel7)
412 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
413 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
414 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
415 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
416 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
417 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
418 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
419 LL_DMA_CHANNEL_7)
420 #else
421 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
422 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
423 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
424 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
425 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
426 LL_DMA_CHANNEL_5)
427 #endif /* DMA1_Channel8 */
428 #endif /* DMA2 */
429
430 /**
431 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
432 * @param __DMA_INSTANCE__ DMAx
433 * @param __CHANNEL__ LL_DMA_CHANNEL_y
434 * @retval DMAx_Channely
435 */
436 #if defined(DMA2)
437 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
438 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
439 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
440 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
441 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
442 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
443 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
444 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
445 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
446 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
447 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
448 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
449 DMA1_Channel7)
450 #else /* DMA1 */
451 #if defined(DMA1_Channel7)
452 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
453 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
454 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
455 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
456 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
457 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
458 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
459 DMA1_Channel7)
460 #else
461 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
462 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
463 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
464 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
465 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
466 DMA1_Channel5)
467 #endif /* DMA1_Channel8 */
468 #endif /* DMA2 */
469
470 /**
471 * @}
472 */
473
474 /**
475 * @}
476 */
477
478 /* Exported functions --------------------------------------------------------*/
479 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
480 * @{
481 */
482
483 /** @defgroup DMA_LL_EF_Configuration Configuration
484 * @{
485 */
486 /**
487 * @brief Enable DMA channel.
488 * @rmtoll CCR EN LL_DMA_EnableChannel
489 * @param DMAx DMAx Instance
490 * @param Channel This parameter can be one of the following values:
491 * @arg @ref LL_DMA_CHANNEL_1
492 * @arg @ref LL_DMA_CHANNEL_2
493 * @arg @ref LL_DMA_CHANNEL_3
494 * @arg @ref LL_DMA_CHANNEL_4
495 * @arg @ref LL_DMA_CHANNEL_5
496 * @arg @ref LL_DMA_CHANNEL_6
497 * @arg @ref LL_DMA_CHANNEL_7
498 * @retval None
499 */
LL_DMA_EnableChannel(DMA_TypeDef * DMAx,uint32_t Channel)500 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
501 {
502 uint32_t dma_base_addr = (uint32_t)DMAx;
503 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN);
504 }
505
506 /**
507 * @brief Disable DMA channel.
508 * @rmtoll CCR EN LL_DMA_DisableChannel
509 * @param DMAx DMAx Instance
510 * @param Channel This parameter can be one of the following values:
511 * @arg @ref LL_DMA_CHANNEL_1
512 * @arg @ref LL_DMA_CHANNEL_2
513 * @arg @ref LL_DMA_CHANNEL_3
514 * @arg @ref LL_DMA_CHANNEL_4
515 * @arg @ref LL_DMA_CHANNEL_5
516 * @arg @ref LL_DMA_CHANNEL_6
517 * @arg @ref LL_DMA_CHANNEL_7
518 * @retval None
519 */
LL_DMA_DisableChannel(DMA_TypeDef * DMAx,uint32_t Channel)520 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
521 {
522 uint32_t dma_base_addr = (uint32_t)DMAx;
523 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN);
524 }
525
526 /**
527 * @brief Check if DMA channel is enabled or disabled.
528 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
529 * @param DMAx DMAx Instance
530 * @param Channel This parameter can be one of the following values:
531 * @arg @ref LL_DMA_CHANNEL_1
532 * @arg @ref LL_DMA_CHANNEL_2
533 * @arg @ref LL_DMA_CHANNEL_3
534 * @arg @ref LL_DMA_CHANNEL_4
535 * @arg @ref LL_DMA_CHANNEL_5
536 * @arg @ref LL_DMA_CHANNEL_6
537 * @arg @ref LL_DMA_CHANNEL_7
538 * @retval State of bit (1 or 0).
539 */
LL_DMA_IsEnabledChannel(DMA_TypeDef * DMAx,uint32_t Channel)540 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
541 {
542 uint32_t dma_base_addr = (uint32_t)DMAx;
543 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
544 DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL);
545 }
546
547 /**
548 * @brief Configure all parameters link to DMA transfer.
549 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
550 * CCR MEM2MEM LL_DMA_ConfigTransfer\n
551 * CCR CIRC LL_DMA_ConfigTransfer\n
552 * CCR PINC LL_DMA_ConfigTransfer\n
553 * CCR MINC LL_DMA_ConfigTransfer\n
554 * CCR PSIZE LL_DMA_ConfigTransfer\n
555 * CCR MSIZE LL_DMA_ConfigTransfer\n
556 * CCR PL LL_DMA_ConfigTransfer
557 * @param DMAx DMAx Instance
558 * @param Channel This parameter can be one of the following values:
559 * @arg @ref LL_DMA_CHANNEL_1
560 * @arg @ref LL_DMA_CHANNEL_2
561 * @arg @ref LL_DMA_CHANNEL_3
562 * @arg @ref LL_DMA_CHANNEL_4
563 * @arg @ref LL_DMA_CHANNEL_5
564 * @arg @ref LL_DMA_CHANNEL_6
565 * @arg @ref LL_DMA_CHANNEL_7
566 * @param Configuration This parameter must be a combination of all the following values:
567 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
568 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
569 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
570 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
571 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
572 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
573 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
574 * @retval None
575 */
LL_DMA_ConfigTransfer(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)576 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
577 {
578 uint32_t dma_base_addr = (uint32_t)DMAx;
579 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
580 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
581 Configuration);
582 }
583
584 /**
585 * @brief Set Data transfer direction (read from peripheral or from memory).
586 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
587 * CCR MEM2MEM LL_DMA_SetDataTransferDirection
588 * @param DMAx DMAx Instance
589 * @param Channel This parameter can be one of the following values:
590 * @arg @ref LL_DMA_CHANNEL_1
591 * @arg @ref LL_DMA_CHANNEL_2
592 * @arg @ref LL_DMA_CHANNEL_3
593 * @arg @ref LL_DMA_CHANNEL_4
594 * @arg @ref LL_DMA_CHANNEL_5
595 * @arg @ref LL_DMA_CHANNEL_6
596 * @arg @ref LL_DMA_CHANNEL_7
597 * @param Direction This parameter can be one of the following values:
598 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
599 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
600 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
601 * @retval None
602 */
LL_DMA_SetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Direction)603 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
604 {
605 uint32_t dma_base_addr = (uint32_t)DMAx;
606 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
607 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
608 }
609
610 /**
611 * @brief Get Data transfer direction (read from peripheral or from memory).
612 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
613 * CCR MEM2MEM LL_DMA_GetDataTransferDirection
614 * @param DMAx DMAx Instance
615 * @param Channel This parameter can be one of the following values:
616 * @arg @ref LL_DMA_CHANNEL_1
617 * @arg @ref LL_DMA_CHANNEL_2
618 * @arg @ref LL_DMA_CHANNEL_3
619 * @arg @ref LL_DMA_CHANNEL_4
620 * @arg @ref LL_DMA_CHANNEL_5
621 * @arg @ref LL_DMA_CHANNEL_6
622 * @arg @ref LL_DMA_CHANNEL_7
623 * @retval Returned value can be one of the following values:
624 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
625 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
626 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
627 */
LL_DMA_GetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel)628 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
629 {
630 uint32_t dma_base_addr = (uint32_t)DMAx;
631 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
632 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
633 }
634
635 /**
636 * @brief Set DMA mode circular or normal.
637 * @note The circular buffer mode cannot be used if the memory-to-memory
638 * data transfer is configured on the selected Channel.
639 * @rmtoll CCR CIRC LL_DMA_SetMode
640 * @param DMAx DMAx Instance
641 * @param Channel This parameter can be one of the following values:
642 * @arg @ref LL_DMA_CHANNEL_1
643 * @arg @ref LL_DMA_CHANNEL_2
644 * @arg @ref LL_DMA_CHANNEL_3
645 * @arg @ref LL_DMA_CHANNEL_4
646 * @arg @ref LL_DMA_CHANNEL_5
647 * @arg @ref LL_DMA_CHANNEL_6
648 * @arg @ref LL_DMA_CHANNEL_7
649 * @param Mode This parameter can be one of the following values:
650 * @arg @ref LL_DMA_MODE_NORMAL
651 * @arg @ref LL_DMA_MODE_CIRCULAR
652 * @retval None
653 */
LL_DMA_SetMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Mode)654 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
655 {
656 uint32_t dma_base_addr = (uint32_t)DMAx;
657 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_CIRC,
658 Mode);
659 }
660
661 /**
662 * @brief Get DMA mode circular or normal.
663 * @rmtoll CCR CIRC LL_DMA_GetMode
664 * @param DMAx DMAx Instance
665 * @param Channel This parameter can be one of the following values:
666 * @arg @ref LL_DMA_CHANNEL_1
667 * @arg @ref LL_DMA_CHANNEL_2
668 * @arg @ref LL_DMA_CHANNEL_3
669 * @arg @ref LL_DMA_CHANNEL_4
670 * @arg @ref LL_DMA_CHANNEL_5
671 * @arg @ref LL_DMA_CHANNEL_6
672 * @arg @ref LL_DMA_CHANNEL_7
673 * @retval Returned value can be one of the following values:
674 * @arg @ref LL_DMA_MODE_NORMAL
675 * @arg @ref LL_DMA_MODE_CIRCULAR
676 */
LL_DMA_GetMode(DMA_TypeDef * DMAx,uint32_t Channel)677 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
678 {
679 uint32_t dma_base_addr = (uint32_t)DMAx;
680 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
681 DMA_CCR_CIRC));
682 }
683
684 /**
685 * @brief Set Peripheral increment mode.
686 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
687 * @param DMAx DMAx Instance
688 * @param Channel This parameter can be one of the following values:
689 * @arg @ref LL_DMA_CHANNEL_1
690 * @arg @ref LL_DMA_CHANNEL_2
691 * @arg @ref LL_DMA_CHANNEL_3
692 * @arg @ref LL_DMA_CHANNEL_4
693 * @arg @ref LL_DMA_CHANNEL_5
694 * @arg @ref LL_DMA_CHANNEL_6
695 * @arg @ref LL_DMA_CHANNEL_7
696 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
697 * @arg @ref LL_DMA_PERIPH_INCREMENT
698 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
699 * @retval None
700 */
LL_DMA_SetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcIncMode)701 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
702 {
703 uint32_t dma_base_addr = (uint32_t)DMAx;
704 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PINC,
705 PeriphOrM2MSrcIncMode);
706 }
707
708 /**
709 * @brief Get Peripheral increment mode.
710 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
711 * @param DMAx DMAx Instance
712 * @param Channel This parameter can be one of the following values:
713 * @arg @ref LL_DMA_CHANNEL_1
714 * @arg @ref LL_DMA_CHANNEL_2
715 * @arg @ref LL_DMA_CHANNEL_3
716 * @arg @ref LL_DMA_CHANNEL_4
717 * @arg @ref LL_DMA_CHANNEL_5
718 * @arg @ref LL_DMA_CHANNEL_6
719 * @arg @ref LL_DMA_CHANNEL_7
720 * @retval Returned value can be one of the following values:
721 * @arg @ref LL_DMA_PERIPH_INCREMENT
722 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
723 */
LL_DMA_GetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel)724 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
725 {
726 uint32_t dma_base_addr = (uint32_t)DMAx;
727 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
728 DMA_CCR_PINC));
729 }
730
731 /**
732 * @brief Set Memory increment mode.
733 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
734 * @param DMAx DMAx Instance
735 * @param Channel This parameter can be one of the following values:
736 * @arg @ref LL_DMA_CHANNEL_1
737 * @arg @ref LL_DMA_CHANNEL_2
738 * @arg @ref LL_DMA_CHANNEL_3
739 * @arg @ref LL_DMA_CHANNEL_4
740 * @arg @ref LL_DMA_CHANNEL_5
741 * @arg @ref LL_DMA_CHANNEL_6
742 * @arg @ref LL_DMA_CHANNEL_7
743 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
744 * @arg @ref LL_DMA_MEMORY_INCREMENT
745 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
746 * @retval None
747 */
LL_DMA_SetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstIncMode)748 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
749 {
750 uint32_t dma_base_addr = (uint32_t)DMAx;
751 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MINC,
752 MemoryOrM2MDstIncMode);
753 }
754
755 /**
756 * @brief Get Memory increment mode.
757 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
758 * @param DMAx DMAx Instance
759 * @param Channel This parameter can be one of the following values:
760 * @arg @ref LL_DMA_CHANNEL_1
761 * @arg @ref LL_DMA_CHANNEL_2
762 * @arg @ref LL_DMA_CHANNEL_3
763 * @arg @ref LL_DMA_CHANNEL_4
764 * @arg @ref LL_DMA_CHANNEL_5
765 * @arg @ref LL_DMA_CHANNEL_6
766 * @arg @ref LL_DMA_CHANNEL_7
767 * @retval Returned value can be one of the following values:
768 * @arg @ref LL_DMA_MEMORY_INCREMENT
769 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
770 */
LL_DMA_GetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel)771 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
772 {
773 uint32_t dma_base_addr = (uint32_t)DMAx;
774 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
775 DMA_CCR_MINC));
776 }
777
778 /**
779 * @brief Set Peripheral size.
780 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
781 * @param DMAx DMAx Instance
782 * @param Channel This parameter can be one of the following values:
783 * @arg @ref LL_DMA_CHANNEL_1
784 * @arg @ref LL_DMA_CHANNEL_2
785 * @arg @ref LL_DMA_CHANNEL_3
786 * @arg @ref LL_DMA_CHANNEL_4
787 * @arg @ref LL_DMA_CHANNEL_5
788 * @arg @ref LL_DMA_CHANNEL_6
789 * @arg @ref LL_DMA_CHANNEL_7
790 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
791 * @arg @ref LL_DMA_PDATAALIGN_BYTE
792 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
793 * @arg @ref LL_DMA_PDATAALIGN_WORD
794 * @retval None
795 */
LL_DMA_SetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcDataSize)796 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
797 {
798 uint32_t dma_base_addr = (uint32_t)DMAx;
799 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PSIZE,
800 PeriphOrM2MSrcDataSize);
801 }
802
803 /**
804 * @brief Get Peripheral size.
805 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
806 * @param DMAx DMAx Instance
807 * @param Channel This parameter can be one of the following values:
808 * @arg @ref LL_DMA_CHANNEL_1
809 * @arg @ref LL_DMA_CHANNEL_2
810 * @arg @ref LL_DMA_CHANNEL_3
811 * @arg @ref LL_DMA_CHANNEL_4
812 * @arg @ref LL_DMA_CHANNEL_5
813 * @arg @ref LL_DMA_CHANNEL_6
814 * @arg @ref LL_DMA_CHANNEL_7
815 * @retval Returned value can be one of the following values:
816 * @arg @ref LL_DMA_PDATAALIGN_BYTE
817 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
818 * @arg @ref LL_DMA_PDATAALIGN_WORD
819 */
LL_DMA_GetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel)820 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
821 {
822 uint32_t dma_base_addr = (uint32_t)DMAx;
823 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
824 DMA_CCR_PSIZE));
825 }
826
827 /**
828 * @brief Set Memory size.
829 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
830 * @param DMAx DMAx Instance
831 * @param Channel This parameter can be one of the following values:
832 * @arg @ref LL_DMA_CHANNEL_1
833 * @arg @ref LL_DMA_CHANNEL_2
834 * @arg @ref LL_DMA_CHANNEL_3
835 * @arg @ref LL_DMA_CHANNEL_4
836 * @arg @ref LL_DMA_CHANNEL_5
837 * @arg @ref LL_DMA_CHANNEL_6
838 * @arg @ref LL_DMA_CHANNEL_7
839 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
840 * @arg @ref LL_DMA_MDATAALIGN_BYTE
841 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
842 * @arg @ref LL_DMA_MDATAALIGN_WORD
843 * @retval None
844 */
LL_DMA_SetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstDataSize)845 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
846 {
847 uint32_t dma_base_addr = (uint32_t)DMAx;
848 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MSIZE,
849 MemoryOrM2MDstDataSize);
850 }
851
852 /**
853 * @brief Get Memory size.
854 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
855 * @param DMAx DMAx Instance
856 * @param Channel This parameter can be one of the following values:
857 * @arg @ref LL_DMA_CHANNEL_1
858 * @arg @ref LL_DMA_CHANNEL_2
859 * @arg @ref LL_DMA_CHANNEL_3
860 * @arg @ref LL_DMA_CHANNEL_4
861 * @arg @ref LL_DMA_CHANNEL_5
862 * @arg @ref LL_DMA_CHANNEL_6
863 * @arg @ref LL_DMA_CHANNEL_7
864 * @retval Returned value can be one of the following values:
865 * @arg @ref LL_DMA_MDATAALIGN_BYTE
866 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
867 * @arg @ref LL_DMA_MDATAALIGN_WORD
868 */
LL_DMA_GetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel)869 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
870 {
871 uint32_t dma_base_addr = (uint32_t)DMAx;
872 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
873 DMA_CCR_MSIZE));
874 }
875
876 /**
877 * @brief Set Channel priority level.
878 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
879 * @param DMAx DMAx Instance
880 * @param Channel This parameter can be one of the following values:
881 * @arg @ref LL_DMA_CHANNEL_1
882 * @arg @ref LL_DMA_CHANNEL_2
883 * @arg @ref LL_DMA_CHANNEL_3
884 * @arg @ref LL_DMA_CHANNEL_4
885 * @arg @ref LL_DMA_CHANNEL_5
886 * @arg @ref LL_DMA_CHANNEL_6
887 * @arg @ref LL_DMA_CHANNEL_7
888 * @param Priority This parameter can be one of the following values:
889 * @arg @ref LL_DMA_PRIORITY_LOW
890 * @arg @ref LL_DMA_PRIORITY_MEDIUM
891 * @arg @ref LL_DMA_PRIORITY_HIGH
892 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
893 * @retval None
894 */
LL_DMA_SetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Priority)895 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
896 {
897 uint32_t dma_base_addr = (uint32_t)DMAx;
898 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PL,
899 Priority);
900 }
901
902 /**
903 * @brief Get Channel priority level.
904 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
905 * @param DMAx DMAx Instance
906 * @param Channel This parameter can be one of the following values:
907 * @arg @ref LL_DMA_CHANNEL_1
908 * @arg @ref LL_DMA_CHANNEL_2
909 * @arg @ref LL_DMA_CHANNEL_3
910 * @arg @ref LL_DMA_CHANNEL_4
911 * @arg @ref LL_DMA_CHANNEL_5
912 * @arg @ref LL_DMA_CHANNEL_6
913 * @arg @ref LL_DMA_CHANNEL_7
914 * @retval Returned value can be one of the following values:
915 * @arg @ref LL_DMA_PRIORITY_LOW
916 * @arg @ref LL_DMA_PRIORITY_MEDIUM
917 * @arg @ref LL_DMA_PRIORITY_HIGH
918 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
919 */
LL_DMA_GetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel)920 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
921 {
922 uint32_t dma_base_addr = (uint32_t)DMAx;
923 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
924 DMA_CCR_PL));
925 }
926
927 /**
928 * @brief Set Number of data to transfer.
929 * @note This action has no effect if
930 * channel is enabled.
931 * @rmtoll CNDTR NDT LL_DMA_SetDataLength
932 * @param DMAx DMAx Instance
933 * @param Channel This parameter can be one of the following values:
934 * @arg @ref LL_DMA_CHANNEL_1
935 * @arg @ref LL_DMA_CHANNEL_2
936 * @arg @ref LL_DMA_CHANNEL_3
937 * @arg @ref LL_DMA_CHANNEL_4
938 * @arg @ref LL_DMA_CHANNEL_5
939 * @arg @ref LL_DMA_CHANNEL_6
940 * @arg @ref LL_DMA_CHANNEL_7
941 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
942 * @retval None
943 */
LL_DMA_SetDataLength(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t NbData)944 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
945 {
946 uint32_t dma_base_addr = (uint32_t)DMAx;
947 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR,
948 DMA_CNDTR_NDT, NbData);
949 }
950
951 /**
952 * @brief Get Number of data to transfer.
953 * @note Once the channel is enabled, the return value indicate the
954 * remaining bytes to be transmitted.
955 * @rmtoll CNDTR NDT LL_DMA_GetDataLength
956 * @param DMAx DMAx Instance
957 * @param Channel This parameter can be one of the following values:
958 * @arg @ref LL_DMA_CHANNEL_1
959 * @arg @ref LL_DMA_CHANNEL_2
960 * @arg @ref LL_DMA_CHANNEL_3
961 * @arg @ref LL_DMA_CHANNEL_4
962 * @arg @ref LL_DMA_CHANNEL_5
963 * @arg @ref LL_DMA_CHANNEL_6
964 * @arg @ref LL_DMA_CHANNEL_7
965 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
966 */
LL_DMA_GetDataLength(DMA_TypeDef * DMAx,uint32_t Channel)967 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
968 {
969 uint32_t dma_base_addr = (uint32_t)DMAx;
970 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR,
971 DMA_CNDTR_NDT));
972 }
973
974 /**
975 * @brief Configure the Source and Destination addresses.
976 * @note This API must not be called when the DMA channel is enabled.
977 * @note Each peripheral using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr).
978 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
979 * CMAR MA LL_DMA_ConfigAddresses
980 * @param DMAx DMAx Instance
981 * @param Channel This parameter can be one of the following values:
982 * @arg @ref LL_DMA_CHANNEL_1
983 * @arg @ref LL_DMA_CHANNEL_2
984 * @arg @ref LL_DMA_CHANNEL_3
985 * @arg @ref LL_DMA_CHANNEL_4
986 * @arg @ref LL_DMA_CHANNEL_5
987 * @arg @ref LL_DMA_CHANNEL_6
988 * @arg @ref LL_DMA_CHANNEL_7
989 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
990 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
991 * @param Direction This parameter can be one of the following values:
992 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
993 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
994 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
995 * @retval None
996 */
LL_DMA_ConfigAddresses(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress,uint32_t DstAddress,uint32_t Direction)997 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
998 uint32_t DstAddress, uint32_t Direction)
999 {
1000 uint32_t dma_base_addr = (uint32_t)DMAx;
1001 /* Direction Memory to Periph */
1002 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
1003 {
1004 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, SrcAddress);
1005 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, DstAddress);
1006 }
1007 /* Direction Periph to Memory and Memory to Memory */
1008 else
1009 {
1010 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, SrcAddress);
1011 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, DstAddress);
1012 }
1013 }
1014
1015 /**
1016 * @brief Set the Memory address.
1017 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1018 * @note This API must not be called when the DMA channel is enabled.
1019 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
1020 * @param DMAx DMAx Instance
1021 * @param Channel This parameter can be one of the following values:
1022 * @arg @ref LL_DMA_CHANNEL_1
1023 * @arg @ref LL_DMA_CHANNEL_2
1024 * @arg @ref LL_DMA_CHANNEL_3
1025 * @arg @ref LL_DMA_CHANNEL_4
1026 * @arg @ref LL_DMA_CHANNEL_5
1027 * @arg @ref LL_DMA_CHANNEL_6
1028 * @arg @ref LL_DMA_CHANNEL_7
1029 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1030 * @retval None
1031 */
LL_DMA_SetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1032 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1033 {
1034 uint32_t dma_base_addr = (uint32_t)DMAx;
1035 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress);
1036 }
1037
1038 /**
1039 * @brief Set the Peripheral address.
1040 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1041 * @note This API must not be called when the DMA channel is enabled.
1042 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
1043 * @param DMAx DMAx Instance
1044 * @param Channel This parameter can be one of the following values:
1045 * @arg @ref LL_DMA_CHANNEL_1
1046 * @arg @ref LL_DMA_CHANNEL_2
1047 * @arg @ref LL_DMA_CHANNEL_3
1048 * @arg @ref LL_DMA_CHANNEL_4
1049 * @arg @ref LL_DMA_CHANNEL_5
1050 * @arg @ref LL_DMA_CHANNEL_6
1051 * @arg @ref LL_DMA_CHANNEL_7
1052 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1053 * @retval None
1054 */
LL_DMA_SetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphAddress)1055 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
1056 {
1057 uint32_t dma_base_addr = (uint32_t)DMAx;
1058 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, PeriphAddress);
1059 }
1060
1061 /**
1062 * @brief Get Memory address.
1063 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1064 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
1065 * @param DMAx DMAx Instance
1066 * @param Channel This parameter can be one of the following values:
1067 * @arg @ref LL_DMA_CHANNEL_1
1068 * @arg @ref LL_DMA_CHANNEL_2
1069 * @arg @ref LL_DMA_CHANNEL_3
1070 * @arg @ref LL_DMA_CHANNEL_4
1071 * @arg @ref LL_DMA_CHANNEL_5
1072 * @arg @ref LL_DMA_CHANNEL_6
1073 * @arg @ref LL_DMA_CHANNEL_7
1074 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1075 */
LL_DMA_GetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel)1076 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1077 {
1078 uint32_t dma_base_addr = (uint32_t)DMAx;
1079 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR));
1080 }
1081
1082 /**
1083 * @brief Get Peripheral address.
1084 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1085 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
1086 * @param DMAx DMAx Instance
1087 * @param Channel This parameter can be one of the following values:
1088 * @arg @ref LL_DMA_CHANNEL_1
1089 * @arg @ref LL_DMA_CHANNEL_2
1090 * @arg @ref LL_DMA_CHANNEL_3
1091 * @arg @ref LL_DMA_CHANNEL_4
1092 * @arg @ref LL_DMA_CHANNEL_5
1093 * @arg @ref LL_DMA_CHANNEL_6
1094 * @arg @ref LL_DMA_CHANNEL_7
1095 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1096 */
LL_DMA_GetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel)1097 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1098 {
1099 uint32_t dma_base_addr = (uint32_t)DMAx;
1100 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR));
1101 }
1102
1103 /**
1104 * @brief Set the Memory to Memory Source address.
1105 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1106 * @note This API must not be called when the DMA channel is enabled.
1107 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
1108 * @param DMAx DMAx Instance
1109 * @param Channel This parameter can be one of the following values:
1110 * @arg @ref LL_DMA_CHANNEL_1
1111 * @arg @ref LL_DMA_CHANNEL_2
1112 * @arg @ref LL_DMA_CHANNEL_3
1113 * @arg @ref LL_DMA_CHANNEL_4
1114 * @arg @ref LL_DMA_CHANNEL_5
1115 * @arg @ref LL_DMA_CHANNEL_6
1116 * @arg @ref LL_DMA_CHANNEL_7
1117 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1118 * @retval None
1119 */
LL_DMA_SetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1120 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1121 {
1122 uint32_t dma_base_addr = (uint32_t)DMAx;
1123 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, MemoryAddress);
1124 }
1125
1126 /**
1127 * @brief Set the Memory to Memory Destination address.
1128 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1129 * @note This API must not be called when the DMA channel is enabled.
1130 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
1131 * @param DMAx DMAx Instance
1132 * @param Channel This parameter can be one of the following values:
1133 * @arg @ref LL_DMA_CHANNEL_1
1134 * @arg @ref LL_DMA_CHANNEL_2
1135 * @arg @ref LL_DMA_CHANNEL_3
1136 * @arg @ref LL_DMA_CHANNEL_4
1137 * @arg @ref LL_DMA_CHANNEL_5
1138 * @arg @ref LL_DMA_CHANNEL_6
1139 * @arg @ref LL_DMA_CHANNEL_7
1140 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1141 * @retval None
1142 */
LL_DMA_SetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1143 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1144 {
1145 uint32_t dma_base_addr = (uint32_t)DMAx;
1146 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress);
1147 }
1148
1149 /**
1150 * @brief Get the Memory to Memory Source address.
1151 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1152 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
1153 * @param DMAx DMAx Instance
1154 * @param Channel This parameter can be one of the following values:
1155 * @arg @ref LL_DMA_CHANNEL_1
1156 * @arg @ref LL_DMA_CHANNEL_2
1157 * @arg @ref LL_DMA_CHANNEL_3
1158 * @arg @ref LL_DMA_CHANNEL_4
1159 * @arg @ref LL_DMA_CHANNEL_5
1160 * @arg @ref LL_DMA_CHANNEL_6
1161 * @arg @ref LL_DMA_CHANNEL_7
1162 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1163 */
LL_DMA_GetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel)1164 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1165 {
1166 uint32_t dma_base_addr = (uint32_t)DMAx;
1167 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR));
1168 }
1169
1170 /**
1171 * @brief Get the Memory to Memory Destination address.
1172 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1173 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
1174 * @param DMAx DMAx Instance
1175 * @param Channel This parameter can be one of the following values:
1176 * @arg @ref LL_DMA_CHANNEL_1
1177 * @arg @ref LL_DMA_CHANNEL_2
1178 * @arg @ref LL_DMA_CHANNEL_3
1179 * @arg @ref LL_DMA_CHANNEL_4
1180 * @arg @ref LL_DMA_CHANNEL_5
1181 * @arg @ref LL_DMA_CHANNEL_6
1182 * @arg @ref LL_DMA_CHANNEL_7
1183 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1184 */
LL_DMA_GetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel)1185 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1186 {
1187 uint32_t dma_base_addr = (uint32_t)DMAx;
1188 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR));
1189 }
1190
1191 /**
1192 * @brief Set DMA request for DMA Channels on DMAMUX Channel x.
1193 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
1194 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
1195 * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest
1196 * @param DMAx DMAx Instance
1197 * @param Channel This parameter can be one of the following values:
1198 * @arg @ref LL_DMA_CHANNEL_1
1199 * @arg @ref LL_DMA_CHANNEL_2
1200 * @arg @ref LL_DMA_CHANNEL_3
1201 * @arg @ref LL_DMA_CHANNEL_4
1202 * @arg @ref LL_DMA_CHANNEL_5
1203 * @arg @ref LL_DMA_CHANNEL_6
1204 * @arg @ref LL_DMA_CHANNEL_7
1205 * @param Request This parameter can be one of the following values:
1206 * @arg @ref LL_DMAMUX_REQ_MEM2MEM
1207 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
1208 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
1209 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
1210 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
1211 * @arg @ref LL_DMAMUX_REQ_ADC1
1212 * @arg @ref LL_DMAMUX_REQ_AES_IN
1213 * @arg @ref LL_DMAMUX_REQ_AES_OUT
1214 * @arg @ref LL_DMAMUX_REQ_DAC1_CH1
1215 * @arg @ref LL_DMAMUX_REQ_DAC1_CH2
1216 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
1217 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
1218 * @arg @ref LL_DMAMUX_REQ_I2C2_RX
1219 * @arg @ref LL_DMAMUX_REQ_I2C2_TX
1220 * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
1221 * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
1222 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
1223 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
1224 * @arg @ref LL_DMAMUX_REQ_SPI2_RX
1225 * @arg @ref LL_DMAMUX_REQ_SPI2_TX
1226 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
1227 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
1228 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
1229 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
1230 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM
1231 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
1232 * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
1233 * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
1234 * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
1235 * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
1236 * @arg @ref LL_DMAMUX_REQ_TIM2_TRIG
1237 * @arg @ref LL_DMAMUX_REQ_TIM2_UP
1238 * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
1239 * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
1240 * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
1241 * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
1242 * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
1243 * @arg @ref LL_DMAMUX_REQ_TIM3_UP
1244 * @arg @ref LL_DMAMUX_REQ_TIM6_UP
1245 * @arg @ref LL_DMAMUX_REQ_TIM7_UP
1246 * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
1247 * @arg @ref LL_DMAMUX_REQ_TIM15_CH2
1248 * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG_COM
1249 * @arg @ref LL_DMAMUX_REQ_TIM15_UP
1250 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
1251 * @arg @ref LL_DMAMUX_REQ_TIM16_COM
1252 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
1253 * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
1254 * @arg @ref LL_DMAMUX_REQ_TIM17_COM
1255 * @arg @ref LL_DMAMUX_REQ_TIM17_UP
1256 * @arg @ref LL_DMAMUX_REQ_USART1_RX
1257 * @arg @ref LL_DMAMUX_REQ_USART1_TX
1258 * @arg @ref LL_DMAMUX_REQ_USART2_RX
1259 * @arg @ref LL_DMAMUX_REQ_USART2_TX
1260 * @arg @ref LL_DMAMUX_REQ_USART3_RX
1261 * @arg @ref LL_DMAMUX_REQ_USART3_TX
1262 * @arg @ref LL_DMAMUX_REQ_USART4_RX
1263 * @arg @ref LL_DMAMUX_REQ_USART4_TX
1264 * @arg @ref LL_DMAMUX_REQ_UCPD1_RX
1265 * @arg @ref LL_DMAMUX_REQ_UCPD1_TX
1266 * @arg @ref LL_DMAMUX_REQ_UCPD2_RX
1267 * @arg @ref LL_DMAMUX_REQ_UCPD2_TX
1268 * @retval None
1269 */
LL_DMA_SetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Request)1270 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
1271 {
1272 uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U);
1273 MODIFY_REG((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
1274 }
1275
1276 /**
1277 * @brief Get DMA request for DMA Channels on DMAMUX Channel x.
1278 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
1279 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
1280 * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest
1281 * @param DMAx DMAx Instance
1282 * @param Channel This parameter can be one of the following values:
1283 * @arg @ref LL_DMA_CHANNEL_1
1284 * @arg @ref LL_DMA_CHANNEL_2
1285 * @arg @ref LL_DMA_CHANNEL_3
1286 * @arg @ref LL_DMA_CHANNEL_4
1287 * @arg @ref LL_DMA_CHANNEL_5
1288 * @arg @ref LL_DMA_CHANNEL_6
1289 * @arg @ref LL_DMA_CHANNEL_7
1290 * @retval Returned value can be one of the following values:
1291 * @arg @ref LL_DMAMUX_REQ_MEM2MEM
1292 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
1293 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
1294 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
1295 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
1296 * @arg @ref LL_DMAMUX_REQ_ADC1
1297 * @arg @ref LL_DMAMUX_REQ_AES_IN
1298 * @arg @ref LL_DMAMUX_REQ_AES_OUT
1299 * @arg @ref LL_DMAMUX_REQ_DAC1_CH1
1300 * @arg @ref LL_DMAMUX_REQ_DAC1_CH2
1301 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
1302 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
1303 * @arg @ref LL_DMAMUX_REQ_I2C2_RX
1304 * @arg @ref LL_DMAMUX_REQ_I2C2_TX
1305 * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
1306 * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
1307 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
1308 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
1309 * @arg @ref LL_DMAMUX_REQ_SPI2_RX
1310 * @arg @ref LL_DMAMUX_REQ_SPI2_TX
1311 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
1312 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
1313 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
1314 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
1315 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM
1316 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
1317 * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
1318 * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
1319 * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
1320 * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
1321 * @arg @ref LL_DMAMUX_REQ_TIM2_TRIG
1322 * @arg @ref LL_DMAMUX_REQ_TIM2_UP
1323 * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
1324 * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
1325 * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
1326 * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
1327 * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
1328 * @arg @ref LL_DMAMUX_REQ_TIM3_UP
1329 * @arg @ref LL_DMAMUX_REQ_TIM6_UP
1330 * @arg @ref LL_DMAMUX_REQ_TIM7_UP
1331 * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
1332 * @arg @ref LL_DMAMUX_REQ_TIM15_CH2
1333 * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG_COM
1334 * @arg @ref LL_DMAMUX_REQ_TIM15_UP
1335 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
1336 * @arg @ref LL_DMAMUX_REQ_TIM16_COM
1337 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
1338 * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
1339 * @arg @ref LL_DMAMUX_REQ_TIM17_COM
1340 * @arg @ref LL_DMAMUX_REQ_TIM17_UP
1341 * @arg @ref LL_DMAMUX_REQ_USART1_RX
1342 * @arg @ref LL_DMAMUX_REQ_USART1_TX
1343 * @arg @ref LL_DMAMUX_REQ_USART2_RX
1344 * @arg @ref LL_DMAMUX_REQ_USART2_TX
1345 * @arg @ref LL_DMAMUX_REQ_USART3_RX
1346 * @arg @ref LL_DMAMUX_REQ_USART3_TX
1347 * @arg @ref LL_DMAMUX_REQ_USART4_RX
1348 * @arg @ref LL_DMAMUX_REQ_USART4_TX
1349 * @arg @ref LL_DMAMUX_REQ_UCPD1_RX
1350 * @arg @ref LL_DMAMUX_REQ_UCPD1_TX
1351 * @arg @ref LL_DMAMUX_REQ_UCPD2_RX
1352 * @arg @ref LL_DMAMUX_REQ_UCPD2_TX
1353 */
LL_DMA_GetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel)1354 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
1355 {
1356 uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U);
1357 return (READ_BIT((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID));
1358 }
1359
1360 /**
1361 * @}
1362 */
1363
1364 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1365 * @{
1366 */
1367
1368 /**
1369 * @brief Get Channel 1 global interrupt flag.
1370 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
1371 * @param DMAx DMAx Instance
1372 * @retval State of bit (1 or 0).
1373 */
LL_DMA_IsActiveFlag_GI1(DMA_TypeDef * DMAx)1374 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
1375 {
1376 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL);
1377 }
1378
1379 /**
1380 * @brief Get Channel 2 global interrupt flag.
1381 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
1382 * @param DMAx DMAx Instance
1383 * @retval State of bit (1 or 0).
1384 */
LL_DMA_IsActiveFlag_GI2(DMA_TypeDef * DMAx)1385 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
1386 {
1387 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL);
1388 }
1389
1390 /**
1391 * @brief Get Channel 3 global interrupt flag.
1392 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
1393 * @param DMAx DMAx Instance
1394 * @retval State of bit (1 or 0).
1395 */
LL_DMA_IsActiveFlag_GI3(DMA_TypeDef * DMAx)1396 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
1397 {
1398 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL);
1399 }
1400
1401 /**
1402 * @brief Get Channel 4 global interrupt flag.
1403 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
1404 * @param DMAx DMAx Instance
1405 * @retval State of bit (1 or 0).
1406 */
LL_DMA_IsActiveFlag_GI4(DMA_TypeDef * DMAx)1407 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
1408 {
1409 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL);
1410 }
1411
1412 /**
1413 * @brief Get Channel 5 global interrupt flag.
1414 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
1415 * @param DMAx DMAx Instance
1416 * @retval State of bit (1 or 0).
1417 */
LL_DMA_IsActiveFlag_GI5(DMA_TypeDef * DMAx)1418 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
1419 {
1420 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL);
1421 }
1422
1423 #if defined(DMA1_Channel6)
1424 /**
1425 * @brief Get Channel 6 global interrupt flag.
1426 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
1427 * @param DMAx DMAx Instance
1428 * @retval State of bit (1 or 0).
1429 */
LL_DMA_IsActiveFlag_GI6(DMA_TypeDef * DMAx)1430 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
1431 {
1432 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL);
1433 }
1434
1435 #endif /* DMA1_Channel6 */
1436 #if defined(DMA1_Channel7)
1437 /**
1438 * @brief Get Channel 7 global interrupt flag.
1439 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
1440 * @param DMAx DMAx Instance
1441 * @retval State of bit (1 or 0).
1442 */
LL_DMA_IsActiveFlag_GI7(DMA_TypeDef * DMAx)1443 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
1444 {
1445 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL);
1446 }
1447
1448 #endif /* DMA1_Channel7 */
1449 /**
1450 * @brief Get Channel 1 transfer complete flag.
1451 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
1452 * @param DMAx DMAx Instance
1453 * @retval State of bit (1 or 0).
1454 */
LL_DMA_IsActiveFlag_TC1(DMA_TypeDef * DMAx)1455 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
1456 {
1457 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL);
1458 }
1459
1460 /**
1461 * @brief Get Channel 2 transfer complete flag.
1462 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
1463 * @param DMAx DMAx Instance
1464 * @retval State of bit (1 or 0).
1465 */
LL_DMA_IsActiveFlag_TC2(DMA_TypeDef * DMAx)1466 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
1467 {
1468 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL);
1469 }
1470
1471 /**
1472 * @brief Get Channel 3 transfer complete flag.
1473 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
1474 * @param DMAx DMAx Instance
1475 * @retval State of bit (1 or 0).
1476 */
LL_DMA_IsActiveFlag_TC3(DMA_TypeDef * DMAx)1477 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
1478 {
1479 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL);
1480 }
1481
1482 /**
1483 * @brief Get Channel 4 transfer complete flag.
1484 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
1485 * @param DMAx DMAx Instance
1486 * @retval State of bit (1 or 0).
1487 */
LL_DMA_IsActiveFlag_TC4(DMA_TypeDef * DMAx)1488 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
1489 {
1490 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL);
1491 }
1492
1493 /**
1494 * @brief Get Channel 5 transfer complete flag.
1495 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
1496 * @param DMAx DMAx Instance
1497 * @retval State of bit (1 or 0).
1498 */
LL_DMA_IsActiveFlag_TC5(DMA_TypeDef * DMAx)1499 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
1500 {
1501 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL);
1502 }
1503
1504 #if defined(DMA1_Channel6)
1505 /**
1506 * @brief Get Channel 6 transfer complete flag.
1507 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
1508 * @param DMAx DMAx Instance
1509 * @retval State of bit (1 or 0).
1510 */
LL_DMA_IsActiveFlag_TC6(DMA_TypeDef * DMAx)1511 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
1512 {
1513 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL);
1514 }
1515
1516 #endif /* DMA1_Channel6 */
1517 #if defined(DMA1_Channel7)
1518 /**
1519 * @brief Get Channel 7 transfer complete flag.
1520 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
1521 * @param DMAx DMAx Instance
1522 * @retval State of bit (1 or 0).
1523 */
LL_DMA_IsActiveFlag_TC7(DMA_TypeDef * DMAx)1524 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
1525 {
1526 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL);
1527 }
1528
1529 #endif /* DMA1_Channel7 */
1530 /**
1531 * @brief Get Channel 1 half transfer flag.
1532 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
1533 * @param DMAx DMAx Instance
1534 * @retval State of bit (1 or 0).
1535 */
LL_DMA_IsActiveFlag_HT1(DMA_TypeDef * DMAx)1536 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
1537 {
1538 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL);
1539 }
1540
1541 /**
1542 * @brief Get Channel 2 half transfer flag.
1543 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
1544 * @param DMAx DMAx Instance
1545 * @retval State of bit (1 or 0).
1546 */
LL_DMA_IsActiveFlag_HT2(DMA_TypeDef * DMAx)1547 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
1548 {
1549 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL);
1550 }
1551
1552 /**
1553 * @brief Get Channel 3 half transfer flag.
1554 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
1555 * @param DMAx DMAx Instance
1556 * @retval State of bit (1 or 0).
1557 */
LL_DMA_IsActiveFlag_HT3(DMA_TypeDef * DMAx)1558 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
1559 {
1560 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL);
1561 }
1562
1563 /**
1564 * @brief Get Channel 4 half transfer flag.
1565 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
1566 * @param DMAx DMAx Instance
1567 * @retval State of bit (1 or 0).
1568 */
LL_DMA_IsActiveFlag_HT4(DMA_TypeDef * DMAx)1569 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
1570 {
1571 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL);
1572 }
1573
1574 /**
1575 * @brief Get Channel 5 half transfer flag.
1576 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
1577 * @param DMAx DMAx Instance
1578 * @retval State of bit (1 or 0).
1579 */
LL_DMA_IsActiveFlag_HT5(DMA_TypeDef * DMAx)1580 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
1581 {
1582 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL);
1583 }
1584
1585 #if defined(DMA1_Channel6)
1586 /**
1587 * @brief Get Channel 6 half transfer flag.
1588 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
1589 * @param DMAx DMAx Instance
1590 * @retval State of bit (1 or 0).
1591 */
LL_DMA_IsActiveFlag_HT6(DMA_TypeDef * DMAx)1592 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
1593 {
1594 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL);
1595 }
1596
1597 #endif /* DMA1_Channel6 */
1598 #if defined(DMA1_Channel7)
1599 /**
1600 * @brief Get Channel 7 half transfer flag.
1601 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
1602 * @param DMAx DMAx Instance
1603 * @retval State of bit (1 or 0).
1604 */
LL_DMA_IsActiveFlag_HT7(DMA_TypeDef * DMAx)1605 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
1606 {
1607 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL);
1608 }
1609
1610 #endif /* DMA1_Channel7 */
1611 /**
1612 * @brief Get Channel 1 transfer error flag.
1613 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
1614 * @param DMAx DMAx Instance
1615 * @retval State of bit (1 or 0).
1616 */
LL_DMA_IsActiveFlag_TE1(DMA_TypeDef * DMAx)1617 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
1618 {
1619 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL);
1620 }
1621
1622 /**
1623 * @brief Get Channel 2 transfer error flag.
1624 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
1625 * @param DMAx DMAx Instance
1626 * @retval State of bit (1 or 0).
1627 */
LL_DMA_IsActiveFlag_TE2(DMA_TypeDef * DMAx)1628 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
1629 {
1630 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL);
1631 }
1632
1633 /**
1634 * @brief Get Channel 3 transfer error flag.
1635 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
1636 * @param DMAx DMAx Instance
1637 * @retval State of bit (1 or 0).
1638 */
LL_DMA_IsActiveFlag_TE3(DMA_TypeDef * DMAx)1639 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
1640 {
1641 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL);
1642 }
1643
1644 /**
1645 * @brief Get Channel 4 transfer error flag.
1646 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
1647 * @param DMAx DMAx Instance
1648 * @retval State of bit (1 or 0).
1649 */
LL_DMA_IsActiveFlag_TE4(DMA_TypeDef * DMAx)1650 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
1651 {
1652 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL);
1653 }
1654
1655 /**
1656 * @brief Get Channel 5 transfer error flag.
1657 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
1658 * @param DMAx DMAx Instance
1659 * @retval State of bit (1 or 0).
1660 */
LL_DMA_IsActiveFlag_TE5(DMA_TypeDef * DMAx)1661 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
1662 {
1663 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL);
1664 }
1665
1666 #if defined(DMA1_Channel6)
1667 /**
1668 * @brief Get Channel 6 transfer error flag.
1669 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
1670 * @param DMAx DMAx Instance
1671 * @retval State of bit (1 or 0).
1672 */
LL_DMA_IsActiveFlag_TE6(DMA_TypeDef * DMAx)1673 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
1674 {
1675 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL);
1676 }
1677
1678 #endif /* DMA1_Channel6 */
1679 #if defined(DMA1_Channel7)
1680 /**
1681 * @brief Get Channel 7 transfer error flag.
1682 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
1683 * @param DMAx DMAx Instance
1684 * @retval State of bit (1 or 0).
1685 */
LL_DMA_IsActiveFlag_TE7(DMA_TypeDef * DMAx)1686 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
1687 {
1688 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL);
1689 }
1690
1691 #endif /* DMA1_Channel7 */
1692 /**
1693 * @brief Clear Channel 1 global interrupt flag.
1694 * @note Do not Clear Channel 1 global interrupt flag when the channel in ON.
1695 Instead clear specific flags transfer complete, half transfer & transfer
1696 error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1,
1697 LL_DMA_ClearFlag_TE1. bug id 2.4.1 in Product Errata Sheet.
1698 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
1699 * @param DMAx DMAx Instance
1700 * @retval None
1701 */
LL_DMA_ClearFlag_GI1(DMA_TypeDef * DMAx)1702 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
1703 {
1704 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
1705 }
1706
1707 /**
1708 * @brief Clear Channel 2 global interrupt flag.
1709 * @note Do not Clear Channel 2 global interrupt flag when the channel in ON.
1710 Instead clear specific flags transfer complete, half transfer & transfer
1711 error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2,
1712 LL_DMA_ClearFlag_TE2. bug id 2.4.1 in Product Errata Sheet.
1713 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
1714 * @param DMAx DMAx Instance
1715 * @retval None
1716 */
LL_DMA_ClearFlag_GI2(DMA_TypeDef * DMAx)1717 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
1718 {
1719 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
1720 }
1721
1722 /**
1723 * @brief Clear Channel 3 global interrupt flag.
1724 * @note Do not Clear Channel 3 global interrupt flag when the channel in ON.
1725 Instead clear specific flags transfer complete, half transfer & transfer
1726 error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3,
1727 LL_DMA_ClearFlag_TE3. bug id 2.4.1 in Product Errata Sheet.
1728 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
1729 * @param DMAx DMAx Instance
1730 * @retval None
1731 */
LL_DMA_ClearFlag_GI3(DMA_TypeDef * DMAx)1732 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
1733 {
1734 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
1735 }
1736
1737 /**
1738 * @brief Clear Channel 4 global interrupt flag.
1739 * @note Do not Clear Channel 4 global interrupt flag when the channel in ON.
1740 Instead clear specific flags transfer complete, half transfer & transfer
1741 error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4,
1742 LL_DMA_ClearFlag_TE4. bug id 2.4.1 in Product Errata Sheet.
1743 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
1744 * @param DMAx DMAx Instance
1745 * @retval None
1746 */
LL_DMA_ClearFlag_GI4(DMA_TypeDef * DMAx)1747 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
1748 {
1749 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
1750 }
1751
1752 /**
1753 * @brief Clear Channel 5 global interrupt flag.
1754 * @note Do not Clear Channel 5 global interrupt flag when the channel in ON.
1755 Instead clear specific flags transfer complete, half transfer & transfer
1756 error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5,
1757 LL_DMA_ClearFlag_TE5. bug id 2.4.1 in Product Errata Sheet.
1758 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
1759 * @param DMAx DMAx Instance
1760 * @retval None
1761 */
LL_DMA_ClearFlag_GI5(DMA_TypeDef * DMAx)1762 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
1763 {
1764 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
1765 }
1766
1767 #if defined(DMA1_Channel6)
1768 /**
1769 * @brief Clear Channel 6 global interrupt flag.
1770 * @note Do not Clear Channel 6 global interrupt flag when the channel in ON.
1771 Instead clear specific flags transfer complete, half transfer & transfer
1772 error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6,
1773 LL_DMA_ClearFlag_TE6. bug id 2.4.1 in Product Errata Sheet.
1774 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
1775 * @param DMAx DMAx Instance
1776 * @retval None
1777 */
LL_DMA_ClearFlag_GI6(DMA_TypeDef * DMAx)1778 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
1779 {
1780 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
1781 }
1782
1783 #endif /* DMA1_Channel6 */
1784 #if defined(DMA1_Channel7)
1785 /**
1786 * @brief Clear Channel 7 global interrupt flag.
1787 * @note Do not Clear Channel 7 global interrupt flag when the channel in ON.
1788 Instead clear specific flags transfer complete, half transfer & transfer
1789 error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7,
1790 LL_DMA_ClearFlag_TE7. bug id 2.4.1 in Product Errata Sheet.
1791 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
1792 * @param DMAx DMAx Instance
1793 * @retval None
1794 */
LL_DMA_ClearFlag_GI7(DMA_TypeDef * DMAx)1795 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
1796 {
1797 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
1798 }
1799
1800 #endif /* DMA1_Channel7 */
1801 /**
1802 * @brief Clear Channel 1 transfer complete flag.
1803 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
1804 * @param DMAx DMAx Instance
1805 * @retval None
1806 */
LL_DMA_ClearFlag_TC1(DMA_TypeDef * DMAx)1807 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
1808 {
1809 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
1810 }
1811
1812 /**
1813 * @brief Clear Channel 2 transfer complete flag.
1814 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
1815 * @param DMAx DMAx Instance
1816 * @retval None
1817 */
LL_DMA_ClearFlag_TC2(DMA_TypeDef * DMAx)1818 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
1819 {
1820 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
1821 }
1822
1823 /**
1824 * @brief Clear Channel 3 transfer complete flag.
1825 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
1826 * @param DMAx DMAx Instance
1827 * @retval None
1828 */
LL_DMA_ClearFlag_TC3(DMA_TypeDef * DMAx)1829 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
1830 {
1831 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
1832 }
1833
1834 /**
1835 * @brief Clear Channel 4 transfer complete flag.
1836 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
1837 * @param DMAx DMAx Instance
1838 * @retval None
1839 */
LL_DMA_ClearFlag_TC4(DMA_TypeDef * DMAx)1840 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
1841 {
1842 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
1843 }
1844
1845 /**
1846 * @brief Clear Channel 5 transfer complete flag.
1847 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
1848 * @param DMAx DMAx Instance
1849 * @retval None
1850 */
LL_DMA_ClearFlag_TC5(DMA_TypeDef * DMAx)1851 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
1852 {
1853 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
1854 }
1855
1856 #if defined(DMA1_Channel6)
1857 /**
1858 * @brief Clear Channel 6 transfer complete flag.
1859 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
1860 * @param DMAx DMAx Instance
1861 * @retval None
1862 */
LL_DMA_ClearFlag_TC6(DMA_TypeDef * DMAx)1863 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
1864 {
1865 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
1866 }
1867
1868 #endif /* DMA1_Channel6 */
1869 #if defined(DMA1_Channel7)
1870 /**
1871 * @brief Clear Channel 7 transfer complete flag.
1872 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
1873 * @param DMAx DMAx Instance
1874 * @retval None
1875 */
LL_DMA_ClearFlag_TC7(DMA_TypeDef * DMAx)1876 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
1877 {
1878 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
1879 }
1880
1881 #endif /* DMA1_Channel7 */
1882 /**
1883 * @brief Clear Channel 1 half transfer flag.
1884 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
1885 * @param DMAx DMAx Instance
1886 * @retval None
1887 */
LL_DMA_ClearFlag_HT1(DMA_TypeDef * DMAx)1888 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
1889 {
1890 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
1891 }
1892
1893 /**
1894 * @brief Clear Channel 2 half transfer flag.
1895 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
1896 * @param DMAx DMAx Instance
1897 * @retval None
1898 */
LL_DMA_ClearFlag_HT2(DMA_TypeDef * DMAx)1899 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
1900 {
1901 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
1902 }
1903
1904 /**
1905 * @brief Clear Channel 3 half transfer flag.
1906 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
1907 * @param DMAx DMAx Instance
1908 * @retval None
1909 */
LL_DMA_ClearFlag_HT3(DMA_TypeDef * DMAx)1910 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
1911 {
1912 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
1913 }
1914
1915 /**
1916 * @brief Clear Channel 4 half transfer flag.
1917 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
1918 * @param DMAx DMAx Instance
1919 * @retval None
1920 */
LL_DMA_ClearFlag_HT4(DMA_TypeDef * DMAx)1921 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
1922 {
1923 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
1924 }
1925
1926 /**
1927 * @brief Clear Channel 5 half transfer flag.
1928 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
1929 * @param DMAx DMAx Instance
1930 * @retval None
1931 */
LL_DMA_ClearFlag_HT5(DMA_TypeDef * DMAx)1932 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
1933 {
1934 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
1935 }
1936
1937 #if defined(DMA1_Channel6)
1938 /**
1939 * @brief Clear Channel 6 half transfer flag.
1940 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
1941 * @param DMAx DMAx Instance
1942 * @retval None
1943 */
LL_DMA_ClearFlag_HT6(DMA_TypeDef * DMAx)1944 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
1945 {
1946 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
1947 }
1948
1949 #endif /* DMA1_Channel6 */
1950 #if defined(DMA1_Channel7)
1951 /**
1952 * @brief Clear Channel 7 half transfer flag.
1953 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
1954 * @param DMAx DMAx Instance
1955 * @retval None
1956 */
LL_DMA_ClearFlag_HT7(DMA_TypeDef * DMAx)1957 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
1958 {
1959 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
1960 }
1961
1962 #endif /* DMA1_Channel7 */
1963 /**
1964 * @brief Clear Channel 1 transfer error flag.
1965 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
1966 * @param DMAx DMAx Instance
1967 * @retval None
1968 */
LL_DMA_ClearFlag_TE1(DMA_TypeDef * DMAx)1969 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
1970 {
1971 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
1972 }
1973
1974 /**
1975 * @brief Clear Channel 2 transfer error flag.
1976 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
1977 * @param DMAx DMAx Instance
1978 * @retval None
1979 */
LL_DMA_ClearFlag_TE2(DMA_TypeDef * DMAx)1980 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
1981 {
1982 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
1983 }
1984
1985 /**
1986 * @brief Clear Channel 3 transfer error flag.
1987 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
1988 * @param DMAx DMAx Instance
1989 * @retval None
1990 */
LL_DMA_ClearFlag_TE3(DMA_TypeDef * DMAx)1991 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
1992 {
1993 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
1994 }
1995
1996 /**
1997 * @brief Clear Channel 4 transfer error flag.
1998 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
1999 * @param DMAx DMAx Instance
2000 * @retval None
2001 */
LL_DMA_ClearFlag_TE4(DMA_TypeDef * DMAx)2002 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
2003 {
2004 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
2005 }
2006
2007 /**
2008 * @brief Clear Channel 5 transfer error flag.
2009 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
2010 * @param DMAx DMAx Instance
2011 * @retval None
2012 */
LL_DMA_ClearFlag_TE5(DMA_TypeDef * DMAx)2013 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
2014 {
2015 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
2016 }
2017
2018 #if defined(DMA1_Channel6)
2019 /**
2020 * @brief Clear Channel 6 transfer error flag.
2021 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
2022 * @param DMAx DMAx Instance
2023 * @retval None
2024 */
LL_DMA_ClearFlag_TE6(DMA_TypeDef * DMAx)2025 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
2026 {
2027 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
2028 }
2029
2030 #endif /* DMA1_Channel6 */
2031 #if defined(DMA1_Channel7)
2032 /**
2033 * @brief Clear Channel 7 transfer error flag.
2034 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
2035 * @param DMAx DMAx Instance
2036 * @retval None
2037 */
LL_DMA_ClearFlag_TE7(DMA_TypeDef * DMAx)2038 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
2039 {
2040 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
2041 }
2042
2043 #endif /* DMA1_Channel7 */
2044 /**
2045 * @}
2046 */
2047
2048 /** @defgroup DMA_LL_EF_IT_Management IT_Management
2049 * @{
2050 */
2051 /**
2052 * @brief Enable Transfer complete interrupt.
2053 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
2054 * @param DMAx DMAx Instance
2055 * @param Channel This parameter can be one of the following values:
2056 * @arg @ref LL_DMA_CHANNEL_1
2057 * @arg @ref LL_DMA_CHANNEL_2
2058 * @arg @ref LL_DMA_CHANNEL_3
2059 * @arg @ref LL_DMA_CHANNEL_4
2060 * @arg @ref LL_DMA_CHANNEL_5
2061 * @arg @ref LL_DMA_CHANNEL_6
2062 * @arg @ref LL_DMA_CHANNEL_7
2063 * @retval None
2064 */
LL_DMA_EnableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)2065 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2066 {
2067 uint32_t dma_base_addr = (uint32_t)DMAx;
2068 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
2069 }
2070
2071 /**
2072 * @brief Enable Half transfer interrupt.
2073 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
2074 * @param DMAx DMAx Instance
2075 * @param Channel This parameter can be one of the following values:
2076 * @arg @ref LL_DMA_CHANNEL_1
2077 * @arg @ref LL_DMA_CHANNEL_2
2078 * @arg @ref LL_DMA_CHANNEL_3
2079 * @arg @ref LL_DMA_CHANNEL_4
2080 * @arg @ref LL_DMA_CHANNEL_5
2081 * @arg @ref LL_DMA_CHANNEL_6
2082 * @arg @ref LL_DMA_CHANNEL_7
2083 * @retval None
2084 */
LL_DMA_EnableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)2085 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2086 {
2087 uint32_t dma_base_addr = (uint32_t)DMAx;
2088 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
2089 }
2090
2091 /**
2092 * @brief Enable Transfer error interrupt.
2093 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
2094 * @param DMAx DMAx Instance
2095 * @param Channel This parameter can be one of the following values:
2096 * @arg @ref LL_DMA_CHANNEL_1
2097 * @arg @ref LL_DMA_CHANNEL_2
2098 * @arg @ref LL_DMA_CHANNEL_3
2099 * @arg @ref LL_DMA_CHANNEL_4
2100 * @arg @ref LL_DMA_CHANNEL_5
2101 * @arg @ref LL_DMA_CHANNEL_6
2102 * @arg @ref LL_DMA_CHANNEL_7
2103 * @retval None
2104 */
LL_DMA_EnableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)2105 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2106 {
2107 uint32_t dma_base_addr = (uint32_t)DMAx;
2108 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE);
2109 }
2110
2111 /**
2112 * @brief Disable Transfer complete interrupt.
2113 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
2114 * @param DMAx DMAx Instance
2115 * @param Channel This parameter can be one of the following values:
2116 * @arg @ref LL_DMA_CHANNEL_1
2117 * @arg @ref LL_DMA_CHANNEL_2
2118 * @arg @ref LL_DMA_CHANNEL_3
2119 * @arg @ref LL_DMA_CHANNEL_4
2120 * @arg @ref LL_DMA_CHANNEL_5
2121 * @arg @ref LL_DMA_CHANNEL_6
2122 * @arg @ref LL_DMA_CHANNEL_7
2123 * @retval None
2124 */
LL_DMA_DisableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)2125 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2126 {
2127 uint32_t dma_base_addr = (uint32_t)DMAx;
2128 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
2129 }
2130
2131 /**
2132 * @brief Disable Half transfer interrupt.
2133 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
2134 * @param DMAx DMAx Instance
2135 * @param Channel This parameter can be one of the following values:
2136 * @arg @ref LL_DMA_CHANNEL_1
2137 * @arg @ref LL_DMA_CHANNEL_2
2138 * @arg @ref LL_DMA_CHANNEL_3
2139 * @arg @ref LL_DMA_CHANNEL_4
2140 * @arg @ref LL_DMA_CHANNEL_5
2141 * @arg @ref LL_DMA_CHANNEL_6
2142 * @arg @ref LL_DMA_CHANNEL_7
2143 * @retval None
2144 */
LL_DMA_DisableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)2145 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2146 {
2147 uint32_t dma_base_addr = (uint32_t)DMAx;
2148 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
2149 }
2150
2151 /**
2152 * @brief Disable Transfer error interrupt.
2153 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
2154 * @param DMAx DMAx Instance
2155 * @param Channel This parameter can be one of the following values:
2156 * @arg @ref LL_DMA_CHANNEL_1
2157 * @arg @ref LL_DMA_CHANNEL_2
2158 * @arg @ref LL_DMA_CHANNEL_3
2159 * @arg @ref LL_DMA_CHANNEL_4
2160 * @arg @ref LL_DMA_CHANNEL_5
2161 * @arg @ref LL_DMA_CHANNEL_6
2162 * @arg @ref LL_DMA_CHANNEL_7
2163 * @retval None
2164 */
LL_DMA_DisableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)2165 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2166 {
2167 uint32_t dma_base_addr = (uint32_t)DMAx;
2168 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE);
2169 }
2170
2171 /**
2172 * @brief Check if Transfer complete Interrupt is enabled.
2173 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
2174 * @param DMAx DMAx Instance
2175 * @param Channel This parameter can be one of the following values:
2176 * @arg @ref LL_DMA_CHANNEL_1
2177 * @arg @ref LL_DMA_CHANNEL_2
2178 * @arg @ref LL_DMA_CHANNEL_3
2179 * @arg @ref LL_DMA_CHANNEL_4
2180 * @arg @ref LL_DMA_CHANNEL_5
2181 * @arg @ref LL_DMA_CHANNEL_6
2182 * @arg @ref LL_DMA_CHANNEL_7
2183 * @retval State of bit (1 or 0).
2184 */
LL_DMA_IsEnabledIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)2185 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2186 {
2187 uint32_t dma_base_addr = (uint32_t)DMAx;
2188 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
2189 DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL);
2190 }
2191
2192 /**
2193 * @brief Check if Half transfer Interrupt is enabled.
2194 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
2195 * @param DMAx DMAx Instance
2196 * @param Channel This parameter can be one of the following values:
2197 * @arg @ref LL_DMA_CHANNEL_1
2198 * @arg @ref LL_DMA_CHANNEL_2
2199 * @arg @ref LL_DMA_CHANNEL_3
2200 * @arg @ref LL_DMA_CHANNEL_4
2201 * @arg @ref LL_DMA_CHANNEL_5
2202 * @arg @ref LL_DMA_CHANNEL_6
2203 * @arg @ref LL_DMA_CHANNEL_7
2204 * @retval State of bit (1 or 0).
2205 */
LL_DMA_IsEnabledIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)2206 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2207 {
2208 uint32_t dma_base_addr = (uint32_t)DMAx;
2209 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
2210 DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL);
2211 }
2212
2213 /**
2214 * @brief Check if Transfer error Interrupt is enabled.
2215 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
2216 * @param DMAx DMAx Instance
2217 * @param Channel This parameter can be one of the following values:
2218 * @arg @ref LL_DMA_CHANNEL_1
2219 * @arg @ref LL_DMA_CHANNEL_2
2220 * @arg @ref LL_DMA_CHANNEL_3
2221 * @arg @ref LL_DMA_CHANNEL_4
2222 * @arg @ref LL_DMA_CHANNEL_5
2223 * @arg @ref LL_DMA_CHANNEL_6
2224 * @arg @ref LL_DMA_CHANNEL_7
2225 * @retval State of bit (1 or 0).
2226 */
LL_DMA_IsEnabledIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)2227 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2228 {
2229 uint32_t dma_base_addr = (uint32_t)DMAx;
2230 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
2231 DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL);
2232 }
2233
2234 /**
2235 * @}
2236 */
2237
2238 #if defined(USE_FULL_LL_DRIVER)
2239 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
2240 * @{
2241 */
2242 ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
2243 ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
2244 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
2245
2246 /**
2247 * @}
2248 */
2249 #endif /* USE_FULL_LL_DRIVER */
2250
2251 /**
2252 * @}
2253 */
2254
2255 /**
2256 * @}
2257 */
2258
2259 #endif /* DMA1 || DMA2 */
2260
2261 /**
2262 * @}
2263 */
2264
2265 #ifdef __cplusplus
2266 }
2267 #endif
2268
2269 #endif /* STM32G0xx_LL_DMA_H */
2270
2271
