1 /**
2 ******************************************************************************
3 * @file stm32g0xx_ll_cortex.h
4 * @author MCD Application Team
5 * @brief Header file of CORTEX LL module.
6 @verbatim
7 ==============================================================================
8 ##### How to use this driver #####
9 ==============================================================================
10 [..]
11 The LL CORTEX driver contains a set of generic APIs that can be
12 used by user:
13 (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
14 functions
15 (+) Low power mode configuration (SCB register of Cortex-MCU)
16 (+) MPU API to configure and enable regions
17 (+) API to access to MCU info (CPUID register)
18
19 @endverbatim
20 ******************************************************************************
21 * @attention
22 *
23 * Copyright (c) 2018 STMicroelectronics.
24 * All rights reserved.
25 *
26 * This software is licensed under terms that can be found in the LICENSE file in
27 * the root directory of this software component.
28 * If no LICENSE file comes with this software, it is provided AS-IS.
29 *
30 ******************************************************************************
31 */
32
33 /* Define to prevent recursive inclusion -------------------------------------*/
34 #ifndef STM32G0xx_LL_CORTEX_H
35 #define STM32G0xx_LL_CORTEX_H
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /* Includes ------------------------------------------------------------------*/
42 #include "stm32g0xx.h"
43
44 /** @addtogroup STM32G0xx_LL_Driver
45 * @{
46 */
47
48 /** @defgroup CORTEX_LL CORTEX
49 * @{
50 */
51
52 /* Private types -------------------------------------------------------------*/
53 /* Private variables ---------------------------------------------------------*/
54
55 /* Private constants ---------------------------------------------------------*/
56
57 /* Private macros ------------------------------------------------------------*/
58
59 /* Exported types ------------------------------------------------------------*/
60 /* Exported constants --------------------------------------------------------*/
61 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
62 * @{
63 */
64
65 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
66 * @{
67 */
68 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
69 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
70 /**
71 * @}
72 */
73
74 #if __MPU_PRESENT
75
76 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
77 * @{
78 */
79 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
80 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
81 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
82 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
83 /**
84 * @}
85 */
86
87 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
88 * @{
89 */
90 #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
91 #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
92 #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
93 #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
94 #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
95 #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
96 #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
97 #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
98 /**
99 * @}
100 */
101
102 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
103 * @{
104 */
105 #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
106 #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
107 #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
108 #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
109 #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
110 #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
111 #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
112 #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
113 #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
114 #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
115 #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
116 #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
117 #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
118 #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
119 #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
120 #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
121 #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
122 #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
123 #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
124 #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
125 #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
126 #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
127 #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
128 #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
129 #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
130 /**
131 * @}
132 */
133
134 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
135 * @{
136 */
137 #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
138 #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
139 #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
140 #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
141 #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
142 #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
143 /**
144 * @}
145 */
146
147 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
148 * @{
149 */
150 #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
151 #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
152 #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
153 #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
154 /**
155 * @}
156 */
157
158 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
159 * @{
160 */
161 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
162 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
163 /**
164 * @}
165 */
166
167 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
168 * @{
169 */
170 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
171 #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
172 /**
173 * @}
174 */
175
176 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
177 * @{
178 */
179 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
180 #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
181 /**
182 * @}
183 */
184
185 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
186 * @{
187 */
188 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
189 #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
190 /**
191 * @}
192 */
193 #endif /* __MPU_PRESENT */
194 /**
195 * @}
196 */
197
198 /* Exported macro ------------------------------------------------------------*/
199
200 /* Exported functions --------------------------------------------------------*/
201 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
202 * @{
203 */
204
205 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
206 * @{
207 */
208
209 /**
210 * @brief This function checks if the Systick counter flag is active or not.
211 * @note It can be used in timeout function on application side.
212 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
213 * @retval State of bit (1 or 0).
214 */
LL_SYSTICK_IsActiveCounterFlag(void)215 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
216 {
217 return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
218 }
219
220 /**
221 * @brief Configures the SysTick clock source
222 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
223 * @param Source This parameter can be one of the following values:
224 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
225 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
226 * @retval None
227 */
LL_SYSTICK_SetClkSource(uint32_t Source)228 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
229 {
230 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
231 {
232 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
233 }
234 else
235 {
236 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
237 }
238 }
239
240 /**
241 * @brief Get the SysTick clock source
242 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
243 * @retval Returned value can be one of the following values:
244 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
245 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
246 */
LL_SYSTICK_GetClkSource(void)247 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
248 {
249 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
250 }
251
252 /**
253 * @brief Enable SysTick exception request
254 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
255 * @retval None
256 */
LL_SYSTICK_EnableIT(void)257 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
258 {
259 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
260 }
261
262 /**
263 * @brief Disable SysTick exception request
264 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
265 * @retval None
266 */
LL_SYSTICK_DisableIT(void)267 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
268 {
269 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
270 }
271
272 /**
273 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
274 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
275 * @retval State of bit (1 or 0).
276 */
LL_SYSTICK_IsEnabledIT(void)277 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
278 {
279 return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
280 }
281
282 /**
283 * @}
284 */
285
286 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
287 * @{
288 */
289
290 /**
291 * @brief Processor uses sleep as its low power mode
292 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
293 * @retval None
294 */
LL_LPM_EnableSleep(void)295 __STATIC_INLINE void LL_LPM_EnableSleep(void)
296 {
297 /* Clear SLEEPDEEP bit of Cortex System Control Register */
298 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
299 }
300
301 /**
302 * @brief Processor uses deep sleep as its low power mode
303 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
304 * @retval None
305 */
LL_LPM_EnableDeepSleep(void)306 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
307 {
308 /* Set SLEEPDEEP bit of Cortex System Control Register */
309 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
310 }
311
312 /**
313 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
314 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
315 * empty main application.
316 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
317 * @retval None
318 */
LL_LPM_EnableSleepOnExit(void)319 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
320 {
321 /* Set SLEEPONEXIT bit of Cortex System Control Register */
322 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
323 }
324
325 /**
326 * @brief Do not sleep when returning to Thread mode.
327 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
328 * @retval None
329 */
LL_LPM_DisableSleepOnExit(void)330 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
331 {
332 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
333 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
334 }
335
336 /**
337 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
338 * processor.
339 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
340 * @retval None
341 */
LL_LPM_EnableEventOnPend(void)342 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
343 {
344 /* Set SEVEONPEND bit of Cortex System Control Register */
345 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
346 }
347
348 /**
349 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
350 * excluded
351 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
352 * @retval None
353 */
LL_LPM_DisableEventOnPend(void)354 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
355 {
356 /* Clear SEVEONPEND bit of Cortex System Control Register */
357 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
358 }
359
360 /**
361 * @}
362 */
363
364 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
365 * @{
366 */
367
368 /**
369 * @brief Get Implementer code
370 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
371 * @retval Value should be equal to 0x41 for ARM
372 */
LL_CPUID_GetImplementer(void)373 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
374 {
375 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
376 }
377
378 /**
379 * @brief Get Variant number (The r value in the rnpn product revision identifier)
380 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
381 * @retval Value between 0 and 255 (0x0: revision 0)
382 */
LL_CPUID_GetVariant(void)383 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
384 {
385 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
386 }
387
388 /**
389 * @brief Get Architecture number
390 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture
391 * @retval Value should be equal to 0xC for Cortex-M0+ devices
392 */
LL_CPUID_GetArchitecture(void)393 __STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
394 {
395 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
396 }
397
398 /**
399 * @brief Get Part number
400 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
401 * @retval Value should be equal to 0xC60 for Cortex-M0+
402 */
LL_CPUID_GetParNo(void)403 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
404 {
405 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
406 }
407
408 /**
409 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
410 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
411 * @retval Value between 0 and 255 (0x1: patch 1)
412 */
LL_CPUID_GetRevision(void)413 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
414 {
415 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
416 }
417
418 /**
419 * @}
420 */
421
422 #if __MPU_PRESENT
423 /** @defgroup CORTEX_LL_EF_MPU MPU
424 * @{
425 */
426
427 /**
428 * @brief Enable MPU with input options
429 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
430 * @param Options This parameter can be one of the following values:
431 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
432 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
433 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
434 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
435 * @retval None
436 */
LL_MPU_Enable(uint32_t Options)437 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
438 {
439 /* Enable the MPU*/
440 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
441 /* Ensure MPU settings take effects */
442 __DSB();
443 /* Sequence instruction fetches using update settings */
444 __ISB();
445 }
446
447 /**
448 * @brief Disable MPU
449 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
450 * @retval None
451 */
LL_MPU_Disable(void)452 __STATIC_INLINE void LL_MPU_Disable(void)
453 {
454 /* Make sure outstanding transfers are done */
455 __DMB();
456 /* Disable MPU*/
457 WRITE_REG(MPU->CTRL, 0U);
458 }
459
460 /**
461 * @brief Check if MPU is enabled or not
462 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
463 * @retval State of bit (1 or 0).
464 */
LL_MPU_IsEnabled(void)465 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
466 {
467 return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
468 }
469
470 /**
471 * @brief Enable a MPU region
472 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
473 * @param Region This parameter can be one of the following values:
474 * @arg @ref LL_MPU_REGION_NUMBER0
475 * @arg @ref LL_MPU_REGION_NUMBER1
476 * @arg @ref LL_MPU_REGION_NUMBER2
477 * @arg @ref LL_MPU_REGION_NUMBER3
478 * @arg @ref LL_MPU_REGION_NUMBER4
479 * @arg @ref LL_MPU_REGION_NUMBER5
480 * @arg @ref LL_MPU_REGION_NUMBER6
481 * @arg @ref LL_MPU_REGION_NUMBER7
482 * @retval None
483 */
LL_MPU_EnableRegion(uint32_t Region)484 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
485 {
486 /* Set Region number */
487 WRITE_REG(MPU->RNR, Region);
488 /* Enable the MPU region */
489 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
490 }
491
492 /**
493 * @brief Configure and enable a region
494 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
495 * MPU_RBAR REGION LL_MPU_ConfigRegion\n
496 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
497 * MPU_RASR XN LL_MPU_ConfigRegion\n
498 * MPU_RASR AP LL_MPU_ConfigRegion\n
499 * MPU_RASR S LL_MPU_ConfigRegion\n
500 * MPU_RASR C LL_MPU_ConfigRegion\n
501 * MPU_RASR B LL_MPU_ConfigRegion\n
502 * MPU_RASR SIZE LL_MPU_ConfigRegion
503 * @param Region This parameter can be one of the following values:
504 * @arg @ref LL_MPU_REGION_NUMBER0
505 * @arg @ref LL_MPU_REGION_NUMBER1
506 * @arg @ref LL_MPU_REGION_NUMBER2
507 * @arg @ref LL_MPU_REGION_NUMBER3
508 * @arg @ref LL_MPU_REGION_NUMBER4
509 * @arg @ref LL_MPU_REGION_NUMBER5
510 * @arg @ref LL_MPU_REGION_NUMBER6
511 * @arg @ref LL_MPU_REGION_NUMBER7
512 * @param Address Value of region base address
513 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
514 * @param Attributes This parameter can be a combination of the following values:
515 * @arg @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
516 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
517 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
518 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
519 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
520 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
521 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
522 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
523 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
524 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
525 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
526 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
527 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
528 * @retval None
529 */
LL_MPU_ConfigRegion(uint32_t Region,uint32_t SubRegionDisable,uint32_t Address,uint32_t Attributes)530 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
531 {
532 /* Set Region number */
533 WRITE_REG(MPU->RNR, Region);
534 /* Set base address */
535 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
536 /* Configure MPU */
537 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
538 }
539
540 /**
541 * @brief Disable a region
542 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
543 * MPU_RASR ENABLE LL_MPU_DisableRegion
544 * @param Region This parameter can be one of the following values:
545 * @arg @ref LL_MPU_REGION_NUMBER0
546 * @arg @ref LL_MPU_REGION_NUMBER1
547 * @arg @ref LL_MPU_REGION_NUMBER2
548 * @arg @ref LL_MPU_REGION_NUMBER3
549 * @arg @ref LL_MPU_REGION_NUMBER4
550 * @arg @ref LL_MPU_REGION_NUMBER5
551 * @arg @ref LL_MPU_REGION_NUMBER6
552 * @arg @ref LL_MPU_REGION_NUMBER7
553 * @retval None
554 */
LL_MPU_DisableRegion(uint32_t Region)555 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
556 {
557 /* Set Region number */
558 WRITE_REG(MPU->RNR, Region);
559 /* Disable the MPU region */
560 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
561 }
562
563 /**
564 * @}
565 */
566
567 #endif /* __MPU_PRESENT */
568 /**
569 * @}
570 */
571
572 /**
573 * @}
574 */
575
576 /**
577 * @}
578 */
579
580 #ifdef __cplusplus
581 }
582 #endif
583
584 #endif /* STM32G0xx_LL_CORTEX_H */
585
586
