1 /** 2 ****************************************************************************** 3 * @file stm32g0xx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2018 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32G0xx_HAL_DMA_H 21 #define STM32G0xx_HAL_DMA_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32g0xx_hal_def.h" 29 #include "stm32g0xx_ll_dma.h" 30 31 /** @addtogroup STM32G0xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup DMA 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup DMA_Exported_Types DMA Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief DMA Configuration Structure definition 46 */ 47 typedef struct 48 { 49 uint32_t Request; /*!< Specifies the request selected for the specified channel. 50 This parameter can be a value of @ref DMA_request */ 51 52 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 53 from memory to memory or from peripheral to memory. 54 This parameter can be a value of @ref DMA_Data_transfer_direction */ 55 56 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 57 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 58 59 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 60 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 61 62 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 63 This parameter can be a value of @ref DMA_Peripheral_data_size */ 64 65 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 66 This parameter can be a value of @ref DMA_Memory_data_size */ 67 68 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. 69 This parameter can be a value of @ref DMA_mode 70 @note The circular buffer mode cannot be used if the memory-to-memory 71 data transfer is configured on the selected Channel */ 72 73 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. 74 This parameter can be a value of @ref DMA_Priority_level */ 75 } DMA_InitTypeDef; 76 77 /** 78 * @brief HAL DMA State structures definition 79 */ 80 typedef enum 81 { 82 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 83 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 84 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 85 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ 86 } HAL_DMA_StateTypeDef; 87 88 /** 89 * @brief HAL DMA Error Code structure definition 90 */ 91 typedef enum 92 { 93 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 94 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ 95 } HAL_DMA_LevelCompleteTypeDef; 96 97 /** 98 * @brief HAL DMA Callback ID structure definition 99 */ 100 typedef enum 101 { 102 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 103 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ 104 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ 105 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ 106 HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ 107 108 } HAL_DMA_CallbackIDTypeDef; 109 110 /** 111 * @brief DMA handle Structure definition 112 */ 113 typedef struct __DMA_HandleTypeDef 114 { 115 DMA_Channel_TypeDef *Instance; /*!< Register base address */ 116 117 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 118 119 HAL_LockTypeDef Lock; /*!< DMA locking object */ 120 121 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 122 123 void *Parent; /*!< Parent object state */ 124 125 void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ 126 127 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */ 128 129 void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ 130 131 void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */ 132 133 __IO uint32_t ErrorCode; /*!< DMA Error code */ 134 135 #if defined(DMA2) 136 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ 137 138 #endif /* DMA2 */ 139 uint32_t ChannelIndex; /*!< DMA Channel Index */ 140 141 DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ 142 143 DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ 144 145 uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ 146 147 DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ 148 149 DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */ 150 151 uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ 152 } DMA_HandleTypeDef; 153 /** 154 * @} 155 */ 156 157 /* Exported constants --------------------------------------------------------*/ 158 159 /** @defgroup DMA_Exported_Constants DMA Exported Constants 160 * @{ 161 */ 162 163 /** @defgroup DMA_Error_Code DMA Error Code 164 * @{ 165 */ 166 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ 167 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ 168 #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ 169 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 170 #define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */ 171 #define HAL_DMA_ERROR_BUSY 0x00000080U /*!< DMA Busy error */ 172 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ 173 #define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */ 174 #define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */ 175 176 /** 177 * @} 178 */ 179 180 /** @defgroup DMA_request DMA request 181 * @{ 182 */ 183 #define DMA_REQUEST_MEM2MEM LL_DMAMUX_REQ_MEM2MEM /*!< memory to memory transfer */ 184 #define DMA_REQUEST_GENERATOR0 LL_DMAMUX_REQ_GENERATOR0 /*!< DMAMUX request generator 0 */ 185 #define DMA_REQUEST_GENERATOR1 LL_DMAMUX_REQ_GENERATOR1 /*!< DMAMUX request generator 1 */ 186 #define DMA_REQUEST_GENERATOR2 LL_DMAMUX_REQ_GENERATOR2 /*!< DMAMUX request generator 2 */ 187 #define DMA_REQUEST_GENERATOR3 LL_DMAMUX_REQ_GENERATOR3 /*!< DMAMUX request generator 3 */ 188 #define DMA_REQUEST_ADC1 LL_DMAMUX_REQ_ADC1 /*!< DMAMUX ADC1 request */ 189 #if defined(AES) 190 #define DMA_REQUEST_AES_IN LL_DMAMUX_REQ_AES_IN /*!< DMAMUX AES_IN request */ 191 #define DMA_REQUEST_AES_OUT LL_DMAMUX_REQ_AES_OUT /*!< DMAMUX AES_OUT request */ 192 #endif /* AES */ 193 #if defined(DAC1) 194 #define DMA_REQUEST_DAC1_CH1 LL_DMAMUX_REQ_DAC1_CH1 /*!< DMAMUX DAC_CH1 request */ 195 #define DMA_REQUEST_DAC1_CH2 LL_DMAMUX_REQ_DAC1_CH2 /*!< DMAMUX DAC_CH2 request */ 196 #endif /* DAC1 */ 197 #define DMA_REQUEST_I2C1_RX LL_DMAMUX_REQ_I2C1_RX /*!< DMAMUX I2C1 RX request */ 198 #define DMA_REQUEST_I2C1_TX LL_DMAMUX_REQ_I2C1_TX /*!< DMAMUX I2C1 TX request */ 199 #define DMA_REQUEST_I2C2_RX LL_DMAMUX_REQ_I2C2_RX /*!< DMAMUX I2C2 RX request */ 200 #define DMA_REQUEST_I2C2_TX LL_DMAMUX_REQ_I2C2_TX /*!< DMAMUX I2C2 TX request */ 201 #if defined(LPUART1) 202 #define DMA_REQUEST_LPUART1_RX LL_DMAMUX_REQ_LPUART1_RX /*!< DMAMUX LPUART1 RX request */ 203 #define DMA_REQUEST_LPUART1_TX LL_DMAMUX_REQ_LPUART1_TX /*!< DMAMUX LPUART1 TX request */ 204 #endif /* LPUART1 */ 205 #define DMA_REQUEST_SPI1_RX LL_DMAMUX_REQ_SPI1_RX /*!< DMAMUX SPI1 RX request */ 206 #define DMA_REQUEST_SPI1_TX LL_DMAMUX_REQ_SPI1_TX /*!< DMAMUX SPI1 TX request */ 207 #define DMA_REQUEST_SPI2_RX LL_DMAMUX_REQ_SPI2_RX /*!< DMAMUX SPI2 RX request */ 208 #define DMA_REQUEST_SPI2_TX LL_DMAMUX_REQ_SPI2_TX /*!< DMAMUX SPI2 TX request */ 209 #define DMA_REQUEST_TIM1_CH1 LL_DMAMUX_REQ_TIM1_CH1 /*!< DMAMUX TIM1 CH1 request */ 210 #define DMA_REQUEST_TIM1_CH2 LL_DMAMUX_REQ_TIM1_CH2 /*!< DMAMUX TIM1 CH2 request */ 211 #define DMA_REQUEST_TIM1_CH3 LL_DMAMUX_REQ_TIM1_CH3 /*!< DMAMUX TIM1 CH3 request */ 212 #define DMA_REQUEST_TIM1_CH4 LL_DMAMUX_REQ_TIM1_CH4 /*!< DMAMUX TIM1 CH4 request */ 213 #define DMA_REQUEST_TIM1_TRIG_COM LL_DMAMUX_REQ_TIM1_TRIG_COM /*!< DMAMUX TIM1 TRIG COM request */ 214 #define DMA_REQUEST_TIM1_UP LL_DMAMUX_REQ_TIM1_UP /*!< DMAMUX TIM1 UP request */ 215 #if defined(TIM2) 216 #define DMA_REQUEST_TIM2_CH1 LL_DMAMUX_REQ_TIM2_CH1 /*!< DMAMUX TIM2 CH1 request */ 217 #define DMA_REQUEST_TIM2_CH2 LL_DMAMUX_REQ_TIM2_CH2 /*!< DMAMUX TIM2 CH2 request */ 218 #define DMA_REQUEST_TIM2_CH3 LL_DMAMUX_REQ_TIM2_CH3 /*!< DMAMUX TIM2 CH3 request */ 219 #define DMA_REQUEST_TIM2_CH4 LL_DMAMUX_REQ_TIM2_CH4 /*!< DMAMUX TIM2 CH4 request */ 220 #define DMA_REQUEST_TIM2_TRIG LL_DMAMUX_REQ_TIM2_TRIG /*!< DMAMUX TIM2 TRIG request */ 221 #define DMA_REQUEST_TIM2_UP LL_DMAMUX_REQ_TIM2_UP /*!< DMAMUX TIM2 UP request */ 222 #endif /* TIM2 */ 223 #define DMA_REQUEST_TIM3_CH1 LL_DMAMUX_REQ_TIM3_CH1 /*!< DMAMUX TIM3 CH1 request */ 224 #define DMA_REQUEST_TIM3_CH2 LL_DMAMUX_REQ_TIM3_CH2 /*!< DMAMUX TIM3 CH2 request */ 225 #define DMA_REQUEST_TIM3_CH3 LL_DMAMUX_REQ_TIM3_CH3 /*!< DMAMUX TIM3 CH3 request */ 226 #define DMA_REQUEST_TIM3_CH4 LL_DMAMUX_REQ_TIM3_CH4 /*!< DMAMUX TIM3 CH4 request */ 227 #define DMA_REQUEST_TIM3_TRIG LL_DMAMUX_REQ_TIM3_TRIG /*!< DMAMUX TIM3 TRIG request */ 228 #define DMA_REQUEST_TIM3_UP LL_DMAMUX_REQ_TIM3_UP /*!< DMAMUX TIM3 UP request */ 229 #if defined(TIM6) 230 #define DMA_REQUEST_TIM6_UP LL_DMAMUX_REQ_TIM6_UP /*!< DMAMUX TIM6 UP request */ 231 #endif /* TIM6 */ 232 #if defined(TIM7) 233 #define DMA_REQUEST_TIM7_UP LL_DMAMUX_REQ_TIM7_UP /*!< DMAMUX TIM7 UP request */ 234 #endif /* TIM7 */ 235 #if defined(TIM15) 236 #define DMA_REQUEST_TIM15_CH1 LL_DMAMUX_REQ_TIM15_CH1 /*!< DMAMUX TIM15 CH1 request */ 237 #define DMA_REQUEST_TIM15_CH2 LL_DMAMUX_REQ_TIM15_CH2 /*!< DMAMUX TIM15 CH2 request */ 238 #define DMA_REQUEST_TIM15_TRIG_COM LL_DMAMUX_REQ_TIM15_TRIG_COM /*!< DMAMUX TIM15 TRIG COM request */ 239 #define DMA_REQUEST_TIM15_UP LL_DMAMUX_REQ_TIM15_UP /*!< DMAMUX TIM15 UP request */ 240 #endif /* TIM15 */ 241 #define DMA_REQUEST_TIM16_CH1 LL_DMAMUX_REQ_TIM16_CH1 /*!< DMAMUX TIM16 CH1 request */ 242 #define DMA_REQUEST_TIM16_COM LL_DMAMUX_REQ_TIM16_COM /*!< DMAMUX TIM16 COM request */ 243 #define DMA_REQUEST_TIM16_UP LL_DMAMUX_REQ_TIM16_UP /*!< DMAMUX TIM16 UP request */ 244 #define DMA_REQUEST_TIM17_CH1 LL_DMAMUX_REQ_TIM17_CH1 /*!< DMAMUX TIM17 CH1 request */ 245 #define DMA_REQUEST_TIM17_COM LL_DMAMUX_REQ_TIM17_COM /*!< DMAMUX TIM17 COM request */ 246 #define DMA_REQUEST_TIM17_UP LL_DMAMUX_REQ_TIM17_UP /*!< DMAMUX TIM17 UP request */ 247 #define DMA_REQUEST_USART1_RX LL_DMAMUX_REQ_USART1_RX /*!< DMAMUX USART1 RX request */ 248 #define DMA_REQUEST_USART1_TX LL_DMAMUX_REQ_USART1_TX /*!< DMAMUX USART1 TX request */ 249 #define DMA_REQUEST_USART2_RX LL_DMAMUX_REQ_USART2_RX /*!< DMAMUX USART2 RX request */ 250 #define DMA_REQUEST_USART2_TX LL_DMAMUX_REQ_USART2_TX /*!< DMAMUX USART2 TX request */ 251 #if defined(USART3) 252 #define DMA_REQUEST_USART3_RX LL_DMAMUX_REQ_USART3_RX /*!< DMAMUX USART3 RX request */ 253 #define DMA_REQUEST_USART3_TX LL_DMAMUX_REQ_USART3_TX /*!< DMAMUX USART3 TX request */ 254 #endif /* USART3 */ 255 #if defined(USART4) 256 #define DMA_REQUEST_USART4_RX LL_DMAMUX_REQ_USART4_RX /*!< DMAMUX USART4 RX request */ 257 #define DMA_REQUEST_USART4_TX LL_DMAMUX_REQ_USART4_TX /*!< DMAMUX USART4 TX request */ 258 #endif /* USART4 */ 259 #if defined(UCPD1) 260 #define DMA_REQUEST_UCPD1_RX LL_DMAMUX_REQ_UCPD1_RX /*!< DMAMUX UCPD1 RX request */ 261 #define DMA_REQUEST_UCPD1_TX LL_DMAMUX_REQ_UCPD1_TX /*!< DMAMUX UCPD1 TX request */ 262 #endif/* UCPD1 */ 263 #if defined(UCPD2) 264 #define DMA_REQUEST_UCPD2_RX LL_DMAMUX_REQ_UCPD2_RX /*!< DMAMUX UCPD2 RX request */ 265 #define DMA_REQUEST_UCPD2_TX LL_DMAMUX_REQ_UCPD2_TX /*!< DMAMUX UCPD2 TX request */ 266 #endif /* UCPD2 */ 267 268 #if defined(I2C3) 269 #define DMA_REQUEST_I2C3_RX LL_DMAMUX_REQ_I2C3_RX /*!< DMAMUX I2C3 RX request */ 270 #define DMA_REQUEST_I2C3_TX LL_DMAMUX_REQ_I2C3_TX /*!< DMAMUX I2C3 TX request */ 271 #endif /* I2C3 */ 272 273 #if defined(LPUART2) 274 #define DMA_REQUEST_LPUART2_RX LL_DMAMUX_REQ_LPUART2_RX /*!< DMAMUX LPUART2 RX request */ 275 #define DMA_REQUEST_LPUART2_TX LL_DMAMUX_REQ_LPUART2_TX /*!< DMAMUX LPUART2 TX request */ 276 #endif /* LPUART2 */ 277 278 #if defined(SPI3) 279 #define DMA_REQUEST_SPI3_RX LL_DMAMUX_REQ_SPI3_RX /*!< DMAMUX SPI3 RX request */ 280 #define DMA_REQUEST_SPI3_TX LL_DMAMUX_REQ_SPI3_TX /*!< DMAMUX SPI3 TX request */ 281 #endif /* SPI3 */ 282 283 #if defined(TIM4) 284 #define DMA_REQUEST_TIM4_CH1 LL_DMAMUX_REQ_TIM4_CH1 /*!< DMAMUX TIM4 CH1 request */ 285 #define DMA_REQUEST_TIM4_CH2 LL_DMAMUX_REQ_TIM4_CH2 /*!< DMAMUX TIM4 CH2 request */ 286 #define DMA_REQUEST_TIM4_CH3 LL_DMAMUX_REQ_TIM4_CH3 /*!< DMAMUX TIM4 CH3 request */ 287 #define DMA_REQUEST_TIM4_CH4 LL_DMAMUX_REQ_TIM4_CH4 /*!< DMAMUX TIM4 CH4 request */ 288 #define DMA_REQUEST_TIM4_TRIG LL_DMAMUX_REQ_TIM4_TRIG /*!< DMAMUX TIM4 TRIG request */ 289 #define DMA_REQUEST_TIM4_UP LL_DMAMUX_REQ_TIM4_UP /*!< DMAMUX TIM4 UP request */ 290 #endif /* TIM4 */ 291 292 #if defined(USART5) 293 #define DMA_REQUEST_USART5_RX LL_DMAMUX_REQ_USART5_RX /*!< DMAMUX USART5 RX request */ 294 #define DMA_REQUEST_USART5_TX LL_DMAMUX_REQ_USART5_TX /*!< DMAMUX USART5 TX request */ 295 #endif /* USART5 */ 296 297 #if defined(USART6) 298 #define DMA_REQUEST_USART6_RX LL_DMAMUX_REQ_USART6_RX /*!< DMAMUX USART6 RX request */ 299 #define DMA_REQUEST_USART6_TX LL_DMAMUX_REQ_USART6_TX /*!< DMAMUX USART6 TX request */ 300 #endif /* USART6 */ 301 302 303 #define DMA_MAX_REQUEST LL_DMAMUX_MAX_REQ 304 /** 305 * @} 306 */ 307 308 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 309 * @{ 310 */ 311 #define DMA_PERIPH_TO_MEMORY LL_DMA_DIRECTION_PERIPH_TO_MEMORY /*!< Peripheral to memory direction */ 312 #define DMA_MEMORY_TO_PERIPH LL_DMA_DIRECTION_MEMORY_TO_PERIPH /*!< Memory to peripheral direction */ 313 #define DMA_MEMORY_TO_MEMORY LL_DMA_DIRECTION_MEMORY_TO_MEMORY /*!< Memory to memory direction */ 314 315 /** 316 * @} 317 */ 318 319 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 320 * @{ 321 */ 322 #define DMA_PINC_ENABLE LL_DMA_PERIPH_INCREMENT /*!< Peripheral increment mode Enable */ 323 #define DMA_PINC_DISABLE LL_DMA_PERIPH_NOINCREMENT /*!< Peripheral increment mode Disable */ 324 /** 325 * @} 326 */ 327 328 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 329 * @{ 330 */ 331 #define DMA_MINC_ENABLE LL_DMA_MEMORY_INCREMENT /*!< Memory increment mode Enable */ 332 #define DMA_MINC_DISABLE LL_DMA_MEMORY_NOINCREMENT /*!< Memory increment mode Disable */ 333 /** 334 * @} 335 */ 336 337 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 338 * @{ 339 */ 340 #define DMA_PDATAALIGN_BYTE LL_DMA_PDATAALIGN_BYTE /*!< Peripheral data alignment : Byte */ 341 #define DMA_PDATAALIGN_HALFWORD LL_DMA_PDATAALIGN_HALFWORD /*!< Peripheral data alignment : HalfWord */ 342 #define DMA_PDATAALIGN_WORD LL_DMA_PDATAALIGN_WORD /*!< Peripheral data alignment : Word */ 343 /** 344 * @} 345 */ 346 347 /** @defgroup DMA_Memory_data_size DMA Memory data size 348 * @{ 349 */ 350 #define DMA_MDATAALIGN_BYTE LL_DMA_MDATAALIGN_BYTE /*!< Memory data alignment : Byte */ 351 #define DMA_MDATAALIGN_HALFWORD LL_DMA_MDATAALIGN_HALFWORD /*!< Memory data alignment : HalfWord */ 352 #define DMA_MDATAALIGN_WORD LL_DMA_MDATAALIGN_WORD /*!< Memory data alignment : Word */ 353 /** 354 * @} 355 */ 356 357 /** @defgroup DMA_mode DMA mode 358 * @{ 359 */ 360 #define DMA_NORMAL LL_DMA_MODE_NORMAL /*!< Normal mode */ 361 #define DMA_CIRCULAR LL_DMA_MODE_CIRCULAR /*!< Circular mode */ 362 /** 363 * @} 364 */ 365 366 /** @defgroup DMA_Priority_level DMA Priority level 367 * @{ 368 */ 369 #define DMA_PRIORITY_LOW LL_DMA_PRIORITY_LOW /*!< Priority level : Low */ 370 #define DMA_PRIORITY_MEDIUM LL_DMA_PRIORITY_MEDIUM /*!< Priority level : Medium */ 371 #define DMA_PRIORITY_HIGH LL_DMA_PRIORITY_HIGH /*!< Priority level : High */ 372 #define DMA_PRIORITY_VERY_HIGH LL_DMA_PRIORITY_VERYHIGH /*!< Priority level : Very_High */ 373 /** 374 * @} 375 */ 376 377 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 378 * @{ 379 */ 380 #define DMA_IT_TC DMA_CCR_TCIE /*!< Transfer Complete interrupt */ 381 #define DMA_IT_HT DMA_CCR_HTIE /*!< Half Transfer Complete interrupt */ 382 #define DMA_IT_TE DMA_CCR_TEIE /*!< Transfer Error interrupt */ 383 /** 384 * @} 385 */ 386 387 /** @defgroup DMA_flag_definitions DMA flag definitions 388 * @{ 389 */ 390 391 #define DMA_FLAG_GI1 DMA_ISR_GIF1 /*!< Global Interrupt flag for Channel 1 */ 392 #define DMA_FLAG_TC1 DMA_ISR_TCIF1 /*!< Transfer Complete flag for Channel 1 */ 393 #define DMA_FLAG_HT1 DMA_ISR_HTIF1 /*!< Half Transfer flag for Channel 1 */ 394 #define DMA_FLAG_TE1 DMA_ISR_TEIF1 /*!< Transfer Error flag for Channel 1 */ 395 #define DMA_FLAG_GI2 DMA_ISR_GIF2 /*!< Global Interrupt flag for Channel 2 */ 396 #define DMA_FLAG_TC2 DMA_ISR_TCIF2 /*!< Transfer Complete flag for Channel 2 */ 397 #define DMA_FLAG_HT2 DMA_ISR_HTIF2 /*!< Half Transfer flag for Channel 2 */ 398 #define DMA_FLAG_TE2 DMA_ISR_TEIF2 /*!< Transfer Error flag for Channel 2 */ 399 #define DMA_FLAG_GI3 DMA_ISR_GIF3 /*!< Global Interrupt flag for Channel 3 */ 400 #define DMA_FLAG_TC3 DMA_ISR_TCIF3 /*!< Transfer Complete flag for Channel 3 */ 401 #define DMA_FLAG_HT3 DMA_ISR_HTIF3 /*!< Half Transfer flag for Channel 3 */ 402 #define DMA_FLAG_TE3 DMA_ISR_TEIF3 /*!< Transfer Error flag for Channel 3 */ 403 #define DMA_FLAG_GI4 DMA_ISR_GIF4 /*!< Global Interrupt flag for Channel 4 */ 404 #define DMA_FLAG_TC4 DMA_ISR_TCIF4 /*!< Transfer Complete flag for Channel 4 */ 405 #define DMA_FLAG_HT4 DMA_ISR_HTIF4 /*!< Half Transfer flag for Channel 4 */ 406 #define DMA_FLAG_TE4 DMA_ISR_TEIF4 /*!< Transfer Error flag for Channel 4 */ 407 #define DMA_FLAG_GI5 DMA_ISR_GIF5 /*!< Global Interrupt flag for Channel 5 */ 408 #define DMA_FLAG_TC5 DMA_ISR_TCIF5 /*!< Transfer Complete flag for Channel 5 */ 409 #define DMA_FLAG_HT5 DMA_ISR_HTIF5 /*!< Half Transfer flag for Channel 5 */ 410 #define DMA_FLAG_TE5 DMA_ISR_TEIF5 /*!< Transfer Error for Channel 5 */ 411 #if defined(DMA1_Channel6) 412 #define DMA_FLAG_GI6 DMA_ISR_GIF6 /*!< Global Interrupt flag for Channel 6 */ 413 #define DMA_FLAG_TC6 DMA_ISR_TCIF6 /*!< Transfer Complete flag for Channel 6 */ 414 #define DMA_FLAG_HT6 DMA_ISR_HTIF6 /*!< Half Transfer flag for Channel 6 */ 415 #define DMA_FLAG_TE6 DMA_ISR_TEIF6 /*!< Transfer Error flag for Channel 6 */ 416 #endif /* DMA1_Channel6 */ 417 #if defined(DMA1_Channel7) 418 #define DMA_FLAG_GI7 DMA_ISR_GIF7 /*!< Global Interrupt flag for Channel 7 */ 419 #define DMA_FLAG_TC7 DMA_ISR_TCIF7 /*!< Transfer Complete flag for Channel 7 */ 420 #define DMA_FLAG_HT7 DMA_ISR_HTIF7 /*!< Half Transfer flag for Channel 7 */ 421 #define DMA_FLAG_TE7 DMA_ISR_TEIF7 /*!< Transfer Error flag for Channel 7 */ 422 #endif /* DMA1_Channel7 */ 423 /** 424 * @} 425 */ 426 427 /** 428 * @} 429 */ 430 431 /* Exported macros -----------------------------------------------------------*/ 432 /** @defgroup DMA_Exported_Macros DMA Exported Macros 433 * @{ 434 */ 435 436 /** @brief Reset DMA handle state 437 * @param __HANDLE__ DMA handle 438 * @retval None 439 */ 440 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 441 442 /** 443 * @brief Enable the specified DMA Channel. 444 * @param __HANDLE__ DMA handle 445 * @retval None 446 */ 447 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) 448 449 /** 450 * @brief Disable the specified DMA Channel. 451 * @param __HANDLE__ DMA handle 452 * @retval None 453 */ 454 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) 455 456 /** 457 * @brief Return the current DMA Channel transfer complete flag. 458 * @param __HANDLE__ DMA handle 459 * @retval The specified transfer complete flag index. 460 */ 461 #if defined(DMA2) 462 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 463 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 464 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ 465 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 466 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ 467 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 468 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ 469 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 470 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ 471 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ 472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ 473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ 474 DMA_FLAG_TC7) 475 #else /* DMA1 */ 476 #if defined(DMA1_Channel7) 477 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 478 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 479 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 480 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 481 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 482 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ 483 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ 484 DMA_FLAG_TC7) 485 #else 486 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 487 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 488 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 489 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 490 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 491 DMA_FLAG_TC5) 492 #endif /* DMA1_Channel8 */ 493 #endif /* DMA2 */ 494 495 /** 496 * @brief Return the current DMA Channel half transfer complete flag. 497 * @param __HANDLE__ DMA handle 498 * @retval The specified half transfer complete flag index. 499 */ 500 #if defined(DMA2) 501 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \ 502 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 503 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ 504 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 505 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ 506 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 507 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ 508 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 509 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ 510 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ 511 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ 512 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ 513 DMA_FLAG_HT7) 514 #else /* DMA1 */ 515 #if defined(DMA1_Channel7) 516 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \ 517 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 518 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 519 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 520 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 521 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ 522 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ 523 DMA_FLAG_HT7) 524 #else 525 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \ 526 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 527 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 528 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 529 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 530 DMA_FLAG_HT5) 531 #endif /* DMA1_Channel8 */ 532 #endif /* DMA2 */ 533 534 /** 535 * @brief Return the current DMA Channel transfer error flag. 536 * @param __HANDLE__ DMA handle 537 * @retval The specified transfer error flag index. 538 */ 539 #if defined(DMA2) 540 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \ 541 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 542 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ 543 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 544 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ 545 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 546 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ 547 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 548 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ 549 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ 550 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ 551 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ 552 DMA_FLAG_TE7) 553 #else /* DMA1 */ 554 #if defined(DMA1_Channel7) 555 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \ 556 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 557 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 558 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 559 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 560 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ 561 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ 562 DMA_FLAG_TE7) 563 #else 564 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \ 565 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 566 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 567 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 568 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 569 DMA_FLAG_TE5) 570 #endif /* DMA1_Channel8 */ 571 #endif /* DMA2 */ 572 573 /** 574 * @brief Return the current DMA Channel Global interrupt flag. 575 * @param __HANDLE__ DMA handle 576 * @retval The specified transfer error flag index. 577 */ 578 #if defined(DMA2) 579 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \ 580 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\ 581 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GI1 :\ 582 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\ 583 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GI2 :\ 584 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\ 585 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GI3 :\ 586 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\ 587 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GI4 :\ 588 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GI5 :\ 589 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_GI5 :\ 590 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GI6 :\ 591 DMA_FLAG_GI7) 592 #else /* DMA1 */ 593 #if defined(DMA1_Channel7) 594 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \ 595 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\ 596 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\ 597 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\ 598 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\ 599 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GI5 :\ 600 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GI6 :\ 601 DMA_FLAG_GI7) 602 #else 603 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \ 604 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\ 605 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\ 606 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\ 607 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\ 608 DMA_FLAG_GI5) 609 #endif /* DMA1_Channel8 */ 610 #endif /* DMA2 */ 611 612 /** 613 * @brief Get the DMA Channel pending flags. 614 * @param __HANDLE__ DMA handle 615 * @param __FLAG__ Get the specified flag. 616 * This parameter can be any combination of the following values: 617 * @arg DMA_FLAG_TCx: Transfer complete flag 618 * @arg DMA_FLAG_HTx: Half transfer complete flag 619 * @arg DMA_FLAG_TEx: Transfer error flag 620 * @arg DMA_FLAG_GIx: Global interrupt flag 621 * Where x can be 1 to max Channel supported by the product to select the DMA Channel flag. 622 * @retval The state of FLAG (SET or RESET). 623 */ 624 #if defined(DMA2) 625 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ 626 (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) 627 #else /* DMA1 */ 628 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) 629 #endif /* DMA2 */ 630 631 /** 632 * @brief Clear the DMA Channel pending flags. 633 * @param __HANDLE__ DMA handle 634 * @param __FLAG__ specifies the flag to clear. 635 * This parameter can be any combination of the following values: 636 * @arg DMA_FLAG_TCx: Transfer complete flag 637 * @arg DMA_FLAG_HTx: Half transfer complete flag 638 * @arg DMA_FLAG_TEx: Transfer error flag 639 * @arg DMA_FLAG_GIx: Global interrupt flag 640 * Where x can be 1 to max Channel supported by the product to select the DMA Channel flag. 641 * @retval None 642 */ 643 #if defined(DMA2) 644 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ 645 (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) 646 #else /* DMA1 */ 647 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR |= (__FLAG__)) 648 #endif /* DMA2 */ 649 650 /** 651 * @brief Enable the specified DMA Channel interrupts. 652 * @param __HANDLE__ DMA handle 653 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 654 * This parameter can be any combination of the following values: 655 * @arg DMA_IT_TC: Transfer complete interrupt mask 656 * @arg DMA_IT_HT: Half transfer complete interrupt mask 657 * @arg DMA_IT_TE: Transfer error interrupt mask 658 * @retval None 659 */ 660 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 661 662 /** 663 * @brief Disable the specified DMA Channel interrupts. 664 * @param __HANDLE__ DMA handle 665 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 666 * This parameter can be any combination of the following values: 667 * @arg DMA_IT_TC: Transfer complete interrupt mask 668 * @arg DMA_IT_HT: Half transfer complete interrupt mask 669 * @arg DMA_IT_TE: Transfer error interrupt mask 670 * @retval None 671 */ 672 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 673 674 /** 675 * @brief Check whether the specified DMA Channel interrupt is enabled or disabled. 676 * @param __HANDLE__ DMA handle 677 * @param __INTERRUPT__ specifies the DMA interrupt source to check. 678 * This parameter can be one of the following values: 679 * @arg DMA_IT_TC: Transfer complete interrupt mask 680 * @arg DMA_IT_HT: Half transfer complete interrupt mask 681 * @arg DMA_IT_TE: Transfer error interrupt mask 682 * @retval The state of DMA_IT (SET or RESET). 683 */ 684 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 685 686 /** 687 * @brief Returns the number of remaining data units in the current DMA Channel transfer. 688 * @param __HANDLE__ DMA handle 689 * @retval The number of remaining data units in the current DMA Channel transfer. 690 */ 691 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) 692 693 /** 694 * @} 695 */ 696 697 /* Include DMA HAL Extension module */ 698 #include "stm32g0xx_hal_dma_ex.h" 699 700 /* Exported functions --------------------------------------------------------*/ 701 702 /** @addtogroup DMA_Exported_Functions 703 * @{ 704 */ 705 706 /** @addtogroup DMA_Exported_Functions_Group1 707 * @{ 708 */ 709 /* Initialization and de-initialization functions *****************************/ 710 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 711 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); 712 /** 713 * @} 714 */ 715 716 /** @addtogroup DMA_Exported_Functions_Group2 717 * @{ 718 */ 719 /* IO operation functions *****************************************************/ 720 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 721 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, 722 uint32_t DataLength); 723 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 724 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 725 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, 726 uint32_t Timeout); 727 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 728 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); 729 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 730 731 /** 732 * @} 733 */ 734 735 /** @addtogroup DMA_Exported_Functions_Group3 736 * @{ 737 */ 738 /* Peripheral State and Error functions ***************************************/ 739 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 740 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 741 /** 742 * @} 743 */ 744 745 /** 746 * @} 747 */ 748 749 /* Private macros ------------------------------------------------------------*/ 750 /** @defgroup DMA_Private_Macros DMA Private Macros 751 * @{ 752 */ 753 754 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 755 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 756 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 757 758 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < DMA_CNDTR_NDT)) 759 760 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 761 ((STATE) == DMA_PINC_DISABLE)) 762 763 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 764 ((STATE) == DMA_MINC_DISABLE)) 765 766 #define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_MAX_REQUEST) 767 768 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 769 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 770 ((SIZE) == DMA_PDATAALIGN_WORD)) 771 772 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 773 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 774 ((SIZE) == DMA_MDATAALIGN_WORD )) 775 776 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 777 ((MODE) == DMA_CIRCULAR)) 778 779 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 780 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 781 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 782 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 783 784 /** 785 * @} 786 */ 787 788 /* Private functions ---------------------------------------------------------*/ 789 790 /** 791 * @} 792 */ 793 794 /** 795 * @} 796 */ 797 798 #ifdef __cplusplus 799 } 800 #endif 801 802 #endif /* STM32G0xx_HAL_DMA_H */ 803 804
