1 /** 2 ****************************************************************************** 3 * @file stm32g0xx_hal_cortex.h 4 * @author MCD Application Team 5 * @brief Header file of CORTEX HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2018 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32G0xx_HAL_CORTEX_H 21 #define STM32G0xx_HAL_CORTEX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32g0xx_hal_def.h" 29 30 /** @addtogroup STM32G0xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @defgroup CORTEX CORTEX 35 * @brief CORTEX HAL module driver 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types 41 * @{ 42 */ 43 44 #if (__MPU_PRESENT == 1) 45 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition 46 * @brief MPU Region initialization structure 47 * @{ 48 */ 49 typedef struct 50 { 51 uint8_t Enable; /*!< Specifies the status of the region. 52 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ 53 uint8_t Number; /*!< Specifies the number of the region to protect. 54 This parameter can be a value of @ref CORTEX_MPU_Region_Number */ 55 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. 56 */ 57 uint8_t Size; /*!< Specifies the size of the region to protect. 58 This parameter can be a value of @ref CORTEX_MPU_Region_Size */ 59 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. 60 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 61 uint8_t TypeExtField; /*!< Specifies the TEX field level. 62 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ 63 uint8_t AccessPermission; /*!< Specifies the region access permission type. 64 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ 65 uint8_t DisableExec; /*!< Specifies the instruction access status. 66 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ 67 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. 68 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ 69 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. 70 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ 71 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. 72 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ 73 } MPU_Region_InitTypeDef; 74 /** 75 * @} 76 */ 77 #endif /* __MPU_PRESENT */ 78 79 /** 80 * @} 81 */ 82 83 /* Exported constants --------------------------------------------------------*/ 84 85 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants 86 * @{ 87 */ 88 89 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source 90 * @{ 91 */ 92 #define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U 93 #define SYSTICK_CLKSOURCE_HCLK 0x00000004U 94 95 /** 96 * @} 97 */ 98 99 #if (__MPU_PRESENT == 1) 100 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control 101 * @{ 102 */ 103 #define MPU_HFNMI_PRIVDEF_NONE 0x00000000U 104 #define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk) 105 #define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk) 106 #define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) 107 /** 108 * @} 109 */ 110 111 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable 112 * @{ 113 */ 114 #define MPU_REGION_ENABLE ((uint8_t)0x01) 115 #define MPU_REGION_DISABLE ((uint8_t)0x00) 116 /** 117 * @} 118 */ 119 120 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access 121 * @{ 122 */ 123 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) 124 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) 125 /** 126 * @} 127 */ 128 129 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable 130 * @{ 131 */ 132 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) 133 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) 134 /** 135 * @} 136 */ 137 138 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable 139 * @{ 140 */ 141 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) 142 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) 143 /** 144 * @} 145 */ 146 147 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable 148 * @{ 149 */ 150 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) 151 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) 152 /** 153 * @} 154 */ 155 156 /** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels 157 * @{ 158 */ 159 #define MPU_TEX_LEVEL0 ((uint8_t)0x00) 160 #define MPU_TEX_LEVEL1 ((uint8_t)0x01) 161 #define MPU_TEX_LEVEL2 ((uint8_t)0x02) 162 /** 163 * @} 164 */ 165 166 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size 167 * @{ 168 */ 169 #define MPU_REGION_SIZE_256B ((uint8_t)0x07) 170 #define MPU_REGION_SIZE_512B ((uint8_t)0x08) 171 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) 172 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) 173 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) 174 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) 175 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) 176 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) 177 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) 178 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) 179 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) 180 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) 181 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13) 182 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14) 183 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15) 184 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16) 185 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) 186 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) 187 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) 188 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) 189 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) 190 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) 191 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) 192 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) 193 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) 194 /** 195 * @} 196 */ 197 198 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 199 * @{ 200 */ 201 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) 202 #define MPU_REGION_PRIV_RW ((uint8_t)0x01) 203 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) 204 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) 205 #define MPU_REGION_PRIV_RO ((uint8_t)0x05) 206 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) 207 /** 208 * @} 209 */ 210 211 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number 212 * @{ 213 */ 214 #define MPU_REGION_NUMBER0 ((uint8_t)0x00) 215 #define MPU_REGION_NUMBER1 ((uint8_t)0x01) 216 #define MPU_REGION_NUMBER2 ((uint8_t)0x02) 217 #define MPU_REGION_NUMBER3 ((uint8_t)0x03) 218 #define MPU_REGION_NUMBER4 ((uint8_t)0x04) 219 #define MPU_REGION_NUMBER5 ((uint8_t)0x05) 220 #define MPU_REGION_NUMBER6 ((uint8_t)0x06) 221 #define MPU_REGION_NUMBER7 ((uint8_t)0x07) 222 /** 223 * @} 224 */ 225 #endif /* __MPU_PRESENT */ 226 227 /** 228 * @} 229 */ 230 231 /* Exported macros -----------------------------------------------------------*/ 232 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros 233 * @{ 234 */ 235 236 /** 237 * @} 238 */ 239 240 /* Exported functions --------------------------------------------------------*/ 241 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions 242 * @{ 243 */ 244 245 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions 246 * @brief Initialization and Configuration functions 247 * @{ 248 */ 249 /* Initialization and Configuration functions *****************************/ 250 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); 251 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 252 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); 253 void HAL_NVIC_SystemReset(void); 254 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); 255 /** 256 * @} 257 */ 258 259 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 260 * @brief Cortex control functions 261 * @{ 262 */ 263 /* Peripheral Control functions *************************************************/ 264 uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn); 265 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); 266 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); 267 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); 268 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); 269 void HAL_SYSTICK_IRQHandler(void); 270 void HAL_SYSTICK_Callback(void); 271 272 #if (__MPU_PRESENT == 1U) 273 void HAL_MPU_Enable(uint32_t MPU_Control); 274 void HAL_MPU_Disable(void); 275 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); 276 #endif /* __MPU_PRESENT */ 277 /** 278 * @} 279 */ 280 281 /** 282 * @} 283 */ 284 285 /* Private types -------------------------------------------------------------*/ 286 /* Private variables ---------------------------------------------------------*/ 287 /* Private constants ---------------------------------------------------------*/ 288 /* Private macros ------------------------------------------------------------*/ 289 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 290 * @{ 291 */ 292 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4U) 293 294 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn) 295 296 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ 297 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) 298 299 #if (__MPU_PRESENT == 1) 300 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ 301 ((STATE) == MPU_REGION_DISABLE)) 302 303 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ 304 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) 305 306 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ 307 ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) 308 309 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ 310 ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) 311 312 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ 313 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) 314 315 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ 316 ((TYPE) == MPU_TEX_LEVEL1) || \ 317 ((TYPE) == MPU_TEX_LEVEL2)) 318 319 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ 320 ((TYPE) == MPU_REGION_PRIV_RW) || \ 321 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ 322 ((TYPE) == MPU_REGION_FULL_ACCESS) || \ 323 ((TYPE) == MPU_REGION_PRIV_RO) || \ 324 ((TYPE) == MPU_REGION_PRIV_RO_URO)) 325 326 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 327 ((NUMBER) == MPU_REGION_NUMBER1) || \ 328 ((NUMBER) == MPU_REGION_NUMBER2) || \ 329 ((NUMBER) == MPU_REGION_NUMBER3) || \ 330 ((NUMBER) == MPU_REGION_NUMBER4) || \ 331 ((NUMBER) == MPU_REGION_NUMBER5) || \ 332 ((NUMBER) == MPU_REGION_NUMBER6) || \ 333 ((NUMBER) == MPU_REGION_NUMBER7)) 334 335 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_256B) || \ 336 ((SIZE) == MPU_REGION_SIZE_512B) || \ 337 ((SIZE) == MPU_REGION_SIZE_1KB) || \ 338 ((SIZE) == MPU_REGION_SIZE_2KB) || \ 339 ((SIZE) == MPU_REGION_SIZE_4KB) || \ 340 ((SIZE) == MPU_REGION_SIZE_8KB) || \ 341 ((SIZE) == MPU_REGION_SIZE_16KB) || \ 342 ((SIZE) == MPU_REGION_SIZE_32KB) || \ 343 ((SIZE) == MPU_REGION_SIZE_64KB) || \ 344 ((SIZE) == MPU_REGION_SIZE_128KB) || \ 345 ((SIZE) == MPU_REGION_SIZE_256KB) || \ 346 ((SIZE) == MPU_REGION_SIZE_512KB) || \ 347 ((SIZE) == MPU_REGION_SIZE_1MB) || \ 348 ((SIZE) == MPU_REGION_SIZE_2MB) || \ 349 ((SIZE) == MPU_REGION_SIZE_4MB) || \ 350 ((SIZE) == MPU_REGION_SIZE_8MB) || \ 351 ((SIZE) == MPU_REGION_SIZE_16MB) || \ 352 ((SIZE) == MPU_REGION_SIZE_32MB) || \ 353 ((SIZE) == MPU_REGION_SIZE_64MB) || \ 354 ((SIZE) == MPU_REGION_SIZE_128MB) || \ 355 ((SIZE) == MPU_REGION_SIZE_256MB) || \ 356 ((SIZE) == MPU_REGION_SIZE_512MB) || \ 357 ((SIZE) == MPU_REGION_SIZE_1GB) || \ 358 ((SIZE) == MPU_REGION_SIZE_2GB) || \ 359 ((SIZE) == MPU_REGION_SIZE_4GB)) 360 361 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU) 362 #endif /* __MPU_PRESENT */ 363 364 /** 365 * @} 366 */ 367 368 /* Private functions ---------------------------------------------------------*/ 369 370 /** 371 * @} 372 */ 373 374 /** 375 * @} 376 */ 377 378 #ifdef __cplusplus 379 } 380 #endif 381 382 #endif /* STM32G0xx_HAL_CORTEX_H */ 383 384 385
