1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_utils.c
4 * @author MCD Application Team
5 * @brief UTILS LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 /* Includes ------------------------------------------------------------------*/
19 #include "stm32f7xx_ll_utils.h"
20 #include "stm32f7xx_ll_rcc.h"
21 #include "stm32f7xx_ll_system.h"
22 #include "stm32f7xx_ll_pwr.h"
23 #ifdef USE_FULL_ASSERT
24 #include "stm32_assert.h"
25 #else
26 #define assert_param(expr) ((void)0U)
27 #endif /* USE_FULL_ASSERT */
28
29 /** @addtogroup STM32F7xx_LL_Driver
30 * @{
31 */
32
33 /** @addtogroup UTILS_LL
34 * @{
35 */
36
37 /* Private types -------------------------------------------------------------*/
38 /* Private variables ---------------------------------------------------------*/
39 /* Private constants ---------------------------------------------------------*/
40 /** @addtogroup UTILS_LL_Private_Constants
41 * @{
42 */
43 #define UTILS_MAX_FREQUENCY_SCALE1 216000000U /*!< Maximum frequency for system clock at power scale1, in Hz */
44 #define UTILS_MAX_FREQUENCY_SCALE2 180000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
45 #define UTILS_MAX_FREQUENCY_SCALE3 144000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
46
47 /* Defines used for PLL range */
48 #define UTILS_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
49 #define UTILS_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
50 #define UTILS_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
51 #define UTILS_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
52
53 /* Defines used for HSE range */
54 #define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
55 #define UTILS_HSE_FREQUENCY_MAX 26000000U /*!< Frequency max for HSE frequency, in Hz */
56
57 /* Defines used for FLASH latency according to HCLK Frequency */
58 #define UTILS_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
59 #define UTILS_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
60 #define UTILS_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
61 #define UTILS_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
62 #define UTILS_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
63 #define UTILS_SCALE1_LATENCY6_FREQ 180000000U /*!< HCLK frequency to set FLASH latency 6 in power scale 1 with over-drive mode */
64 #define UTILS_SCALE1_LATENCY7_FREQ 210000000U /*!< HCLK frequency to set FLASH latency 7 in power scale 1 with over-drive mode */
65 #define UTILS_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
66 #define UTILS_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
67 #define UTILS_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
68 #define UTILS_SCALE2_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
69 #define UTILS_SCALE2_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
70 #define UTILS_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
71 #define UTILS_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
72 #define UTILS_SCALE3_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
73 #define UTILS_SCALE3_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 3 */
74 /**
75 * @}
76 */
77
78 /* Private macros ------------------------------------------------------------*/
79 /** @addtogroup UTILS_LL_Private_Macros
80 * @{
81 */
82 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
83 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
84 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
85 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
86 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
87 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
88 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
89 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
90 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
91
92 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
93 || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
94 || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
95 || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
96 || ((__VALUE__) == LL_RCC_APB1_DIV_16))
97
98 #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
99 || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
100 || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
101 || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
102 || ((__VALUE__) == LL_RCC_APB2_DIV_16))
103
104 #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_2) \
105 || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
106 || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
107 || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
108 || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
109 || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
110 || ((__VALUE__) == LL_RCC_PLLM_DIV_8) \
111 || ((__VALUE__) == LL_RCC_PLLM_DIV_9) \
112 || ((__VALUE__) == LL_RCC_PLLM_DIV_10) \
113 || ((__VALUE__) == LL_RCC_PLLM_DIV_11) \
114 || ((__VALUE__) == LL_RCC_PLLM_DIV_12) \
115 || ((__VALUE__) == LL_RCC_PLLM_DIV_13) \
116 || ((__VALUE__) == LL_RCC_PLLM_DIV_14) \
117 || ((__VALUE__) == LL_RCC_PLLM_DIV_15) \
118 || ((__VALUE__) == LL_RCC_PLLM_DIV_16) \
119 || ((__VALUE__) == LL_RCC_PLLM_DIV_17) \
120 || ((__VALUE__) == LL_RCC_PLLM_DIV_18) \
121 || ((__VALUE__) == LL_RCC_PLLM_DIV_19) \
122 || ((__VALUE__) == LL_RCC_PLLM_DIV_20) \
123 || ((__VALUE__) == LL_RCC_PLLM_DIV_21) \
124 || ((__VALUE__) == LL_RCC_PLLM_DIV_22) \
125 || ((__VALUE__) == LL_RCC_PLLM_DIV_23) \
126 || ((__VALUE__) == LL_RCC_PLLM_DIV_24) \
127 || ((__VALUE__) == LL_RCC_PLLM_DIV_25) \
128 || ((__VALUE__) == LL_RCC_PLLM_DIV_26) \
129 || ((__VALUE__) == LL_RCC_PLLM_DIV_27) \
130 || ((__VALUE__) == LL_RCC_PLLM_DIV_28) \
131 || ((__VALUE__) == LL_RCC_PLLM_DIV_29) \
132 || ((__VALUE__) == LL_RCC_PLLM_DIV_30) \
133 || ((__VALUE__) == LL_RCC_PLLM_DIV_31) \
134 || ((__VALUE__) == LL_RCC_PLLM_DIV_32) \
135 || ((__VALUE__) == LL_RCC_PLLM_DIV_33) \
136 || ((__VALUE__) == LL_RCC_PLLM_DIV_34) \
137 || ((__VALUE__) == LL_RCC_PLLM_DIV_35) \
138 || ((__VALUE__) == LL_RCC_PLLM_DIV_36) \
139 || ((__VALUE__) == LL_RCC_PLLM_DIV_37) \
140 || ((__VALUE__) == LL_RCC_PLLM_DIV_38) \
141 || ((__VALUE__) == LL_RCC_PLLM_DIV_39) \
142 || ((__VALUE__) == LL_RCC_PLLM_DIV_40) \
143 || ((__VALUE__) == LL_RCC_PLLM_DIV_41) \
144 || ((__VALUE__) == LL_RCC_PLLM_DIV_42) \
145 || ((__VALUE__) == LL_RCC_PLLM_DIV_43) \
146 || ((__VALUE__) == LL_RCC_PLLM_DIV_44) \
147 || ((__VALUE__) == LL_RCC_PLLM_DIV_45) \
148 || ((__VALUE__) == LL_RCC_PLLM_DIV_46) \
149 || ((__VALUE__) == LL_RCC_PLLM_DIV_47) \
150 || ((__VALUE__) == LL_RCC_PLLM_DIV_48) \
151 || ((__VALUE__) == LL_RCC_PLLM_DIV_49) \
152 || ((__VALUE__) == LL_RCC_PLLM_DIV_50) \
153 || ((__VALUE__) == LL_RCC_PLLM_DIV_51) \
154 || ((__VALUE__) == LL_RCC_PLLM_DIV_52) \
155 || ((__VALUE__) == LL_RCC_PLLM_DIV_53) \
156 || ((__VALUE__) == LL_RCC_PLLM_DIV_54) \
157 || ((__VALUE__) == LL_RCC_PLLM_DIV_55) \
158 || ((__VALUE__) == LL_RCC_PLLM_DIV_56) \
159 || ((__VALUE__) == LL_RCC_PLLM_DIV_57) \
160 || ((__VALUE__) == LL_RCC_PLLM_DIV_58) \
161 || ((__VALUE__) == LL_RCC_PLLM_DIV_59) \
162 || ((__VALUE__) == LL_RCC_PLLM_DIV_60) \
163 || ((__VALUE__) == LL_RCC_PLLM_DIV_61) \
164 || ((__VALUE__) == LL_RCC_PLLM_DIV_62) \
165 || ((__VALUE__) == LL_RCC_PLLM_DIV_63))
166
167 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((50 <= (__VALUE__)) && ((__VALUE__) <= 432))
168
169 #define IS_LL_UTILS_PLLP_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLP_DIV_2) \
170 || ((__VALUE__) == LL_RCC_PLLP_DIV_4) \
171 || ((__VALUE__) == LL_RCC_PLLP_DIV_6) \
172 || ((__VALUE__) == LL_RCC_PLLP_DIV_8))
173
174 #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
175
176 #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
177
178 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
179 (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
180 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
181
182 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
183 || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
184
185 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
186 /**
187 * @}
188 */
189 /* Private function prototypes -----------------------------------------------*/
190 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
191 * @{
192 */
193 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
194 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
195 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
196 static ErrorStatus UTILS_PLL_IsBusy(void);
197 /**
198 * @}
199 */
200
201 /* Exported functions --------------------------------------------------------*/
202 /** @addtogroup UTILS_LL_Exported_Functions
203 * @{
204 */
205
206 /** @addtogroup UTILS_LL_EF_DELAY
207 * @{
208 */
209
210 /**
211 * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
212 * @note When a RTOS is used, it is recommended to avoid changing the Systick
213 * configuration by calling this function, for a delay use rather osDelay RTOS service.
214 * @param HCLKFrequency HCLK frequency in Hz
215 * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
216 * @retval None
217 */
LL_Init1msTick(uint32_t HCLKFrequency)218 void LL_Init1msTick(uint32_t HCLKFrequency)
219 {
220 /* Use frequency provided in argument */
221 LL_InitTick(HCLKFrequency, 1000U);
222 }
223
224 /**
225 * @brief This function provides accurate delay (in milliseconds) based
226 * on SysTick counter flag
227 * @note When a RTOS is used, it is recommended to avoid using blocking delay
228 * and use rather osDelay service.
229 * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
230 * will configure Systick to 1ms
231 * @param Delay specifies the delay time length, in milliseconds.
232 * @retval None
233 */
LL_mDelay(uint32_t Delay)234 void LL_mDelay(uint32_t Delay)
235 {
236 __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
237 /* Add this code to indicate that local variable is not used */
238 ((void)tmp);
239
240 /* Add a period to guaranty minimum wait */
241 if(Delay < LL_MAX_DELAY)
242 {
243 Delay++;
244 }
245
246 while (Delay)
247 {
248 if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
249 {
250 Delay--;
251 }
252 }
253 }
254
255 /**
256 * @}
257 */
258
259 /** @addtogroup UTILS_EF_SYSTEM
260 * @brief System Configuration functions
261 *
262 @verbatim
263 ===============================================================================
264 ##### System Configuration functions #####
265 ===============================================================================
266 [..]
267 System, AHB and APB buses clocks configuration
268
269 (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 216000000 Hz.
270 @endverbatim
271 @internal
272 Depending on the device voltage range, the maximum frequency should be
273 adapted accordingly:
274 (++) +------------------------------------------------------------------------------------------------+
275 (++) | Wait states | HCLK clock frequency (MHz) |
276 (++) | |-------------------------------------------------------------------------------|
277 (++) | (Latency) | voltage range | voltage range | voltage range | voltage range |
278 (++) | | 2.7V - 3.6V | 2.4V - 2.7V | 2.1V - 2.7V | 1.8V - 2.1V |
279 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
280 (++) |0WS(1CPU cycle) | 0 < HCLK <= 30 | 0 < HCLK <= 24 | 0 < HCLK <= 22 | 0 < HCLK <= 20 |
281 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
282 (++) |1WS(2CPU cycle) | 30 < HCLK <= 60 | 24 < HCLK <= 48 | 22 < HCLK <= 44 | 20 < HCLK <= 44 |
283 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
284 (++) |2WS(3CPU cycle) | 60 < HCLK <= 90 | 48 < HCLK <= 72 | 44 < HCLK <= 66 | 40 < HCLK <= 60 |
285 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
286 (++) |3WS(4CPU cycle) | 90 < HCLK <= 120 | 72 < HCLK <= 96 | 66 < HCLK <= 88 | 60 < HCLK <= 80 |
287 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
288 (++) |4WS(5CPU cycle) | 120 < HCLK <= 150 | 96 < HCLK <= 120 | 88 < HCLK <= 110 | 80 < HCLK <= 100 |
289 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
290 (++) |5WS(6CPU cycle) | 150 < HCLK <= 180 | 120 < HCLK <= 144 | 110 < HCLK <= 132 | 100 < HCLK <= 120 |
291 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
292 (++) |6WS(7CPU cycle) | 180 < HCLK <= 210 | 144 < HCLK <= 168 | 132 < HCLK <= 154 | 120 < HCLK <= 140 |
293 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
294 (++) |7WS(8CPU cycle) | 210 < HCLK <= 216 | 168 < HCLK <= 192 | 154 < HCLK <= 176 | 140 < HCLK <= 160 |
295 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
296 (++) |8WS(9CPU cycle) | -- | 192 < HCLK <= 216 | 176 < HCLK <= 198 | 160 < HCLK <= 180 |
297 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
298 (++) |9WS(10CPU cycle)| -- | -- | 198 < HCLK <= 216 | -- |
299 (++) +------------------------------------------------------------------------------------------------+
300
301 @endinternal
302 * @{
303 */
304
305 /**
306 * @brief This function sets directly SystemCoreClock CMSIS variable.
307 * @note Variable can be calculated also through SystemCoreClockUpdate function.
308 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
309 * @retval None
310 */
LL_SetSystemCoreClock(uint32_t HCLKFrequency)311 void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
312 {
313 /* HCLK clock frequency */
314 SystemCoreClock = HCLKFrequency;
315 }
316
317 /**
318 * @brief Update number of Flash wait states in line with new frequency and current
319 voltage range.
320 * @note This Function support ONLY devices with supply voltage (voltage range) between 2.7V and 3.6V
321 * @param HCLK_Frequency HCLK frequency
322 * @retval An ErrorStatus enumeration value:
323 * - SUCCESS: Latency has been modified
324 * - ERROR: Latency cannot be modified
325 */
LL_SetFlashLatency(uint32_t HCLK_Frequency)326 ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency)
327 {
328 uint32_t timeout;
329 uint32_t getlatency;
330 uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
331 ErrorStatus status = SUCCESS;
332
333 /* Frequency cannot be equal to 0 */
334 if(HCLK_Frequency == 0U)
335 {
336 status = ERROR;
337 }
338 else
339 {
340 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
341 {
342 if(LL_PWR_IsEnabledOverDriveMode() != 0U)
343 {
344 if(HCLK_Frequency > UTILS_SCALE1_LATENCY7_FREQ)
345 {
346 /* 210 < HCLK <= 216 => 7WS (8 CPU cycles) */
347 latency = LL_FLASH_LATENCY_7;
348 }
349 else /* (HCLK_Frequency > UTILS_SCALE1_LATENCY6_FREQ) */
350 {
351 /* 180 < HCLK <= 210 => 6WS (7 CPU cycles) */
352 latency = LL_FLASH_LATENCY_6;
353 }
354 }
355 if((HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ) && (latency == LL_FLASH_LATENCY_0))
356 {
357 /* 150 < HCLK <= 180 => 5WS (6 CPU cycles) */
358 latency = LL_FLASH_LATENCY_5;
359 }
360 else if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) && (latency == LL_FLASH_LATENCY_0))
361 {
362 /* 120 < HCLK <= 150 => 4WS (5 CPU cycles) */
363 latency = LL_FLASH_LATENCY_4;
364 }
365 else if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) && (latency == LL_FLASH_LATENCY_0))
366 {
367 /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */
368 latency = LL_FLASH_LATENCY_3;
369 }
370 else if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) && (latency == LL_FLASH_LATENCY_0))
371 {
372 /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */
373 latency = LL_FLASH_LATENCY_2;
374 }
375 else
376 {
377 if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (latency == LL_FLASH_LATENCY_0))
378 {
379 /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */
380 latency = LL_FLASH_LATENCY_1;
381 }
382 /* else HCLK_Frequency < 30MHz default LL_FLASH_LATENCY_0 0WS */
383 }
384 }
385 else if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
386 {
387 if(HCLK_Frequency > UTILS_SCALE2_LATENCY5_FREQ)
388 {
389 /* 150 < HCLK <= 168 OR 150 < HCLK <= 180 (when OverDrive mode is enable) => 5WS (6 CPU cycles) */
390 latency = LL_FLASH_LATENCY_5;
391 }
392 else if(HCLK_Frequency > UTILS_SCALE2_LATENCY4_FREQ)
393 {
394 /* 120 < HCLK <= 150 => 4WS (5 CPU cycles) */
395 latency = LL_FLASH_LATENCY_4;
396 }
397 else if(HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)
398 {
399 /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */
400 latency = LL_FLASH_LATENCY_3;
401 }
402 else if(HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)
403 {
404 /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */
405 latency = LL_FLASH_LATENCY_2;
406 }
407 else
408 {
409 if(HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)
410 {
411 /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */
412 latency = LL_FLASH_LATENCY_1;
413 }
414 /* else HCLK_Frequency < 24MHz default LL_FLASH_LATENCY_0 0WS */
415 }
416 }
417 else /* Scale 3 */
418 {
419 if(HCLK_Frequency > UTILS_SCALE3_LATENCY4_FREQ)
420 {
421 /* 120 < HCLK <= 144 => 4WS (5 CPU cycles) */
422 latency = LL_FLASH_LATENCY_4;
423 }
424 else if(HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ)
425 {
426 /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */
427 latency = LL_FLASH_LATENCY_3;
428 }
429 else if(HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ)
430 {
431 /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */
432 latency = LL_FLASH_LATENCY_2;
433 }
434 else
435 {
436 if(HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ)
437 {
438 /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */
439 latency = LL_FLASH_LATENCY_1;
440 }
441 /* else HCLK_Frequency < 22MHz default LL_FLASH_LATENCY_0 0WS */
442 }
443 }
444
445 if (status != ERROR)
446 {
447 LL_FLASH_SetLatency(latency);
448
449 /* Check that the new number of wait states is taken into account to access the Flash
450 memory by reading the FLASH_ACR register */
451 timeout = 2;
452 do
453 {
454 /* Wait for Flash latency to be updated */
455 getlatency = LL_FLASH_GetLatency();
456 timeout--;
457 } while ((getlatency != latency) && (timeout > 0));
458
459 if(getlatency != latency)
460 {
461 status = ERROR;
462 }
463 else
464 {
465 status = SUCCESS;
466 }
467 }
468 }
469 return status;
470 }
471
472 /**
473 * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL
474 * @note The application need to ensure that PLL is disabled.
475 * @note Function is based on the following formula:
476 * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
477 * - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.1 MHz (PLLVCO_input = HSI frequency / PLLM)
478 * - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz (PLLVCO_output = PLLVCO_input * PLLN)
479 * - PLLP: ensure that max frequency at 216000000 Hz is reach (PLLVCO_output / PLLP)
480 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
481 * the configuration information for the PLL.
482 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
483 * the configuration information for the BUS prescalers.
484 * @retval An ErrorStatus enumeration value:
485 * - SUCCESS: Max frequency configuration done
486 * - ERROR: Max frequency configuration not done
487 */
LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct,LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct)488 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
489 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
490 {
491 ErrorStatus status = SUCCESS;
492 uint32_t pllfreq = 0U;
493
494 /* Check if one of the PLL is enabled */
495 if(UTILS_PLL_IsBusy() == SUCCESS)
496 {
497 /* Calculate the new PLL output frequency */
498 pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
499
500 /* Enable HSI if not enabled */
501 if(LL_RCC_HSI_IsReady() != 1U)
502 {
503 LL_RCC_HSI_Enable();
504 while (LL_RCC_HSI_IsReady() != 1U)
505 {
506 /* Wait for HSI ready */
507 }
508 }
509
510 /* Configure PLL */
511 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
512 UTILS_PLLInitStruct->PLLP);
513
514 /* Enable PLL and switch system clock to PLL */
515 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
516 }
517 else
518 {
519 /* Current PLL configuration cannot be modified */
520 status = ERROR;
521 }
522
523 return status;
524 }
525
526 /**
527 * @brief This function configures system clock with HSE as clock source of the PLL
528 * @note The application need to ensure that PLL is disabled.
529 * @note Function is based on the following formula:
530 * - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP)
531 * - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input = HSE frequency / PLLM)
532 * - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz (PLLVCO_output = PLLVCO_input * PLLN)
533 * - PLLP: ensure that max frequency at 216000000 Hz is reached (PLLVCO_output / PLLP)
534 * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 26000000
535 * @param HSEBypass This parameter can be one of the following values:
536 * @arg @ref LL_UTILS_HSEBYPASS_ON
537 * @arg @ref LL_UTILS_HSEBYPASS_OFF
538 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
539 * the configuration information for the PLL.
540 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
541 * the configuration information for the BUS prescalers.
542 * @retval An ErrorStatus enumeration value:
543 * - SUCCESS: Max frequency configuration done
544 * - ERROR: Max frequency configuration not done
545 */
LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency,uint32_t HSEBypass,LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct,LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct)546 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
547 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
548 {
549 ErrorStatus status = SUCCESS;
550 uint32_t pllfreq = 0U;
551
552 /* Check the parameters */
553 assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
554 assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
555
556 /* Check if one of the PLL is enabled */
557 if(UTILS_PLL_IsBusy() == SUCCESS)
558 {
559 /* Calculate the new PLL output frequency */
560 pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
561
562 /* Enable HSE if not enabled */
563 if(LL_RCC_HSE_IsReady() != 1U)
564 {
565 /* Check if need to enable HSE bypass feature or not */
566 if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
567 {
568 LL_RCC_HSE_EnableBypass();
569 }
570 else
571 {
572 LL_RCC_HSE_DisableBypass();
573 }
574
575 /* Enable HSE */
576 LL_RCC_HSE_Enable();
577 while (LL_RCC_HSE_IsReady() != 1U)
578 {
579 /* Wait for HSE ready */
580 }
581 }
582
583 /* Configure PLL */
584 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
585 UTILS_PLLInitStruct->PLLP);
586
587 /* Enable PLL and switch system clock to PLL */
588 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
589 }
590 else
591 {
592 /* Current PLL configuration cannot be modified */
593 status = ERROR;
594 }
595
596 return status;
597 }
598
599 /**
600 * @}
601 */
602
603 /**
604 * @}
605 */
606
607 /** @addtogroup UTILS_LL_Private_Functions
608 * @{
609 */
610 /**
611 * @brief Function to check that PLL can be modified
612 * @param PLL_InputFrequency PLL input frequency (in Hz)
613 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
614 * the configuration information for the PLL.
615 * @retval PLL output frequency (in Hz)
616 */
UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct)617 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
618 {
619 uint32_t pllfreq = 0U;
620
621 /* Check the parameters */
622 assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
623 assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
624 assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
625
626 /* Check different PLL parameters according to RM */
627 /* - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.1 MHz. */
628 pllfreq = PLL_InputFrequency / (UTILS_PLLInitStruct->PLLM & (RCC_PLLCFGR_PLLM >> RCC_PLLCFGR_PLLM_Pos));
629 assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
630
631 /* - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz.*/
632 pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
633 assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
634
635 /* - PLLP: ensure that max frequency at 216000000 Hz is reached */
636 pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLP >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
637 assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
638
639 return pllfreq;
640 }
641
642 /**
643 * @brief Function to check that PLL can be modified
644 * @retval An ErrorStatus enumeration value:
645 * - SUCCESS: PLL modification can be done
646 * - ERROR: PLL is busy
647 */
UTILS_PLL_IsBusy(void)648 static ErrorStatus UTILS_PLL_IsBusy(void)
649 {
650 ErrorStatus status = SUCCESS;
651
652 /* Check if PLL is busy*/
653 if(LL_RCC_PLL_IsReady() != 0U)
654 {
655 /* PLL configuration cannot be modified */
656 status = ERROR;
657 }
658
659 /* Check if PLLSAI is busy*/
660 if(LL_RCC_PLLSAI_IsReady() != 0U)
661 {
662 /* PLLSAI1 configuration cannot be modified */
663 status = ERROR;
664 }
665 /* Check if PLLI2S is busy*/
666 if(LL_RCC_PLLI2S_IsReady() != 0U)
667 {
668 /* PLLI2S configuration cannot be modified */
669 status = ERROR;
670 }
671 return status;
672 }
673
674 /**
675 * @brief Function to enable PLL and switch system clock to PLL
676 * @param SYSCLK_Frequency SYSCLK frequency
677 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
678 * the configuration information for the BUS prescalers.
679 * @retval An ErrorStatus enumeration value:
680 * - SUCCESS: No problem to switch system to PLL
681 * - ERROR: Problem to switch system to PLL
682 */
UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency,LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct)683 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
684 {
685 ErrorStatus status = SUCCESS;
686 uint32_t hclk_frequency = 0U;
687
688 assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
689 assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
690 assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
691
692 /* Calculate HCLK frequency */
693 hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
694
695 /* Increasing the number of wait states because of higher CPU frequency */
696 if(SystemCoreClock < hclk_frequency)
697 {
698 /* Set FLASH latency to highest latency */
699 status = LL_SetFlashLatency(hclk_frequency);
700 }
701
702 /* Update system clock configuration */
703 if(status == SUCCESS)
704 {
705 /* Enable PLL */
706 LL_RCC_PLL_Enable();
707 while (LL_RCC_PLL_IsReady() != 1U)
708 {
709 /* Wait for PLL ready */
710 }
711
712 /* Sysclk activation on the main PLL */
713 LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
714 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
715 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
716 {
717 /* Wait for system clock switch to PLL */
718 }
719
720 /* Set APB1 & APB2 prescaler*/
721 LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
722 LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
723 }
724
725 /* Decreasing the number of wait states because of lower CPU frequency */
726 if(SystemCoreClock > hclk_frequency)
727 {
728 /* Set FLASH latency to lowest latency */
729 status = LL_SetFlashLatency(hclk_frequency);
730 }
731
732 /* Update SystemCoreClock variable */
733 if(status == SUCCESS)
734 {
735 LL_SetSystemCoreClock(hclk_frequency);
736 }
737
738 return status;
739 }
740
741 /**
742 * @}
743 */
744
745 /**
746 * @}
747 */
748
749 /**
750 * @}
751 */
752
753
