1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_spi.c
4 * @author MCD Application Team
5 * @brief SPI LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32f7xx_ll_spi.h"
22 #include "stm32f7xx_ll_bus.h"
23 #include "stm32f7xx_ll_rcc.h"
24
25 #ifdef USE_FULL_ASSERT
26 #include "stm32_assert.h"
27 #else
28 #define assert_param(expr) ((void)0U)
29 #endif /* USE_FULL_ASSERT */
30
31 /** @addtogroup STM32F7xx_LL_Driver
32 * @{
33 */
34
35 #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6)
36
37 /** @addtogroup SPI_LL
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup SPI_LL_Private_Constants SPI Private Constants
46 * @{
47 */
48 /* SPI registers Masks */
49 #define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
50 SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
51 SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_CRCL | \
52 SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
53 SPI_CR1_BIDIMODE)
54 /**
55 * @}
56 */
57
58 /* Private macros ------------------------------------------------------------*/
59 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
60 * @{
61 */
62 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
63 || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
64 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
65 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
66
67 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
68 || ((__VALUE__) == LL_SPI_MODE_SLAVE))
69
70 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \
71 || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \
72 || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \
73 || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \
74 || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
75 || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \
76 || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
77 || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
78 || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
79 || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
80 || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
81 || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
82 || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
83
84 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
85 || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
86
87 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
88 || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
89
90 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
91 || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
92 || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
93
94 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
95 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
96 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
97 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
98 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
99 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
100 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
101 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
102
103 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
104 || ((__VALUE__) == LL_SPI_MSB_FIRST))
105
106 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
107 || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
108
109 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
110
111 /**
112 * @}
113 */
114
115 /* Private function prototypes -----------------------------------------------*/
116
117 /* Exported functions --------------------------------------------------------*/
118 /** @addtogroup SPI_LL_Exported_Functions
119 * @{
120 */
121
122 /** @addtogroup SPI_LL_EF_Init
123 * @{
124 */
125
126 /**
127 * @brief De-initialize the SPI registers to their default reset values.
128 * @param SPIx SPI Instance
129 * @retval An ErrorStatus enumeration value:
130 * - SUCCESS: SPI registers are de-initialized
131 * - ERROR: SPI registers are not de-initialized
132 */
LL_SPI_DeInit(SPI_TypeDef * SPIx)133 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
134 {
135 ErrorStatus status = ERROR;
136
137 /* Check the parameters */
138 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
139
140 #if defined(SPI1)
141 if (SPIx == SPI1)
142 {
143 /* Force reset of SPI clock */
144 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
145
146 /* Release reset of SPI clock */
147 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
148
149 status = SUCCESS;
150 }
151 #endif /* SPI1 */
152 #if defined(SPI2)
153 if (SPIx == SPI2)
154 {
155 /* Force reset of SPI clock */
156 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
157
158 /* Release reset of SPI clock */
159 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
160
161 status = SUCCESS;
162 }
163 #endif /* SPI2 */
164 #if defined(SPI3)
165 if (SPIx == SPI3)
166 {
167 /* Force reset of SPI clock */
168 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
169
170 /* Release reset of SPI clock */
171 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
172
173 status = SUCCESS;
174 }
175 #endif /* SPI3 */
176 #if defined(SPI4)
177 if (SPIx == SPI4)
178 {
179 /* Force reset of SPI clock */
180 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
181
182 /* Release reset of SPI clock */
183 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
184
185 status = SUCCESS;
186 }
187 #endif /* SPI4 */
188 #if defined(SPI5)
189 if (SPIx == SPI5)
190 {
191 /* Force reset of SPI clock */
192 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5);
193
194 /* Release reset of SPI clock */
195 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5);
196
197 status = SUCCESS;
198 }
199 #endif /* SPI5 */
200 #if defined(SPI6)
201 if (SPIx == SPI6)
202 {
203 /* Force reset of SPI clock */
204 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI6);
205
206 /* Release reset of SPI clock */
207 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI6);
208
209 status = SUCCESS;
210 }
211 #endif /* SPI6 */
212
213 return status;
214 }
215
216 /**
217 * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
218 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
219 * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
220 * @param SPIx SPI Instance
221 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
222 * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
223 */
LL_SPI_Init(SPI_TypeDef * SPIx,LL_SPI_InitTypeDef * SPI_InitStruct)224 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
225 {
226 ErrorStatus status = ERROR;
227
228 /* Check the SPI Instance SPIx*/
229 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
230
231 /* Check the SPI parameters from SPI_InitStruct*/
232 assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
233 assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
234 assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
235 assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
236 assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
237 assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
238 assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
239 assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
240 assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
241
242 if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
243 {
244 /*---------------------------- SPIx CR1 Configuration ------------------------
245 * Configure SPIx CR1 with parameters:
246 * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
247 * - Master/Slave Mode: SPI_CR1_MSTR bit
248 * - ClockPolarity: SPI_CR1_CPOL bit
249 * - ClockPhase: SPI_CR1_CPHA bit
250 * - NSS management: SPI_CR1_SSM bit
251 * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
252 * - BitOrder: SPI_CR1_LSBFIRST bit
253 * - CRCCalculation: SPI_CR1_CRCEN bit
254 */
255 MODIFY_REG(SPIx->CR1,
256 SPI_CR1_CLEAR_MASK,
257 SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
258 SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
259 SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
260 SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
261
262 /*---------------------------- SPIx CR2 Configuration ------------------------
263 * Configure SPIx CR2 with parameters:
264 * - DataWidth: DS[3:0] bits
265 * - NSS management: SSOE bit
266 */
267 MODIFY_REG(SPIx->CR2,
268 SPI_CR2_DS | SPI_CR2_SSOE,
269 SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
270
271 /* Set Rx FIFO to Quarter (1 Byte) in case of 8 Bits mode. No DataPacking by default */
272 if (SPI_InitStruct->DataWidth < LL_SPI_DATAWIDTH_9BIT)
273 {
274 LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_QUARTER);
275 }
276
277 /*---------------------------- SPIx CRCPR Configuration ----------------------
278 * Configure SPIx CRCPR with parameters:
279 * - CRCPoly: CRCPOLY[15:0] bits
280 */
281 if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
282 {
283 assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
284 LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
285 }
286 status = SUCCESS;
287 }
288
289 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
290 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
291 return status;
292 }
293
294 /**
295 * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
296 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
297 * whose fields will be set to default values.
298 * @retval None
299 */
LL_SPI_StructInit(LL_SPI_InitTypeDef * SPI_InitStruct)300 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
301 {
302 /* Set SPI_InitStruct fields to default values */
303 SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
304 SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
305 SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
306 SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
307 SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
308 SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
309 SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
310 SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
311 SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
312 SPI_InitStruct->CRCPoly = 7U;
313 }
314
315 /**
316 * @}
317 */
318
319 /**
320 * @}
321 */
322
323 /**
324 * @}
325 */
326
327 /** @addtogroup I2S_LL
328 * @{
329 */
330
331 /* Private types -------------------------------------------------------------*/
332 /* Private variables ---------------------------------------------------------*/
333 /* Private constants ---------------------------------------------------------*/
334 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
335 * @{
336 */
337 /* I2S registers Masks */
338 #define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
339 SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
340 SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
341
342 #define I2S_I2SPR_CLEAR_MASK 0x0002U
343 /**
344 * @}
345 */
346 /* Private macros ------------------------------------------------------------*/
347 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
348 * @{
349 */
350
351 #define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
352 || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
353 || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
354 || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
355
356 #define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
357 || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
358
359 #define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
360 || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
361 || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
362 || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
363 || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
364
365 #define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
366 || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
367 || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
368 || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
369
370 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
371 || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
372
373 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
374 && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
375 || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
376
377 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
378
379 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
380 || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
381 /**
382 * @}
383 */
384
385 /* Private function prototypes -----------------------------------------------*/
386
387 /* Exported functions --------------------------------------------------------*/
388 /** @addtogroup I2S_LL_Exported_Functions
389 * @{
390 */
391
392 /** @addtogroup I2S_LL_EF_Init
393 * @{
394 */
395
396 /**
397 * @brief De-initialize the SPI/I2S registers to their default reset values.
398 * @param SPIx SPI Instance
399 * @retval An ErrorStatus enumeration value:
400 * - SUCCESS: SPI registers are de-initialized
401 * - ERROR: SPI registers are not de-initialized
402 */
LL_I2S_DeInit(SPI_TypeDef * SPIx)403 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
404 {
405 return LL_SPI_DeInit(SPIx);
406 }
407
408 /**
409 * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
410 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
411 * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
412 * @param SPIx SPI Instance
413 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
414 * @retval An ErrorStatus enumeration value:
415 * - SUCCESS: SPI registers are Initialized
416 * - ERROR: SPI registers are not Initialized
417 */
LL_I2S_Init(SPI_TypeDef * SPIx,LL_I2S_InitTypeDef * I2S_InitStruct)418 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
419 {
420 uint32_t i2sdiv = 2U;
421 uint32_t i2sodd = 0U;
422 uint32_t packetlength = 1U;
423 uint32_t tmp;
424 uint32_t sourceclock;
425 ErrorStatus status = ERROR;
426
427 /* Check the I2S parameters */
428 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
429 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
430 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
431 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
432 assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
433 assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
434 assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
435
436 if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
437 {
438 /*---------------------------- SPIx I2SCFGR Configuration --------------------
439 * Configure SPIx I2SCFGR with parameters:
440 * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
441 * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
442 * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
443 * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
444 */
445
446 /* Write to SPIx I2SCFGR */
447 MODIFY_REG(SPIx->I2SCFGR,
448 I2S_I2SCFGR_CLEAR_MASK,
449 I2S_InitStruct->Mode | I2S_InitStruct->Standard |
450 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
451 SPI_I2SCFGR_I2SMOD);
452
453 /*---------------------------- SPIx I2SPR Configuration ----------------------
454 * Configure SPIx I2SPR with parameters:
455 * - MCLKOutput: SPI_I2SPR_MCKOE bit
456 * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
457 */
458
459 /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
460 * else, default values are used: i2sodd = 0U, i2sdiv = 2U.
461 */
462 if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
463 {
464 /* Check the frame length (For the Prescaler computing)
465 * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
466 */
467 if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
468 {
469 /* Packet length is 32 bits */
470 packetlength = 2U;
471 }
472
473 /* If an external I2S clock has to be used, the specific define should be set
474 in the project configuration or in the stm32f7xx_ll_rcc.h file */
475 /* Get the I2S source clock value */
476 sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
477
478 /* Compute the Real divider depending on the MCLK output state with a floating point */
479 if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
480 {
481 /* MCLK output is enabled */
482 tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
483 }
484 else
485 {
486 /* MCLK output is disabled */
487 tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
488 }
489
490 /* Remove the floating point */
491 tmp = tmp / 10U;
492
493 /* Check the parity of the divider */
494 i2sodd = (tmp & (uint16_t)0x0001U);
495
496 /* Compute the i2sdiv prescaler */
497 i2sdiv = ((tmp - i2sodd) / 2U);
498
499 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
500 i2sodd = (i2sodd << 8U);
501 }
502
503 /* Test if the divider is 1 or 0 or greater than 0xFF */
504 if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
505 {
506 /* Set the default values */
507 i2sdiv = 2U;
508 i2sodd = 0U;
509 }
510
511 /* Write to SPIx I2SPR register the computed value */
512 WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
513
514 status = SUCCESS;
515 }
516 return status;
517 }
518
519 /**
520 * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
521 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
522 * whose fields will be set to default values.
523 * @retval None
524 */
LL_I2S_StructInit(LL_I2S_InitTypeDef * I2S_InitStruct)525 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
526 {
527 /*--------------- Reset I2S init structure parameters values -----------------*/
528 I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
529 I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
530 I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
531 I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
532 I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
533 I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
534 }
535
536 /**
537 * @brief Set linear and parity prescaler.
538 * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
539 * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
540 * @param SPIx SPI Instance
541 * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
542 * @param PrescalerParity This parameter can be one of the following values:
543 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
544 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
545 * @retval None
546 */
LL_I2S_ConfigPrescaler(SPI_TypeDef * SPIx,uint32_t PrescalerLinear,uint32_t PrescalerParity)547 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
548 {
549 /* Check the I2S parameters */
550 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
551 assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
552 assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
553
554 /* Write to SPIx I2SPR */
555 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
556 }
557
558 /**
559 * @}
560 */
561
562 /**
563 * @}
564 */
565
566 /**
567 * @}
568 */
569
570 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) */
571
572 /**
573 * @}
574 */
575
576 #endif /* USE_FULL_LL_DRIVER */
577
578
