1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_rcc.c
4 * @author MCD Application Team
5 * @brief RCC LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 ******************************************************************************
16 */
17 #if defined(USE_FULL_LL_DRIVER)
18
19 /* Includes ------------------------------------------------------------------*/
20 #include "stm32f7xx_ll_rcc.h"
21 #ifdef USE_FULL_ASSERT
22 #include "stm32_assert.h"
23 #else
24 #define assert_param(expr) ((void)0U)
25 #endif
26
27 /** @addtogroup STM32F7xx_LL_Driver
28 * @{
29 */
30
31 #if defined(RCC)
32
33 /** @addtogroup RCC_LL
34 * @{
35 */
36
37 /* Private types -------------------------------------------------------------*/
38 /* Private variables ---------------------------------------------------------*/
39 /* Private constants ---------------------------------------------------------*/
40 /* Private macros ------------------------------------------------------------*/
41 /** @addtogroup RCC_LL_Private_Macros
42 * @{
43 */
44 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
45 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
46 || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE) \
47 || ((__VALUE__) == LL_RCC_USART6_CLKSOURCE))
48
49 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
50 || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE) \
51 || ((__VALUE__) == LL_RCC_UART7_CLKSOURCE) \
52 || ((__VALUE__) == LL_RCC_UART8_CLKSOURCE))
53
54 #if defined(I2C4)
55 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
56 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
57 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \
58 || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
59 #else
60 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
61 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
62 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
63 #endif /* I2C4 */
64
65 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE))
66
67 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
68 || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
69
70 #if defined(SDMMC2)
71 #define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE) \
72 || ((__VALUE__) == LL_RCC_SDMMC2_CLKSOURCE))
73 #else
74 #define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE))
75 #endif /* SDMMC2 */
76
77 #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
78
79 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
80
81 #if defined(DFSDM1_Channel0)
82 #define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
83
84 #define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE))
85 #endif /* DFSDM1_Channel0 */
86
87 #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE))
88
89 #if defined(CEC)
90 #define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
91 #endif /* CEC */
92
93 #if defined(DSI)
94 #define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DSI_CLKSOURCE))
95 #endif /* DSI */
96
97 #if defined(LTDC)
98 #define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE))
99 #endif /* LTDC */
100
101 #if defined(SPDIFRX)
102 #define IS_LL_RCC_SPDIFRX_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPDIFRX1_CLKSOURCE))
103 #endif /* SPDIFRX */
104
105 /**
106 * @}
107 */
108
109 /* Private function prototypes -----------------------------------------------*/
110 /** @defgroup RCC_LL_Private_Functions RCC Private functions
111 * @{
112 */
113 uint32_t RCC_GetSystemClockFreq(void);
114 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
115 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
116 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
117 uint32_t RCC_PLL_GetFreqDomain_SYS(void);
118 uint32_t RCC_PLL_GetFreqDomain_SAI(void);
119 uint32_t RCC_PLL_GetFreqDomain_48M(void);
120 #if defined(DSI)
121 uint32_t RCC_PLL_GetFreqDomain_DSI(void);
122 #endif /* DSI */
123 uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void);
124 uint32_t RCC_PLLSAI_GetFreqDomain_48M(void);
125 #if defined(LTDC)
126 uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void);
127 #endif /* LTDC */
128 uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);
129 uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void);
130 #if defined(SPDIFRX)
131 uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void);
132 #endif /* SPDIFRX */
133 /**
134 * @}
135 */
136
137
138 /* Exported functions --------------------------------------------------------*/
139 /** @addtogroup RCC_LL_Exported_Functions
140 * @{
141 */
142
143 /** @addtogroup RCC_LL_EF_Init
144 * @{
145 */
146
147 /**
148 * @brief Reset the RCC clock configuration to the default reset state.
149 * @note The default reset state of the clock configuration is given below:
150 * - HSI ON and used as system clock source
151 * - HSE, PLL, PLLI2S, PLLSAI OFF
152 * - AHB, APB1 and APB2 prescaler set to 1.
153 * - CSS, MCO OFF
154 * - All interrupts disabled
155 * @note This function doesn't modify the configuration of the
156 * - Peripheral clocks
157 * - LSI, LSE and RTC clocks
158 * @retval An ErrorStatus enumeration value:
159 * - SUCCESS: RCC registers are de-initialized
160 * - ERROR: not applicable
161 */
LL_RCC_DeInit(void)162 ErrorStatus LL_RCC_DeInit(void)
163 {
164 __IO uint32_t vl_mask;
165
166 /* Set HSION bit */
167 LL_RCC_HSI_Enable();
168
169 /* Wait for HSI READY bit */
170 while(LL_RCC_HSI_IsReady() != 1U)
171 {}
172
173 /* Reset CFGR register */
174 LL_RCC_WriteReg(CFGR, 0x00000000U);
175
176 /* Read CR register */
177 vl_mask = LL_RCC_ReadReg(CR);
178
179 /* Reset HSEON, HSEBYP, PLLON, CSSON, PLLI2SON and PLLSAION bits */
180 CLEAR_BIT(vl_mask, (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_PLLSAION | RCC_CR_PLLI2SON));
181
182 /* Write new value in CR register */
183 LL_RCC_WriteReg(CR, vl_mask);
184
185 /* Set HSITRIM bits to the reset value*/
186 LL_RCC_HSI_SetCalibTrimming(0x10U);
187
188 /* Wait for PLL READY bit to be reset */
189 while(LL_RCC_PLL_IsReady() != 0U)
190 {}
191
192 /* Wait for PLLI2S READY bit to be reset */
193 while(LL_RCC_PLLI2S_IsReady() != 0U)
194 {}
195
196 /* Wait for PLLSAI READY bit to be reset */
197 while(LL_RCC_PLLSAI_IsReady() != 0U)
198 {}
199
200 /* Reset PLLCFGR register */
201 LL_RCC_WriteReg(PLLCFGR, 0x24003010U);
202
203 /* Reset PLLI2SCFGR register */
204 LL_RCC_WriteReg(PLLI2SCFGR, 0x24003000U);
205
206 /* Reset PLLSAICFGR register */
207 LL_RCC_WriteReg(PLLSAICFGR, 0x24003000U);
208
209 /* Disable all interrupts */
210 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE | RCC_CIR_PLLI2SRDYIE | RCC_CIR_PLLSAIRDYIE);
211
212 /* Clear all interrupt flags */
213 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_PLLI2SRDYC | RCC_CIR_PLLSAIRDYC | RCC_CIR_CSSC);
214
215 /* Clear LSION bit */
216 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
217
218 /* Reset all CSR flags */
219 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
220
221 return SUCCESS;
222 }
223
224 /**
225 * @}
226 */
227
228 /** @addtogroup RCC_LL_EF_Get_Freq
229 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
230 * and different peripheral clocks available on the device.
231 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
232 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
233 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
234 * or HSI_VALUE(**) multiplied/divided by the PLL factors.
235 * @note (**) HSI_VALUE is a constant defined in this file (default value
236 * 16 MHz) but the real value may vary depending on the variations
237 * in voltage and temperature.
238 * @note (***) HSE_VALUE is a constant defined in this file (default value
239 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
240 * frequency of the crystal used. Otherwise, this function may
241 * have wrong result.
242 * @note The result of this function could be incorrect when using fractional
243 * value for HSE crystal.
244 * @note This function can be used by the user application to compute the
245 * baud-rate for the communication peripherals or configure other parameters.
246 * @{
247 */
248
249 /**
250 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
251 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
252 * must be called to update structure fields. Otherwise, any
253 * configuration based on this function will be incorrect.
254 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
255 * @retval None
256 */
LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef * RCC_Clocks)257 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
258 {
259 /* Get SYSCLK frequency */
260 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
261
262 /* HCLK clock frequency */
263 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
264
265 /* PCLK1 clock frequency */
266 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
267
268 /* PCLK2 clock frequency */
269 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
270 }
271
272 /**
273 * @brief Return USARTx clock frequency
274 * @param USARTxSource This parameter can be one of the following values:
275 * @arg @ref LL_RCC_USART1_CLKSOURCE
276 * @arg @ref LL_RCC_USART2_CLKSOURCE
277 * @arg @ref LL_RCC_USART3_CLKSOURCE
278 * @arg @ref LL_RCC_USART6_CLKSOURCE
279 * @retval USART clock frequency (in Hz)
280 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
281 */
LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)282 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
283 {
284 uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
285
286 /* Check parameter */
287 assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
288
289 if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
290 {
291 /* USART1CLK clock frequency */
292 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
293 {
294 case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
295 usart_frequency = RCC_GetSystemClockFreq();
296 break;
297
298 case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
299 if (LL_RCC_HSI_IsReady())
300 {
301 usart_frequency = HSI_VALUE;
302 }
303 break;
304
305 case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
306 if (LL_RCC_LSE_IsReady())
307 {
308 usart_frequency = LSE_VALUE;
309 }
310 break;
311
312 case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */
313 default:
314 usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
315 break;
316 }
317 }
318 else if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
319 {
320 /* USART2CLK clock frequency */
321 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
322 {
323 case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
324 usart_frequency = RCC_GetSystemClockFreq();
325 break;
326
327 case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */
328 if (LL_RCC_HSI_IsReady())
329 {
330 usart_frequency = HSI_VALUE;
331 }
332 break;
333
334 case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */
335 if (LL_RCC_LSE_IsReady())
336 {
337 usart_frequency = LSE_VALUE;
338 }
339 break;
340
341 case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */
342 default:
343 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
344 break;
345 }
346 }
347 else if (USARTxSource == LL_RCC_USART6_CLKSOURCE)
348 {
349 /* USART6CLK clock frequency */
350 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
351 {
352 case LL_RCC_USART6_CLKSOURCE_SYSCLK: /* USART6 Clock is System Clock */
353 usart_frequency = RCC_GetSystemClockFreq();
354 break;
355
356 case LL_RCC_USART6_CLKSOURCE_HSI: /* USART6 Clock is HSI Osc. */
357 if (LL_RCC_HSI_IsReady())
358 {
359 usart_frequency = HSI_VALUE;
360 }
361 break;
362
363 case LL_RCC_USART6_CLKSOURCE_LSE: /* USART6 Clock is LSE Osc. */
364 if (LL_RCC_LSE_IsReady())
365 {
366 usart_frequency = LSE_VALUE;
367 }
368 break;
369
370 case LL_RCC_USART6_CLKSOURCE_PCLK2: /* USART6 Clock is PCLK2 */
371 default:
372 usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
373 break;
374 }
375 }
376 else
377 {
378 if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
379 {
380 /* USART3CLK clock frequency */
381 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
382 {
383 case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
384 usart_frequency = RCC_GetSystemClockFreq();
385 break;
386
387 case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */
388 if (LL_RCC_HSI_IsReady())
389 {
390 usart_frequency = HSI_VALUE;
391 }
392 break;
393
394 case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */
395 if (LL_RCC_LSE_IsReady())
396 {
397 usart_frequency = LSE_VALUE;
398 }
399 break;
400
401 case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */
402 default:
403 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
404 break;
405 }
406 }
407 }
408 return usart_frequency;
409 }
410
411 /**
412 * @brief Return UARTx clock frequency
413 * @param UARTxSource This parameter can be one of the following values:
414 * @arg @ref LL_RCC_UART4_CLKSOURCE
415 * @arg @ref LL_RCC_UART5_CLKSOURCE
416 * @arg @ref LL_RCC_UART7_CLKSOURCE
417 * @arg @ref LL_RCC_UART8_CLKSOURCE
418 * @retval UART clock frequency (in Hz)
419 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
420 */
LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)421 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
422 {
423 uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
424
425 /* Check parameter */
426 assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
427
428 if (UARTxSource == LL_RCC_UART4_CLKSOURCE)
429 {
430 /* UART4CLK clock frequency */
431 switch (LL_RCC_GetUARTClockSource(UARTxSource))
432 {
433 case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */
434 uart_frequency = RCC_GetSystemClockFreq();
435 break;
436
437 case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */
438 if (LL_RCC_HSI_IsReady())
439 {
440 uart_frequency = HSI_VALUE;
441 }
442 break;
443
444 case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */
445 if (LL_RCC_LSE_IsReady())
446 {
447 uart_frequency = LSE_VALUE;
448 }
449 break;
450
451 case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */
452 default:
453 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
454 break;
455 }
456 }
457 else if (UARTxSource == LL_RCC_UART5_CLKSOURCE)
458 {
459 /* UART5CLK clock frequency */
460 switch (LL_RCC_GetUARTClockSource(UARTxSource))
461 {
462 case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */
463 uart_frequency = RCC_GetSystemClockFreq();
464 break;
465
466 case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */
467 if (LL_RCC_HSI_IsReady())
468 {
469 uart_frequency = HSI_VALUE;
470 }
471 break;
472
473 case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */
474 if (LL_RCC_LSE_IsReady())
475 {
476 uart_frequency = LSE_VALUE;
477 }
478 break;
479
480 case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */
481 default:
482 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
483 break;
484 }
485 }
486 else if (UARTxSource == LL_RCC_UART7_CLKSOURCE)
487 {
488 /* UART7CLK clock frequency */
489 switch (LL_RCC_GetUARTClockSource(UARTxSource))
490 {
491 case LL_RCC_UART7_CLKSOURCE_SYSCLK: /* UART7 Clock is System Clock */
492 uart_frequency = RCC_GetSystemClockFreq();
493 break;
494
495 case LL_RCC_UART7_CLKSOURCE_HSI: /* UART7 Clock is HSI Osc. */
496 if (LL_RCC_HSI_IsReady())
497 {
498 uart_frequency = HSI_VALUE;
499 }
500 break;
501
502 case LL_RCC_UART7_CLKSOURCE_LSE: /* UART7 Clock is LSE Osc. */
503 if (LL_RCC_LSE_IsReady())
504 {
505 uart_frequency = LSE_VALUE;
506 }
507 break;
508
509 case LL_RCC_UART7_CLKSOURCE_PCLK1: /* UART7 Clock is PCLK1 */
510 default:
511 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
512 break;
513 }
514 }
515 else
516 {
517 if (UARTxSource == LL_RCC_UART8_CLKSOURCE)
518 {
519 /* UART8CLK clock frequency */
520 switch (LL_RCC_GetUARTClockSource(UARTxSource))
521 {
522 case LL_RCC_UART8_CLKSOURCE_SYSCLK: /* UART8 Clock is System Clock */
523 uart_frequency = RCC_GetSystemClockFreq();
524 break;
525
526 case LL_RCC_UART8_CLKSOURCE_HSI: /* UART8 Clock is HSI Osc. */
527 if (LL_RCC_HSI_IsReady())
528 {
529 uart_frequency = HSI_VALUE;
530 }
531 break;
532
533 case LL_RCC_UART8_CLKSOURCE_LSE: /* UART8 Clock is LSE Osc. */
534 if (LL_RCC_LSE_IsReady())
535 {
536 uart_frequency = LSE_VALUE;
537 }
538 break;
539
540 case LL_RCC_UART8_CLKSOURCE_PCLK1: /* UART8 Clock is PCLK1 */
541 default:
542 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
543 break;
544 }
545 }
546 }
547 return uart_frequency;
548 }
549
550 /**
551 * @brief Return I2Cx clock frequency
552 * @param I2CxSource This parameter can be one of the following values:
553 * @arg @ref LL_RCC_I2C1_CLKSOURCE
554 * @arg @ref LL_RCC_I2C2_CLKSOURCE
555 * @arg @ref LL_RCC_I2C3_CLKSOURCE
556 * @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
557 *
558 * (*) value not defined in all devices.
559 * @retval I2C clock frequency (in Hz)
560 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
561 */
LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)562 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
563 {
564 uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
565
566 /* Check parameter */
567 assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
568
569 if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
570 {
571 /* I2C1 CLK clock frequency */
572 switch (LL_RCC_GetI2CClockSource(I2CxSource))
573 {
574 case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
575 i2c_frequency = RCC_GetSystemClockFreq();
576 break;
577
578 case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
579 if (LL_RCC_HSI_IsReady())
580 {
581 i2c_frequency = HSI_VALUE;
582 }
583 break;
584
585 case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */
586 default:
587 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
588 break;
589 }
590 }
591 else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
592 {
593 /* I2C2 CLK clock frequency */
594 switch (LL_RCC_GetI2CClockSource(I2CxSource))
595 {
596 case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
597 i2c_frequency = RCC_GetSystemClockFreq();
598 break;
599
600 case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */
601 if (LL_RCC_HSI_IsReady())
602 {
603 i2c_frequency = HSI_VALUE;
604 }
605 break;
606
607 case LL_RCC_I2C2_CLKSOURCE_PCLK1: /* I2C2 Clock is PCLK1 */
608 default:
609 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
610 break;
611 }
612 }
613 else if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
614 {
615 /* I2C3 CLK clock frequency */
616 switch (LL_RCC_GetI2CClockSource(I2CxSource))
617 {
618 case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
619 i2c_frequency = RCC_GetSystemClockFreq();
620 break;
621
622 case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */
623 if (LL_RCC_HSI_IsReady())
624 {
625 i2c_frequency = HSI_VALUE;
626 }
627 break;
628
629 case LL_RCC_I2C3_CLKSOURCE_PCLK1: /* I2C3 Clock is PCLK1 */
630 default:
631 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
632 break;
633 }
634 }
635 #if defined(I2C4)
636 else
637 {
638 if (I2CxSource == LL_RCC_I2C4_CLKSOURCE)
639 {
640 /* I2C4 CLK clock frequency */
641 switch (LL_RCC_GetI2CClockSource(I2CxSource))
642 {
643 case LL_RCC_I2C4_CLKSOURCE_SYSCLK: /* I2C4 Clock is System Clock */
644 i2c_frequency = RCC_GetSystemClockFreq();
645 break;
646
647 case LL_RCC_I2C4_CLKSOURCE_HSI: /* I2C4 Clock is HSI Osc. */
648 if (LL_RCC_HSI_IsReady())
649 {
650 i2c_frequency = HSI_VALUE;
651 }
652 break;
653
654 case LL_RCC_I2C4_CLKSOURCE_PCLK1: /* I2C4 Clock is PCLK1 */
655 default:
656 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
657 break;
658 }
659 }
660 }
661 #endif /* I2C4 */
662
663 return i2c_frequency;
664 }
665
666 /**
667 * @brief Return I2Sx clock frequency
668 * @param I2SxSource This parameter can be one of the following values:
669 * @arg @ref LL_RCC_I2S1_CLKSOURCE
670 * @retval I2S clock frequency (in Hz)
671 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLLI2S oscillator is not ready
672 */
LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)673 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
674 {
675 uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
676
677 /* Check parameter */
678 assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
679
680 if (I2SxSource == LL_RCC_I2S1_CLKSOURCE)
681 {
682 /* I2S1 CLK clock frequency */
683 switch (LL_RCC_GetI2SClockSource(I2SxSource))
684 {
685 case LL_RCC_I2S1_CLKSOURCE_PLLI2S: /* I2S1 Clock is PLLI2S */
686 if (LL_RCC_PLLI2S_IsReady())
687 {
688 i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S();
689 }
690 break;
691
692 case LL_RCC_I2S1_CLKSOURCE_PIN: /* I2S1 Clock is External clock */
693 default:
694 i2s_frequency = EXTERNAL_CLOCK_VALUE;
695 break;
696 }
697 }
698
699 return i2s_frequency;
700 }
701
702 /**
703 * @brief Return LPTIMx clock frequency
704 * @param LPTIMxSource This parameter can be one of the following values:
705 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
706 * @retval LPTIM clock frequency (in Hz)
707 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
708 */
LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)709 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
710 {
711 uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
712
713 /* Check parameter */
714 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
715
716 if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
717 {
718 /* LPTIM1CLK clock frequency */
719 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
720 {
721 case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */
722 if (LL_RCC_LSI_IsReady())
723 {
724 lptim_frequency = LSI_VALUE;
725 }
726 break;
727
728 case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */
729 if (LL_RCC_HSI_IsReady())
730 {
731 lptim_frequency = HSI_VALUE;
732 }
733 break;
734
735 case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */
736 if (LL_RCC_LSE_IsReady())
737 {
738 lptim_frequency = LSE_VALUE;
739 }
740 break;
741
742 case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */
743 default:
744 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
745 break;
746 }
747 }
748
749 return lptim_frequency;
750 }
751
752 /**
753 * @brief Return SAIx clock frequency
754 * @param SAIxSource This parameter can be one of the following values:
755 * @arg @ref LL_RCC_SAI1_CLKSOURCE
756 * @arg @ref LL_RCC_SAI2_CLKSOURCE
757 * @retval SAI clock frequency (in Hz)
758 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
759 */
LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)760 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
761 {
762 uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
763
764 /* Check parameter */
765 assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
766
767 if (SAIxSource == LL_RCC_SAI1_CLKSOURCE)
768 {
769 /* SAI1CLK clock frequency */
770 switch (LL_RCC_GetSAIClockSource(SAIxSource))
771 {
772 case LL_RCC_SAI1_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 clock source */
773 if (LL_RCC_PLLSAI_IsReady())
774 {
775 sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
776 }
777 break;
778
779 case LL_RCC_SAI1_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 clock source */
780 if (LL_RCC_PLLI2S_IsReady())
781 {
782 sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
783 }
784 break;
785
786 #if defined(RCC_SAI1SEL_PLLSRC_SUPPORT)
787 case LL_RCC_SAI1_CLKSOURCE_PLLSRC:
788 switch (LL_RCC_PLL_GetMainSource())
789 {
790 case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI1 clock source */
791 if (LL_RCC_HSE_IsReady())
792 {
793 sai_frequency = HSE_VALUE;
794 }
795 break;
796
797 case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI1 clock source */
798 default:
799 if (LL_RCC_HSI_IsReady())
800 {
801 sai_frequency = HSI_VALUE;
802 }
803 break;
804 }
805 break;
806 #endif /* RCC_SAI1SEL_PLLSRC_SUPPORT */
807 case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */
808 sai_frequency = EXTERNAL_SAI1_CLOCK_VALUE;
809 break;
810
811 default:
812 break;
813 }
814 }
815 else
816 {
817 if (SAIxSource == LL_RCC_SAI2_CLKSOURCE)
818 {
819 /* SAI2CLK clock frequency */
820 switch (LL_RCC_GetSAIClockSource(SAIxSource))
821 {
822 case LL_RCC_SAI2_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI2 clock source */
823 if (LL_RCC_PLLSAI_IsReady())
824 {
825 sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
826 }
827 break;
828
829 case LL_RCC_SAI2_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI2 clock source */
830 if (LL_RCC_PLLI2S_IsReady())
831 {
832 sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
833 }
834 break;
835
836 #if defined(RCC_SAI2SEL_PLLSRC_SUPPORT)
837 case LL_RCC_SAI2_CLKSOURCE_PLLSRC:
838 switch (LL_RCC_PLL_GetMainSource())
839 {
840 case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI2 clock source */
841 if (LL_RCC_HSE_IsReady())
842 {
843 sai_frequency = HSE_VALUE;
844 }
845 break;
846
847 case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI2 clock source */
848 default:
849 if (LL_RCC_HSI_IsReady())
850 {
851 sai_frequency = HSI_VALUE;
852 }
853 break;
854 }
855 break;
856 #endif /* RCC_SAI2SEL_PLLSRC_SUPPORT */
857 case LL_RCC_SAI2_CLKSOURCE_PIN: /* External input clock used as SAI2 clock source */
858 sai_frequency = EXTERNAL_SAI2_CLOCK_VALUE;
859 break;
860
861 default:
862 break;
863 }
864 }
865 }
866
867 return sai_frequency;
868 }
869
870 /**
871 * @brief Return SDMMCx clock frequency
872 * @param SDMMCxSource This parameter can be one of the following values:
873 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE
874 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE (*)
875 *
876 * (*) value not defined in all devices.
877 * @retval SDMMC clock frequency (in Hz)
878 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLL is not ready
879 */
LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)880 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
881 {
882 uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
883
884 /* Check parameter */
885 assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource));
886
887 if (SDMMCxSource == LL_RCC_SDMMC1_CLKSOURCE)
888 {
889 /* SDMMC1CLK clock frequency */
890 switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
891 {
892 case LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK: /* PLL48 clock used as SDMMC1 clock source */
893 switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE))
894 {
895 case LL_RCC_CK48M_CLKSOURCE_PLL: /* PLL clock used as 48Mhz domain clock */
896 if (LL_RCC_PLL_IsReady())
897 {
898 sdmmc_frequency = RCC_PLL_GetFreqDomain_48M();
899 }
900 break;
901
902 case LL_RCC_CK48M_CLKSOURCE_PLLSAI: /* PLLSAI clock used as 48Mhz domain clock */
903 default:
904 if (LL_RCC_PLLSAI_IsReady())
905 {
906 sdmmc_frequency = RCC_PLLSAI_GetFreqDomain_48M();
907 }
908 break;
909 }
910 break;
911
912 case LL_RCC_SDMMC1_CLKSOURCE_SYSCLK: /* PLL clock used as SDMMC1 clock source */
913 default:
914 sdmmc_frequency = RCC_GetSystemClockFreq();
915 break;
916 }
917 }
918 #if defined(SDMMC2)
919 else
920 {
921 /* SDMMC2CLK clock frequency */
922 switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
923 {
924 case LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK: /* PLL48 clock used as SDMMC2 clock source */
925 switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE))
926 {
927 case LL_RCC_CK48M_CLKSOURCE_PLL: /* PLL clock used as 48Mhz domain clock */
928 if (LL_RCC_PLL_IsReady())
929 {
930 sdmmc_frequency = RCC_PLL_GetFreqDomain_48M();
931 }
932 break;
933
934 case LL_RCC_CK48M_CLKSOURCE_PLLSAI: /* PLLSAI clock used as 48Mhz domain clock */
935 default:
936 if (LL_RCC_PLLSAI_IsReady())
937 {
938 sdmmc_frequency = RCC_PLLSAI_GetFreqDomain_48M();
939 }
940 break;
941 }
942 break;
943
944 case LL_RCC_SDMMC2_CLKSOURCE_SYSCLK: /* PLL clock used as SDMMC2 clock source */
945 default:
946 sdmmc_frequency = RCC_GetSystemClockFreq();
947 break;
948 }
949 }
950 #endif /* SDMMC2 */
951
952 return sdmmc_frequency;
953 }
954
955 /**
956 * @brief Return RNGx clock frequency
957 * @param RNGxSource This parameter can be one of the following values:
958 * @arg @ref LL_RCC_RNG_CLKSOURCE
959 * @retval RNG clock frequency (in Hz)
960 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
961 */
LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)962 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
963 {
964 uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
965
966 /* Check parameter */
967 assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
968
969 /* RNGCLK clock frequency */
970 switch (LL_RCC_GetRNGClockSource(RNGxSource))
971 {
972 case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */
973 if (LL_RCC_PLL_IsReady())
974 {
975 rng_frequency = RCC_PLL_GetFreqDomain_48M();
976 }
977 break;
978
979 case LL_RCC_RNG_CLKSOURCE_PLLSAI: /* PLLSAI clock used as RNG clock source */
980 default:
981 if (LL_RCC_PLLSAI_IsReady())
982 {
983 rng_frequency = RCC_PLLSAI_GetFreqDomain_48M();
984 }
985 break;
986 }
987
988 return rng_frequency;
989 }
990
991 #if defined(CEC)
992 /**
993 * @brief Return CEC clock frequency
994 * @param CECxSource This parameter can be one of the following values:
995 * @arg @ref LL_RCC_CEC_CLKSOURCE
996 * @retval CEC clock frequency (in Hz)
997 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
998 */
LL_RCC_GetCECClockFreq(uint32_t CECxSource)999 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
1000 {
1001 uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1002
1003 /* Check parameter */
1004 assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
1005
1006 /* CECCLK clock frequency */
1007 switch (LL_RCC_GetCECClockSource(CECxSource))
1008 {
1009 case LL_RCC_CEC_CLKSOURCE_LSE: /* CEC Clock is LSE Osc. */
1010 if (LL_RCC_LSE_IsReady())
1011 {
1012 cec_frequency = LSE_VALUE;
1013 }
1014 break;
1015
1016 case LL_RCC_CEC_CLKSOURCE_HSI_DIV488: /* CEC Clock is HSI Osc. */
1017 default:
1018 if (LL_RCC_HSI_IsReady())
1019 {
1020 cec_frequency = HSI_VALUE/488U;
1021 }
1022 break;
1023 }
1024
1025 return cec_frequency;
1026 }
1027 #endif /* CEC */
1028
1029 /**
1030 * @brief Return USBx clock frequency
1031 * @param USBxSource This parameter can be one of the following values:
1032 * @arg @ref LL_RCC_USB_CLKSOURCE
1033 * @retval USB clock frequency (in Hz)
1034 */
LL_RCC_GetUSBClockFreq(uint32_t USBxSource)1035 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
1036 {
1037 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1038
1039 /* Check parameter */
1040 assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
1041
1042 /* USBCLK clock frequency */
1043 switch (LL_RCC_GetUSBClockSource(USBxSource))
1044 {
1045 case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
1046 if (LL_RCC_PLL_IsReady())
1047 {
1048 usb_frequency = RCC_PLL_GetFreqDomain_48M();
1049 }
1050 break;
1051
1052 case LL_RCC_USB_CLKSOURCE_PLLSAI: /* PLLSAI clock used as USB clock source */
1053 default:
1054 if (LL_RCC_PLLSAI_IsReady())
1055 {
1056 usb_frequency = RCC_PLLSAI_GetFreqDomain_48M();
1057 }
1058 break;
1059 }
1060
1061 return usb_frequency;
1062 }
1063
1064 #if defined(DFSDM1_Channel0)
1065 /**
1066 * @brief Return DFSDMx clock frequency
1067 * @param DFSDMxSource This parameter can be one of the following values:
1068 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
1069 * @retval DFSDM clock frequency (in Hz)
1070 */
LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)1071 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
1072 {
1073 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1074
1075 /* Check parameter */
1076 assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource));
1077
1078 /* DFSDM1CLK clock frequency */
1079 switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
1080 {
1081 case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK: /* DFSDM1 Clock is SYSCLK */
1082 dfsdm_frequency = RCC_GetSystemClockFreq();
1083 break;
1084
1085 case LL_RCC_DFSDM1_CLKSOURCE_PCLK2: /* DFSDM1 Clock is PCLK2 */
1086 default:
1087 dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1088 break;
1089 }
1090
1091 return dfsdm_frequency;
1092 }
1093
1094 /**
1095 * @brief Return DFSDMx Audio clock frequency
1096 * @param DFSDMxSource This parameter can be one of the following values:
1097 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
1098 * @retval DFSDM clock frequency (in Hz)
1099 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1100 */
LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)1101 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)
1102 {
1103 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1104
1105 /* Check parameter */
1106 assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource));
1107
1108 /* DFSDM1CLK clock frequency */
1109 switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))
1110 {
1111 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1: /* SAI1 clock used as DFSDM1 audio clock */
1112 dfsdm_frequency = LL_RCC_GetSAIClockFreq(LL_RCC_SAI1_CLKSOURCE);
1113 break;
1114
1115 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2: /* SAI2 clock used as DFSDM1 audio clock */
1116 default:
1117 dfsdm_frequency = LL_RCC_GetSAIClockFreq(LL_RCC_SAI2_CLKSOURCE);
1118 break;
1119 }
1120
1121 return dfsdm_frequency;
1122 }
1123 #endif /* DFSDM1_Channel0 */
1124
1125 #if defined(DSI)
1126 /**
1127 * @brief Return DSI clock frequency
1128 * @param DSIxSource This parameter can be one of the following values:
1129 * @arg @ref LL_RCC_DSI_CLKSOURCE
1130 * @retval DSI clock frequency (in Hz)
1131 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1132 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
1133 */
LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)1134 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)
1135 {
1136 uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1137
1138 /* Check parameter */
1139 assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource));
1140
1141 /* DSICLK clock frequency */
1142 switch (LL_RCC_GetDSIClockSource(DSIxSource))
1143 {
1144 case LL_RCC_DSI_CLKSOURCE_PLL: /* DSI Clock is PLL Osc. */
1145 if (LL_RCC_PLL_IsReady())
1146 {
1147 dsi_frequency = RCC_PLL_GetFreqDomain_DSI();
1148 }
1149 break;
1150
1151 case LL_RCC_DSI_CLKSOURCE_PHY: /* DSI Clock is DSI physical clock. */
1152 default:
1153 dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
1154 break;
1155 }
1156
1157 return dsi_frequency;
1158 }
1159 #endif /* DSI */
1160
1161 #if defined(LTDC)
1162 /**
1163 * @brief Return LTDC clock frequency
1164 * @param LTDCxSource This parameter can be one of the following values:
1165 * @arg @ref LL_RCC_LTDC_CLKSOURCE
1166 * @retval LTDC clock frequency (in Hz)
1167 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready
1168 */
LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)1169 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)
1170 {
1171 uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1172
1173 /* Check parameter */
1174 assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource));
1175
1176 if (LL_RCC_PLLSAI_IsReady())
1177 {
1178 ltdc_frequency = RCC_PLLSAI_GetFreqDomain_LTDC();
1179 }
1180
1181 return ltdc_frequency;
1182 }
1183 #endif /* LTDC */
1184
1185 #if defined(SPDIFRX)
1186 /**
1187 * @brief Return SPDIFRX clock frequency
1188 * @param SPDIFRXxSource This parameter can be one of the following values:
1189 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
1190 * @retval SPDIFRX clock frequency (in Hz)
1191 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1192 */
LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource)1193 uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource)
1194 {
1195 uint32_t spdifrx_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1196
1197 /* Check parameter */
1198 assert_param(IS_LL_RCC_SPDIFRX_CLKSOURCE(SPDIFRXxSource));
1199
1200 if (LL_RCC_PLLI2S_IsReady())
1201 {
1202 spdifrx_frequency = RCC_PLLI2S_GetFreqDomain_SPDIFRX();
1203 }
1204
1205 return spdifrx_frequency;
1206 }
1207 #endif /* SPDIFRX */
1208
1209 /**
1210 * @}
1211 */
1212
1213 /**
1214 * @}
1215 */
1216
1217 /** @addtogroup RCC_LL_Private_Functions
1218 * @{
1219 */
1220
1221 /**
1222 * @brief Return SYSTEM clock frequency
1223 * @retval SYSTEM clock frequency (in Hz)
1224 */
RCC_GetSystemClockFreq(void)1225 uint32_t RCC_GetSystemClockFreq(void)
1226 {
1227 uint32_t frequency = 0U;
1228
1229 /* Get SYSCLK source -------------------------------------------------------*/
1230 switch (LL_RCC_GetSysClkSource())
1231 {
1232 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
1233 frequency = HSI_VALUE;
1234 break;
1235
1236 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
1237 frequency = HSE_VALUE;
1238 break;
1239
1240 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
1241 frequency = RCC_PLL_GetFreqDomain_SYS();
1242 break;
1243
1244 default:
1245 frequency = HSI_VALUE;
1246 break;
1247 }
1248
1249 return frequency;
1250 }
1251
1252 /**
1253 * @brief Return HCLK clock frequency
1254 * @param SYSCLK_Frequency SYSCLK clock frequency
1255 * @retval HCLK clock frequency (in Hz)
1256 */
RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)1257 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
1258 {
1259 /* HCLK clock frequency */
1260 return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
1261 }
1262
1263 /**
1264 * @brief Return PCLK1 clock frequency
1265 * @param HCLK_Frequency HCLK clock frequency
1266 * @retval PCLK1 clock frequency (in Hz)
1267 */
RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)1268 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
1269 {
1270 /* PCLK1 clock frequency */
1271 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
1272 }
1273
1274 /**
1275 * @brief Return PCLK2 clock frequency
1276 * @param HCLK_Frequency HCLK clock frequency
1277 * @retval PCLK2 clock frequency (in Hz)
1278 */
RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)1279 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
1280 {
1281 /* PCLK2 clock frequency */
1282 return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
1283 }
1284
1285 /**
1286 * @brief Return PLL clock frequency used for system domain
1287 * @retval PLL clock frequency (in Hz)
1288 */
RCC_PLL_GetFreqDomain_SYS(void)1289 uint32_t RCC_PLL_GetFreqDomain_SYS(void)
1290 {
1291 uint32_t pllinputfreq = 0U, pllsource = 0U;
1292
1293 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1294 SYSCLK = PLL_VCO / PLLP
1295 */
1296 pllsource = LL_RCC_PLL_GetMainSource();
1297
1298 switch (pllsource)
1299 {
1300 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1301 pllinputfreq = HSI_VALUE;
1302 break;
1303
1304 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1305 pllinputfreq = HSE_VALUE;
1306 break;
1307
1308 default:
1309 pllinputfreq = HSI_VALUE;
1310 break;
1311 }
1312 return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1313 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
1314 }
1315
1316 /**
1317 * @brief Return PLL clock frequency used for 48 MHz domain
1318 * @retval PLL clock frequency (in Hz)
1319 */
RCC_PLL_GetFreqDomain_48M(void)1320 uint32_t RCC_PLL_GetFreqDomain_48M(void)
1321 {
1322 uint32_t pllinputfreq = 0U, pllsource = 0U;
1323
1324 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN
1325 48M Domain clock = PLL_VCO / PLLQ
1326 */
1327 pllsource = LL_RCC_PLL_GetMainSource();
1328
1329 switch (pllsource)
1330 {
1331 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1332 pllinputfreq = HSI_VALUE;
1333 break;
1334
1335 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1336 pllinputfreq = HSE_VALUE;
1337 break;
1338
1339 default:
1340 pllinputfreq = HSI_VALUE;
1341 break;
1342 }
1343 return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1344 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
1345 }
1346
1347 #if defined(DSI)
1348 /**
1349 * @brief Return PLL clock frequency used for DSI clock
1350 * @retval PLL clock frequency (in Hz)
1351 */
RCC_PLL_GetFreqDomain_DSI(void)1352 uint32_t RCC_PLL_GetFreqDomain_DSI(void)
1353 {
1354 uint32_t pllinputfreq = 0U, pllsource = 0U;
1355
1356 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1357 DSICLK = PLL_VCO / PLLR
1358 */
1359 pllsource = LL_RCC_PLL_GetMainSource();
1360
1361 switch (pllsource)
1362 {
1363 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1364 pllinputfreq = HSE_VALUE;
1365 break;
1366
1367 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1368 default:
1369 pllinputfreq = HSI_VALUE;
1370 break;
1371 }
1372 return __LL_RCC_CALC_PLLCLK_DSI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1373 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1374 }
1375 #endif /* DSI */
1376
1377 /**
1378 * @brief Return PLLSAI clock frequency used for SAI1 and SAI2 domains
1379 * @retval PLLSAI clock frequency (in Hz)
1380 */
RCC_PLLSAI_GetFreqDomain_SAI(void)1381 uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void)
1382 {
1383 uint32_t pllinputfreq = 0U, pllsource = 0U;
1384
1385 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN
1386 SAI1 and SAI2 domains clock = (PLLSAI_VCO / PLLSAIQ) / PLLSAIDIVQ
1387 */
1388 pllsource = LL_RCC_PLL_GetMainSource();
1389
1390 switch (pllsource)
1391 {
1392 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
1393 pllinputfreq = HSI_VALUE;
1394 break;
1395
1396 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
1397 pllinputfreq = HSE_VALUE;
1398 break;
1399
1400 default:
1401 pllinputfreq = HSI_VALUE;
1402 break;
1403 }
1404 return __LL_RCC_CALC_PLLSAI_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1405 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetQ(), LL_RCC_PLLSAI_GetDIVQ());
1406 }
1407
1408 /**
1409 * @brief Return PLLSAI clock frequency used for 48Mhz domain
1410 * @retval PLLSAI clock frequency (in Hz)
1411 */
RCC_PLLSAI_GetFreqDomain_48M(void)1412 uint32_t RCC_PLLSAI_GetFreqDomain_48M(void)
1413 {
1414 uint32_t pllinputfreq = 0U, pllsource = 0U;
1415
1416 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN
1417 48M Domain clock = PLLSAI_VCO / PLLSAIP
1418 */
1419 pllsource = LL_RCC_PLL_GetMainSource();
1420
1421 switch (pllsource)
1422 {
1423 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
1424 pllinputfreq = HSI_VALUE;
1425 break;
1426
1427 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
1428 pllinputfreq = HSE_VALUE;
1429 break;
1430
1431 default:
1432 pllinputfreq = HSI_VALUE;
1433 break;
1434 }
1435 return __LL_RCC_CALC_PLLSAI_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1436 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetP());
1437 }
1438
1439 #if defined(LTDC)
1440 /**
1441 * @brief Return PLLSAI clock frequency used for LTDC domain
1442 * @retval PLLSAI clock frequency (in Hz)
1443 */
RCC_PLLSAI_GetFreqDomain_LTDC(void)1444 uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void)
1445 {
1446 uint32_t pllinputfreq = 0U, pllsource = 0U;
1447
1448 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN
1449 LTDC Domain clock = (PLLSAI_VCO / PLLSAIR) / PLLSAIDIVR
1450 */
1451 pllsource = LL_RCC_PLL_GetMainSource();
1452
1453 switch (pllsource)
1454 {
1455 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
1456 pllinputfreq = HSI_VALUE;
1457 break;
1458
1459 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
1460 pllinputfreq = HSE_VALUE;
1461 break;
1462
1463 default:
1464 pllinputfreq = HSI_VALUE;
1465 break;
1466 }
1467 return __LL_RCC_CALC_PLLSAI_LTDC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1468 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetR(), LL_RCC_PLLSAI_GetDIVR());
1469 }
1470 #endif /* LTDC */
1471
1472 /**
1473 * @brief Return PLLI2S clock frequency used for SAI1 and SAI2 domains
1474 * @retval PLLI2S clock frequency (in Hz)
1475 */
RCC_PLLI2S_GetFreqDomain_SAI(void)1476 uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void)
1477 {
1478 uint32_t pllinputfreq = 0U, pllsource = 0U;
1479
1480 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN
1481 SAI1 and SAI2 domains clock = (PLLI2S_VCO / PLLI2SQ) / PLLI2SDIVQ
1482 */
1483 pllsource = LL_RCC_PLL_GetMainSource();
1484
1485 switch (pllsource)
1486 {
1487 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
1488 pllinputfreq = HSI_VALUE;
1489 break;
1490
1491 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
1492 pllinputfreq = HSE_VALUE;
1493 break;
1494
1495 default:
1496 pllinputfreq = HSI_VALUE;
1497 break;
1498 }
1499 return __LL_RCC_CALC_PLLI2S_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1500 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ(), LL_RCC_PLLI2S_GetDIVQ());
1501 }
1502
1503 #if defined(SPDIFRX)
1504 /**
1505 * @brief Return PLLI2S clock frequency used for SPDIFRX domain
1506 * @retval PLLI2S clock frequency (in Hz)
1507 */
RCC_PLLI2S_GetFreqDomain_SPDIFRX(void)1508 uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void)
1509 {
1510 uint32_t pllinputfreq = 0U, pllsource = 0U;
1511
1512 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN
1513 SPDIFRX Domain clock = PLLI2S_VCO / PLLI2SP
1514 */
1515 pllsource = LL_RCC_PLL_GetMainSource();
1516
1517 switch (pllsource)
1518 {
1519 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
1520 pllinputfreq = HSI_VALUE;
1521 break;
1522
1523 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
1524 pllinputfreq = HSE_VALUE;
1525 break;
1526
1527 default:
1528 pllinputfreq = HSI_VALUE;
1529 break;
1530 }
1531
1532 return __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1533 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetP());
1534 }
1535 #endif /* SPDIFRX */
1536
1537 /**
1538 * @brief Return PLLI2S clock frequency used for I2S domain
1539 * @retval PLLI2S clock frequency (in Hz)
1540 */
RCC_PLLI2S_GetFreqDomain_I2S(void)1541 uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void)
1542 {
1543 uint32_t pllinputfreq = 0U, pllsource = 0U;
1544
1545 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN
1546 I2S Domain clock = PLLI2S_VCO / PLLI2SR
1547 */
1548 pllsource = LL_RCC_PLL_GetMainSource();
1549
1550 switch (pllsource)
1551 {
1552 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
1553 pllinputfreq = HSE_VALUE;
1554 break;
1555
1556 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
1557 default:
1558 pllinputfreq = HSI_VALUE;
1559 break;
1560 }
1561 return __LL_RCC_CALC_PLLI2S_I2S_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1562 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR());
1563 }
1564
1565 /**
1566 * @}
1567 */
1568
1569 /**
1570 * @}
1571 */
1572
1573 #endif /* defined(RCC) */
1574
1575 /**
1576 * @}
1577 */
1578
1579 #endif /* USE_FULL_LL_DRIVER */
1580
1581
