1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_adc.c
4 * @author MCD Application Team
5 * @brief ADC LL module driver
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32f7xx_ll_adc.h"
22 #include "stm32f7xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif
29
30 /** @addtogroup STM32F7xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
35
36 /** @addtogroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44
45 /** @addtogroup ADC_LL_Private_Macros
46 * @{
47 */
48
49 /* Check of parameters for configuration of ADC hierarchical scope: */
50 /* common to several ADC instances. */
51 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
52 ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
53 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
54 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV6) \
55 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV8) \
56 )
57
58 /* Check of parameters for configuration of ADC hierarchical scope: */
59 /* ADC instance. */
60 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
61 ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
62 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
63 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
64 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
65 )
66
67 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
68 ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
69 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
70 )
71
72 #define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \
73 ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \
74 || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \
75 )
76
77 #define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \
78 ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \
79 || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \
80 )
81
82 /* Check of parameters for configuration of ADC hierarchical scope: */
83 /* ADC group regular */
84 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
85 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
86 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
87 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
88 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
89 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
90 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_TRGO) \
91 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
92 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
93 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
94 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
95 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
96 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
97 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
98 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
99 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
100 )
101
102 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
103 ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
104 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
105 )
106
107 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
108 ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
109 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
110 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
111 )
112
113 #define IS_LL_ADC_REG_FLAG_EOC_SELECTION(__REG_FLAG_EOC_SELECTION__) \
114 ( ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV) \
115 || ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_UNITARY_CONV) \
116 )
117
118 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
119 ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
120 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
121 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
122 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
123 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
124 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
125 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
126 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
127 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
128 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
129 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
130 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
131 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
132 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
133 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
134 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
135 )
136
137 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
138 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
139 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
140 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
141 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
142 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
143 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
144 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
145 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
146 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
147 )
148
149 /* Check of parameters for configuration of ADC hierarchical scope: */
150 /* ADC group injected */
151 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
152 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
153 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
154 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
155 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
156 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
157 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
158 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
159 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
160 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
161 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
162 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
163 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
164 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \
165 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
166 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
167 )
168 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
169 ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
170 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
171 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
172 )
173
174 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
175 ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
176 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
177 )
178
179 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
180 ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
181 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
182 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
183 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
184 )
185
186 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
187 ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
188 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
189 )
190
191 /* Check of parameters for configuration of ADC hierarchical scope: */
192 /* multimode. */
193 #if defined(ADC3)
194 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
195 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
196 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
197 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
198 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
199 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
200 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
201 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
202 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
203 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM) \
204 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT) \
205 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_SIMULT) \
206 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIMULT) \
207 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_INTERL) \
208 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_ALTERN) \
209 )
210 #else
211 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
212 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
213 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
214 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
215 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
216 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
217 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
218 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
219 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
220 )
221 #endif
222
223 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
224 ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
225 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_1) \
226 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_2) \
227 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_3) \
228 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_1) \
229 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_2) \
230 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_3) \
231 )
232
233 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
234 ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \
235 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
236 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \
237 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
238 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
239 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \
240 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \
241 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \
242 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES) \
243 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES) \
244 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES) \
245 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES) \
246 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES) \
247 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES) \
248 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES) \
249 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES) \
250 )
251
252 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
253 ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
254 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
255 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
256 )
257
258 /**
259 * @}
260 */
261
262
263 /* Private function prototypes -----------------------------------------------*/
264
265 /* Exported functions --------------------------------------------------------*/
266 /** @addtogroup ADC_LL_Exported_Functions
267 * @{
268 */
269
270 /** @addtogroup ADC_LL_EF_Init
271 * @{
272 */
273
274 /**
275 * @brief De-initialize registers of all ADC instances belonging to
276 * the same ADC common instance to their default reset values.
277 * @param ADCxy_COMMON ADC common instance
278 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
279 * @retval An ErrorStatus enumeration value:
280 * - SUCCESS: ADC common registers are de-initialized
281 * - ERROR: not applicable
282 */
LL_ADC_CommonDeInit(ADC_Common_TypeDef * ADCxy_COMMON)283 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
284 {
285 /* Check the parameters */
286 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
287
288
289 /* Force reset of ADC clock (core clock) */
290 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC);
291
292 /* Release reset of ADC clock (core clock) */
293 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC);
294
295 return SUCCESS;
296 }
297
298 /**
299 * @brief Initialize some features of ADC common parameters
300 * (all ADC instances belonging to the same ADC common instance)
301 * and multimode (for devices with several ADC instances available).
302 * @note The setting of ADC common parameters is conditioned to
303 * ADC instances state:
304 * All ADC instances belonging to the same ADC common instance
305 * must be disabled.
306 * @param ADCxy_COMMON ADC common instance
307 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
308 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
309 * @retval An ErrorStatus enumeration value:
310 * - SUCCESS: ADC common registers are initialized
311 * - ERROR: ADC common registers are not initialized
312 */
LL_ADC_CommonInit(ADC_Common_TypeDef * ADCxy_COMMON,LL_ADC_CommonInitTypeDef * ADC_CommonInitStruct)313 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
314 {
315 ErrorStatus status = SUCCESS;
316
317 /* Check the parameters */
318 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
319 assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
320
321 assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
322 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
323 {
324 assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
325 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
326 }
327
328 /* Note: Hardware constraint (refer to description of functions */
329 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
330 /* On this STM32 series, setting of these features is conditioned to */
331 /* ADC state: */
332 /* All ADC instances of the ADC common group must be disabled. */
333 if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
334 {
335 /* Configuration of ADC hierarchical scope: */
336 /* - common to several ADC */
337 /* (all ADC instances belonging to the same ADC common instance) */
338 /* - Set ADC clock (conversion clock) */
339 /* - multimode (if several ADC instances available on the */
340 /* selected device) */
341 /* - Set ADC multimode configuration */
342 /* - Set ADC multimode DMA transfer */
343 /* - Set ADC multimode: delay between 2 sampling phases */
344 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
345 {
346 MODIFY_REG(ADCxy_COMMON->CCR,
347 ADC_CCR_ADCPRE
348 | ADC_CCR_MULTI
349 | ADC_CCR_DMA
350 | ADC_CCR_DDS
351 | ADC_CCR_DELAY
352 ,
353 ADC_CommonInitStruct->CommonClock
354 | ADC_CommonInitStruct->Multimode
355 | ADC_CommonInitStruct->MultiDMATransfer
356 | ADC_CommonInitStruct->MultiTwoSamplingDelay
357 );
358 }
359 else
360 {
361 MODIFY_REG(ADCxy_COMMON->CCR,
362 ADC_CCR_ADCPRE
363 | ADC_CCR_MULTI
364 | ADC_CCR_DMA
365 | ADC_CCR_DDS
366 | ADC_CCR_DELAY
367 ,
368 ADC_CommonInitStruct->CommonClock
369 | LL_ADC_MULTI_INDEPENDENT
370 );
371 }
372 }
373 else
374 {
375 /* Initialization error: One or several ADC instances belonging to */
376 /* the same ADC common instance are not disabled. */
377 status = ERROR;
378 }
379
380 return status;
381 }
382
383 /**
384 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
385 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
386 * whose fields will be set to default values.
387 * @retval None
388 */
LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef * ADC_CommonInitStruct)389 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
390 {
391 /* Set ADC_CommonInitStruct fields to default values */
392 /* Set fields of ADC common */
393 /* (all ADC instances belonging to the same ADC common instance) */
394 ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
395
396 /* Set fields of ADC multimode */
397 ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
398 ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
399 ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES;
400 }
401
402 /**
403 * @brief De-initialize registers of the selected ADC instance
404 * to their default reset values.
405 * @note To reset all ADC instances quickly (perform a hard reset),
406 * use function @ref LL_ADC_CommonDeInit().
407 * @param ADCx ADC instance
408 * @retval An ErrorStatus enumeration value:
409 * - SUCCESS: ADC registers are de-initialized
410 * - ERROR: ADC registers are not de-initialized
411 */
LL_ADC_DeInit(ADC_TypeDef * ADCx)412 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
413 {
414 ErrorStatus status = SUCCESS;
415
416 /* Check the parameters */
417 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
418
419 /* Disable ADC instance if not already disabled. */
420 if(LL_ADC_IsEnabled(ADCx) == 1U)
421 {
422 /* Set ADC group regular trigger source to SW start to ensure to not */
423 /* have an external trigger event occurring during the conversion stop */
424 /* ADC disable process. */
425 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
426
427 /* Set ADC group injected trigger source to SW start to ensure to not */
428 /* have an external trigger event occurring during the conversion stop */
429 /* ADC disable process. */
430 LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
431
432 /* Disable the ADC instance */
433 LL_ADC_Disable(ADCx);
434 }
435
436 /* Check whether ADC state is compliant with expected state */
437 /* (hardware requirements of bits state to reset registers below) */
438 if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U)
439 {
440 /* ========== Reset ADC registers ========== */
441 /* Reset register SR */
442 CLEAR_BIT(ADCx->SR,
443 ( LL_ADC_FLAG_STRT
444 | LL_ADC_FLAG_JSTRT
445 | LL_ADC_FLAG_EOCS
446 | LL_ADC_FLAG_OVR
447 | LL_ADC_FLAG_JEOS
448 | LL_ADC_FLAG_AWD1 )
449 );
450
451 /* Reset register CR1 */
452 CLEAR_BIT(ADCx->CR1,
453 ( ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN
454 | ADC_CR1_JAWDEN
455 | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN
456 | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN
457 | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE
458 | ADC_CR1_AWDCH )
459 );
460
461 /* Reset register CR2 */
462 CLEAR_BIT(ADCx->CR2,
463 ( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL
464 | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL
465 | ADC_CR2_ALIGN | ADC_CR2_EOCS
466 | ADC_CR2_DDS | ADC_CR2_DMA
467 | ADC_CR2_CONT | ADC_CR2_ADON )
468 );
469
470 /* Reset register SMPR1 */
471 CLEAR_BIT(ADCx->SMPR1,
472 ( ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16
473 | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13
474 | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10)
475 );
476
477 /* Reset register SMPR2 */
478 CLEAR_BIT(ADCx->SMPR2,
479 ( ADC_SMPR2_SMP9
480 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6
481 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3
482 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0)
483 );
484
485 /* Reset register JOFR1 */
486 CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1);
487 /* Reset register JOFR2 */
488 CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2);
489 /* Reset register JOFR3 */
490 CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3);
491 /* Reset register JOFR4 */
492 CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4);
493
494 /* Reset register HTR */
495 SET_BIT(ADCx->HTR, ADC_HTR_HT);
496 /* Reset register LTR */
497 CLEAR_BIT(ADCx->LTR, ADC_LTR_LT);
498
499 /* Reset register SQR1 */
500 CLEAR_BIT(ADCx->SQR1,
501 ( ADC_SQR1_L
502 | ADC_SQR1_SQ16
503 | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13)
504 );
505
506 /* Reset register SQR2 */
507 CLEAR_BIT(ADCx->SQR2,
508 ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10
509 | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7)
510 );
511
512 /* Reset register SQR3 */
513 CLEAR_BIT(ADCx->SQR3,
514 ( ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4
515 | ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1)
516 );
517
518 /* Reset register JSQR */
519 CLEAR_BIT(ADCx->JSQR,
520 ( ADC_JSQR_JL
521 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
522 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )
523 );
524
525 /* Reset register DR */
526 /* bits in access mode read only, no direct reset applicable */
527
528 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
529 /* bits in access mode read only, no direct reset applicable */
530
531 /* Reset register CCR */
532 CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE | ADC_CCR_ADCPRE);
533 }
534
535 return status;
536 }
537
538 /**
539 * @brief Initialize some features of ADC instance.
540 * @note These parameters have an impact on ADC scope: ADC instance.
541 * Affects both group regular and group injected (availability
542 * of ADC group injected depends on STM32 families).
543 * Refer to corresponding unitary functions into
544 * @ref ADC_LL_EF_Configuration_ADC_Instance .
545 * @note The setting of these parameters by function @ref LL_ADC_Init()
546 * is conditioned to ADC state:
547 * ADC instance must be disabled.
548 * This condition is applied to all ADC features, for efficiency
549 * and compatibility over all STM32 families. However, the different
550 * features can be set under different ADC state conditions
551 * (setting possible with ADC enabled without conversion on going,
552 * ADC enabled with conversion on going, ...)
553 * Each feature can be updated afterwards with a unitary function
554 * and potentially with ADC in a different state than disabled,
555 * refer to description of each function for setting
556 * conditioned to ADC state.
557 * @note After using this function, some other features must be configured
558 * using LL unitary functions.
559 * The minimum configuration remaining to be done is:
560 * - Set ADC group regular or group injected sequencer:
561 * map channel on the selected sequencer rank.
562 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
563 * - Set ADC channel sampling time
564 * Refer to function LL_ADC_SetChannelSamplingTime();
565 * @param ADCx ADC instance
566 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
567 * @retval An ErrorStatus enumeration value:
568 * - SUCCESS: ADC registers are initialized
569 * - ERROR: ADC registers are not initialized
570 */
LL_ADC_Init(ADC_TypeDef * ADCx,LL_ADC_InitTypeDef * ADC_InitStruct)571 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
572 {
573 ErrorStatus status = SUCCESS;
574
575 /* Check the parameters */
576 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
577
578 assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
579 assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
580 assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode));
581
582 /* Note: Hardware constraint (refer to description of this function): */
583 /* ADC instance must be disabled. */
584 if(LL_ADC_IsEnabled(ADCx) == 0U)
585 {
586 /* Configuration of ADC hierarchical scope: */
587 /* - ADC instance */
588 /* - Set ADC data resolution */
589 /* - Set ADC conversion data alignment */
590 MODIFY_REG(ADCx->CR1,
591 ADC_CR1_RES
592 | ADC_CR1_SCAN
593 ,
594 ADC_InitStruct->Resolution
595 | ADC_InitStruct->SequencersScanMode
596 );
597
598 MODIFY_REG(ADCx->CR2,
599 ADC_CR2_ALIGN
600 ,
601 ADC_InitStruct->DataAlignment
602 );
603
604 }
605 else
606 {
607 /* Initialization error: ADC instance is not disabled. */
608 status = ERROR;
609 }
610 return status;
611 }
612
613 /**
614 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
615 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
616 * whose fields will be set to default values.
617 * @retval None
618 */
LL_ADC_StructInit(LL_ADC_InitTypeDef * ADC_InitStruct)619 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
620 {
621 /* Set ADC_InitStruct fields to default values */
622 /* Set fields of ADC instance */
623 ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
624 ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
625
626 /* Enable scan mode to have a generic behavior with ADC of other */
627 /* STM32 families, without this setting available: */
628 /* ADC group regular sequencer and ADC group injected sequencer depend */
629 /* only of their own configuration. */
630 ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE;
631
632 }
633
634 /**
635 * @brief Initialize some features of ADC group regular.
636 * @note These parameters have an impact on ADC scope: ADC group regular.
637 * Refer to corresponding unitary functions into
638 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
639 * (functions with prefix "REG").
640 * @note The setting of these parameters by function @ref LL_ADC_Init()
641 * is conditioned to ADC state:
642 * ADC instance must be disabled.
643 * This condition is applied to all ADC features, for efficiency
644 * and compatibility over all STM32 families. However, the different
645 * features can be set under different ADC state conditions
646 * (setting possible with ADC enabled without conversion on going,
647 * ADC enabled with conversion on going, ...)
648 * Each feature can be updated afterwards with a unitary function
649 * and potentially with ADC in a different state than disabled,
650 * refer to description of each function for setting
651 * conditioned to ADC state.
652 * @note After using this function, other features must be configured
653 * using LL unitary functions.
654 * The minimum configuration remaining to be done is:
655 * - Set ADC group regular or group injected sequencer:
656 * map channel on the selected sequencer rank.
657 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
658 * - Set ADC channel sampling time
659 * Refer to function LL_ADC_SetChannelSamplingTime();
660 * @param ADCx ADC instance
661 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
662 * @retval An ErrorStatus enumeration value:
663 * - SUCCESS: ADC registers are initialized
664 * - ERROR: ADC registers are not initialized
665 */
LL_ADC_REG_Init(ADC_TypeDef * ADCx,LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct)666 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
667 {
668 ErrorStatus status = SUCCESS;
669
670 /* Check the parameters */
671 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
672 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
673 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
674 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
675 {
676 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
677 }
678 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
679 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
680
681 /* ADC group regular continuous mode and discontinuous mode */
682 /* can not be enabled simultenaeously */
683 assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
684 || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
685
686 /* Note: Hardware constraint (refer to description of this function): */
687 /* ADC instance must be disabled. */
688 if(LL_ADC_IsEnabled(ADCx) == 0U)
689 {
690 /* Configuration of ADC hierarchical scope: */
691 /* - ADC group regular */
692 /* - Set ADC group regular trigger source */
693 /* - Set ADC group regular sequencer length */
694 /* - Set ADC group regular sequencer discontinuous mode */
695 /* - Set ADC group regular continuous mode */
696 /* - Set ADC group regular conversion data transfer: no transfer or */
697 /* transfer by DMA, and DMA requests mode */
698 /* Note: On this STM32 series, ADC trigger edge is set when starting */
699 /* ADC conversion. */
700 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
701 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
702 {
703 MODIFY_REG(ADCx->CR1,
704 ADC_CR1_DISCEN
705 | ADC_CR1_DISCNUM
706 ,
707 ADC_REG_InitStruct->SequencerLength
708 | ADC_REG_InitStruct->SequencerDiscont
709 );
710 }
711 else
712 {
713 MODIFY_REG(ADCx->CR1,
714 ADC_CR1_DISCEN
715 | ADC_CR1_DISCNUM
716 ,
717 ADC_REG_InitStruct->SequencerLength
718 | LL_ADC_REG_SEQ_DISCONT_DISABLE
719 );
720 }
721
722 MODIFY_REG(ADCx->CR2,
723 ADC_CR2_EXTSEL
724 | ADC_CR2_EXTEN
725 | ADC_CR2_CONT
726 | ADC_CR2_DMA
727 | ADC_CR2_DDS
728 ,
729 (ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL)
730 | ADC_REG_InitStruct->ContinuousMode
731 | ADC_REG_InitStruct->DMATransfer
732 );
733
734 /* Set ADC group regular sequencer length and scan direction */
735 /* Note: Hardware constraint (refer to description of this function): */
736 /* Note: If ADC instance feature scan mode is disabled */
737 /* (refer to ADC instance initialization structure */
738 /* parameter @ref SequencersScanMode */
739 /* or function @ref LL_ADC_SetSequencersScanMode() ), */
740 /* this parameter is discarded. */
741 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
742 }
743 else
744 {
745 /* Initialization error: ADC instance is not disabled. */
746 status = ERROR;
747 }
748 return status;
749 }
750
751 /**
752 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
753 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
754 * whose fields will be set to default values.
755 * @retval None
756 */
LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct)757 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
758 {
759 /* Set ADC_REG_InitStruct fields to default values */
760 /* Set fields of ADC group regular */
761 /* Note: On this STM32 series, ADC trigger edge is set when starting */
762 /* ADC conversion. */
763 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
764 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
765 ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
766 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
767 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
768 ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
769 }
770
771 /**
772 * @brief Initialize some features of ADC group injected.
773 * @note These parameters have an impact on ADC scope: ADC group injected.
774 * Refer to corresponding unitary functions into
775 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
776 * (functions with prefix "INJ").
777 * @note The setting of these parameters by function @ref LL_ADC_Init()
778 * is conditioned to ADC state:
779 * ADC instance must be disabled.
780 * This condition is applied to all ADC features, for efficiency
781 * and compatibility over all STM32 families. However, the different
782 * features can be set under different ADC state conditions
783 * (setting possible with ADC enabled without conversion on going,
784 * ADC enabled with conversion on going, ...)
785 * Each feature can be updated afterwards with a unitary function
786 * and potentially with ADC in a different state than disabled,
787 * refer to description of each function for setting
788 * conditioned to ADC state.
789 * @note After using this function, other features must be configured
790 * using LL unitary functions.
791 * The minimum configuration remaining to be done is:
792 * - Set ADC group injected sequencer:
793 * map channel on the selected sequencer rank.
794 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
795 * - Set ADC channel sampling time
796 * Refer to function LL_ADC_SetChannelSamplingTime();
797 * @param ADCx ADC instance
798 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
799 * @retval An ErrorStatus enumeration value:
800 * - SUCCESS: ADC registers are initialized
801 * - ERROR: ADC registers are not initialized
802 */
LL_ADC_INJ_Init(ADC_TypeDef * ADCx,LL_ADC_INJ_InitTypeDef * ADC_INJ_InitStruct)803 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
804 {
805 ErrorStatus status = SUCCESS;
806
807 /* Check the parameters */
808 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
809 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
810 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
811 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
812 {
813 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
814 }
815 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
816
817 /* Note: Hardware constraint (refer to description of this function): */
818 /* ADC instance must be disabled. */
819 if(LL_ADC_IsEnabled(ADCx) == 0U)
820 {
821 /* Configuration of ADC hierarchical scope: */
822 /* - ADC group injected */
823 /* - Set ADC group injected trigger source */
824 /* - Set ADC group injected sequencer length */
825 /* - Set ADC group injected sequencer discontinuous mode */
826 /* - Set ADC group injected conversion trigger: independent or */
827 /* from ADC group regular */
828 /* Note: On this STM32 series, ADC trigger edge is set when starting */
829 /* ADC conversion. */
830 /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */
831 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
832 {
833 MODIFY_REG(ADCx->CR1,
834 ADC_CR1_JDISCEN
835 | ADC_CR1_JAUTO
836 ,
837 ADC_INJ_InitStruct->SequencerDiscont
838 | ADC_INJ_InitStruct->TrigAuto
839 );
840 }
841 else
842 {
843 MODIFY_REG(ADCx->CR1,
844 ADC_CR1_JDISCEN
845 | ADC_CR1_JAUTO
846 ,
847 LL_ADC_REG_SEQ_DISCONT_DISABLE
848 | ADC_INJ_InitStruct->TrigAuto
849 );
850 }
851
852 MODIFY_REG(ADCx->CR2,
853 ADC_CR2_JEXTSEL
854 | ADC_CR2_JEXTEN
855 ,
856 (ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL)
857 );
858
859 /* Note: Hardware constraint (refer to description of this function): */
860 /* Note: If ADC instance feature scan mode is disabled */
861 /* (refer to ADC instance initialization structure */
862 /* parameter @ref SequencersScanMode */
863 /* or function @ref LL_ADC_SetSequencersScanMode() ), */
864 /* this parameter is discarded. */
865 LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength);
866 }
867 else
868 {
869 /* Initialization error: ADC instance is not disabled. */
870 status = ERROR;
871 }
872 return status;
873 }
874
875 /**
876 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
877 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
878 * whose fields will be set to default values.
879 * @retval None
880 */
LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef * ADC_INJ_InitStruct)881 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
882 {
883 /* Set ADC_INJ_InitStruct fields to default values */
884 /* Set fields of ADC group injected */
885 ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
886 ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
887 ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
888 ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
889 }
890
891 /**
892 * @}
893 */
894
895 /**
896 * @}
897 */
898
899 /**
900 * @}
901 */
902
903 #endif /* ADC1 || ADC2 || ADC3 */
904
905 /**
906 * @}
907 */
908
909 #endif /* USE_FULL_LL_DRIVER */
910
911
