1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_sram.c
4 * @author MCD Application Team
5 * @brief SRAM HAL module driver.
6 * This file provides a generic firmware to drive SRAM memories
7 * mounted as external device.
8 *
9 ******************************************************************************
10 * @attention
11 *
12 * Copyright (c) 2017 STMicroelectronics.
13 * All rights reserved.
14 *
15 * This software is licensed under terms that can be found in the LICENSE file
16 * in the root directory of this software component.
17 * If no LICENSE file comes with this software, it is provided AS-IS.
18 *
19 ******************************************************************************
20 @verbatim
21 ==============================================================================
22 ##### How to use this driver #####
23 ==============================================================================
24 [..]
25 This driver is a generic layered driver which contains a set of APIs used to
26 control SRAM memories. It uses the FMC layer functions to interface
27 with SRAM devices.
28 The following sequence should be followed to configure the FMC to interface
29 with SRAM/PSRAM memories:
30
31 (#) Declare a SRAM_HandleTypeDef handle structure, for example:
32 SRAM_HandleTypeDef hsram; and:
33
34 (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
35 values of the structure member.
36
37 (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
38 base register instance for NOR or SRAM device
39
40 (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
41 base register instance for NOR or SRAM extended mode
42
43 (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
44 mode timings; for example:
45 FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
46 and fill its fields with the allowed values of the structure member.
47
48 (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
49 performs the following sequence:
50
51 (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
52 (##) Control register configuration using the FMC NORSRAM interface function
53 FMC_NORSRAM_Init()
54 (##) Timing register configuration using the FMC NORSRAM interface function
55 FMC_NORSRAM_Timing_Init()
56 (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
57 FMC_NORSRAM_Extended_Timing_Init()
58 (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
59
60 (#) At this stage you can perform read/write accesses from/to the memory connected
61 to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
62 following APIs:
63 (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
64 (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
65
66 (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
67 HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
68
69 (#) You can continuously monitor the SRAM device HAL state by calling the function
70 HAL_SRAM_GetState()
71
72 *** Callback registration ***
73 =============================================
74 [..]
75 The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1
76 allows the user to configure dynamically the driver callbacks.
77
78 Use Functions HAL_SRAM_RegisterCallback() to register a user callback,
79 it allows to register following callbacks:
80 (+) MspInitCallback : SRAM MspInit.
81 (+) MspDeInitCallback : SRAM MspDeInit.
82 This function takes as parameters the HAL peripheral handle, the Callback ID
83 and a pointer to the user callback function.
84
85 Use function HAL_SRAM_UnRegisterCallback() to reset a callback to the default
86 weak (surcharged) function. It allows to reset following callbacks:
87 (+) MspInitCallback : SRAM MspInit.
88 (+) MspDeInitCallback : SRAM MspDeInit.
89 This function) takes as parameters the HAL peripheral handle and the Callback ID.
90
91 By default, after the HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
92 all callbacks are reset to the corresponding legacy weak (surcharged) functions.
93 Exception done for MspInit and MspDeInit callbacks that are respectively
94 reset to the legacy weak (surcharged) functions in the HAL_SRAM_Init
95 and HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
96 If not, MspInit or MspDeInit are not null, the HAL_SRAM_Init and HAL_SRAM_DeInit
97 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
98
99 Callbacks can be registered/unregistered in READY state only.
100 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
101 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
102 during the Init/DeInit.
103 In that case first register the MspInit/MspDeInit user callbacks
104 using HAL_SRAM_RegisterCallback before calling HAL_SRAM_DeInit
105 or HAL_SRAM_Init function.
106
107 When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
108 not defined, the callback registering feature is not available
109 and weak (surcharged) callbacks are used.
110
111 @endverbatim
112 ******************************************************************************
113 */
114
115 /* Includes ------------------------------------------------------------------*/
116 #include "stm32f7xx_hal.h"
117
118
119 /** @addtogroup STM32F7xx_HAL_Driver
120 * @{
121 */
122
123 #ifdef HAL_SRAM_MODULE_ENABLED
124
125 /** @defgroup SRAM SRAM
126 * @brief SRAM driver modules
127 * @{
128 */
129
130 /* Private typedef -----------------------------------------------------------*/
131 /* Private define ------------------------------------------------------------*/
132 /* Private macro -------------------------------------------------------------*/
133 /* Private variables ---------------------------------------------------------*/
134 /* Private function prototypes -----------------------------------------------*/
135 static void SRAM_DMACplt(DMA_HandleTypeDef *hdma);
136 static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
137 static void SRAM_DMAError(DMA_HandleTypeDef *hdma);
138
139 /* Exported functions --------------------------------------------------------*/
140
141 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
142 * @{
143 */
144
145 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
146 * @brief Initialization and Configuration functions.
147 *
148 @verbatim
149 ==============================================================================
150 ##### SRAM Initialization and de_initialization functions #####
151 ==============================================================================
152 [..] This section provides functions allowing to initialize/de-initialize
153 the SRAM memory
154
155 @endverbatim
156 * @{
157 */
158
159 /**
160 * @brief Performs the SRAM device initialization sequence
161 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
162 * the configuration information for SRAM module.
163 * @param Timing Pointer to SRAM control timing structure
164 * @param ExtTiming Pointer to SRAM extended mode timing structure
165 * @retval HAL status
166 */
HAL_SRAM_Init(SRAM_HandleTypeDef * hsram,FMC_NORSRAM_TimingTypeDef * Timing,FMC_NORSRAM_TimingTypeDef * ExtTiming)167 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing,
168 FMC_NORSRAM_TimingTypeDef *ExtTiming)
169 {
170 /* Check the SRAM handle parameter */
171 if (hsram == NULL)
172 {
173 return HAL_ERROR;
174 }
175
176 if (hsram->State == HAL_SRAM_STATE_RESET)
177 {
178 /* Allocate lock resource and initialize it */
179 hsram->Lock = HAL_UNLOCKED;
180
181 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
182 if (hsram->MspInitCallback == NULL)
183 {
184 hsram->MspInitCallback = HAL_SRAM_MspInit;
185 }
186 hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
187 hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
188
189 /* Init the low level hardware */
190 hsram->MspInitCallback(hsram);
191 #else
192 /* Initialize the low level hardware (MSP) */
193 HAL_SRAM_MspInit(hsram);
194 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
195 }
196
197 /* Initialize SRAM control Interface */
198 (void)FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
199
200 /* Initialize SRAM timing Interface */
201 (void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
202
203 /* Initialize SRAM extended mode timing Interface */
204 (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,
205 hsram->Init.ExtendedMode);
206
207 /* Enable the NORSRAM device */
208 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
209
210 /* Initialize the SRAM controller state */
211 hsram->State = HAL_SRAM_STATE_READY;
212
213 return HAL_OK;
214 }
215
216 /**
217 * @brief Performs the SRAM device De-initialization sequence.
218 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
219 * the configuration information for SRAM module.
220 * @retval HAL status
221 */
HAL_SRAM_DeInit(SRAM_HandleTypeDef * hsram)222 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
223 {
224 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
225 if (hsram->MspDeInitCallback == NULL)
226 {
227 hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
228 }
229
230 /* DeInit the low level hardware */
231 hsram->MspDeInitCallback(hsram);
232 #else
233 /* De-Initialize the low level hardware (MSP) */
234 HAL_SRAM_MspDeInit(hsram);
235 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
236
237 /* Configure the SRAM registers with their reset values */
238 (void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
239
240 /* Reset the SRAM controller state */
241 hsram->State = HAL_SRAM_STATE_RESET;
242
243 /* Release Lock */
244 __HAL_UNLOCK(hsram);
245
246 return HAL_OK;
247 }
248
249 /**
250 * @brief SRAM MSP Init.
251 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
252 * the configuration information for SRAM module.
253 * @retval None
254 */
HAL_SRAM_MspInit(SRAM_HandleTypeDef * hsram)255 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
256 {
257 /* Prevent unused argument(s) compilation warning */
258 UNUSED(hsram);
259
260 /* NOTE : This function Should not be modified, when the callback is needed,
261 the HAL_SRAM_MspInit could be implemented in the user file
262 */
263 }
264
265 /**
266 * @brief SRAM MSP DeInit.
267 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
268 * the configuration information for SRAM module.
269 * @retval None
270 */
HAL_SRAM_MspDeInit(SRAM_HandleTypeDef * hsram)271 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
272 {
273 /* Prevent unused argument(s) compilation warning */
274 UNUSED(hsram);
275
276 /* NOTE : This function Should not be modified, when the callback is needed,
277 the HAL_SRAM_MspDeInit could be implemented in the user file
278 */
279 }
280
281 /**
282 * @brief DMA transfer complete callback.
283 * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
284 * the configuration information for SRAM module.
285 * @retval None
286 */
HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef * hdma)287 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
288 {
289 /* Prevent unused argument(s) compilation warning */
290 UNUSED(hdma);
291
292 /* NOTE : This function Should not be modified, when the callback is needed,
293 the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
294 */
295 }
296
297 /**
298 * @brief DMA transfer complete error callback.
299 * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
300 * the configuration information for SRAM module.
301 * @retval None
302 */
HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef * hdma)303 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
304 {
305 /* Prevent unused argument(s) compilation warning */
306 UNUSED(hdma);
307
308 /* NOTE : This function Should not be modified, when the callback is needed,
309 the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
310 */
311 }
312
313 /**
314 * @}
315 */
316
317 /** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
318 * @brief Input Output and memory control functions
319 *
320 @verbatim
321 ==============================================================================
322 ##### SRAM Input and Output functions #####
323 ==============================================================================
324 [..]
325 This section provides functions allowing to use and control the SRAM memory
326
327 @endverbatim
328 * @{
329 */
330
331 /**
332 * @brief Reads 8-bit buffer from SRAM memory.
333 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
334 * the configuration information for SRAM module.
335 * @param pAddress Pointer to read start address
336 * @param pDstBuffer Pointer to destination buffer
337 * @param BufferSize Size of the buffer to read from memory
338 * @retval HAL status
339 */
HAL_SRAM_Read_8b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint8_t * pDstBuffer,uint32_t BufferSize)340 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
341 uint32_t BufferSize)
342 {
343 uint32_t size;
344 __IO uint8_t *psramaddress = (uint8_t *)pAddress;
345 uint8_t *pdestbuff = pDstBuffer;
346 HAL_SRAM_StateTypeDef state = hsram->State;
347
348 /* Check the SRAM controller state */
349 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
350 {
351 /* Process Locked */
352 __HAL_LOCK(hsram);
353
354 /* Update the SRAM controller state */
355 hsram->State = HAL_SRAM_STATE_BUSY;
356
357 /* Read data from memory */
358 for (size = BufferSize; size != 0U; size--)
359 {
360 *pdestbuff = *psramaddress;
361 pdestbuff++;
362 psramaddress++;
363 }
364
365 /* Update the SRAM controller state */
366 hsram->State = state;
367
368 /* Process unlocked */
369 __HAL_UNLOCK(hsram);
370 }
371 else
372 {
373 return HAL_ERROR;
374 }
375
376 return HAL_OK;
377 }
378
379 /**
380 * @brief Writes 8-bit buffer to SRAM memory.
381 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
382 * the configuration information for SRAM module.
383 * @param pAddress Pointer to write start address
384 * @param pSrcBuffer Pointer to source buffer to write
385 * @param BufferSize Size of the buffer to write to memory
386 * @retval HAL status
387 */
HAL_SRAM_Write_8b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint8_t * pSrcBuffer,uint32_t BufferSize)388 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
389 uint32_t BufferSize)
390 {
391 uint32_t size;
392 __IO uint8_t *psramaddress = (uint8_t *)pAddress;
393 uint8_t *psrcbuff = pSrcBuffer;
394
395 /* Check the SRAM controller state */
396 if (hsram->State == HAL_SRAM_STATE_READY)
397 {
398 /* Process Locked */
399 __HAL_LOCK(hsram);
400
401 /* Update the SRAM controller state */
402 hsram->State = HAL_SRAM_STATE_BUSY;
403
404 /* Write data to memory */
405 for (size = BufferSize; size != 0U; size--)
406 {
407 *psramaddress = *psrcbuff;
408 psrcbuff++;
409 psramaddress++;
410 }
411
412 /* Update the SRAM controller state */
413 hsram->State = HAL_SRAM_STATE_READY;
414
415 /* Process unlocked */
416 __HAL_UNLOCK(hsram);
417 }
418 else
419 {
420 return HAL_ERROR;
421 }
422
423 return HAL_OK;
424 }
425
426 /**
427 * @brief Reads 16-bit buffer from SRAM memory.
428 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
429 * the configuration information for SRAM module.
430 * @param pAddress Pointer to read start address
431 * @param pDstBuffer Pointer to destination buffer
432 * @param BufferSize Size of the buffer to read from memory
433 * @retval HAL status
434 */
HAL_SRAM_Read_16b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint16_t * pDstBuffer,uint32_t BufferSize)435 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
436 uint32_t BufferSize)
437 {
438 uint32_t size;
439 __IO uint32_t *psramaddress = pAddress;
440 uint16_t *pdestbuff = pDstBuffer;
441 uint8_t limit;
442 HAL_SRAM_StateTypeDef state = hsram->State;
443
444 /* Check the SRAM controller state */
445 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
446 {
447 /* Process Locked */
448 __HAL_LOCK(hsram);
449
450 /* Update the SRAM controller state */
451 hsram->State = HAL_SRAM_STATE_BUSY;
452
453 /* Check if the size is a 32-bits multiple */
454 limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
455
456 /* Read data from memory */
457 for (size = BufferSize; size != limit; size -= 2U)
458 {
459 *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
460 pdestbuff++;
461 *pdestbuff = (uint16_t)(((*psramaddress) & 0xFFFF0000U) >> 16U);
462 pdestbuff++;
463 psramaddress++;
464 }
465
466 /* Read last 16-bits if size is not 32-bits multiple */
467 if (limit != 0U)
468 {
469 *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
470 }
471
472 /* Update the SRAM controller state */
473 hsram->State = state;
474
475 /* Process unlocked */
476 __HAL_UNLOCK(hsram);
477 }
478 else
479 {
480 return HAL_ERROR;
481 }
482
483 return HAL_OK;
484 }
485
486 /**
487 * @brief Writes 16-bit buffer to SRAM memory.
488 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
489 * the configuration information for SRAM module.
490 * @param pAddress Pointer to write start address
491 * @param pSrcBuffer Pointer to source buffer to write
492 * @param BufferSize Size of the buffer to write to memory
493 * @retval HAL status
494 */
HAL_SRAM_Write_16b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint16_t * pSrcBuffer,uint32_t BufferSize)495 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
496 uint32_t BufferSize)
497 {
498 uint32_t size;
499 __IO uint32_t *psramaddress = pAddress;
500 uint16_t *psrcbuff = pSrcBuffer;
501 uint8_t limit;
502
503 /* Check the SRAM controller state */
504 if (hsram->State == HAL_SRAM_STATE_READY)
505 {
506 /* Process Locked */
507 __HAL_LOCK(hsram);
508
509 /* Update the SRAM controller state */
510 hsram->State = HAL_SRAM_STATE_BUSY;
511
512 /* Check if the size is a 32-bits multiple */
513 limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
514
515 /* Write data to memory */
516 for (size = BufferSize; size != limit; size -= 2U)
517 {
518 *psramaddress = (uint32_t)(*psrcbuff);
519 psrcbuff++;
520 *psramaddress |= ((uint32_t)(*psrcbuff) << 16U);
521 psrcbuff++;
522 psramaddress++;
523 }
524
525 /* Write last 16-bits if size is not 32-bits multiple */
526 if (limit != 0U)
527 {
528 *psramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psramaddress) & 0xFFFF0000U);
529 }
530
531 /* Update the SRAM controller state */
532 hsram->State = HAL_SRAM_STATE_READY;
533
534 /* Process unlocked */
535 __HAL_UNLOCK(hsram);
536 }
537 else
538 {
539 return HAL_ERROR;
540 }
541
542 return HAL_OK;
543 }
544
545 /**
546 * @brief Reads 32-bit buffer from SRAM memory.
547 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
548 * the configuration information for SRAM module.
549 * @param pAddress Pointer to read start address
550 * @param pDstBuffer Pointer to destination buffer
551 * @param BufferSize Size of the buffer to read from memory
552 * @retval HAL status
553 */
HAL_SRAM_Read_32b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)554 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
555 uint32_t BufferSize)
556 {
557 uint32_t size;
558 __IO uint32_t *psramaddress = pAddress;
559 uint32_t *pdestbuff = pDstBuffer;
560 HAL_SRAM_StateTypeDef state = hsram->State;
561
562 /* Check the SRAM controller state */
563 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
564 {
565 /* Process Locked */
566 __HAL_LOCK(hsram);
567
568 /* Update the SRAM controller state */
569 hsram->State = HAL_SRAM_STATE_BUSY;
570
571 /* Read data from memory */
572 for (size = BufferSize; size != 0U; size--)
573 {
574 *pdestbuff = *psramaddress;
575 pdestbuff++;
576 psramaddress++;
577 }
578
579 /* Update the SRAM controller state */
580 hsram->State = state;
581
582 /* Process unlocked */
583 __HAL_UNLOCK(hsram);
584 }
585 else
586 {
587 return HAL_ERROR;
588 }
589
590 return HAL_OK;
591 }
592
593 /**
594 * @brief Writes 32-bit buffer to SRAM memory.
595 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
596 * the configuration information for SRAM module.
597 * @param pAddress Pointer to write start address
598 * @param pSrcBuffer Pointer to source buffer to write
599 * @param BufferSize Size of the buffer to write to memory
600 * @retval HAL status
601 */
HAL_SRAM_Write_32b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)602 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
603 uint32_t BufferSize)
604 {
605 uint32_t size;
606 __IO uint32_t *psramaddress = pAddress;
607 uint32_t *psrcbuff = pSrcBuffer;
608
609 /* Check the SRAM controller state */
610 if (hsram->State == HAL_SRAM_STATE_READY)
611 {
612 /* Process Locked */
613 __HAL_LOCK(hsram);
614
615 /* Update the SRAM controller state */
616 hsram->State = HAL_SRAM_STATE_BUSY;
617
618 /* Write data to memory */
619 for (size = BufferSize; size != 0U; size--)
620 {
621 *psramaddress = *psrcbuff;
622 psrcbuff++;
623 psramaddress++;
624 }
625
626 /* Update the SRAM controller state */
627 hsram->State = HAL_SRAM_STATE_READY;
628
629 /* Process unlocked */
630 __HAL_UNLOCK(hsram);
631 }
632 else
633 {
634 return HAL_ERROR;
635 }
636
637 return HAL_OK;
638 }
639
640 /**
641 * @brief Reads a Words data from the SRAM memory using DMA transfer.
642 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
643 * the configuration information for SRAM module.
644 * @param pAddress Pointer to read start address
645 * @param pDstBuffer Pointer to destination buffer
646 * @param BufferSize Size of the buffer to read from memory
647 * @retval HAL status
648 */
HAL_SRAM_Read_DMA(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)649 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
650 uint32_t BufferSize)
651 {
652 HAL_StatusTypeDef status;
653 HAL_SRAM_StateTypeDef state = hsram->State;
654
655 /* Check the SRAM controller state */
656 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
657 {
658 /* Process Locked */
659 __HAL_LOCK(hsram);
660
661 /* Update the SRAM controller state */
662 hsram->State = HAL_SRAM_STATE_BUSY;
663
664 /* Configure DMA user callbacks */
665 if (state == HAL_SRAM_STATE_READY)
666 {
667 hsram->hdma->XferCpltCallback = SRAM_DMACplt;
668 }
669 else
670 {
671 hsram->hdma->XferCpltCallback = SRAM_DMACpltProt;
672 }
673 hsram->hdma->XferErrorCallback = SRAM_DMAError;
674
675 /* Enable the DMA Stream */
676 status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
677
678 /* Process unlocked */
679 __HAL_UNLOCK(hsram);
680 }
681 else
682 {
683 status = HAL_ERROR;
684 }
685
686 return status;
687 }
688
689 /**
690 * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
691 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
692 * the configuration information for SRAM module.
693 * @param pAddress Pointer to write start address
694 * @param pSrcBuffer Pointer to source buffer to write
695 * @param BufferSize Size of the buffer to write to memory
696 * @retval HAL status
697 */
HAL_SRAM_Write_DMA(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)698 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
699 uint32_t BufferSize)
700 {
701 HAL_StatusTypeDef status;
702
703 /* Check the SRAM controller state */
704 if (hsram->State == HAL_SRAM_STATE_READY)
705 {
706 /* Process Locked */
707 __HAL_LOCK(hsram);
708
709 /* Update the SRAM controller state */
710 hsram->State = HAL_SRAM_STATE_BUSY;
711
712 /* Configure DMA user callbacks */
713 hsram->hdma->XferCpltCallback = SRAM_DMACplt;
714 hsram->hdma->XferErrorCallback = SRAM_DMAError;
715
716 /* Enable the DMA Stream */
717 status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
718
719 /* Process unlocked */
720 __HAL_UNLOCK(hsram);
721 }
722 else
723 {
724 status = HAL_ERROR;
725 }
726
727 return status;
728 }
729
730 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
731 /**
732 * @brief Register a User SRAM Callback
733 * To be used instead of the weak (surcharged) predefined callback
734 * @param hsram : SRAM handle
735 * @param CallbackId : ID of the callback to be registered
736 * This parameter can be one of the following values:
737 * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
738 * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
739 * @param pCallback : pointer to the Callback function
740 * @retval status
741 */
HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef * hsram,HAL_SRAM_CallbackIDTypeDef CallbackId,pSRAM_CallbackTypeDef pCallback)742 HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
743 pSRAM_CallbackTypeDef pCallback)
744 {
745 HAL_StatusTypeDef status = HAL_OK;
746 HAL_SRAM_StateTypeDef state;
747
748 if (pCallback == NULL)
749 {
750 return HAL_ERROR;
751 }
752
753 /* Process locked */
754 __HAL_LOCK(hsram);
755
756 state = hsram->State;
757 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
758 {
759 switch (CallbackId)
760 {
761 case HAL_SRAM_MSP_INIT_CB_ID :
762 hsram->MspInitCallback = pCallback;
763 break;
764 case HAL_SRAM_MSP_DEINIT_CB_ID :
765 hsram->MspDeInitCallback = pCallback;
766 break;
767 default :
768 /* update return status */
769 status = HAL_ERROR;
770 break;
771 }
772 }
773 else
774 {
775 /* update return status */
776 status = HAL_ERROR;
777 }
778
779 /* Release Lock */
780 __HAL_UNLOCK(hsram);
781 return status;
782 }
783
784 /**
785 * @brief Unregister a User SRAM Callback
786 * SRAM Callback is redirected to the weak (surcharged) predefined callback
787 * @param hsram : SRAM handle
788 * @param CallbackId : ID of the callback to be unregistered
789 * This parameter can be one of the following values:
790 * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
791 * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
792 * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
793 * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
794 * @retval status
795 */
HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef * hsram,HAL_SRAM_CallbackIDTypeDef CallbackId)796 HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
797 {
798 HAL_StatusTypeDef status = HAL_OK;
799 HAL_SRAM_StateTypeDef state;
800
801 /* Process locked */
802 __HAL_LOCK(hsram);
803
804 state = hsram->State;
805 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
806 {
807 switch (CallbackId)
808 {
809 case HAL_SRAM_MSP_INIT_CB_ID :
810 hsram->MspInitCallback = HAL_SRAM_MspInit;
811 break;
812 case HAL_SRAM_MSP_DEINIT_CB_ID :
813 hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
814 break;
815 case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
816 hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
817 break;
818 case HAL_SRAM_DMA_XFER_ERR_CB_ID :
819 hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
820 break;
821 default :
822 /* update return status */
823 status = HAL_ERROR;
824 break;
825 }
826 }
827 else if (state == HAL_SRAM_STATE_RESET)
828 {
829 switch (CallbackId)
830 {
831 case HAL_SRAM_MSP_INIT_CB_ID :
832 hsram->MspInitCallback = HAL_SRAM_MspInit;
833 break;
834 case HAL_SRAM_MSP_DEINIT_CB_ID :
835 hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
836 break;
837 default :
838 /* update return status */
839 status = HAL_ERROR;
840 break;
841 }
842 }
843 else
844 {
845 /* update return status */
846 status = HAL_ERROR;
847 }
848
849 /* Release Lock */
850 __HAL_UNLOCK(hsram);
851 return status;
852 }
853
854 /**
855 * @brief Register a User SRAM Callback for DMA transfers
856 * To be used instead of the weak (surcharged) predefined callback
857 * @param hsram : SRAM handle
858 * @param CallbackId : ID of the callback to be registered
859 * This parameter can be one of the following values:
860 * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
861 * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
862 * @param pCallback : pointer to the Callback function
863 * @retval status
864 */
HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef * hsram,HAL_SRAM_CallbackIDTypeDef CallbackId,pSRAM_DmaCallbackTypeDef pCallback)865 HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
866 pSRAM_DmaCallbackTypeDef pCallback)
867 {
868 HAL_StatusTypeDef status = HAL_OK;
869 HAL_SRAM_StateTypeDef state;
870
871 if (pCallback == NULL)
872 {
873 return HAL_ERROR;
874 }
875
876 /* Process locked */
877 __HAL_LOCK(hsram);
878
879 state = hsram->State;
880 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
881 {
882 switch (CallbackId)
883 {
884 case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
885 hsram->DmaXferCpltCallback = pCallback;
886 break;
887 case HAL_SRAM_DMA_XFER_ERR_CB_ID :
888 hsram->DmaXferErrorCallback = pCallback;
889 break;
890 default :
891 /* update return status */
892 status = HAL_ERROR;
893 break;
894 }
895 }
896 else
897 {
898 /* update return status */
899 status = HAL_ERROR;
900 }
901
902 /* Release Lock */
903 __HAL_UNLOCK(hsram);
904 return status;
905 }
906 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
907
908 /**
909 * @}
910 */
911
912 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
913 * @brief Control functions
914 *
915 @verbatim
916 ==============================================================================
917 ##### SRAM Control functions #####
918 ==============================================================================
919 [..]
920 This subsection provides a set of functions allowing to control dynamically
921 the SRAM interface.
922
923 @endverbatim
924 * @{
925 */
926
927 /**
928 * @brief Enables dynamically SRAM write operation.
929 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
930 * the configuration information for SRAM module.
931 * @retval HAL status
932 */
HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef * hsram)933 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
934 {
935 /* Check the SRAM controller state */
936 if (hsram->State == HAL_SRAM_STATE_PROTECTED)
937 {
938 /* Process Locked */
939 __HAL_LOCK(hsram);
940
941 /* Update the SRAM controller state */
942 hsram->State = HAL_SRAM_STATE_BUSY;
943
944 /* Enable write operation */
945 (void)FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
946
947 /* Update the SRAM controller state */
948 hsram->State = HAL_SRAM_STATE_READY;
949
950 /* Process unlocked */
951 __HAL_UNLOCK(hsram);
952 }
953 else
954 {
955 return HAL_ERROR;
956 }
957
958 return HAL_OK;
959 }
960
961 /**
962 * @brief Disables dynamically SRAM write operation.
963 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
964 * the configuration information for SRAM module.
965 * @retval HAL status
966 */
HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef * hsram)967 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
968 {
969 /* Check the SRAM controller state */
970 if (hsram->State == HAL_SRAM_STATE_READY)
971 {
972 /* Process Locked */
973 __HAL_LOCK(hsram);
974
975 /* Update the SRAM controller state */
976 hsram->State = HAL_SRAM_STATE_BUSY;
977
978 /* Disable write operation */
979 (void)FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
980
981 /* Update the SRAM controller state */
982 hsram->State = HAL_SRAM_STATE_PROTECTED;
983
984 /* Process unlocked */
985 __HAL_UNLOCK(hsram);
986 }
987 else
988 {
989 return HAL_ERROR;
990 }
991
992 return HAL_OK;
993 }
994
995 /**
996 * @}
997 */
998
999 /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
1000 * @brief Peripheral State functions
1001 *
1002 @verbatim
1003 ==============================================================================
1004 ##### SRAM State functions #####
1005 ==============================================================================
1006 [..]
1007 This subsection permits to get in run-time the status of the SRAM controller
1008 and the data flow.
1009
1010 @endverbatim
1011 * @{
1012 */
1013
1014 /**
1015 * @brief Returns the SRAM controller state
1016 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
1017 * the configuration information for SRAM module.
1018 * @retval HAL state
1019 */
HAL_SRAM_GetState(SRAM_HandleTypeDef * hsram)1020 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
1021 {
1022 return hsram->State;
1023 }
1024
1025 /**
1026 * @}
1027 */
1028
1029 /**
1030 * @}
1031 */
1032
1033 /**
1034 * @brief DMA SRAM process complete callback.
1035 * @param hdma : DMA handle
1036 * @retval None
1037 */
SRAM_DMACplt(DMA_HandleTypeDef * hdma)1038 static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
1039 {
1040 SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
1041
1042 /* Disable the DMA channel */
1043 __HAL_DMA_DISABLE(hdma);
1044
1045 /* Update the SRAM controller state */
1046 hsram->State = HAL_SRAM_STATE_READY;
1047
1048 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
1049 hsram->DmaXferCpltCallback(hdma);
1050 #else
1051 HAL_SRAM_DMA_XferCpltCallback(hdma);
1052 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
1053 }
1054
1055 /**
1056 * @brief DMA SRAM process complete callback.
1057 * @param hdma : DMA handle
1058 * @retval None
1059 */
SRAM_DMACpltProt(DMA_HandleTypeDef * hdma)1060 static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
1061 {
1062 SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
1063
1064 /* Disable the DMA channel */
1065 __HAL_DMA_DISABLE(hdma);
1066
1067 /* Update the SRAM controller state */
1068 hsram->State = HAL_SRAM_STATE_PROTECTED;
1069
1070 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
1071 hsram->DmaXferCpltCallback(hdma);
1072 #else
1073 HAL_SRAM_DMA_XferCpltCallback(hdma);
1074 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
1075 }
1076
1077 /**
1078 * @brief DMA SRAM error callback.
1079 * @param hdma : DMA handle
1080 * @retval None
1081 */
SRAM_DMAError(DMA_HandleTypeDef * hdma)1082 static void SRAM_DMAError(DMA_HandleTypeDef *hdma)
1083 {
1084 SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
1085
1086 /* Disable the DMA channel */
1087 __HAL_DMA_DISABLE(hdma);
1088
1089 /* Update the SRAM controller state */
1090 hsram->State = HAL_SRAM_STATE_ERROR;
1091
1092 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
1093 hsram->DmaXferErrorCallback(hdma);
1094 #else
1095 HAL_SRAM_DMA_XferErrorCallback(hdma);
1096 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
1097 }
1098
1099 /**
1100 * @}
1101 */
1102
1103 #endif /* HAL_SRAM_MODULE_ENABLED */
1104
1105 /**
1106 * @}
1107 */
1108
1109
