1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_spi.c
4 * @author MCD Application Team
5 * @brief SPI HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2017 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 @verbatim
24 ==============================================================================
25 ##### How to use this driver #####
26 ==============================================================================
27 [..]
28 The SPI HAL driver can be used as follows:
29
30 (#) Declare a SPI_HandleTypeDef handle structure, for example:
31 SPI_HandleTypeDef hspi;
32
33 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
34 (##) Enable the SPIx interface clock
35 (##) SPI pins configuration
36 (+++) Enable the clock for the SPI GPIOs
37 (+++) Configure these SPI pins as alternate function push-pull
38 (##) NVIC configuration if you need to use interrupt process
39 (+++) Configure the SPIx interrupt priority
40 (+++) Enable the NVIC SPI IRQ handle
41 (##) DMA Configuration if you need to use DMA process
42 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
43 (+++) Enable the DMAx clock
44 (+++) Configure the DMA handle parameters
45 (+++) Configure the DMA Tx or Rx Stream/Channel
46 (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle
47 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
48
49 (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
50 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
51
52 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
53 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
54 by calling the customized HAL_SPI_MspInit() API.
55 [..]
56 Circular mode restriction:
57 (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
58 (##) Master 2Lines RxOnly
59 (##) Master 1Line Rx
60 (#) The CRC feature is not managed when the DMA circular mode is enabled
61 (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
62 the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
63 [..]
64 Master Receive mode restriction:
65 (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
66 bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
67 does not initiate a new transfer the following procedure has to be respected:
68 (##) HAL_SPI_DeInit()
69 (##) HAL_SPI_Init()
70 [..]
71 Callback registration:
72
73 (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
74 allows the user to configure dynamically the driver callbacks.
75 Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
76
77 Function HAL_SPI_RegisterCallback() allows to register following callbacks:
78 (++) TxCpltCallback : SPI Tx Completed callback
79 (++) RxCpltCallback : SPI Rx Completed callback
80 (++) TxRxCpltCallback : SPI TxRx Completed callback
81 (++) TxHalfCpltCallback : SPI Tx Half Completed callback
82 (++) RxHalfCpltCallback : SPI Rx Half Completed callback
83 (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
84 (++) ErrorCallback : SPI Error callback
85 (++) AbortCpltCallback : SPI Abort callback
86 (++) MspInitCallback : SPI Msp Init callback
87 (++) MspDeInitCallback : SPI Msp DeInit callback
88 This function takes as parameters the HAL peripheral handle, the Callback ID
89 and a pointer to the user callback function.
90
91
92 (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
93 weak function.
94 HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
95 and the Callback ID.
96 This function allows to reset following callbacks:
97 (++) TxCpltCallback : SPI Tx Completed callback
98 (++) RxCpltCallback : SPI Rx Completed callback
99 (++) TxRxCpltCallback : SPI TxRx Completed callback
100 (++) TxHalfCpltCallback : SPI Tx Half Completed callback
101 (++) RxHalfCpltCallback : SPI Rx Half Completed callback
102 (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
103 (++) ErrorCallback : SPI Error callback
104 (++) AbortCpltCallback : SPI Abort callback
105 (++) MspInitCallback : SPI Msp Init callback
106 (++) MspDeInitCallback : SPI Msp DeInit callback
107
108 [..]
109 By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
110 all callbacks are set to the corresponding weak functions:
111 examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
112 Exception done for MspInit and MspDeInit functions that are
113 reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
114 these callbacks are null (not registered beforehand).
115 If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
116 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
117
118 [..]
119 Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
120 Exception done MspInit/MspDeInit functions that can be registered/unregistered
121 in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
122 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
123 Then, the user first registers the MspInit/MspDeInit user callbacks
124 using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
125 or HAL_SPI_Init() function.
126
127 [..]
128 When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
129 not defined, the callback registering feature is not available
130 and weak (surcharged) callbacks are used.
131
132 [..]
133 Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
134 the following table resume the max SPI frequency reached with data size 8bits/16bits,
135 according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
136
137 @endverbatim
138
139 Additional table :
140
141 DataSize = SPI_DATASIZE_8BIT:
142 +----------------------------------------------------------------------------------------------+
143 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
144 | Process | Transfer mode |---------------------|----------------------|----------------------|
145 | | | Master | Slave | Master | Slave | Master | Slave |
146 |==============================================================================================|
147 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
148 | X |----------------|----------|----------|-----------|----------|-----------|----------|
149 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
150 | R |----------------|----------|----------|-----------|----------|-----------|----------|
151 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
152 |=========|================|==========|==========|===========|==========|===========|==========|
153 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
154 | |----------------|----------|----------|-----------|----------|-----------|----------|
155 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
156 | X |----------------|----------|----------|-----------|----------|-----------|----------|
157 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
158 |=========|================|==========|==========|===========|==========|===========|==========|
159 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
160 | |----------------|----------|----------|-----------|----------|-----------|----------|
161 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
162 | X |----------------|----------|----------|-----------|----------|-----------|----------|
163 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
164 +----------------------------------------------------------------------------------------------+
165
166 DataSize = SPI_DATASIZE_16BIT:
167 +----------------------------------------------------------------------------------------------+
168 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
169 | Process | Transfer mode |---------------------|----------------------|----------------------|
170 | | | Master | Slave | Master | Slave | Master | Slave |
171 |==============================================================================================|
172 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
173 | X |----------------|----------|----------|-----------|----------|-----------|----------|
174 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
175 | R |----------------|----------|----------|-----------|----------|-----------|----------|
176 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
177 |=========|================|==========|==========|===========|==========|===========|==========|
178 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
179 | |----------------|----------|----------|-----------|----------|-----------|----------|
180 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
181 | X |----------------|----------|----------|-----------|----------|-----------|----------|
182 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
183 |=========|================|==========|==========|===========|==========|===========|==========|
184 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
185 | |----------------|----------|----------|-----------|----------|-----------|----------|
186 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
187 | X |----------------|----------|----------|-----------|----------|-----------|----------|
188 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
189 +----------------------------------------------------------------------------------------------+
190 @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
191 SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
192 @note
193 (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
194 (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
195 (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
196
197 */
198
199 /* Includes ------------------------------------------------------------------*/
200 #include "stm32f7xx_hal.h"
201
202 /** @addtogroup STM32F7xx_HAL_Driver
203 * @{
204 */
205
206 /** @defgroup SPI SPI
207 * @brief SPI HAL module driver
208 * @{
209 */
210 #ifdef HAL_SPI_MODULE_ENABLED
211
212 /* Private typedef -----------------------------------------------------------*/
213 /* Private defines -----------------------------------------------------------*/
214 /** @defgroup SPI_Private_Constants SPI Private Constants
215 * @{
216 */
217 #define SPI_DEFAULT_TIMEOUT 100U
218 #define SPI_BSY_FLAG_WORKAROUND_TIMEOUT 1000U /*!< Timeout 1000 µs */
219 /**
220 * @}
221 */
222
223 /* Private macros ------------------------------------------------------------*/
224 /* Private variables ---------------------------------------------------------*/
225 /* Private function prototypes -----------------------------------------------*/
226 /** @defgroup SPI_Private_Functions SPI Private Functions
227 * @{
228 */
229 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
230 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
231 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
232 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
233 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
234 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
235 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
236 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
237 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
238 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
239 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
240 uint32_t Timeout, uint32_t Tickstart);
241 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
242 uint32_t Timeout, uint32_t Tickstart);
243 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
244 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
245 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
246 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
247 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
248 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
249 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
250 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
251 #if (USE_SPI_CRC != 0U)
252 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
253 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
254 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
255 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
256 #endif /* USE_SPI_CRC */
257 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
258 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
259 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
260 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
261 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
262 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
263 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
264 /**
265 * @}
266 */
267
268 /* Exported functions --------------------------------------------------------*/
269 /** @defgroup SPI_Exported_Functions SPI Exported Functions
270 * @{
271 */
272
273 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
274 * @brief Initialization and Configuration functions
275 *
276 @verbatim
277 ===============================================================================
278 ##### Initialization and de-initialization functions #####
279 ===============================================================================
280 [..] This subsection provides a set of functions allowing to initialize and
281 de-initialize the SPIx peripheral:
282
283 (+) User must implement HAL_SPI_MspInit() function in which he configures
284 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
285
286 (+) Call the function HAL_SPI_Init() to configure the selected device with
287 the selected configuration:
288 (++) Mode
289 (++) Direction
290 (++) Data Size
291 (++) Clock Polarity and Phase
292 (++) NSS Management
293 (++) BaudRate Prescaler
294 (++) FirstBit
295 (++) TIMode
296 (++) CRC Calculation
297 (++) CRC Polynomial if CRC enabled
298 (++) CRC Length, used only with Data8 and Data16
299 (++) FIFO reception threshold
300
301 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
302 of the selected SPIx peripheral.
303
304 @endverbatim
305 * @{
306 */
307
308 /**
309 * @brief Initialize the SPI according to the specified parameters
310 * in the SPI_InitTypeDef and initialize the associated handle.
311 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
312 * the configuration information for SPI module.
313 * @retval HAL status
314 */
HAL_SPI_Init(SPI_HandleTypeDef * hspi)315 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
316 {
317 uint32_t frxth;
318
319 /* Check the SPI handle allocation */
320 if (hspi == NULL)
321 {
322 return HAL_ERROR;
323 }
324
325 /* Check the parameters */
326 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
327 assert_param(IS_SPI_MODE(hspi->Init.Mode));
328 assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
329 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
330 assert_param(IS_SPI_NSS(hspi->Init.NSS));
331 assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
332 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
333 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
334 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
335 if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
336 {
337 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
338 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
339
340 if (hspi->Init.Mode == SPI_MODE_MASTER)
341 {
342 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
343 }
344 else
345 {
346 /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
347 hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
348 }
349 }
350 else
351 {
352 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
353
354 /* Force polarity and phase to TI protocaol requirements */
355 hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
356 hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
357 }
358 #if (USE_SPI_CRC != 0U)
359 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
360 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
361 {
362 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
363 assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
364 }
365 #else
366 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
367 #endif /* USE_SPI_CRC */
368
369 if (hspi->State == HAL_SPI_STATE_RESET)
370 {
371 /* Allocate lock resource and initialize it */
372 hspi->Lock = HAL_UNLOCKED;
373
374 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
375 /* Init the SPI Callback settings */
376 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
377 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
378 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
379 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
380 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
381 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
382 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
383 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
384
385 if (hspi->MspInitCallback == NULL)
386 {
387 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
388 }
389
390 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
391 hspi->MspInitCallback(hspi);
392 #else
393 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
394 HAL_SPI_MspInit(hspi);
395 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
396 }
397
398 hspi->State = HAL_SPI_STATE_BUSY;
399
400 /* Disable the selected SPI peripheral */
401 __HAL_SPI_DISABLE(hspi);
402
403 /* Align by default the rs fifo threshold on the data size */
404 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
405 {
406 frxth = SPI_RXFIFO_THRESHOLD_HF;
407 }
408 else
409 {
410 frxth = SPI_RXFIFO_THRESHOLD_QF;
411 }
412
413 /* CRC calculation is valid only for 16Bit and 8 Bit */
414 if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
415 {
416 /* CRC must be disabled */
417 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
418 }
419
420 /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
421 /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
422 Communication speed, First bit and CRC calculation state */
423 WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
424 (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) |
425 (hspi->Init.CLKPolarity & SPI_CR1_CPOL) |
426 (hspi->Init.CLKPhase & SPI_CR1_CPHA) |
427 (hspi->Init.NSS & SPI_CR1_SSM) |
428 (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
429 (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
430 (hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
431 #if (USE_SPI_CRC != 0U)
432 /*---------------------------- SPIx CRCL Configuration -------------------*/
433 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
434 {
435 /* Align the CRC Length on the data size */
436 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
437 {
438 /* CRC Length aligned on the data size : value set by default */
439 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
440 {
441 hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
442 }
443 else
444 {
445 hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
446 }
447 }
448
449 /* Configure : CRC Length */
450 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
451 {
452 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCL);
453 }
454 }
455 #endif /* USE_SPI_CRC */
456
457 /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
458 WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) |
459 (hspi->Init.TIMode & SPI_CR2_FRF) |
460 (hspi->Init.NSSPMode & SPI_CR2_NSSP) |
461 (hspi->Init.DataSize & SPI_CR2_DS_Msk) |
462 (frxth & SPI_CR2_FRXTH)));
463
464 #if (USE_SPI_CRC != 0U)
465 /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
466 /* Configure : CRC Polynomial */
467 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
468 {
469 WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk));
470 }
471 #endif /* USE_SPI_CRC */
472
473 #if defined(SPI_I2SCFGR_I2SMOD)
474 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
475 CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
476 #endif /* SPI_I2SCFGR_I2SMOD */
477
478 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
479 hspi->State = HAL_SPI_STATE_READY;
480
481 return HAL_OK;
482 }
483
484 /**
485 * @brief De-Initialize the SPI peripheral.
486 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
487 * the configuration information for SPI module.
488 * @retval HAL status
489 */
HAL_SPI_DeInit(SPI_HandleTypeDef * hspi)490 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
491 {
492 /* Check the SPI handle allocation */
493 if (hspi == NULL)
494 {
495 return HAL_ERROR;
496 }
497
498 /* Check SPI Instance parameter */
499 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
500
501 hspi->State = HAL_SPI_STATE_BUSY;
502
503 /* Disable the SPI Peripheral Clock */
504 __HAL_SPI_DISABLE(hspi);
505
506 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
507 if (hspi->MspDeInitCallback == NULL)
508 {
509 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
510 }
511
512 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
513 hspi->MspDeInitCallback(hspi);
514 #else
515 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
516 HAL_SPI_MspDeInit(hspi);
517 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
518
519 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
520 hspi->State = HAL_SPI_STATE_RESET;
521
522 /* Release Lock */
523 __HAL_UNLOCK(hspi);
524
525 return HAL_OK;
526 }
527
528 /**
529 * @brief Initialize the SPI MSP.
530 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
531 * the configuration information for SPI module.
532 * @retval None
533 */
HAL_SPI_MspInit(SPI_HandleTypeDef * hspi)534 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
535 {
536 /* Prevent unused argument(s) compilation warning */
537 UNUSED(hspi);
538
539 /* NOTE : This function should not be modified, when the callback is needed,
540 the HAL_SPI_MspInit should be implemented in the user file
541 */
542 }
543
544 /**
545 * @brief De-Initialize the SPI MSP.
546 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
547 * the configuration information for SPI module.
548 * @retval None
549 */
HAL_SPI_MspDeInit(SPI_HandleTypeDef * hspi)550 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
551 {
552 /* Prevent unused argument(s) compilation warning */
553 UNUSED(hspi);
554
555 /* NOTE : This function should not be modified, when the callback is needed,
556 the HAL_SPI_MspDeInit should be implemented in the user file
557 */
558 }
559
560 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
561 /**
562 * @brief Register a User SPI Callback
563 * To be used instead of the weak predefined callback
564 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
565 * the configuration information for the specified SPI.
566 * @param CallbackID ID of the callback to be registered
567 * @param pCallback pointer to the Callback function
568 * @retval HAL status
569 */
HAL_SPI_RegisterCallback(SPI_HandleTypeDef * hspi,HAL_SPI_CallbackIDTypeDef CallbackID,pSPI_CallbackTypeDef pCallback)570 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
571 pSPI_CallbackTypeDef pCallback)
572 {
573 HAL_StatusTypeDef status = HAL_OK;
574
575 if (pCallback == NULL)
576 {
577 /* Update the error code */
578 hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
579
580 return HAL_ERROR;
581 }
582 /* Process locked */
583 __HAL_LOCK(hspi);
584
585 if (HAL_SPI_STATE_READY == hspi->State)
586 {
587 switch (CallbackID)
588 {
589 case HAL_SPI_TX_COMPLETE_CB_ID :
590 hspi->TxCpltCallback = pCallback;
591 break;
592
593 case HAL_SPI_RX_COMPLETE_CB_ID :
594 hspi->RxCpltCallback = pCallback;
595 break;
596
597 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
598 hspi->TxRxCpltCallback = pCallback;
599 break;
600
601 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
602 hspi->TxHalfCpltCallback = pCallback;
603 break;
604
605 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
606 hspi->RxHalfCpltCallback = pCallback;
607 break;
608
609 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
610 hspi->TxRxHalfCpltCallback = pCallback;
611 break;
612
613 case HAL_SPI_ERROR_CB_ID :
614 hspi->ErrorCallback = pCallback;
615 break;
616
617 case HAL_SPI_ABORT_CB_ID :
618 hspi->AbortCpltCallback = pCallback;
619 break;
620
621 case HAL_SPI_MSPINIT_CB_ID :
622 hspi->MspInitCallback = pCallback;
623 break;
624
625 case HAL_SPI_MSPDEINIT_CB_ID :
626 hspi->MspDeInitCallback = pCallback;
627 break;
628
629 default :
630 /* Update the error code */
631 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
632
633 /* Return error status */
634 status = HAL_ERROR;
635 break;
636 }
637 }
638 else if (HAL_SPI_STATE_RESET == hspi->State)
639 {
640 switch (CallbackID)
641 {
642 case HAL_SPI_MSPINIT_CB_ID :
643 hspi->MspInitCallback = pCallback;
644 break;
645
646 case HAL_SPI_MSPDEINIT_CB_ID :
647 hspi->MspDeInitCallback = pCallback;
648 break;
649
650 default :
651 /* Update the error code */
652 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
653
654 /* Return error status */
655 status = HAL_ERROR;
656 break;
657 }
658 }
659 else
660 {
661 /* Update the error code */
662 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
663
664 /* Return error status */
665 status = HAL_ERROR;
666 }
667
668 /* Release Lock */
669 __HAL_UNLOCK(hspi);
670 return status;
671 }
672
673 /**
674 * @brief Unregister an SPI Callback
675 * SPI callback is redirected to the weak predefined callback
676 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
677 * the configuration information for the specified SPI.
678 * @param CallbackID ID of the callback to be unregistered
679 * @retval HAL status
680 */
HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef * hspi,HAL_SPI_CallbackIDTypeDef CallbackID)681 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
682 {
683 HAL_StatusTypeDef status = HAL_OK;
684
685 /* Process locked */
686 __HAL_LOCK(hspi);
687
688 if (HAL_SPI_STATE_READY == hspi->State)
689 {
690 switch (CallbackID)
691 {
692 case HAL_SPI_TX_COMPLETE_CB_ID :
693 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
694 break;
695
696 case HAL_SPI_RX_COMPLETE_CB_ID :
697 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
698 break;
699
700 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
701 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
702 break;
703
704 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
705 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
706 break;
707
708 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
709 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
710 break;
711
712 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
713 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
714 break;
715
716 case HAL_SPI_ERROR_CB_ID :
717 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
718 break;
719
720 case HAL_SPI_ABORT_CB_ID :
721 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
722 break;
723
724 case HAL_SPI_MSPINIT_CB_ID :
725 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
726 break;
727
728 case HAL_SPI_MSPDEINIT_CB_ID :
729 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
730 break;
731
732 default :
733 /* Update the error code */
734 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
735
736 /* Return error status */
737 status = HAL_ERROR;
738 break;
739 }
740 }
741 else if (HAL_SPI_STATE_RESET == hspi->State)
742 {
743 switch (CallbackID)
744 {
745 case HAL_SPI_MSPINIT_CB_ID :
746 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
747 break;
748
749 case HAL_SPI_MSPDEINIT_CB_ID :
750 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
751 break;
752
753 default :
754 /* Update the error code */
755 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
756
757 /* Return error status */
758 status = HAL_ERROR;
759 break;
760 }
761 }
762 else
763 {
764 /* Update the error code */
765 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
766
767 /* Return error status */
768 status = HAL_ERROR;
769 }
770
771 /* Release Lock */
772 __HAL_UNLOCK(hspi);
773 return status;
774 }
775 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
776 /**
777 * @}
778 */
779
780 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
781 * @brief Data transfers functions
782 *
783 @verbatim
784 ==============================================================================
785 ##### IO operation functions #####
786 ===============================================================================
787 [..]
788 This subsection provides a set of functions allowing to manage the SPI
789 data transfers.
790
791 [..] The SPI supports master and slave mode :
792
793 (#) There are two modes of transfer:
794 (++) Blocking mode: The communication is performed in polling mode.
795 The HAL status of all data processing is returned by the same function
796 after finishing transfer.
797 (++) No-Blocking mode: The communication is performed using Interrupts
798 or DMA, These APIs return the HAL status.
799 The end of the data processing will be indicated through the
800 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
801 using DMA mode.
802 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
803 will be executed respectively at the end of the transmit or Receive process
804 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
805
806 (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
807 exist for 1Line (simplex) and 2Lines (full duplex) modes.
808
809 @endverbatim
810 * @{
811 */
812
813 /**
814 * @brief Transmit an amount of data in blocking mode.
815 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
816 * the configuration information for SPI module.
817 * @param pData pointer to data buffer
818 * @param Size amount of data to be sent
819 * @param Timeout Timeout duration
820 * @retval HAL status
821 */
HAL_SPI_Transmit(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size,uint32_t Timeout)822 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
823 {
824 uint32_t tickstart;
825 HAL_StatusTypeDef errorcode = HAL_OK;
826 uint16_t initial_TxXferCount;
827
828 /* Check Direction parameter */
829 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
830
831 /* Process Locked */
832 __HAL_LOCK(hspi);
833
834 /* Init tickstart for timeout management*/
835 tickstart = HAL_GetTick();
836 initial_TxXferCount = Size;
837
838 if (hspi->State != HAL_SPI_STATE_READY)
839 {
840 errorcode = HAL_BUSY;
841 goto error;
842 }
843
844 if ((pData == NULL) || (Size == 0U))
845 {
846 errorcode = HAL_ERROR;
847 goto error;
848 }
849
850 /* Set the transaction information */
851 hspi->State = HAL_SPI_STATE_BUSY_TX;
852 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
853 hspi->pTxBuffPtr = (uint8_t *)pData;
854 hspi->TxXferSize = Size;
855 hspi->TxXferCount = Size;
856
857 /*Init field not used in handle to zero */
858 hspi->pRxBuffPtr = (uint8_t *)NULL;
859 hspi->RxXferSize = 0U;
860 hspi->RxXferCount = 0U;
861 hspi->TxISR = NULL;
862 hspi->RxISR = NULL;
863
864 /* Configure communication direction : 1Line */
865 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
866 {
867 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
868 __HAL_SPI_DISABLE(hspi);
869 SPI_1LINE_TX(hspi);
870 }
871
872 #if (USE_SPI_CRC != 0U)
873 /* Reset CRC Calculation */
874 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
875 {
876 SPI_RESET_CRC(hspi);
877 }
878 #endif /* USE_SPI_CRC */
879
880 /* Check if the SPI is already enabled */
881 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
882 {
883 /* Enable SPI peripheral */
884 __HAL_SPI_ENABLE(hspi);
885 }
886
887 /* Transmit data in 16 Bit mode */
888 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
889 {
890 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
891 {
892 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
893 hspi->pTxBuffPtr += sizeof(uint16_t);
894 hspi->TxXferCount--;
895 }
896 /* Transmit data in 16 Bit mode */
897 while (hspi->TxXferCount > 0U)
898 {
899 /* Wait until TXE flag is set to send data */
900 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
901 {
902 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
903 hspi->pTxBuffPtr += sizeof(uint16_t);
904 hspi->TxXferCount--;
905 }
906 else
907 {
908 /* Timeout management */
909 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
910 {
911 errorcode = HAL_TIMEOUT;
912 goto error;
913 }
914 }
915 }
916 }
917 /* Transmit data in 8 Bit mode */
918 else
919 {
920 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
921 {
922 if (hspi->TxXferCount > 1U)
923 {
924 /* write on the data register in packing mode */
925 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
926 hspi->pTxBuffPtr += sizeof(uint16_t);
927 hspi->TxXferCount -= 2U;
928 }
929 else
930 {
931 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
932 hspi->pTxBuffPtr ++;
933 hspi->TxXferCount--;
934 }
935 }
936 while (hspi->TxXferCount > 0U)
937 {
938 /* Wait until TXE flag is set to send data */
939 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
940 {
941 if (hspi->TxXferCount > 1U)
942 {
943 /* write on the data register in packing mode */
944 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
945 hspi->pTxBuffPtr += sizeof(uint16_t);
946 hspi->TxXferCount -= 2U;
947 }
948 else
949 {
950 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
951 hspi->pTxBuffPtr++;
952 hspi->TxXferCount--;
953 }
954 }
955 else
956 {
957 /* Timeout management */
958 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
959 {
960 errorcode = HAL_TIMEOUT;
961 goto error;
962 }
963 }
964 }
965 }
966 #if (USE_SPI_CRC != 0U)
967 /* Enable CRC Transmission */
968 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
969 {
970 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
971 }
972 #endif /* USE_SPI_CRC */
973
974 /* Check the end of the transaction */
975 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
976 {
977 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
978 }
979
980 /* Clear overrun flag in 2 Lines communication mode because received is not read */
981 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
982 {
983 __HAL_SPI_CLEAR_OVRFLAG(hspi);
984 }
985
986 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
987 {
988 errorcode = HAL_ERROR;
989 }
990
991 error:
992 hspi->State = HAL_SPI_STATE_READY;
993 /* Process Unlocked */
994 __HAL_UNLOCK(hspi);
995 return errorcode;
996 }
997
998 /**
999 * @brief Receive an amount of data in blocking mode.
1000 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1001 * the configuration information for SPI module.
1002 * @param pData pointer to data buffer
1003 * @param Size amount of data to be received
1004 * @param Timeout Timeout duration
1005 * @retval HAL status
1006 */
HAL_SPI_Receive(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size,uint32_t Timeout)1007 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1008 {
1009 #if (USE_SPI_CRC != 0U)
1010 __IO uint32_t tmpreg = 0U;
1011 __IO uint8_t *ptmpreg8;
1012 __IO uint8_t tmpreg8 = 0;
1013 #endif /* USE_SPI_CRC */
1014 uint32_t tickstart;
1015 HAL_StatusTypeDef errorcode = HAL_OK;
1016
1017 if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
1018 {
1019 hspi->State = HAL_SPI_STATE_BUSY_RX;
1020 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1021 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
1022 }
1023
1024 /* Process Locked */
1025 __HAL_LOCK(hspi);
1026
1027 /* Init tickstart for timeout management*/
1028 tickstart = HAL_GetTick();
1029
1030 if (hspi->State != HAL_SPI_STATE_READY)
1031 {
1032 errorcode = HAL_BUSY;
1033 goto error;
1034 }
1035
1036 if ((pData == NULL) || (Size == 0U))
1037 {
1038 errorcode = HAL_ERROR;
1039 goto error;
1040 }
1041
1042 /* Set the transaction information */
1043 hspi->State = HAL_SPI_STATE_BUSY_RX;
1044 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1045 hspi->pRxBuffPtr = (uint8_t *)pData;
1046 hspi->RxXferSize = Size;
1047 hspi->RxXferCount = Size;
1048
1049 /*Init field not used in handle to zero */
1050 hspi->pTxBuffPtr = (uint8_t *)NULL;
1051 hspi->TxXferSize = 0U;
1052 hspi->TxXferCount = 0U;
1053 hspi->RxISR = NULL;
1054 hspi->TxISR = NULL;
1055
1056 #if (USE_SPI_CRC != 0U)
1057 /* Reset CRC Calculation */
1058 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1059 {
1060 SPI_RESET_CRC(hspi);
1061 /* this is done to handle the CRCNEXT before the latest data */
1062 hspi->RxXferCount--;
1063 }
1064 #endif /* USE_SPI_CRC */
1065
1066 /* Set the Rx Fifo threshold */
1067 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1068 {
1069 /* Set RX Fifo threshold according the reception data length: 16bit */
1070 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1071 }
1072 else
1073 {
1074 /* Set RX Fifo threshold according the reception data length: 8bit */
1075 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1076 }
1077
1078 /* Configure communication direction: 1Line */
1079 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1080 {
1081 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1082 __HAL_SPI_DISABLE(hspi);
1083 SPI_1LINE_RX(hspi);
1084 }
1085
1086 /* Check if the SPI is already enabled */
1087 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1088 {
1089 /* Enable SPI peripheral */
1090 __HAL_SPI_ENABLE(hspi);
1091 }
1092
1093 /* Receive data in 8 Bit mode */
1094 if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
1095 {
1096 /* Transfer loop */
1097 while (hspi->RxXferCount > 0U)
1098 {
1099 /* Check the RXNE flag */
1100 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
1101 {
1102 /* read the received data */
1103 (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1104 hspi->pRxBuffPtr += sizeof(uint8_t);
1105 hspi->RxXferCount--;
1106 }
1107 else
1108 {
1109 /* Timeout management */
1110 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1111 {
1112 errorcode = HAL_TIMEOUT;
1113 goto error;
1114 }
1115 }
1116 }
1117 }
1118 else
1119 {
1120 /* Transfer loop */
1121 while (hspi->RxXferCount > 0U)
1122 {
1123 /* Check the RXNE flag */
1124 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
1125 {
1126 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1127 hspi->pRxBuffPtr += sizeof(uint16_t);
1128 hspi->RxXferCount--;
1129 }
1130 else
1131 {
1132 /* Timeout management */
1133 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1134 {
1135 errorcode = HAL_TIMEOUT;
1136 goto error;
1137 }
1138 }
1139 }
1140 }
1141
1142 #if (USE_SPI_CRC != 0U)
1143 /* Handle the CRC Transmission */
1144 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1145 {
1146 /* freeze the CRC before the latest data */
1147 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1148
1149 /* Read the latest data */
1150 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1151 {
1152 /* the latest data has not been received */
1153 errorcode = HAL_TIMEOUT;
1154 goto error;
1155 }
1156
1157 /* Receive last data in 16 Bit mode */
1158 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1159 {
1160 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1161 }
1162 /* Receive last data in 8 Bit mode */
1163 else
1164 {
1165 (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1166 }
1167
1168 /* Wait the CRC data */
1169 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1170 {
1171 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1172 errorcode = HAL_TIMEOUT;
1173 goto error;
1174 }
1175
1176 /* Read CRC to Flush DR and RXNE flag */
1177 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1178 {
1179 /* Read 16bit CRC */
1180 tmpreg = READ_REG(hspi->Instance->DR);
1181 /* To avoid GCC warning */
1182 UNUSED(tmpreg);
1183 }
1184 else
1185 {
1186 /* Initialize the 8bit temporary pointer */
1187 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
1188 /* Read 8bit CRC */
1189 tmpreg8 = *ptmpreg8;
1190 /* To avoid GCC warning */
1191 UNUSED(tmpreg8);
1192
1193 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1194 {
1195 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1196 {
1197 /* Error on the CRC reception */
1198 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1199 errorcode = HAL_TIMEOUT;
1200 goto error;
1201 }
1202 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
1203 tmpreg8 = *ptmpreg8;
1204 /* To avoid GCC warning */
1205 UNUSED(tmpreg8);
1206 }
1207 }
1208 }
1209 #endif /* USE_SPI_CRC */
1210
1211 /* Check the end of the transaction */
1212 if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1213 {
1214 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1215 }
1216
1217 #if (USE_SPI_CRC != 0U)
1218 /* Check if CRC error occurred */
1219 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1220 {
1221 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1222 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1223 }
1224 #endif /* USE_SPI_CRC */
1225
1226 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1227 {
1228 errorcode = HAL_ERROR;
1229 }
1230
1231 error :
1232 hspi->State = HAL_SPI_STATE_READY;
1233 __HAL_UNLOCK(hspi);
1234 return errorcode;
1235 }
1236
1237 /**
1238 * @brief Transmit and Receive an amount of data in blocking mode.
1239 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1240 * the configuration information for SPI module.
1241 * @param pTxData pointer to transmission data buffer
1242 * @param pRxData pointer to reception data buffer
1243 * @param Size amount of data to be sent and received
1244 * @param Timeout Timeout duration
1245 * @retval HAL status
1246 */
HAL_SPI_TransmitReceive(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size,uint32_t Timeout)1247 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
1248 uint32_t Timeout)
1249 {
1250 uint16_t initial_TxXferCount;
1251 uint16_t initial_RxXferCount;
1252 uint32_t tmp_mode;
1253 HAL_SPI_StateTypeDef tmp_state;
1254 uint32_t tickstart;
1255 #if (USE_SPI_CRC != 0U)
1256 __IO uint32_t tmpreg = 0U;
1257 uint32_t spi_cr1;
1258 uint32_t spi_cr2;
1259 __IO uint8_t *ptmpreg8;
1260 __IO uint8_t tmpreg8 = 0;
1261 #endif /* USE_SPI_CRC */
1262
1263 /* Variable used to alternate Rx and Tx during transfer */
1264 uint32_t txallowed = 1U;
1265 HAL_StatusTypeDef errorcode = HAL_OK;
1266
1267 /* Check Direction parameter */
1268 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1269
1270 /* Process Locked */
1271 __HAL_LOCK(hspi);
1272
1273 /* Init tickstart for timeout management*/
1274 tickstart = HAL_GetTick();
1275
1276 /* Init temporary variables */
1277 tmp_state = hspi->State;
1278 tmp_mode = hspi->Init.Mode;
1279 initial_TxXferCount = Size;
1280 initial_RxXferCount = Size;
1281 #if (USE_SPI_CRC != 0U)
1282 spi_cr1 = READ_REG(hspi->Instance->CR1);
1283 spi_cr2 = READ_REG(hspi->Instance->CR2);
1284 #endif /* USE_SPI_CRC */
1285
1286 if (!((tmp_state == HAL_SPI_STATE_READY) || \
1287 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1288 {
1289 errorcode = HAL_BUSY;
1290 goto error;
1291 }
1292
1293 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1294 {
1295 errorcode = HAL_ERROR;
1296 goto error;
1297 }
1298
1299 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1300 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1301 {
1302 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1303 }
1304
1305 /* Set the transaction information */
1306 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1307 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1308 hspi->RxXferCount = Size;
1309 hspi->RxXferSize = Size;
1310 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1311 hspi->TxXferCount = Size;
1312 hspi->TxXferSize = Size;
1313
1314 /*Init field not used in handle to zero */
1315 hspi->RxISR = NULL;
1316 hspi->TxISR = NULL;
1317
1318 #if (USE_SPI_CRC != 0U)
1319 /* Reset CRC Calculation */
1320 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1321 {
1322 SPI_RESET_CRC(hspi);
1323 }
1324 #endif /* USE_SPI_CRC */
1325
1326 /* Set the Rx Fifo threshold */
1327 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U))
1328 {
1329 /* Set fiforxthreshold according the reception data length: 16bit */
1330 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1331 }
1332 else
1333 {
1334 /* Set fiforxthreshold according the reception data length: 8bit */
1335 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1336 }
1337
1338 /* Check if the SPI is already enabled */
1339 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1340 {
1341 /* Enable SPI peripheral */
1342 __HAL_SPI_ENABLE(hspi);
1343 }
1344
1345 /* Transmit and Receive data in 16 Bit mode */
1346 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1347 {
1348 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1349 {
1350 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1351 hspi->pTxBuffPtr += sizeof(uint16_t);
1352 hspi->TxXferCount--;
1353 }
1354 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1355 {
1356 /* Check TXE flag */
1357 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1358 {
1359 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1360 hspi->pTxBuffPtr += sizeof(uint16_t);
1361 hspi->TxXferCount--;
1362 /* Next Data is a reception (Rx). Tx not allowed */
1363 txallowed = 0U;
1364
1365 #if (USE_SPI_CRC != 0U)
1366 /* Enable CRC Transmission */
1367 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1368 {
1369 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
1370 if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
1371 {
1372 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
1373 }
1374 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1375 }
1376 #endif /* USE_SPI_CRC */
1377 }
1378
1379 /* Check RXNE flag */
1380 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1381 {
1382 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1383 hspi->pRxBuffPtr += sizeof(uint16_t);
1384 hspi->RxXferCount--;
1385 /* Next Data is a Transmission (Tx). Tx is allowed */
1386 txallowed = 1U;
1387 }
1388 if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
1389 {
1390 errorcode = HAL_TIMEOUT;
1391 goto error;
1392 }
1393 }
1394 }
1395 /* Transmit and Receive data in 8 Bit mode */
1396 else
1397 {
1398 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1399 {
1400 if (hspi->TxXferCount > 1U)
1401 {
1402 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1403 hspi->pTxBuffPtr += sizeof(uint16_t);
1404 hspi->TxXferCount -= 2U;
1405 }
1406 else
1407 {
1408 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
1409 hspi->pTxBuffPtr++;
1410 hspi->TxXferCount--;
1411 }
1412 }
1413 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1414 {
1415 /* Check TXE flag */
1416 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1417 {
1418 if (hspi->TxXferCount > 1U)
1419 {
1420 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1421 hspi->pTxBuffPtr += sizeof(uint16_t);
1422 hspi->TxXferCount -= 2U;
1423 }
1424 else
1425 {
1426 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
1427 hspi->pTxBuffPtr++;
1428 hspi->TxXferCount--;
1429 }
1430 /* Next Data is a reception (Rx). Tx not allowed */
1431 txallowed = 0U;
1432
1433 #if (USE_SPI_CRC != 0U)
1434 /* Enable CRC Transmission */
1435 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1436 {
1437 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
1438 if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
1439 {
1440 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
1441 }
1442 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1443 }
1444 #endif /* USE_SPI_CRC */
1445 }
1446
1447 /* Wait until RXNE flag is reset */
1448 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1449 {
1450 if (hspi->RxXferCount > 1U)
1451 {
1452 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1453 hspi->pRxBuffPtr += sizeof(uint16_t);
1454 hspi->RxXferCount -= 2U;
1455 if (hspi->RxXferCount <= 1U)
1456 {
1457 /* Set RX Fifo threshold before to switch on 8 bit data size */
1458 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1459 }
1460 }
1461 else
1462 {
1463 (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1464 hspi->pRxBuffPtr++;
1465 hspi->RxXferCount--;
1466 }
1467 /* Next Data is a Transmission (Tx). Tx is allowed */
1468 txallowed = 1U;
1469 }
1470 if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
1471 {
1472 errorcode = HAL_TIMEOUT;
1473 goto error;
1474 }
1475 }
1476 }
1477
1478 #if (USE_SPI_CRC != 0U)
1479 /* Read CRC from DR to close CRC calculation process */
1480 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1481 {
1482 /* Wait until TXE flag */
1483 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1484 {
1485 /* Error on the CRC reception */
1486 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1487 errorcode = HAL_TIMEOUT;
1488 goto error;
1489 }
1490 /* Read CRC */
1491 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1492 {
1493 /* Read 16bit CRC */
1494 tmpreg = READ_REG(hspi->Instance->DR);
1495 /* To avoid GCC warning */
1496 UNUSED(tmpreg);
1497 }
1498 else
1499 {
1500 /* Initialize the 8bit temporary pointer */
1501 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
1502 /* Read 8bit CRC */
1503 tmpreg8 = *ptmpreg8;
1504 /* To avoid GCC warning */
1505 UNUSED(tmpreg8);
1506
1507 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
1508 {
1509 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1510 {
1511 /* Error on the CRC reception */
1512 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1513 errorcode = HAL_TIMEOUT;
1514 goto error;
1515 }
1516 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
1517 tmpreg8 = *ptmpreg8;
1518 /* To avoid GCC warning */
1519 UNUSED(tmpreg8);
1520 }
1521 }
1522 }
1523
1524 /* Check if CRC error occurred */
1525 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1526 {
1527 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1528 /* Clear CRC Flag */
1529 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1530
1531 errorcode = HAL_ERROR;
1532 }
1533 #endif /* USE_SPI_CRC */
1534
1535 /* Check the end of the transaction */
1536 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1537 {
1538 errorcode = HAL_ERROR;
1539 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1540 }
1541
1542 error :
1543 hspi->State = HAL_SPI_STATE_READY;
1544 __HAL_UNLOCK(hspi);
1545 return errorcode;
1546 }
1547
1548 /**
1549 * @brief Transmit an amount of data in non-blocking mode with Interrupt.
1550 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1551 * the configuration information for SPI module.
1552 * @param pData pointer to data buffer
1553 * @param Size amount of data to be sent
1554 * @retval HAL status
1555 */
HAL_SPI_Transmit_IT(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1556 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1557 {
1558 HAL_StatusTypeDef errorcode = HAL_OK;
1559
1560 /* Check Direction parameter */
1561 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1562
1563 /* Process Locked */
1564 __HAL_LOCK(hspi);
1565
1566 if ((pData == NULL) || (Size == 0U))
1567 {
1568 errorcode = HAL_ERROR;
1569 goto error;
1570 }
1571
1572 if (hspi->State != HAL_SPI_STATE_READY)
1573 {
1574 errorcode = HAL_BUSY;
1575 goto error;
1576 }
1577
1578 /* Set the transaction information */
1579 hspi->State = HAL_SPI_STATE_BUSY_TX;
1580 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1581 hspi->pTxBuffPtr = (uint8_t *)pData;
1582 hspi->TxXferSize = Size;
1583 hspi->TxXferCount = Size;
1584
1585 /* Init field not used in handle to zero */
1586 hspi->pRxBuffPtr = (uint8_t *)NULL;
1587 hspi->RxXferSize = 0U;
1588 hspi->RxXferCount = 0U;
1589 hspi->RxISR = NULL;
1590
1591 /* Set the function for IT treatment */
1592 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1593 {
1594 hspi->TxISR = SPI_TxISR_16BIT;
1595 }
1596 else
1597 {
1598 hspi->TxISR = SPI_TxISR_8BIT;
1599 }
1600
1601 /* Configure communication direction : 1Line */
1602 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1603 {
1604 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1605 __HAL_SPI_DISABLE(hspi);
1606 SPI_1LINE_TX(hspi);
1607 }
1608
1609 #if (USE_SPI_CRC != 0U)
1610 /* Reset CRC Calculation */
1611 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1612 {
1613 SPI_RESET_CRC(hspi);
1614 }
1615 #endif /* USE_SPI_CRC */
1616
1617 /* Enable TXE and ERR interrupt */
1618 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
1619
1620
1621 /* Check if the SPI is already enabled */
1622 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1623 {
1624 /* Enable SPI peripheral */
1625 __HAL_SPI_ENABLE(hspi);
1626 }
1627
1628 error :
1629 __HAL_UNLOCK(hspi);
1630 return errorcode;
1631 }
1632
1633 /**
1634 * @brief Receive an amount of data in non-blocking mode with Interrupt.
1635 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1636 * the configuration information for SPI module.
1637 * @param pData pointer to data buffer
1638 * @param Size amount of data to be sent
1639 * @retval HAL status
1640 */
HAL_SPI_Receive_IT(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1641 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1642 {
1643 HAL_StatusTypeDef errorcode = HAL_OK;
1644
1645 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1646 {
1647 hspi->State = HAL_SPI_STATE_BUSY_RX;
1648 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1649 return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
1650 }
1651
1652 /* Process Locked */
1653 __HAL_LOCK(hspi);
1654
1655 if (hspi->State != HAL_SPI_STATE_READY)
1656 {
1657 errorcode = HAL_BUSY;
1658 goto error;
1659 }
1660
1661 if ((pData == NULL) || (Size == 0U))
1662 {
1663 errorcode = HAL_ERROR;
1664 goto error;
1665 }
1666
1667 /* Set the transaction information */
1668 hspi->State = HAL_SPI_STATE_BUSY_RX;
1669 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1670 hspi->pRxBuffPtr = (uint8_t *)pData;
1671 hspi->RxXferSize = Size;
1672 hspi->RxXferCount = Size;
1673
1674 /* Init field not used in handle to zero */
1675 hspi->pTxBuffPtr = (uint8_t *)NULL;
1676 hspi->TxXferSize = 0U;
1677 hspi->TxXferCount = 0U;
1678 hspi->TxISR = NULL;
1679
1680 /* Check the data size to adapt Rx threshold and the set the function for IT treatment */
1681 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1682 {
1683 /* Set RX Fifo threshold according the reception data length: 16 bit */
1684 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1685 hspi->RxISR = SPI_RxISR_16BIT;
1686 }
1687 else
1688 {
1689 /* Set RX Fifo threshold according the reception data length: 8 bit */
1690 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1691 hspi->RxISR = SPI_RxISR_8BIT;
1692 }
1693
1694 /* Configure communication direction : 1Line */
1695 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1696 {
1697 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1698 __HAL_SPI_DISABLE(hspi);
1699 SPI_1LINE_RX(hspi);
1700 }
1701
1702 #if (USE_SPI_CRC != 0U)
1703 /* Reset CRC Calculation */
1704 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1705 {
1706 hspi->CRCSize = 1U;
1707 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1708 {
1709 hspi->CRCSize = 2U;
1710 }
1711 SPI_RESET_CRC(hspi);
1712 }
1713 else
1714 {
1715 hspi->CRCSize = 0U;
1716 }
1717 #endif /* USE_SPI_CRC */
1718
1719 /* Enable TXE and ERR interrupt */
1720 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
1721
1722 /* Note : The SPI must be enabled after unlocking current process
1723 to avoid the risk of SPI interrupt handle execution before current
1724 process unlock */
1725
1726 /* Check if the SPI is already enabled */
1727 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1728 {
1729 /* Enable SPI peripheral */
1730 __HAL_SPI_ENABLE(hspi);
1731 }
1732
1733 error :
1734 /* Process Unlocked */
1735 __HAL_UNLOCK(hspi);
1736 return errorcode;
1737 }
1738
1739 /**
1740 * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
1741 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1742 * the configuration information for SPI module.
1743 * @param pTxData pointer to transmission data buffer
1744 * @param pRxData pointer to reception data buffer
1745 * @param Size amount of data to be sent and received
1746 * @retval HAL status
1747 */
HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size)1748 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
1749 {
1750 uint32_t tmp_mode;
1751 HAL_SPI_StateTypeDef tmp_state;
1752 HAL_StatusTypeDef errorcode = HAL_OK;
1753
1754 /* Check Direction parameter */
1755 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1756
1757 /* Process locked */
1758 __HAL_LOCK(hspi);
1759
1760 /* Init temporary variables */
1761 tmp_state = hspi->State;
1762 tmp_mode = hspi->Init.Mode;
1763
1764 if (!((tmp_state == HAL_SPI_STATE_READY) || \
1765 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1766 {
1767 errorcode = HAL_BUSY;
1768 goto error;
1769 }
1770
1771 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1772 {
1773 errorcode = HAL_ERROR;
1774 goto error;
1775 }
1776
1777 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1778 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1779 {
1780 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1781 }
1782
1783 /* Set the transaction information */
1784 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1785 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1786 hspi->TxXferSize = Size;
1787 hspi->TxXferCount = Size;
1788 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1789 hspi->RxXferSize = Size;
1790 hspi->RxXferCount = Size;
1791
1792 /* Set the function for IT treatment */
1793 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1794 {
1795 hspi->RxISR = SPI_2linesRxISR_16BIT;
1796 hspi->TxISR = SPI_2linesTxISR_16BIT;
1797 }
1798 else
1799 {
1800 hspi->RxISR = SPI_2linesRxISR_8BIT;
1801 hspi->TxISR = SPI_2linesTxISR_8BIT;
1802 }
1803
1804 #if (USE_SPI_CRC != 0U)
1805 /* Reset CRC Calculation */
1806 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1807 {
1808 hspi->CRCSize = 1U;
1809 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1810 {
1811 hspi->CRCSize = 2U;
1812 }
1813 SPI_RESET_CRC(hspi);
1814 }
1815 else
1816 {
1817 hspi->CRCSize = 0U;
1818 }
1819 #endif /* USE_SPI_CRC */
1820
1821 /* Check if packing mode is enabled and if there is more than 2 data to receive */
1822 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U))
1823 {
1824 /* Set RX Fifo threshold according the reception data length: 16 bit */
1825 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1826 }
1827 else
1828 {
1829 /* Set RX Fifo threshold according the reception data length: 8 bit */
1830 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1831 }
1832
1833 /* Enable TXE, RXNE and ERR interrupt */
1834 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
1835
1836 /* Check if the SPI is already enabled */
1837 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1838 {
1839 /* Enable SPI peripheral */
1840 __HAL_SPI_ENABLE(hspi);
1841 }
1842
1843 error :
1844 /* Process Unlocked */
1845 __HAL_UNLOCK(hspi);
1846 return errorcode;
1847 }
1848
1849 /**
1850 * @brief Transmit an amount of data in non-blocking mode with DMA.
1851 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1852 * the configuration information for SPI module.
1853 * @param pData pointer to data buffer
1854 * @param Size amount of data to be sent
1855 * @retval HAL status
1856 */
HAL_SPI_Transmit_DMA(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1857 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1858 {
1859 HAL_StatusTypeDef errorcode = HAL_OK;
1860
1861 /* Check tx dma handle */
1862 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1863
1864 /* Check Direction parameter */
1865 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1866
1867 /* Process Locked */
1868 __HAL_LOCK(hspi);
1869
1870 if (hspi->State != HAL_SPI_STATE_READY)
1871 {
1872 errorcode = HAL_BUSY;
1873 goto error;
1874 }
1875
1876 if ((pData == NULL) || (Size == 0U))
1877 {
1878 errorcode = HAL_ERROR;
1879 goto error;
1880 }
1881
1882 /* Set the transaction information */
1883 hspi->State = HAL_SPI_STATE_BUSY_TX;
1884 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1885 hspi->pTxBuffPtr = (uint8_t *)pData;
1886 hspi->TxXferSize = Size;
1887 hspi->TxXferCount = Size;
1888
1889 /* Init field not used in handle to zero */
1890 hspi->pRxBuffPtr = (uint8_t *)NULL;
1891 hspi->TxISR = NULL;
1892 hspi->RxISR = NULL;
1893 hspi->RxXferSize = 0U;
1894 hspi->RxXferCount = 0U;
1895
1896 /* Configure communication direction : 1Line */
1897 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1898 {
1899 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1900 __HAL_SPI_DISABLE(hspi);
1901 SPI_1LINE_TX(hspi);
1902 }
1903
1904 #if (USE_SPI_CRC != 0U)
1905 /* Reset CRC Calculation */
1906 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1907 {
1908 SPI_RESET_CRC(hspi);
1909 }
1910 #endif /* USE_SPI_CRC */
1911
1912 /* Set the SPI TxDMA Half transfer complete callback */
1913 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
1914
1915 /* Set the SPI TxDMA transfer complete callback */
1916 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
1917
1918 /* Set the DMA error callback */
1919 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
1920
1921 /* Set the DMA AbortCpltCallback */
1922 hspi->hdmatx->XferAbortCallback = NULL;
1923
1924 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1925 /* Packing mode is enabled only if the DMA setting is HALWORD */
1926 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
1927 {
1928 /* Check the even/odd of the data size + crc if enabled */
1929 if ((hspi->TxXferCount & 0x1U) == 0U)
1930 {
1931 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1932 hspi->TxXferCount = (hspi->TxXferCount >> 1U);
1933 }
1934 else
1935 {
1936 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1937 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
1938 }
1939 }
1940
1941 /* Enable the Tx DMA Stream/Channel */
1942 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
1943 hspi->TxXferCount))
1944 {
1945 /* Update SPI error code */
1946 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
1947 errorcode = HAL_ERROR;
1948
1949 hspi->State = HAL_SPI_STATE_READY;
1950 goto error;
1951 }
1952
1953 /* Check if the SPI is already enabled */
1954 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1955 {
1956 /* Enable SPI peripheral */
1957 __HAL_SPI_ENABLE(hspi);
1958 }
1959
1960 /* Enable the SPI Error Interrupt Bit */
1961 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
1962
1963 /* Enable Tx DMA Request */
1964 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
1965
1966 error :
1967 /* Process Unlocked */
1968 __HAL_UNLOCK(hspi);
1969 return errorcode;
1970 }
1971
1972 /**
1973 * @brief Receive an amount of data in non-blocking mode with DMA.
1974 * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
1975 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1976 * the configuration information for SPI module.
1977 * @param pData pointer to data buffer
1978 * @note When the CRC feature is enabled the pData Length must be Size + 1.
1979 * @param Size amount of data to be sent
1980 * @retval HAL status
1981 */
HAL_SPI_Receive_DMA(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1982 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1983 {
1984 HAL_StatusTypeDef errorcode = HAL_OK;
1985
1986 /* Check rx dma handle */
1987 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
1988
1989 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1990 {
1991 hspi->State = HAL_SPI_STATE_BUSY_RX;
1992
1993 /* Check tx dma handle */
1994 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1995
1996 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1997 return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
1998 }
1999
2000 /* Process Locked */
2001 __HAL_LOCK(hspi);
2002
2003 if (hspi->State != HAL_SPI_STATE_READY)
2004 {
2005 errorcode = HAL_BUSY;
2006 goto error;
2007 }
2008
2009 if ((pData == NULL) || (Size == 0U))
2010 {
2011 errorcode = HAL_ERROR;
2012 goto error;
2013 }
2014
2015 /* Set the transaction information */
2016 hspi->State = HAL_SPI_STATE_BUSY_RX;
2017 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2018 hspi->pRxBuffPtr = (uint8_t *)pData;
2019 hspi->RxXferSize = Size;
2020 hspi->RxXferCount = Size;
2021
2022 /*Init field not used in handle to zero */
2023 hspi->RxISR = NULL;
2024 hspi->TxISR = NULL;
2025 hspi->TxXferSize = 0U;
2026 hspi->TxXferCount = 0U;
2027
2028 /* Configure communication direction : 1Line */
2029 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
2030 {
2031 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
2032 __HAL_SPI_DISABLE(hspi);
2033 SPI_1LINE_RX(hspi);
2034 }
2035
2036 #if (USE_SPI_CRC != 0U)
2037 /* Reset CRC Calculation */
2038 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2039 {
2040 SPI_RESET_CRC(hspi);
2041 }
2042 #endif /* USE_SPI_CRC */
2043
2044
2045 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2046 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
2047 {
2048 /* Set RX Fifo threshold according the reception data length: 16bit */
2049 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2050 }
2051 else
2052 {
2053 /* Set RX Fifo threshold according the reception data length: 8bit */
2054 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2055
2056 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2057 {
2058 /* Set RX Fifo threshold according the reception data length: 16bit */
2059 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2060
2061 if ((hspi->RxXferCount & 0x1U) == 0x0U)
2062 {
2063 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2064 hspi->RxXferCount = hspi->RxXferCount >> 1U;
2065 }
2066 else
2067 {
2068 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2069 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
2070 }
2071 }
2072 }
2073
2074 /* Set the SPI RxDMA Half transfer complete callback */
2075 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
2076
2077 /* Set the SPI Rx DMA transfer complete callback */
2078 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
2079
2080 /* Set the DMA error callback */
2081 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
2082
2083 /* Set the DMA AbortCpltCallback */
2084 hspi->hdmarx->XferAbortCallback = NULL;
2085
2086 /* Enable the Rx DMA Stream/Channel */
2087 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
2088 hspi->RxXferCount))
2089 {
2090 /* Update SPI error code */
2091 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2092 errorcode = HAL_ERROR;
2093
2094 hspi->State = HAL_SPI_STATE_READY;
2095 goto error;
2096 }
2097
2098 /* Check if the SPI is already enabled */
2099 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
2100 {
2101 /* Enable SPI peripheral */
2102 __HAL_SPI_ENABLE(hspi);
2103 }
2104
2105 /* Enable the SPI Error Interrupt Bit */
2106 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
2107
2108 /* Enable Rx DMA Request */
2109 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2110
2111 error:
2112 /* Process Unlocked */
2113 __HAL_UNLOCK(hspi);
2114 return errorcode;
2115 }
2116
2117 /**
2118 * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
2119 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2120 * the configuration information for SPI module.
2121 * @param pTxData pointer to transmission data buffer
2122 * @param pRxData pointer to reception data buffer
2123 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
2124 * @param Size amount of data to be sent
2125 * @retval HAL status
2126 */
HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size)2127 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
2128 uint16_t Size)
2129 {
2130 uint32_t tmp_mode;
2131 HAL_SPI_StateTypeDef tmp_state;
2132 HAL_StatusTypeDef errorcode = HAL_OK;
2133
2134 /* Check rx & tx dma handles */
2135 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
2136 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
2137
2138 /* Check Direction parameter */
2139 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
2140
2141 /* Process locked */
2142 __HAL_LOCK(hspi);
2143
2144 /* Init temporary variables */
2145 tmp_state = hspi->State;
2146 tmp_mode = hspi->Init.Mode;
2147
2148 if (!((tmp_state == HAL_SPI_STATE_READY) ||
2149 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
2150 {
2151 errorcode = HAL_BUSY;
2152 goto error;
2153 }
2154
2155 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
2156 {
2157 errorcode = HAL_ERROR;
2158 goto error;
2159 }
2160
2161 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
2162 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
2163 {
2164 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
2165 }
2166
2167 /* Set the transaction information */
2168 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2169 hspi->pTxBuffPtr = (uint8_t *)pTxData;
2170 hspi->TxXferSize = Size;
2171 hspi->TxXferCount = Size;
2172 hspi->pRxBuffPtr = (uint8_t *)pRxData;
2173 hspi->RxXferSize = Size;
2174 hspi->RxXferCount = Size;
2175
2176 /* Init field not used in handle to zero */
2177 hspi->RxISR = NULL;
2178 hspi->TxISR = NULL;
2179
2180 #if (USE_SPI_CRC != 0U)
2181 /* Reset CRC Calculation */
2182 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2183 {
2184 SPI_RESET_CRC(hspi);
2185 }
2186 #endif /* USE_SPI_CRC */
2187
2188 /* Reset the threshold bit */
2189 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
2190
2191 /* The packing mode management is enabled by the DMA settings according the spi data size */
2192 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
2193 {
2194 /* Set fiforxthreshold according the reception data length: 16bit */
2195 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2196 }
2197 else
2198 {
2199 /* Set RX Fifo threshold according the reception data length: 8bit */
2200 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2201
2202 if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2203 {
2204 if ((hspi->TxXferSize & 0x1U) == 0x0U)
2205 {
2206 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
2207 hspi->TxXferCount = hspi->TxXferCount >> 1U;
2208 }
2209 else
2210 {
2211 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
2212 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
2213 }
2214 }
2215
2216 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2217 {
2218 /* Set RX Fifo threshold according the reception data length: 16bit */
2219 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2220
2221 if ((hspi->RxXferCount & 0x1U) == 0x0U)
2222 {
2223 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2224 hspi->RxXferCount = hspi->RxXferCount >> 1U;
2225 }
2226 else
2227 {
2228 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2229 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
2230 }
2231 }
2232 }
2233
2234 /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
2235 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
2236 {
2237 /* Set the SPI Rx DMA Half transfer complete callback */
2238 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
2239 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
2240 }
2241 else
2242 {
2243 /* Set the SPI Tx/Rx DMA Half transfer complete callback */
2244 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
2245 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
2246 }
2247
2248 /* Set the DMA error callback */
2249 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
2250
2251 /* Set the DMA AbortCpltCallback */
2252 hspi->hdmarx->XferAbortCallback = NULL;
2253
2254 /* Enable the Rx DMA Stream/Channel */
2255 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
2256 hspi->RxXferCount))
2257 {
2258 /* Update SPI error code */
2259 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2260 errorcode = HAL_ERROR;
2261
2262 hspi->State = HAL_SPI_STATE_READY;
2263 goto error;
2264 }
2265
2266 /* Enable Rx DMA Request */
2267 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2268
2269 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
2270 is performed in DMA reception complete callback */
2271 hspi->hdmatx->XferHalfCpltCallback = NULL;
2272 hspi->hdmatx->XferCpltCallback = NULL;
2273 hspi->hdmatx->XferErrorCallback = NULL;
2274 hspi->hdmatx->XferAbortCallback = NULL;
2275
2276 /* Enable the Tx DMA Stream/Channel */
2277 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
2278 hspi->TxXferCount))
2279 {
2280 /* Update SPI error code */
2281 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2282 errorcode = HAL_ERROR;
2283
2284 hspi->State = HAL_SPI_STATE_READY;
2285 goto error;
2286 }
2287
2288 /* Check if the SPI is already enabled */
2289 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
2290 {
2291 /* Enable SPI peripheral */
2292 __HAL_SPI_ENABLE(hspi);
2293 }
2294 /* Enable the SPI Error Interrupt Bit */
2295 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
2296
2297 /* Enable Tx DMA Request */
2298 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
2299
2300 error :
2301 /* Process Unlocked */
2302 __HAL_UNLOCK(hspi);
2303 return errorcode;
2304 }
2305
2306 /**
2307 * @brief Abort ongoing transfer (blocking mode).
2308 * @param hspi SPI handle.
2309 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2310 * started in Interrupt or DMA mode.
2311 * This procedure performs following operations :
2312 * - Disable SPI Interrupts (depending of transfer direction)
2313 * - Disable the DMA transfer in the peripheral register (if enabled)
2314 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
2315 * - Set handle State to READY
2316 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
2317 * @retval HAL status
2318 */
HAL_SPI_Abort(SPI_HandleTypeDef * hspi)2319 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
2320 {
2321 HAL_StatusTypeDef errorcode;
2322 __IO uint32_t count;
2323 __IO uint32_t resetcount;
2324
2325 /* Initialized local variable */
2326 errorcode = HAL_OK;
2327 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2328 count = resetcount;
2329
2330 /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
2331 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
2332
2333 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
2334 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
2335 {
2336 hspi->TxISR = SPI_AbortTx_ISR;
2337 /* Wait HAL_SPI_STATE_ABORT state */
2338 do
2339 {
2340 if (count == 0U)
2341 {
2342 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2343 break;
2344 }
2345 count--;
2346 } while (hspi->State != HAL_SPI_STATE_ABORT);
2347 /* Reset Timeout Counter */
2348 count = resetcount;
2349 }
2350
2351 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
2352 {
2353 hspi->RxISR = SPI_AbortRx_ISR;
2354 /* Wait HAL_SPI_STATE_ABORT state */
2355 do
2356 {
2357 if (count == 0U)
2358 {
2359 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2360 break;
2361 }
2362 count--;
2363 } while (hspi->State != HAL_SPI_STATE_ABORT);
2364 /* Reset Timeout Counter */
2365 count = resetcount;
2366 }
2367
2368 /* Disable the SPI DMA Tx request if enabled */
2369 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2370 {
2371 /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
2372 if (hspi->hdmatx != NULL)
2373 {
2374 /* Set the SPI DMA Abort callback :
2375 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2376 hspi->hdmatx->XferAbortCallback = NULL;
2377
2378 /* Abort DMA Tx Handle linked to SPI Peripheral */
2379 if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
2380 {
2381 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2382 }
2383
2384 /* Disable Tx DMA Request */
2385 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
2386
2387 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2388 {
2389 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2390 }
2391
2392 /* Disable SPI Peripheral */
2393 __HAL_SPI_DISABLE(hspi);
2394
2395 /* Empty the FRLVL fifo */
2396 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2397 {
2398 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2399 }
2400 }
2401 }
2402
2403 /* Disable the SPI DMA Rx request if enabled */
2404 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2405 {
2406 /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
2407 if (hspi->hdmarx != NULL)
2408 {
2409 /* Set the SPI DMA Abort callback :
2410 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2411 hspi->hdmarx->XferAbortCallback = NULL;
2412
2413 /* Abort DMA Rx Handle linked to SPI Peripheral */
2414 if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
2415 {
2416 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2417 }
2418
2419 /* Disable peripheral */
2420 __HAL_SPI_DISABLE(hspi);
2421
2422 /* Control the BSY flag */
2423 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2424 {
2425 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2426 }
2427
2428 /* Empty the FRLVL fifo */
2429 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2430 {
2431 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2432 }
2433
2434 /* Disable Rx DMA Request */
2435 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
2436 }
2437 }
2438 /* Reset Tx and Rx transfer counters */
2439 hspi->RxXferCount = 0U;
2440 hspi->TxXferCount = 0U;
2441
2442 /* Check error during Abort procedure */
2443 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2444 {
2445 /* return HAL_Error in case of error during Abort procedure */
2446 errorcode = HAL_ERROR;
2447 }
2448 else
2449 {
2450 /* Reset errorCode */
2451 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2452 }
2453
2454 /* Clear the Error flags in the SR register */
2455 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2456 __HAL_SPI_CLEAR_FREFLAG(hspi);
2457
2458 /* Restore hspi->state to ready */
2459 hspi->State = HAL_SPI_STATE_READY;
2460
2461 return errorcode;
2462 }
2463
2464 /**
2465 * @brief Abort ongoing transfer (Interrupt mode).
2466 * @param hspi SPI handle.
2467 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2468 * started in Interrupt or DMA mode.
2469 * This procedure performs following operations :
2470 * - Disable SPI Interrupts (depending of transfer direction)
2471 * - Disable the DMA transfer in the peripheral register (if enabled)
2472 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
2473 * - Set handle State to READY
2474 * - At abort completion, call user abort complete callback
2475 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
2476 * considered as completed only when user abort complete callback is executed (not when exiting function).
2477 * @retval HAL status
2478 */
HAL_SPI_Abort_IT(SPI_HandleTypeDef * hspi)2479 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
2480 {
2481 HAL_StatusTypeDef errorcode;
2482 uint32_t abortcplt ;
2483 __IO uint32_t count;
2484 __IO uint32_t resetcount;
2485
2486 /* Initialized local variable */
2487 errorcode = HAL_OK;
2488 abortcplt = 1U;
2489 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2490 count = resetcount;
2491
2492 /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
2493 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
2494
2495 /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
2496 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
2497 {
2498 hspi->TxISR = SPI_AbortTx_ISR;
2499 /* Wait HAL_SPI_STATE_ABORT state */
2500 do
2501 {
2502 if (count == 0U)
2503 {
2504 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2505 break;
2506 }
2507 count--;
2508 } while (hspi->State != HAL_SPI_STATE_ABORT);
2509 /* Reset Timeout Counter */
2510 count = resetcount;
2511 }
2512
2513 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
2514 {
2515 hspi->RxISR = SPI_AbortRx_ISR;
2516 /* Wait HAL_SPI_STATE_ABORT state */
2517 do
2518 {
2519 if (count == 0U)
2520 {
2521 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2522 break;
2523 }
2524 count--;
2525 } while (hspi->State != HAL_SPI_STATE_ABORT);
2526 /* Reset Timeout Counter */
2527 count = resetcount;
2528 }
2529
2530 /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
2531 before any call to DMA Abort functions */
2532 /* DMA Tx Handle is valid */
2533 if (hspi->hdmatx != NULL)
2534 {
2535 /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
2536 Otherwise, set it to NULL */
2537 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2538 {
2539 hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
2540 }
2541 else
2542 {
2543 hspi->hdmatx->XferAbortCallback = NULL;
2544 }
2545 }
2546 /* DMA Rx Handle is valid */
2547 if (hspi->hdmarx != NULL)
2548 {
2549 /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
2550 Otherwise, set it to NULL */
2551 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2552 {
2553 hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
2554 }
2555 else
2556 {
2557 hspi->hdmarx->XferAbortCallback = NULL;
2558 }
2559 }
2560
2561 /* Disable the SPI DMA Tx request if enabled */
2562 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2563 {
2564 /* Abort the SPI DMA Tx Stream/Channel */
2565 if (hspi->hdmatx != NULL)
2566 {
2567 /* Abort DMA Tx Handle linked to SPI Peripheral */
2568 if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
2569 {
2570 hspi->hdmatx->XferAbortCallback = NULL;
2571 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2572 }
2573 else
2574 {
2575 abortcplt = 0U;
2576 }
2577 }
2578 }
2579 /* Disable the SPI DMA Rx request if enabled */
2580 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2581 {
2582 /* Abort the SPI DMA Rx Stream/Channel */
2583 if (hspi->hdmarx != NULL)
2584 {
2585 /* Abort DMA Rx Handle linked to SPI Peripheral */
2586 if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
2587 {
2588 hspi->hdmarx->XferAbortCallback = NULL;
2589 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2590 }
2591 else
2592 {
2593 abortcplt = 0U;
2594 }
2595 }
2596 }
2597
2598 if (abortcplt == 1U)
2599 {
2600 /* Reset Tx and Rx transfer counters */
2601 hspi->RxXferCount = 0U;
2602 hspi->TxXferCount = 0U;
2603
2604 /* Check error during Abort procedure */
2605 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2606 {
2607 /* return HAL_Error in case of error during Abort procedure */
2608 errorcode = HAL_ERROR;
2609 }
2610 else
2611 {
2612 /* Reset errorCode */
2613 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2614 }
2615
2616 /* Clear the Error flags in the SR register */
2617 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2618 __HAL_SPI_CLEAR_FREFLAG(hspi);
2619
2620 /* Restore hspi->State to Ready */
2621 hspi->State = HAL_SPI_STATE_READY;
2622
2623 /* As no DMA to be aborted, call directly user Abort complete callback */
2624 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2625 hspi->AbortCpltCallback(hspi);
2626 #else
2627 HAL_SPI_AbortCpltCallback(hspi);
2628 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2629 }
2630
2631 return errorcode;
2632 }
2633
2634 /**
2635 * @brief Pause the DMA Transfer.
2636 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2637 * the configuration information for the specified SPI module.
2638 * @retval HAL status
2639 */
HAL_SPI_DMAPause(SPI_HandleTypeDef * hspi)2640 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
2641 {
2642 /* Process Locked */
2643 __HAL_LOCK(hspi);
2644
2645 /* Disable the SPI DMA Tx & Rx requests */
2646 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2647
2648 /* Process Unlocked */
2649 __HAL_UNLOCK(hspi);
2650
2651 return HAL_OK;
2652 }
2653
2654 /**
2655 * @brief Resume the DMA Transfer.
2656 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2657 * the configuration information for the specified SPI module.
2658 * @retval HAL status
2659 */
HAL_SPI_DMAResume(SPI_HandleTypeDef * hspi)2660 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
2661 {
2662 /* Process Locked */
2663 __HAL_LOCK(hspi);
2664
2665 /* Enable the SPI DMA Tx & Rx requests */
2666 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2667
2668 /* Process Unlocked */
2669 __HAL_UNLOCK(hspi);
2670
2671 return HAL_OK;
2672 }
2673
2674 /**
2675 * @brief Stop the DMA Transfer.
2676 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2677 * the configuration information for the specified SPI module.
2678 * @retval HAL status
2679 */
HAL_SPI_DMAStop(SPI_HandleTypeDef * hspi)2680 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
2681 {
2682 HAL_StatusTypeDef errorcode = HAL_OK;
2683 /* The Lock is not implemented on this API to allow the user application
2684 to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
2685 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
2686 and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
2687 */
2688
2689 /* Abort the SPI DMA tx Stream/Channel */
2690 if (hspi->hdmatx != NULL)
2691 {
2692 if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
2693 {
2694 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2695 errorcode = HAL_ERROR;
2696 }
2697 }
2698 /* Abort the SPI DMA rx Stream/Channel */
2699 if (hspi->hdmarx != NULL)
2700 {
2701 if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
2702 {
2703 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2704 errorcode = HAL_ERROR;
2705 }
2706 }
2707
2708 /* Disable the SPI DMA Tx & Rx requests */
2709 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2710 hspi->State = HAL_SPI_STATE_READY;
2711 return errorcode;
2712 }
2713
2714 /**
2715 * @brief Handle SPI interrupt request.
2716 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2717 * the configuration information for the specified SPI module.
2718 * @retval None
2719 */
HAL_SPI_IRQHandler(SPI_HandleTypeDef * hspi)2720 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
2721 {
2722 uint32_t itsource = hspi->Instance->CR2;
2723 uint32_t itflag = hspi->Instance->SR;
2724
2725 /* SPI in mode Receiver ----------------------------------------------------*/
2726 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
2727 (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
2728 {
2729 hspi->RxISR(hspi);
2730 return;
2731 }
2732
2733 /* SPI in mode Transmitter -------------------------------------------------*/
2734 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
2735 {
2736 hspi->TxISR(hspi);
2737 return;
2738 }
2739
2740 /* SPI in Error Treatment --------------------------------------------------*/
2741 if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
2742 || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
2743 {
2744 /* SPI Overrun error interrupt occurred ----------------------------------*/
2745 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
2746 {
2747 if (hspi->State != HAL_SPI_STATE_BUSY_TX)
2748 {
2749 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
2750 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2751 }
2752 else
2753 {
2754 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2755 return;
2756 }
2757 }
2758
2759 /* SPI Mode Fault error interrupt occurred -------------------------------*/
2760 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
2761 {
2762 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
2763 __HAL_SPI_CLEAR_MODFFLAG(hspi);
2764 }
2765
2766 /* SPI Frame error interrupt occurred ------------------------------------*/
2767 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
2768 {
2769 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
2770 __HAL_SPI_CLEAR_FREFLAG(hspi);
2771 }
2772
2773 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2774 {
2775 /* Disable all interrupts */
2776 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
2777
2778 hspi->State = HAL_SPI_STATE_READY;
2779 /* Disable the SPI DMA requests if enabled */
2780 if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
2781 {
2782 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
2783
2784 /* Abort the SPI DMA Rx channel */
2785 if (hspi->hdmarx != NULL)
2786 {
2787 /* Set the SPI DMA Abort callback :
2788 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2789 hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
2790 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
2791 {
2792 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2793 }
2794 }
2795 /* Abort the SPI DMA Tx channel */
2796 if (hspi->hdmatx != NULL)
2797 {
2798 /* Set the SPI DMA Abort callback :
2799 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2800 hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
2801 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
2802 {
2803 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2804 }
2805 }
2806 }
2807 else
2808 {
2809 /* Call user error callback */
2810 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2811 hspi->ErrorCallback(hspi);
2812 #else
2813 HAL_SPI_ErrorCallback(hspi);
2814 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2815 }
2816 }
2817 return;
2818 }
2819 }
2820
2821 /**
2822 * @brief Tx Transfer completed callback.
2823 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2824 * the configuration information for SPI module.
2825 * @retval None
2826 */
HAL_SPI_TxCpltCallback(SPI_HandleTypeDef * hspi)2827 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
2828 {
2829 /* Prevent unused argument(s) compilation warning */
2830 UNUSED(hspi);
2831
2832 /* NOTE : This function should not be modified, when the callback is needed,
2833 the HAL_SPI_TxCpltCallback should be implemented in the user file
2834 */
2835 }
2836
2837 /**
2838 * @brief Rx Transfer completed callback.
2839 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2840 * the configuration information for SPI module.
2841 * @retval None
2842 */
HAL_SPI_RxCpltCallback(SPI_HandleTypeDef * hspi)2843 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
2844 {
2845 /* Prevent unused argument(s) compilation warning */
2846 UNUSED(hspi);
2847
2848 /* NOTE : This function should not be modified, when the callback is needed,
2849 the HAL_SPI_RxCpltCallback should be implemented in the user file
2850 */
2851 }
2852
2853 /**
2854 * @brief Tx and Rx Transfer completed callback.
2855 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2856 * the configuration information for SPI module.
2857 * @retval None
2858 */
HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef * hspi)2859 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
2860 {
2861 /* Prevent unused argument(s) compilation warning */
2862 UNUSED(hspi);
2863
2864 /* NOTE : This function should not be modified, when the callback is needed,
2865 the HAL_SPI_TxRxCpltCallback should be implemented in the user file
2866 */
2867 }
2868
2869 /**
2870 * @brief Tx Half Transfer completed callback.
2871 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2872 * the configuration information for SPI module.
2873 * @retval None
2874 */
HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef * hspi)2875 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2876 {
2877 /* Prevent unused argument(s) compilation warning */
2878 UNUSED(hspi);
2879
2880 /* NOTE : This function should not be modified, when the callback is needed,
2881 the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
2882 */
2883 }
2884
2885 /**
2886 * @brief Rx Half Transfer completed callback.
2887 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2888 * the configuration information for SPI module.
2889 * @retval None
2890 */
HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef * hspi)2891 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2892 {
2893 /* Prevent unused argument(s) compilation warning */
2894 UNUSED(hspi);
2895
2896 /* NOTE : This function should not be modified, when the callback is needed,
2897 the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
2898 */
2899 }
2900
2901 /**
2902 * @brief Tx and Rx Half Transfer callback.
2903 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2904 * the configuration information for SPI module.
2905 * @retval None
2906 */
HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef * hspi)2907 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2908 {
2909 /* Prevent unused argument(s) compilation warning */
2910 UNUSED(hspi);
2911
2912 /* NOTE : This function should not be modified, when the callback is needed,
2913 the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
2914 */
2915 }
2916
2917 /**
2918 * @brief SPI error callback.
2919 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2920 * the configuration information for SPI module.
2921 * @retval None
2922 */
HAL_SPI_ErrorCallback(SPI_HandleTypeDef * hspi)2923 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
2924 {
2925 /* Prevent unused argument(s) compilation warning */
2926 UNUSED(hspi);
2927
2928 /* NOTE : This function should not be modified, when the callback is needed,
2929 the HAL_SPI_ErrorCallback should be implemented in the user file
2930 */
2931 /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
2932 and user can use HAL_SPI_GetError() API to check the latest error occurred
2933 */
2934 }
2935
2936 /**
2937 * @brief SPI Abort Complete callback.
2938 * @param hspi SPI handle.
2939 * @retval None
2940 */
HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef * hspi)2941 __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
2942 {
2943 /* Prevent unused argument(s) compilation warning */
2944 UNUSED(hspi);
2945
2946 /* NOTE : This function should not be modified, when the callback is needed,
2947 the HAL_SPI_AbortCpltCallback can be implemented in the user file.
2948 */
2949 }
2950
2951 /**
2952 * @}
2953 */
2954
2955 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
2956 * @brief SPI control functions
2957 *
2958 @verbatim
2959 ===============================================================================
2960 ##### Peripheral State and Errors functions #####
2961 ===============================================================================
2962 [..]
2963 This subsection provides a set of functions allowing to control the SPI.
2964 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
2965 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
2966 @endverbatim
2967 * @{
2968 */
2969
2970 /**
2971 * @brief Return the SPI handle state.
2972 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2973 * the configuration information for SPI module.
2974 * @retval SPI state
2975 */
HAL_SPI_GetState(SPI_HandleTypeDef * hspi)2976 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
2977 {
2978 /* Return SPI handle state */
2979 return hspi->State;
2980 }
2981
2982 /**
2983 * @brief Return the SPI error code.
2984 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2985 * the configuration information for SPI module.
2986 * @retval SPI error code in bitmap format
2987 */
HAL_SPI_GetError(SPI_HandleTypeDef * hspi)2988 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
2989 {
2990 /* Return SPI ErrorCode */
2991 return hspi->ErrorCode;
2992 }
2993
2994 /**
2995 * @}
2996 */
2997
2998 /**
2999 * @}
3000 */
3001
3002 /** @addtogroup SPI_Private_Functions
3003 * @brief Private functions
3004 * @{
3005 */
3006
3007 /**
3008 * @brief DMA SPI transmit process complete callback.
3009 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3010 * the configuration information for the specified DMA module.
3011 * @retval None
3012 */
SPI_DMATransmitCplt(DMA_HandleTypeDef * hdma)3013 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
3014 {
3015 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3016 uint32_t tickstart;
3017
3018 /* Init tickstart for timeout management*/
3019 tickstart = HAL_GetTick();
3020
3021 /* DMA Normal Mode */
3022 if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)
3023 {
3024 /* Disable ERR interrupt */
3025 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3026
3027 /* Disable Tx DMA Request */
3028 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
3029
3030 /* Check the end of the transaction */
3031 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3032 {
3033 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3034 }
3035
3036 /* Clear overrun flag in 2 Lines communication mode because received data is not read */
3037 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
3038 {
3039 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3040 }
3041
3042 hspi->TxXferCount = 0U;
3043 hspi->State = HAL_SPI_STATE_READY;
3044
3045 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3046 {
3047 /* Call user error callback */
3048 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3049 hspi->ErrorCallback(hspi);
3050 #else
3051 HAL_SPI_ErrorCallback(hspi);
3052 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3053 return;
3054 }
3055 }
3056 /* Call user Tx complete callback */
3057 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3058 hspi->TxCpltCallback(hspi);
3059 #else
3060 HAL_SPI_TxCpltCallback(hspi);
3061 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3062 }
3063
3064 /**
3065 * @brief DMA SPI receive process complete callback.
3066 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3067 * the configuration information for the specified DMA module.
3068 * @retval None
3069 */
SPI_DMAReceiveCplt(DMA_HandleTypeDef * hdma)3070 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
3071 {
3072 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3073 uint32_t tickstart;
3074 #if (USE_SPI_CRC != 0U)
3075 __IO uint32_t tmpreg = 0U;
3076 __IO uint8_t *ptmpreg8;
3077 __IO uint8_t tmpreg8 = 0;
3078 #endif /* USE_SPI_CRC */
3079
3080 /* Init tickstart for timeout management*/
3081 tickstart = HAL_GetTick();
3082
3083 /* DMA Normal Mode */
3084 if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)
3085 {
3086 /* Disable ERR interrupt */
3087 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3088
3089 #if (USE_SPI_CRC != 0U)
3090 /* CRC handling */
3091 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3092 {
3093 /* Wait until RXNE flag */
3094 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3095 {
3096 /* Error on the CRC reception */
3097 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3098 }
3099 /* Read CRC */
3100 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
3101 {
3102 /* Read 16bit CRC */
3103 tmpreg = READ_REG(hspi->Instance->DR);
3104 /* To avoid GCC warning */
3105 UNUSED(tmpreg);
3106 }
3107 else
3108 {
3109 /* Initialize the 8bit temporary pointer */
3110 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3111 /* Read 8bit CRC */
3112 tmpreg8 = *ptmpreg8;
3113 /* To avoid GCC warning */
3114 UNUSED(tmpreg8);
3115
3116 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
3117 {
3118 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3119 {
3120 /* Error on the CRC reception */
3121 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3122 }
3123 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
3124 tmpreg8 = *ptmpreg8;
3125 /* To avoid GCC warning */
3126 UNUSED(tmpreg8);
3127 }
3128 }
3129 }
3130 #endif /* USE_SPI_CRC */
3131
3132 /* Check if we are in Master RX 2 line mode */
3133 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
3134 {
3135 /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
3136 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3137 }
3138 else
3139 {
3140 /* Normal case */
3141 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
3142 }
3143
3144 /* Check the end of the transaction */
3145 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3146 {
3147 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
3148 }
3149
3150 hspi->RxXferCount = 0U;
3151 hspi->State = HAL_SPI_STATE_READY;
3152
3153 #if (USE_SPI_CRC != 0U)
3154 /* Check if CRC error occurred */
3155 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
3156 {
3157 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3158 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3159 }
3160 #endif /* USE_SPI_CRC */
3161
3162 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3163 {
3164 /* Call user error callback */
3165 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3166 hspi->ErrorCallback(hspi);
3167 #else
3168 HAL_SPI_ErrorCallback(hspi);
3169 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3170 return;
3171 }
3172 }
3173 /* Call user Rx complete callback */
3174 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3175 hspi->RxCpltCallback(hspi);
3176 #else
3177 HAL_SPI_RxCpltCallback(hspi);
3178 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3179 }
3180
3181 /**
3182 * @brief DMA SPI transmit receive process complete callback.
3183 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3184 * the configuration information for the specified DMA module.
3185 * @retval None
3186 */
SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef * hdma)3187 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
3188 {
3189 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3190 uint32_t tickstart;
3191 #if (USE_SPI_CRC != 0U)
3192 __IO uint32_t tmpreg = 0U;
3193 __IO uint8_t *ptmpreg8;
3194 __IO uint8_t tmpreg8 = 0;
3195 #endif /* USE_SPI_CRC */
3196
3197 /* Init tickstart for timeout management*/
3198 tickstart = HAL_GetTick();
3199
3200 /* DMA Normal Mode */
3201 if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)
3202 {
3203 /* Disable ERR interrupt */
3204 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3205
3206 #if (USE_SPI_CRC != 0U)
3207 /* CRC handling */
3208 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3209 {
3210 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
3211 {
3212 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
3213 tickstart) != HAL_OK)
3214 {
3215 /* Error on the CRC reception */
3216 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3217 }
3218 /* Initialize the 8bit temporary pointer */
3219 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3220 /* Read 8bit CRC */
3221 tmpreg8 = *ptmpreg8;
3222 /* To avoid GCC warning */
3223 UNUSED(tmpreg8);
3224 }
3225 else
3226 {
3227 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3228 {
3229 /* Error on the CRC reception */
3230 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3231 }
3232 /* Read CRC to Flush DR and RXNE flag */
3233 tmpreg = READ_REG(hspi->Instance->DR);
3234 /* To avoid GCC warning */
3235 UNUSED(tmpreg);
3236 }
3237 }
3238 #endif /* USE_SPI_CRC */
3239
3240 /* Check the end of the transaction */
3241 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3242 {
3243 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3244 }
3245
3246 /* Disable Rx/Tx DMA Request */
3247 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3248
3249 hspi->TxXferCount = 0U;
3250 hspi->RxXferCount = 0U;
3251 hspi->State = HAL_SPI_STATE_READY;
3252
3253 #if (USE_SPI_CRC != 0U)
3254 /* Check if CRC error occurred */
3255 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
3256 {
3257 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3258 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3259 }
3260 #endif /* USE_SPI_CRC */
3261
3262 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3263 {
3264 /* Call user error callback */
3265 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3266 hspi->ErrorCallback(hspi);
3267 #else
3268 HAL_SPI_ErrorCallback(hspi);
3269 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3270 return;
3271 }
3272 }
3273 /* Call user TxRx complete callback */
3274 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3275 hspi->TxRxCpltCallback(hspi);
3276 #else
3277 HAL_SPI_TxRxCpltCallback(hspi);
3278 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3279 }
3280
3281 /**
3282 * @brief DMA SPI half transmit process complete callback.
3283 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3284 * the configuration information for the specified DMA module.
3285 * @retval None
3286 */
SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef * hdma)3287 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
3288 {
3289 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3290
3291 /* Call user Tx half complete callback */
3292 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3293 hspi->TxHalfCpltCallback(hspi);
3294 #else
3295 HAL_SPI_TxHalfCpltCallback(hspi);
3296 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3297 }
3298
3299 /**
3300 * @brief DMA SPI half receive process complete callback
3301 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3302 * the configuration information for the specified DMA module.
3303 * @retval None
3304 */
SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef * hdma)3305 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
3306 {
3307 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3308
3309 /* Call user Rx half complete callback */
3310 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3311 hspi->RxHalfCpltCallback(hspi);
3312 #else
3313 HAL_SPI_RxHalfCpltCallback(hspi);
3314 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3315 }
3316
3317 /**
3318 * @brief DMA SPI half transmit receive process complete callback.
3319 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3320 * the configuration information for the specified DMA module.
3321 * @retval None
3322 */
SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef * hdma)3323 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
3324 {
3325 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3326
3327 /* Call user TxRx half complete callback */
3328 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3329 hspi->TxRxHalfCpltCallback(hspi);
3330 #else
3331 HAL_SPI_TxRxHalfCpltCallback(hspi);
3332 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3333 }
3334
3335 /**
3336 * @brief DMA SPI communication error callback.
3337 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3338 * the configuration information for the specified DMA module.
3339 * @retval None
3340 */
SPI_DMAError(DMA_HandleTypeDef * hdma)3341 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
3342 {
3343 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3344
3345 /* Stop the disable DMA transfer on SPI side */
3346 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3347
3348 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
3349 hspi->State = HAL_SPI_STATE_READY;
3350 /* Call user error callback */
3351 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3352 hspi->ErrorCallback(hspi);
3353 #else
3354 HAL_SPI_ErrorCallback(hspi);
3355 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3356 }
3357
3358 /**
3359 * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
3360 * (To be called at end of DMA Abort procedure following error occurrence).
3361 * @param hdma DMA handle.
3362 * @retval None
3363 */
SPI_DMAAbortOnError(DMA_HandleTypeDef * hdma)3364 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
3365 {
3366 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3367 hspi->RxXferCount = 0U;
3368 hspi->TxXferCount = 0U;
3369
3370 /* Call user error callback */
3371 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3372 hspi->ErrorCallback(hspi);
3373 #else
3374 HAL_SPI_ErrorCallback(hspi);
3375 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3376 }
3377
3378 /**
3379 * @brief DMA SPI Tx communication abort callback, when initiated by user
3380 * (To be called at end of DMA Tx Abort procedure following user abort request).
3381 * @note When this callback is executed, User Abort complete call back is called only if no
3382 * Abort still ongoing for Rx DMA Handle.
3383 * @param hdma DMA handle.
3384 * @retval None
3385 */
SPI_DMATxAbortCallback(DMA_HandleTypeDef * hdma)3386 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
3387 {
3388 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3389
3390 hspi->hdmatx->XferAbortCallback = NULL;
3391
3392 /* Disable Tx DMA Request */
3393 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
3394
3395 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3396 {
3397 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3398 }
3399
3400 /* Disable SPI Peripheral */
3401 __HAL_SPI_DISABLE(hspi);
3402
3403 /* Empty the FRLVL fifo */
3404 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3405 {
3406 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3407 }
3408
3409 /* Check if an Abort process is still ongoing */
3410 if (hspi->hdmarx != NULL)
3411 {
3412 if (hspi->hdmarx->XferAbortCallback != NULL)
3413 {
3414 return;
3415 }
3416 }
3417
3418 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3419 hspi->RxXferCount = 0U;
3420 hspi->TxXferCount = 0U;
3421
3422 /* Check no error during Abort procedure */
3423 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3424 {
3425 /* Reset errorCode */
3426 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3427 }
3428
3429 /* Clear the Error flags in the SR register */
3430 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3431 __HAL_SPI_CLEAR_FREFLAG(hspi);
3432
3433 /* Restore hspi->State to Ready */
3434 hspi->State = HAL_SPI_STATE_READY;
3435
3436 /* Call user Abort complete callback */
3437 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3438 hspi->AbortCpltCallback(hspi);
3439 #else
3440 HAL_SPI_AbortCpltCallback(hspi);
3441 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3442 }
3443
3444 /**
3445 * @brief DMA SPI Rx communication abort callback, when initiated by user
3446 * (To be called at end of DMA Rx Abort procedure following user abort request).
3447 * @note When this callback is executed, User Abort complete call back is called only if no
3448 * Abort still ongoing for Tx DMA Handle.
3449 * @param hdma DMA handle.
3450 * @retval None
3451 */
SPI_DMARxAbortCallback(DMA_HandleTypeDef * hdma)3452 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
3453 {
3454 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3455
3456 /* Disable SPI Peripheral */
3457 __HAL_SPI_DISABLE(hspi);
3458
3459 hspi->hdmarx->XferAbortCallback = NULL;
3460
3461 /* Disable Rx DMA Request */
3462 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
3463
3464 /* Control the BSY flag */
3465 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3466 {
3467 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3468 }
3469
3470 /* Empty the FRLVL fifo */
3471 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3472 {
3473 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3474 }
3475
3476 /* Check if an Abort process is still ongoing */
3477 if (hspi->hdmatx != NULL)
3478 {
3479 if (hspi->hdmatx->XferAbortCallback != NULL)
3480 {
3481 return;
3482 }
3483 }
3484
3485 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3486 hspi->RxXferCount = 0U;
3487 hspi->TxXferCount = 0U;
3488
3489 /* Check no error during Abort procedure */
3490 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3491 {
3492 /* Reset errorCode */
3493 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3494 }
3495
3496 /* Clear the Error flags in the SR register */
3497 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3498 __HAL_SPI_CLEAR_FREFLAG(hspi);
3499
3500 /* Restore hspi->State to Ready */
3501 hspi->State = HAL_SPI_STATE_READY;
3502
3503 /* Call user Abort complete callback */
3504 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3505 hspi->AbortCpltCallback(hspi);
3506 #else
3507 HAL_SPI_AbortCpltCallback(hspi);
3508 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3509 }
3510
3511 /**
3512 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3513 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3514 * the configuration information for SPI module.
3515 * @retval None
3516 */
SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3517 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3518 {
3519 /* Receive data in packing mode */
3520 if (hspi->RxXferCount > 1U)
3521 {
3522 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3523 hspi->pRxBuffPtr += sizeof(uint16_t);
3524 hspi->RxXferCount -= 2U;
3525 if (hspi->RxXferCount == 1U)
3526 {
3527 /* Set RX Fifo threshold according the reception data length: 8bit */
3528 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
3529 }
3530 }
3531 /* Receive data in 8 Bit mode */
3532 else
3533 {
3534 *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
3535 hspi->pRxBuffPtr++;
3536 hspi->RxXferCount--;
3537 }
3538
3539 /* Check end of the reception */
3540 if (hspi->RxXferCount == 0U)
3541 {
3542 #if (USE_SPI_CRC != 0U)
3543 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3544 {
3545 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
3546 hspi->RxISR = SPI_2linesRxISR_8BITCRC;
3547 return;
3548 }
3549 #endif /* USE_SPI_CRC */
3550
3551 /* Disable RXNE and ERR interrupt */
3552 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3553
3554 if (hspi->TxXferCount == 0U)
3555 {
3556 SPI_CloseRxTx_ISR(hspi);
3557 }
3558 }
3559 }
3560
3561 #if (USE_SPI_CRC != 0U)
3562 /**
3563 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3564 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3565 * the configuration information for SPI module.
3566 * @retval None
3567 */
SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef * hspi)3568 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3569 {
3570 __IO uint8_t *ptmpreg8;
3571 __IO uint8_t tmpreg8 = 0;
3572
3573 /* Initialize the 8bit temporary pointer */
3574 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3575 /* Read 8bit CRC to flush Data Register */
3576 tmpreg8 = *ptmpreg8;
3577 /* To avoid GCC warning */
3578 UNUSED(tmpreg8);
3579
3580 hspi->CRCSize--;
3581
3582 /* Check end of the reception */
3583 if (hspi->CRCSize == 0U)
3584 {
3585 /* Disable RXNE and ERR interrupt */
3586 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3587
3588 if (hspi->TxXferCount == 0U)
3589 {
3590 SPI_CloseRxTx_ISR(hspi);
3591 }
3592 }
3593 }
3594 #endif /* USE_SPI_CRC */
3595
3596 /**
3597 * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
3598 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3599 * the configuration information for SPI module.
3600 * @retval None
3601 */
SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3602 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3603 {
3604 /* Transmit data in packing Bit mode */
3605 if (hspi->TxXferCount >= 2U)
3606 {
3607 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3608 hspi->pTxBuffPtr += sizeof(uint16_t);
3609 hspi->TxXferCount -= 2U;
3610 }
3611 /* Transmit data in 8 Bit mode */
3612 else
3613 {
3614 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3615 hspi->pTxBuffPtr++;
3616 hspi->TxXferCount--;
3617 }
3618
3619 /* Check the end of the transmission */
3620 if (hspi->TxXferCount == 0U)
3621 {
3622 #if (USE_SPI_CRC != 0U)
3623 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3624 {
3625 /* Set CRC Next Bit to send CRC */
3626 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3627 /* Disable TXE interrupt */
3628 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3629 return;
3630 }
3631 #endif /* USE_SPI_CRC */
3632
3633 /* Disable TXE interrupt */
3634 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3635
3636 if (hspi->RxXferCount == 0U)
3637 {
3638 SPI_CloseRxTx_ISR(hspi);
3639 }
3640 }
3641 }
3642
3643 /**
3644 * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
3645 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3646 * the configuration information for SPI module.
3647 * @retval None
3648 */
SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3649 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3650 {
3651 /* Receive data in 16 Bit mode */
3652 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3653 hspi->pRxBuffPtr += sizeof(uint16_t);
3654 hspi->RxXferCount--;
3655
3656 if (hspi->RxXferCount == 0U)
3657 {
3658 #if (USE_SPI_CRC != 0U)
3659 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3660 {
3661 hspi->RxISR = SPI_2linesRxISR_16BITCRC;
3662 return;
3663 }
3664 #endif /* USE_SPI_CRC */
3665
3666 /* Disable RXNE interrupt */
3667 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3668
3669 if (hspi->TxXferCount == 0U)
3670 {
3671 SPI_CloseRxTx_ISR(hspi);
3672 }
3673 }
3674 }
3675
3676 #if (USE_SPI_CRC != 0U)
3677 /**
3678 * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
3679 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3680 * the configuration information for SPI module.
3681 * @retval None
3682 */
SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef * hspi)3683 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3684 {
3685 __IO uint32_t tmpreg = 0U;
3686
3687 /* Read 16bit CRC to flush Data Register */
3688 tmpreg = READ_REG(hspi->Instance->DR);
3689 /* To avoid GCC warning */
3690 UNUSED(tmpreg);
3691
3692 /* Disable RXNE interrupt */
3693 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3694
3695 SPI_CloseRxTx_ISR(hspi);
3696 }
3697 #endif /* USE_SPI_CRC */
3698
3699 /**
3700 * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
3701 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3702 * the configuration information for SPI module.
3703 * @retval None
3704 */
SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3705 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3706 {
3707 /* Transmit data in 16 Bit mode */
3708 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3709 hspi->pTxBuffPtr += sizeof(uint16_t);
3710 hspi->TxXferCount--;
3711
3712 /* Enable CRC Transmission */
3713 if (hspi->TxXferCount == 0U)
3714 {
3715 #if (USE_SPI_CRC != 0U)
3716 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3717 {
3718 /* Set CRC Next Bit to send CRC */
3719 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3720 /* Disable TXE interrupt */
3721 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3722 return;
3723 }
3724 #endif /* USE_SPI_CRC */
3725
3726 /* Disable TXE interrupt */
3727 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3728
3729 if (hspi->RxXferCount == 0U)
3730 {
3731 SPI_CloseRxTx_ISR(hspi);
3732 }
3733 }
3734 }
3735
3736 #if (USE_SPI_CRC != 0U)
3737 /**
3738 * @brief Manage the CRC 8-bit receive in Interrupt context.
3739 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3740 * the configuration information for SPI module.
3741 * @retval None
3742 */
SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef * hspi)3743 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3744 {
3745 __IO uint8_t *ptmpreg8;
3746 __IO uint8_t tmpreg8 = 0;
3747
3748 /* Initialize the 8bit temporary pointer */
3749 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3750 /* Read 8bit CRC to flush Data Register */
3751 tmpreg8 = *ptmpreg8;
3752 /* To avoid GCC warning */
3753 UNUSED(tmpreg8);
3754
3755 hspi->CRCSize--;
3756
3757 if (hspi->CRCSize == 0U)
3758 {
3759 SPI_CloseRx_ISR(hspi);
3760 }
3761 }
3762 #endif /* USE_SPI_CRC */
3763
3764 /**
3765 * @brief Manage the receive 8-bit in Interrupt context.
3766 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3767 * the configuration information for SPI module.
3768 * @retval None
3769 */
SPI_RxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3770 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3771 {
3772 *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
3773 hspi->pRxBuffPtr++;
3774 hspi->RxXferCount--;
3775
3776 #if (USE_SPI_CRC != 0U)
3777 /* Enable CRC Transmission */
3778 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3779 {
3780 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3781 }
3782 #endif /* USE_SPI_CRC */
3783
3784 if (hspi->RxXferCount == 0U)
3785 {
3786 #if (USE_SPI_CRC != 0U)
3787 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3788 {
3789 hspi->RxISR = SPI_RxISR_8BITCRC;
3790 return;
3791 }
3792 #endif /* USE_SPI_CRC */
3793 SPI_CloseRx_ISR(hspi);
3794 }
3795 }
3796
3797 #if (USE_SPI_CRC != 0U)
3798 /**
3799 * @brief Manage the CRC 16-bit receive in Interrupt context.
3800 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3801 * the configuration information for SPI module.
3802 * @retval None
3803 */
SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef * hspi)3804 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3805 {
3806 __IO uint32_t tmpreg = 0U;
3807
3808 /* Read 16bit CRC to flush Data Register */
3809 tmpreg = READ_REG(hspi->Instance->DR);
3810 /* To avoid GCC warning */
3811 UNUSED(tmpreg);
3812
3813 /* Disable RXNE and ERR interrupt */
3814 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3815
3816 SPI_CloseRx_ISR(hspi);
3817 }
3818 #endif /* USE_SPI_CRC */
3819
3820 /**
3821 * @brief Manage the 16-bit receive in Interrupt context.
3822 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3823 * the configuration information for SPI module.
3824 * @retval None
3825 */
SPI_RxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3826 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3827 {
3828 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3829 hspi->pRxBuffPtr += sizeof(uint16_t);
3830 hspi->RxXferCount--;
3831
3832 #if (USE_SPI_CRC != 0U)
3833 /* Enable CRC Transmission */
3834 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3835 {
3836 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3837 }
3838 #endif /* USE_SPI_CRC */
3839
3840 if (hspi->RxXferCount == 0U)
3841 {
3842 #if (USE_SPI_CRC != 0U)
3843 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3844 {
3845 hspi->RxISR = SPI_RxISR_16BITCRC;
3846 return;
3847 }
3848 #endif /* USE_SPI_CRC */
3849 SPI_CloseRx_ISR(hspi);
3850 }
3851 }
3852
3853 /**
3854 * @brief Handle the data 8-bit transmit in Interrupt mode.
3855 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3856 * the configuration information for SPI module.
3857 * @retval None
3858 */
SPI_TxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3859 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3860 {
3861 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3862 hspi->pTxBuffPtr++;
3863 hspi->TxXferCount--;
3864
3865 if (hspi->TxXferCount == 0U)
3866 {
3867 #if (USE_SPI_CRC != 0U)
3868 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3869 {
3870 /* Enable CRC Transmission */
3871 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3872 }
3873 #endif /* USE_SPI_CRC */
3874 SPI_CloseTx_ISR(hspi);
3875 }
3876 }
3877
3878 /**
3879 * @brief Handle the data 16-bit transmit in Interrupt mode.
3880 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3881 * the configuration information for SPI module.
3882 * @retval None
3883 */
SPI_TxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3884 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3885 {
3886 /* Transmit data in 16 Bit mode */
3887 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3888 hspi->pTxBuffPtr += sizeof(uint16_t);
3889 hspi->TxXferCount--;
3890
3891 if (hspi->TxXferCount == 0U)
3892 {
3893 #if (USE_SPI_CRC != 0U)
3894 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3895 {
3896 /* Enable CRC Transmission */
3897 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3898 }
3899 #endif /* USE_SPI_CRC */
3900 SPI_CloseTx_ISR(hspi);
3901 }
3902 }
3903
3904 /**
3905 * @brief Handle SPI Communication Timeout.
3906 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3907 * the configuration information for SPI module.
3908 * @param Flag SPI flag to check
3909 * @param State flag state to check
3910 * @param Timeout Timeout duration
3911 * @param Tickstart tick start value
3912 * @retval HAL status
3913 */
SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef * hspi,uint32_t Flag,FlagStatus State,uint32_t Timeout,uint32_t Tickstart)3914 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
3915 uint32_t Timeout, uint32_t Tickstart)
3916 {
3917 __IO uint32_t count;
3918 uint32_t tmp_timeout;
3919 uint32_t tmp_tickstart;
3920
3921 /* Adjust Timeout value in case of end of transfer */
3922 tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
3923 tmp_tickstart = HAL_GetTick();
3924
3925 /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
3926 count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
3927
3928 while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
3929 {
3930 if (Timeout != HAL_MAX_DELAY)
3931 {
3932 if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
3933 {
3934 /* Disable the SPI and reset the CRC: the CRC value should be cleared
3935 on both master and slave sides in order to resynchronize the master
3936 and slave for their respective CRC calculation */
3937
3938 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
3939 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
3940
3941 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3942 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3943 {
3944 /* Disable SPI peripheral */
3945 __HAL_SPI_DISABLE(hspi);
3946 }
3947
3948 /* Reset CRC Calculation */
3949 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3950 {
3951 SPI_RESET_CRC(hspi);
3952 }
3953
3954 hspi->State = HAL_SPI_STATE_READY;
3955
3956 /* Process Unlocked */
3957 __HAL_UNLOCK(hspi);
3958
3959 return HAL_TIMEOUT;
3960 }
3961 /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
3962 if (count == 0U)
3963 {
3964 tmp_timeout = 0U;
3965 }
3966 count--;
3967 }
3968 }
3969
3970 return HAL_OK;
3971 }
3972
3973 /**
3974 * @brief Handle SPI FIFO Communication Timeout.
3975 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3976 * the configuration information for SPI module.
3977 * @param Fifo Fifo to check
3978 * @param State Fifo state to check
3979 * @param Timeout Timeout duration
3980 * @param Tickstart tick start value
3981 * @retval HAL status
3982 */
SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef * hspi,uint32_t Fifo,uint32_t State,uint32_t Timeout,uint32_t Tickstart)3983 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
3984 uint32_t Timeout, uint32_t Tickstart)
3985 {
3986 __IO uint32_t count;
3987 uint32_t tmp_timeout;
3988 uint32_t tmp_tickstart;
3989 __IO uint8_t *ptmpreg8;
3990 __IO uint8_t tmpreg8 = 0;
3991
3992 /* Adjust Timeout value in case of end of transfer */
3993 tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
3994 tmp_tickstart = HAL_GetTick();
3995
3996 /* Initialize the 8bit temporary pointer */
3997 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3998
3999 /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
4000 count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U);
4001
4002 while ((hspi->Instance->SR & Fifo) != State)
4003 {
4004 if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
4005 {
4006 /* Flush Data Register by a blank read */
4007 tmpreg8 = *ptmpreg8;
4008 /* To avoid GCC warning */
4009 UNUSED(tmpreg8);
4010 }
4011
4012 if (Timeout != HAL_MAX_DELAY)
4013 {
4014 if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
4015 {
4016 /* Disable the SPI and reset the CRC: the CRC value should be cleared
4017 on both master and slave sides in order to resynchronize the master
4018 and slave for their respective CRC calculation */
4019
4020 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
4021 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
4022
4023 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
4024 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
4025 {
4026 /* Disable SPI peripheral */
4027 __HAL_SPI_DISABLE(hspi);
4028 }
4029
4030 /* Reset CRC Calculation */
4031 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
4032 {
4033 SPI_RESET_CRC(hspi);
4034 }
4035
4036 hspi->State = HAL_SPI_STATE_READY;
4037
4038 /* Process Unlocked */
4039 __HAL_UNLOCK(hspi);
4040
4041 return HAL_TIMEOUT;
4042 }
4043 /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
4044 if (count == 0U)
4045 {
4046 tmp_timeout = 0U;
4047 }
4048 count--;
4049 }
4050 }
4051
4052 return HAL_OK;
4053 }
4054
4055 /**
4056 * @brief Handle the check of the RX transaction complete.
4057 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4058 * the configuration information for SPI module.
4059 * @param Timeout Timeout duration
4060 * @param Tickstart tick start value
4061 * @retval HAL status
4062 */
SPI_EndRxTransaction(SPI_HandleTypeDef * hspi,uint32_t Timeout,uint32_t Tickstart)4063 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
4064 {
4065 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
4066 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
4067 {
4068 /* Disable SPI peripheral */
4069 __HAL_SPI_DISABLE(hspi);
4070 }
4071
4072 /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */
4073 if (hspi->Init.Mode == SPI_MODE_MASTER)
4074 {
4075 /* Control the BSY flag */
4076 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
4077 {
4078 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4079 return HAL_TIMEOUT;
4080 }
4081 }
4082 else /* SPI_MODE_SLAVE */
4083 {
4084 /* Timeout in µs */
4085 __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U);
4086
4087 /* Wait BSY flag during 1 Byte time transfer in case of Rx transfer
4088 * If Timeout is reached, the transfer is considered as finish.
4089 * User have to calculate the timeout value to fit with the time of 1 byte transfer.
4090 * This time is directly link with the SPI clock from Master device.
4091 */
4092 do
4093 {
4094 if (count == 0U)
4095 {
4096 break;
4097 }
4098 count--;
4099 } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET);
4100 }
4101
4102 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
4103 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
4104 {
4105 /* Empty the FRLVL fifo */
4106 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
4107 {
4108 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4109 return HAL_TIMEOUT;
4110 }
4111 }
4112 return HAL_OK;
4113 }
4114
4115 /**
4116 * @brief Handle the check of the RXTX or TX transaction complete.
4117 * @param hspi SPI handle
4118 * @param Timeout Timeout duration
4119 * @param Tickstart tick start value
4120 * @retval HAL status
4121 */
SPI_EndRxTxTransaction(SPI_HandleTypeDef * hspi,uint32_t Timeout,uint32_t Tickstart)4122 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
4123 {
4124 /* Control if the TX fifo is empty */
4125 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
4126 {
4127 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4128 return HAL_TIMEOUT;
4129 }
4130
4131 /* Timeout in µs */
4132 __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U);
4133 /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */
4134 if (hspi->Init.Mode == SPI_MODE_MASTER)
4135 {
4136 /* Control the BSY flag */
4137 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
4138 {
4139 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4140 return HAL_TIMEOUT;
4141 }
4142 }
4143 else
4144 {
4145 /* Wait BSY flag during 1 Byte time transfer in case of Full-Duplex and Tx transfer
4146 * If Timeout is reached, the transfer is considered as finish.
4147 * User have to calculate the timeout value to fit with the time of 1 byte transfer.
4148 * This time is directly link with the SPI clock from Master device.
4149 */
4150 do
4151 {
4152 if (count == 0U)
4153 {
4154 break;
4155 }
4156 count--;
4157 } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET);
4158 }
4159
4160
4161 /* Control if the RX fifo is empty */
4162 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
4163 {
4164 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4165 return HAL_TIMEOUT;
4166 }
4167
4168 return HAL_OK;
4169 }
4170
4171 /**
4172 * @brief Handle the end of the RXTX transaction.
4173 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4174 * the configuration information for SPI module.
4175 * @retval None
4176 */
SPI_CloseRxTx_ISR(SPI_HandleTypeDef * hspi)4177 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
4178 {
4179 uint32_t tickstart;
4180
4181 /* Init tickstart for timeout management */
4182 tickstart = HAL_GetTick();
4183
4184 /* Disable ERR interrupt */
4185 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
4186
4187 /* Check the end of the transaction */
4188 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
4189 {
4190 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4191 }
4192
4193 #if (USE_SPI_CRC != 0U)
4194 /* Check if CRC error occurred */
4195 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
4196 {
4197 hspi->State = HAL_SPI_STATE_READY;
4198 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
4199 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
4200 /* Call user error callback */
4201 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4202 hspi->ErrorCallback(hspi);
4203 #else
4204 HAL_SPI_ErrorCallback(hspi);
4205 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4206 }
4207 else
4208 {
4209 #endif /* USE_SPI_CRC */
4210 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
4211 {
4212 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
4213 {
4214 hspi->State = HAL_SPI_STATE_READY;
4215 /* Call user Rx complete callback */
4216 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4217 hspi->RxCpltCallback(hspi);
4218 #else
4219 HAL_SPI_RxCpltCallback(hspi);
4220 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4221 }
4222 else
4223 {
4224 hspi->State = HAL_SPI_STATE_READY;
4225 /* Call user TxRx complete callback */
4226 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4227 hspi->TxRxCpltCallback(hspi);
4228 #else
4229 HAL_SPI_TxRxCpltCallback(hspi);
4230 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4231 }
4232 }
4233 else
4234 {
4235 hspi->State = HAL_SPI_STATE_READY;
4236 /* Call user error callback */
4237 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4238 hspi->ErrorCallback(hspi);
4239 #else
4240 HAL_SPI_ErrorCallback(hspi);
4241 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4242 }
4243 #if (USE_SPI_CRC != 0U)
4244 }
4245 #endif /* USE_SPI_CRC */
4246 }
4247
4248 /**
4249 * @brief Handle the end of the RX transaction.
4250 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4251 * the configuration information for SPI module.
4252 * @retval None
4253 */
SPI_CloseRx_ISR(SPI_HandleTypeDef * hspi)4254 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
4255 {
4256 /* Disable RXNE and ERR interrupt */
4257 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
4258
4259 /* Check the end of the transaction */
4260 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4261 {
4262 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4263 }
4264 hspi->State = HAL_SPI_STATE_READY;
4265
4266 #if (USE_SPI_CRC != 0U)
4267 /* Check if CRC error occurred */
4268 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
4269 {
4270 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
4271 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
4272 /* Call user error callback */
4273 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4274 hspi->ErrorCallback(hspi);
4275 #else
4276 HAL_SPI_ErrorCallback(hspi);
4277 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4278 }
4279 else
4280 {
4281 #endif /* USE_SPI_CRC */
4282 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
4283 {
4284 /* Call user Rx complete callback */
4285 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4286 hspi->RxCpltCallback(hspi);
4287 #else
4288 HAL_SPI_RxCpltCallback(hspi);
4289 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4290 }
4291 else
4292 {
4293 /* Call user error callback */
4294 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4295 hspi->ErrorCallback(hspi);
4296 #else
4297 HAL_SPI_ErrorCallback(hspi);
4298 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4299 }
4300 #if (USE_SPI_CRC != 0U)
4301 }
4302 #endif /* USE_SPI_CRC */
4303 }
4304
4305 /**
4306 * @brief Handle the end of the TX transaction.
4307 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4308 * the configuration information for SPI module.
4309 * @retval None
4310 */
SPI_CloseTx_ISR(SPI_HandleTypeDef * hspi)4311 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
4312 {
4313 uint32_t tickstart;
4314
4315 /* Init tickstart for timeout management*/
4316 tickstart = HAL_GetTick();
4317
4318 /* Disable TXE and ERR interrupt */
4319 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
4320
4321 /* Check the end of the transaction */
4322 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
4323 {
4324 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4325 }
4326
4327 /* Clear overrun flag in 2 Lines communication mode because received is not read */
4328 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
4329 {
4330 __HAL_SPI_CLEAR_OVRFLAG(hspi);
4331 }
4332
4333 hspi->State = HAL_SPI_STATE_READY;
4334 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
4335 {
4336 /* Call user error callback */
4337 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4338 hspi->ErrorCallback(hspi);
4339 #else
4340 HAL_SPI_ErrorCallback(hspi);
4341 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4342 }
4343 else
4344 {
4345 /* Call user Rx complete callback */
4346 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4347 hspi->TxCpltCallback(hspi);
4348 #else
4349 HAL_SPI_TxCpltCallback(hspi);
4350 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4351 }
4352 }
4353
4354 /**
4355 * @brief Handle abort a Rx transaction.
4356 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4357 * the configuration information for SPI module.
4358 * @retval None
4359 */
SPI_AbortRx_ISR(SPI_HandleTypeDef * hspi)4360 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
4361 {
4362 __IO uint32_t count;
4363
4364 /* Disable SPI Peripheral */
4365 __HAL_SPI_DISABLE(hspi);
4366
4367 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
4368
4369 /* Disable RXNEIE interrupt */
4370 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
4371
4372 /* Check RXNEIE is disabled */
4373 do
4374 {
4375 if (count == 0U)
4376 {
4377 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4378 break;
4379 }
4380 count--;
4381 } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
4382
4383 /* Control the BSY flag */
4384 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4385 {
4386 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4387 }
4388
4389 /* Empty the FRLVL fifo */
4390 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4391 {
4392 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4393 }
4394
4395 hspi->State = HAL_SPI_STATE_ABORT;
4396 }
4397
4398 /**
4399 * @brief Handle abort a Tx or Rx/Tx transaction.
4400 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4401 * the configuration information for SPI module.
4402 * @retval None
4403 */
SPI_AbortTx_ISR(SPI_HandleTypeDef * hspi)4404 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
4405 {
4406 __IO uint32_t count;
4407
4408 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
4409
4410 /* Disable TXEIE interrupt */
4411 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
4412
4413 /* Check TXEIE is disabled */
4414 do
4415 {
4416 if (count == 0U)
4417 {
4418 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4419 break;
4420 }
4421 count--;
4422 } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
4423
4424 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4425 {
4426 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4427 }
4428
4429 /* Disable SPI Peripheral */
4430 __HAL_SPI_DISABLE(hspi);
4431
4432 /* Empty the FRLVL fifo */
4433 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4434 {
4435 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4436 }
4437
4438 /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */
4439 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
4440 {
4441 /* Disable RXNEIE interrupt */
4442 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
4443
4444 /* Check RXNEIE is disabled */
4445 do
4446 {
4447 if (count == 0U)
4448 {
4449 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4450 break;
4451 }
4452 count--;
4453 } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
4454
4455 /* Control the BSY flag */
4456 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4457 {
4458 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4459 }
4460
4461 /* Empty the FRLVL fifo */
4462 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4463 {
4464 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4465 }
4466 }
4467 hspi->State = HAL_SPI_STATE_ABORT;
4468 }
4469
4470 /**
4471 * @}
4472 */
4473
4474 #endif /* HAL_SPI_MODULE_ENABLED */
4475
4476 /**
4477 * @}
4478 */
4479
4480 /**
4481 * @}
4482 */
4483
4484
