1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_sdram.c
4 * @author MCD Application Team
5 * @brief SDRAM HAL module driver.
6 * This file provides a generic firmware to drive SDRAM memories mounted
7 * as external device.
8 *
9 ******************************************************************************
10 * @attention
11 *
12 * Copyright (c) 2017 STMicroelectronics.
13 * All rights reserved.
14 *
15 * This software is licensed under terms that can be found in the LICENSE file
16 * in the root directory of this software component.
17 * If no LICENSE file comes with this software, it is provided AS-IS.
18 *
19 ******************************************************************************
20 @verbatim
21 ==============================================================================
22 ##### How to use this driver #####
23 ==============================================================================
24 [..]
25 This driver is a generic layered driver which contains a set of APIs used to
26 control SDRAM memories. It uses the FMC layer functions to interface
27 with SDRAM devices.
28 The following sequence should be followed to configure the FMC to interface
29 with SDRAM memories:
30
31 (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
32 SDRAM_HandleTypeDef hsdram
33
34 (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
35 values of the structure member.
36
37 (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
38 base register instance for NOR or SDRAM device
39
40 (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
41 FMC_SDRAM_TimingTypeDef Timing;
42 and fill its fields with the allowed values of the structure member.
43
44 (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
45 performs the following sequence:
46
47 (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
48 (##) Control register configuration using the FMC SDRAM interface function
49 FMC_SDRAM_Init()
50 (##) Timing register configuration using the FMC SDRAM interface function
51 FMC_SDRAM_Timing_Init()
52 (##) Program the SDRAM external device by applying its initialization sequence
53 according to the device plugged in your hardware. This step is mandatory
54 for accessing the SDRAM device.
55
56 (#) At this stage you can perform read/write accesses from/to the memory connected
57 to the SDRAM Bank. You can perform either polling or DMA transfer using the
58 following APIs:
59 (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
60 (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
61
62 (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
63 HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
64 the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
65 device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
66 structure.
67
68 (#) You can continuously monitor the SDRAM device HAL state by calling the function
69 HAL_SDRAM_GetState()
70
71 *** Callback registration ***
72 =============================================
73 [..]
74 The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS when set to 1
75 allows the user to configure dynamically the driver callbacks.
76
77 Use Functions HAL_SDRAM_RegisterCallback() to register a user callback,
78 it allows to register following callbacks:
79 (+) MspInitCallback : SDRAM MspInit.
80 (+) MspDeInitCallback : SDRAM MspDeInit.
81 This function takes as parameters the HAL peripheral handle, the Callback ID
82 and a pointer to the user callback function.
83
84 Use function HAL_SDRAM_UnRegisterCallback() to reset a callback to the default
85 weak (surcharged) function. It allows to reset following callbacks:
86 (+) MspInitCallback : SDRAM MspInit.
87 (+) MspDeInitCallback : SDRAM MspDeInit.
88 This function) takes as parameters the HAL peripheral handle and the Callback ID.
89
90 By default, after the HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET
91 all callbacks are reset to the corresponding legacy weak (surcharged) functions.
92 Exception done for MspInit and MspDeInit callbacks that are respectively
93 reset to the legacy weak (surcharged) functions in the HAL_SDRAM_Init
94 and HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand).
95 If not, MspInit or MspDeInit are not null, the HAL_SDRAM_Init and HAL_SDRAM_DeInit
96 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
97
98 Callbacks can be registered/unregistered in READY state only.
99 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
100 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
101 during the Init/DeInit.
102 In that case first register the MspInit/MspDeInit user callbacks
103 using HAL_SDRAM_RegisterCallback before calling HAL_SDRAM_DeInit
104 or HAL_SDRAM_Init function.
105
106 When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or
107 not defined, the callback registering feature is not available
108 and weak (surcharged) callbacks are used.
109
110 @endverbatim
111 ******************************************************************************
112 */
113
114 /* Includes ------------------------------------------------------------------*/
115 #include "stm32f7xx_hal.h"
116
117
118 /** @addtogroup STM32F7xx_HAL_Driver
119 * @{
120 */
121
122 #ifdef HAL_SDRAM_MODULE_ENABLED
123
124 /** @defgroup SDRAM SDRAM
125 * @brief SDRAM driver modules
126 * @{
127 */
128
129 /* Private typedef -----------------------------------------------------------*/
130 /* Private define ------------------------------------------------------------*/
131 /* Private macro -------------------------------------------------------------*/
132 /* Private variables ---------------------------------------------------------*/
133 /* Private function prototypes -----------------------------------------------*/
134 static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma);
135 static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
136 static void SDRAM_DMAError(DMA_HandleTypeDef *hdma);
137
138 /* Exported functions --------------------------------------------------------*/
139 /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
140 * @{
141 */
142
143 /** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions
144 * @brief Initialization and Configuration functions
145 *
146 @verbatim
147 ==============================================================================
148 ##### SDRAM Initialization and de_initialization functions #####
149 ==============================================================================
150 [..]
151 This section provides functions allowing to initialize/de-initialize
152 the SDRAM memory
153
154 @endverbatim
155 * @{
156 */
157
158 /**
159 * @brief Performs the SDRAM device initialization sequence.
160 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
161 * the configuration information for SDRAM module.
162 * @param Timing Pointer to SDRAM control timing structure
163 * @retval HAL status
164 */
HAL_SDRAM_Init(SDRAM_HandleTypeDef * hsdram,FMC_SDRAM_TimingTypeDef * Timing)165 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
166 {
167 /* Check the SDRAM handle parameter */
168 if (hsdram == NULL)
169 {
170 return HAL_ERROR;
171 }
172
173 if (hsdram->State == HAL_SDRAM_STATE_RESET)
174 {
175 /* Allocate lock resource and initialize it */
176 hsdram->Lock = HAL_UNLOCKED;
177 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
178 if (hsdram->MspInitCallback == NULL)
179 {
180 hsdram->MspInitCallback = HAL_SDRAM_MspInit;
181 }
182 hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
183 hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
184 hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
185
186 /* Init the low level hardware */
187 hsdram->MspInitCallback(hsdram);
188 #else
189 /* Initialize the low level hardware (MSP) */
190 HAL_SDRAM_MspInit(hsdram);
191 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
192 }
193
194 /* Initialize the SDRAM controller state */
195 hsdram->State = HAL_SDRAM_STATE_BUSY;
196
197 /* Initialize SDRAM control Interface */
198 (void)FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
199
200 /* Initialize SDRAM timing Interface */
201 (void)FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
202 /* Update the SDRAM controller state */
203 hsdram->State = HAL_SDRAM_STATE_READY;
204
205 return HAL_OK;
206 }
207
208 /**
209 * @brief Perform the SDRAM device initialization sequence.
210 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
211 * the configuration information for SDRAM module.
212 * @retval HAL status
213 */
HAL_SDRAM_DeInit(SDRAM_HandleTypeDef * hsdram)214 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
215 {
216 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
217 if (hsdram->MspDeInitCallback == NULL)
218 {
219 hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
220 }
221
222 /* DeInit the low level hardware */
223 hsdram->MspDeInitCallback(hsdram);
224 #else
225 /* Initialize the low level hardware (MSP) */
226 HAL_SDRAM_MspDeInit(hsdram);
227 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
228
229 /* Configure the SDRAM registers with their reset values */
230 (void)FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
231
232 /* Reset the SDRAM controller state */
233 hsdram->State = HAL_SDRAM_STATE_RESET;
234
235 /* Release Lock */
236 __HAL_UNLOCK(hsdram);
237
238 return HAL_OK;
239 }
240
241 /**
242 * @brief SDRAM MSP Init.
243 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
244 * the configuration information for SDRAM module.
245 * @retval None
246 */
HAL_SDRAM_MspInit(SDRAM_HandleTypeDef * hsdram)247 __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
248 {
249 /* Prevent unused argument(s) compilation warning */
250 UNUSED(hsdram);
251
252 /* NOTE: This function Should not be modified, when the callback is needed,
253 the HAL_SDRAM_MspInit could be implemented in the user file
254 */
255 }
256
257 /**
258 * @brief SDRAM MSP DeInit.
259 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
260 * the configuration information for SDRAM module.
261 * @retval None
262 */
HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef * hsdram)263 __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
264 {
265 /* Prevent unused argument(s) compilation warning */
266 UNUSED(hsdram);
267
268 /* NOTE: This function Should not be modified, when the callback is needed,
269 the HAL_SDRAM_MspDeInit could be implemented in the user file
270 */
271 }
272
273 /**
274 * @brief This function handles SDRAM refresh error interrupt request.
275 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
276 * the configuration information for SDRAM module.
277 * @retval HAL status
278 */
HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef * hsdram)279 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
280 {
281 /* Check SDRAM interrupt Rising edge flag */
282 if (__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
283 {
284 /* SDRAM refresh error interrupt callback */
285 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
286 hsdram->RefreshErrorCallback(hsdram);
287 #else
288 HAL_SDRAM_RefreshErrorCallback(hsdram);
289 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
290
291 /* Clear SDRAM refresh error interrupt pending bit */
292 __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
293 }
294 }
295
296 /**
297 * @brief SDRAM Refresh error callback.
298 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
299 * the configuration information for SDRAM module.
300 * @retval None
301 */
HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef * hsdram)302 __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
303 {
304 /* Prevent unused argument(s) compilation warning */
305 UNUSED(hsdram);
306
307 /* NOTE: This function Should not be modified, when the callback is needed,
308 the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
309 */
310 }
311
312 /**
313 * @brief DMA transfer complete callback.
314 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
315 * the configuration information for the specified DMA module.
316 * @retval None
317 */
HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef * hdma)318 __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
319 {
320 /* Prevent unused argument(s) compilation warning */
321 UNUSED(hdma);
322
323 /* NOTE: This function Should not be modified, when the callback is needed,
324 the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
325 */
326 }
327
328 /**
329 * @brief DMA transfer complete error callback.
330 * @param hdma DMA handle
331 * @retval None
332 */
HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef * hdma)333 __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
334 {
335 /* Prevent unused argument(s) compilation warning */
336 UNUSED(hdma);
337
338 /* NOTE: This function Should not be modified, when the callback is needed,
339 the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
340 */
341 }
342
343 /**
344 * @}
345 */
346
347 /** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions
348 * @brief Input Output and memory control functions
349 *
350 @verbatim
351 ==============================================================================
352 ##### SDRAM Input and Output functions #####
353 ==============================================================================
354 [..]
355 This section provides functions allowing to use and control the SDRAM memory
356
357 @endverbatim
358 * @{
359 */
360
361 /**
362 * @brief Reads 8-bit data buffer from the SDRAM memory.
363 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
364 * the configuration information for SDRAM module.
365 * @param pAddress Pointer to read start address
366 * @param pDstBuffer Pointer to destination buffer
367 * @param BufferSize Size of the buffer to read from memory
368 * @retval HAL status
369 */
HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint8_t * pDstBuffer,uint32_t BufferSize)370 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer,
371 uint32_t BufferSize)
372 {
373 uint32_t size;
374 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
375 uint8_t *pdestbuff = pDstBuffer;
376 HAL_SDRAM_StateTypeDef state = hsdram->State;
377
378 /* Check the SDRAM controller state */
379 if (state == HAL_SDRAM_STATE_BUSY)
380 {
381 return HAL_BUSY;
382 }
383 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
384 {
385 /* Process Locked */
386 __HAL_LOCK(hsdram);
387
388 /* Update the SDRAM controller state */
389 hsdram->State = HAL_SDRAM_STATE_BUSY;
390
391 /* Read data from source */
392 for (size = BufferSize; size != 0U; size--)
393 {
394 *pdestbuff = *(__IO uint8_t *)pSdramAddress;
395 pdestbuff++;
396 pSdramAddress++;
397 }
398
399 /* Update the SDRAM controller state */
400 hsdram->State = state;
401
402 /* Process Unlocked */
403 __HAL_UNLOCK(hsdram);
404 }
405 else
406 {
407 return HAL_ERROR;
408 }
409
410 return HAL_OK;
411 }
412
413 /**
414 * @brief Writes 8-bit data buffer to SDRAM memory.
415 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
416 * the configuration information for SDRAM module.
417 * @param pAddress Pointer to write start address
418 * @param pSrcBuffer Pointer to source buffer to write
419 * @param BufferSize Size of the buffer to write to memory
420 * @retval HAL status
421 */
HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint8_t * pSrcBuffer,uint32_t BufferSize)422 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer,
423 uint32_t BufferSize)
424 {
425 uint32_t size;
426 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
427 uint8_t *psrcbuff = pSrcBuffer;
428
429 /* Check the SDRAM controller state */
430 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
431 {
432 return HAL_BUSY;
433 }
434 else if (hsdram->State == HAL_SDRAM_STATE_READY)
435 {
436 /* Process Locked */
437 __HAL_LOCK(hsdram);
438
439 /* Update the SDRAM controller state */
440 hsdram->State = HAL_SDRAM_STATE_BUSY;
441
442 /* Write data to memory */
443 for (size = BufferSize; size != 0U; size--)
444 {
445 *(__IO uint8_t *)pSdramAddress = *psrcbuff;
446 psrcbuff++;
447 pSdramAddress++;
448 }
449
450 /* Update the SDRAM controller state */
451 hsdram->State = HAL_SDRAM_STATE_READY;
452
453 /* Process Unlocked */
454 __HAL_UNLOCK(hsdram);
455 }
456 else
457 {
458 return HAL_ERROR;
459 }
460
461 return HAL_OK;
462 }
463
464 /**
465 * @brief Reads 16-bit data buffer from the SDRAM memory.
466 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
467 * the configuration information for SDRAM module.
468 * @param pAddress Pointer to read start address
469 * @param pDstBuffer Pointer to destination buffer
470 * @param BufferSize Size of the buffer to read from memory
471 * @retval HAL status
472 */
HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint16_t * pDstBuffer,uint32_t BufferSize)473 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer,
474 uint32_t BufferSize)
475 {
476 uint32_t size;
477 __IO uint32_t *pSdramAddress = pAddress;
478 uint16_t *pdestbuff = pDstBuffer;
479 HAL_SDRAM_StateTypeDef state = hsdram->State;
480
481 /* Check the SDRAM controller state */
482 if (state == HAL_SDRAM_STATE_BUSY)
483 {
484 return HAL_BUSY;
485 }
486 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
487 {
488 /* Process Locked */
489 __HAL_LOCK(hsdram);
490
491 /* Update the SDRAM controller state */
492 hsdram->State = HAL_SDRAM_STATE_BUSY;
493
494 /* Read data from memory */
495 for (size = BufferSize; size >= 2U ; size -= 2U)
496 {
497 *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU);
498 pdestbuff++;
499 *pdestbuff = (uint16_t)(((*pSdramAddress) & 0xFFFF0000U) >> 16U);
500 pdestbuff++;
501 pSdramAddress++;
502 }
503
504 /* Read last 16-bits if size is not 32-bits multiple */
505 if ((BufferSize % 2U) != 0U)
506 {
507 *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU);
508 }
509
510 /* Update the SDRAM controller state */
511 hsdram->State = state;
512
513 /* Process Unlocked */
514 __HAL_UNLOCK(hsdram);
515 }
516 else
517 {
518 return HAL_ERROR;
519 }
520
521 return HAL_OK;
522 }
523
524 /**
525 * @brief Writes 16-bit data buffer to SDRAM memory.
526 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
527 * the configuration information for SDRAM module.
528 * @param pAddress Pointer to write start address
529 * @param pSrcBuffer Pointer to source buffer to write
530 * @param BufferSize Size of the buffer to write to memory
531 * @retval HAL status
532 */
HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint16_t * pSrcBuffer,uint32_t BufferSize)533 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer,
534 uint32_t BufferSize)
535 {
536 uint32_t size;
537 __IO uint32_t *psdramaddress = pAddress;
538 uint16_t *psrcbuff = pSrcBuffer;
539
540 /* Check the SDRAM controller state */
541 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
542 {
543 return HAL_BUSY;
544 }
545 else if (hsdram->State == HAL_SDRAM_STATE_READY)
546 {
547 /* Process Locked */
548 __HAL_LOCK(hsdram);
549
550 /* Update the SDRAM controller state */
551 hsdram->State = HAL_SDRAM_STATE_BUSY;
552
553 /* Write data to memory */
554 for (size = BufferSize; size >= 2U ; size -= 2U)
555 {
556 *psdramaddress = (uint32_t)(*psrcbuff);
557 psrcbuff++;
558 *psdramaddress |= ((uint32_t)(*psrcbuff) << 16U);
559 psrcbuff++;
560 psdramaddress++;
561 }
562
563 /* Write last 16-bits if size is not 32-bits multiple */
564 if ((BufferSize % 2U) != 0U)
565 {
566 *psdramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psdramaddress) & 0xFFFF0000U);
567 }
568
569 /* Update the SDRAM controller state */
570 hsdram->State = HAL_SDRAM_STATE_READY;
571
572 /* Process Unlocked */
573 __HAL_UNLOCK(hsdram);
574 }
575 else
576 {
577 return HAL_ERROR;
578 }
579
580 return HAL_OK;
581 }
582
583 /**
584 * @brief Reads 32-bit data buffer from the SDRAM memory.
585 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
586 * the configuration information for SDRAM module.
587 * @param pAddress Pointer to read start address
588 * @param pDstBuffer Pointer to destination buffer
589 * @param BufferSize Size of the buffer to read from memory
590 * @retval HAL status
591 */
HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)592 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
593 uint32_t BufferSize)
594 {
595 uint32_t size;
596 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
597 uint32_t *pdestbuff = pDstBuffer;
598 HAL_SDRAM_StateTypeDef state = hsdram->State;
599
600 /* Check the SDRAM controller state */
601 if (state == HAL_SDRAM_STATE_BUSY)
602 {
603 return HAL_BUSY;
604 }
605 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
606 {
607 /* Process Locked */
608 __HAL_LOCK(hsdram);
609
610 /* Update the SDRAM controller state */
611 hsdram->State = HAL_SDRAM_STATE_BUSY;
612
613 /* Read data from source */
614 for (size = BufferSize; size != 0U; size--)
615 {
616 *pdestbuff = *(__IO uint32_t *)pSdramAddress;
617 pdestbuff++;
618 pSdramAddress++;
619 }
620
621 /* Update the SDRAM controller state */
622 hsdram->State = state;
623
624 /* Process Unlocked */
625 __HAL_UNLOCK(hsdram);
626 }
627 else
628 {
629 return HAL_ERROR;
630 }
631
632 return HAL_OK;
633 }
634
635 /**
636 * @brief Writes 32-bit data buffer to SDRAM memory.
637 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
638 * the configuration information for SDRAM module.
639 * @param pAddress Pointer to write start address
640 * @param pSrcBuffer Pointer to source buffer to write
641 * @param BufferSize Size of the buffer to write to memory
642 * @retval HAL status
643 */
HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)644 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
645 uint32_t BufferSize)
646 {
647 uint32_t size;
648 __IO uint32_t *pSdramAddress = pAddress;
649 uint32_t *psrcbuff = pSrcBuffer;
650
651 /* Check the SDRAM controller state */
652 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
653 {
654 return HAL_BUSY;
655 }
656 else if (hsdram->State == HAL_SDRAM_STATE_READY)
657 {
658 /* Process Locked */
659 __HAL_LOCK(hsdram);
660
661 /* Update the SDRAM controller state */
662 hsdram->State = HAL_SDRAM_STATE_BUSY;
663
664 /* Write data to memory */
665 for (size = BufferSize; size != 0U; size--)
666 {
667 *pSdramAddress = *psrcbuff;
668 psrcbuff++;
669 pSdramAddress++;
670 }
671
672 /* Update the SDRAM controller state */
673 hsdram->State = HAL_SDRAM_STATE_READY;
674
675 /* Process Unlocked */
676 __HAL_UNLOCK(hsdram);
677 }
678 else
679 {
680 return HAL_ERROR;
681 }
682
683 return HAL_OK;
684 }
685
686 /**
687 * @brief Reads a Words data from the SDRAM memory using DMA transfer.
688 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
689 * the configuration information for SDRAM module.
690 * @param pAddress Pointer to read start address
691 * @param pDstBuffer Pointer to destination buffer
692 * @param BufferSize Size of the buffer to read from memory
693 * @retval HAL status
694 */
HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)695 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
696 uint32_t BufferSize)
697 {
698 HAL_StatusTypeDef status;
699 HAL_SDRAM_StateTypeDef state = hsdram->State;
700
701 /* Check the SDRAM controller state */
702 if (state == HAL_SDRAM_STATE_BUSY)
703 {
704 status = HAL_BUSY;
705 }
706 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
707 {
708 /* Process Locked */
709 __HAL_LOCK(hsdram);
710
711 /* Update the SDRAM controller state */
712 hsdram->State = HAL_SDRAM_STATE_BUSY;
713
714 /* Configure DMA user callbacks */
715 if (state == HAL_SDRAM_STATE_READY)
716 {
717 hsdram->hdma->XferCpltCallback = SDRAM_DMACplt;
718 }
719 else
720 {
721 hsdram->hdma->XferCpltCallback = SDRAM_DMACpltProt;
722 }
723 hsdram->hdma->XferErrorCallback = SDRAM_DMAError;
724
725 /* Enable the DMA Stream */
726 status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
727
728 /* Process Unlocked */
729 __HAL_UNLOCK(hsdram);
730 }
731 else
732 {
733 status = HAL_ERROR;
734 }
735
736 return status;
737 }
738
739 /**
740 * @brief Writes a Words data buffer to SDRAM memory using DMA transfer.
741 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
742 * the configuration information for SDRAM module.
743 * @param pAddress Pointer to write start address
744 * @param pSrcBuffer Pointer to source buffer to write
745 * @param BufferSize Size of the buffer to write to memory
746 * @retval HAL status
747 */
HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)748 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
749 uint32_t BufferSize)
750 {
751 HAL_StatusTypeDef status;
752
753 /* Check the SDRAM controller state */
754 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
755 {
756 status = HAL_BUSY;
757 }
758 else if (hsdram->State == HAL_SDRAM_STATE_READY)
759 {
760 /* Process Locked */
761 __HAL_LOCK(hsdram);
762
763 /* Update the SDRAM controller state */
764 hsdram->State = HAL_SDRAM_STATE_BUSY;
765
766 /* Configure DMA user callbacks */
767 hsdram->hdma->XferCpltCallback = SDRAM_DMACplt;
768 hsdram->hdma->XferErrorCallback = SDRAM_DMAError;
769
770 /* Enable the DMA Stream */
771 status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
772
773 /* Process Unlocked */
774 __HAL_UNLOCK(hsdram);
775 }
776 else
777 {
778 status = HAL_ERROR;
779 }
780
781 return status;
782 }
783
784 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
785 /**
786 * @brief Register a User SDRAM Callback
787 * To be used instead of the weak (surcharged) predefined callback
788 * @param hsdram : SDRAM handle
789 * @param CallbackId : ID of the callback to be registered
790 * This parameter can be one of the following values:
791 * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID
792 * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID
793 * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID
794 * @param pCallback : pointer to the Callback function
795 * @retval status
796 */
HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef * hsdram,HAL_SDRAM_CallbackIDTypeDef CallbackId,pSDRAM_CallbackTypeDef pCallback)797 HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
798 pSDRAM_CallbackTypeDef pCallback)
799 {
800 HAL_StatusTypeDef status = HAL_OK;
801 HAL_SDRAM_StateTypeDef state;
802
803 if (pCallback == NULL)
804 {
805 return HAL_ERROR;
806 }
807
808 /* Process locked */
809 __HAL_LOCK(hsdram);
810
811 state = hsdram->State;
812 if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
813 {
814 switch (CallbackId)
815 {
816 case HAL_SDRAM_MSP_INIT_CB_ID :
817 hsdram->MspInitCallback = pCallback;
818 break;
819 case HAL_SDRAM_MSP_DEINIT_CB_ID :
820 hsdram->MspDeInitCallback = pCallback;
821 break;
822 case HAL_SDRAM_REFRESH_ERR_CB_ID :
823 hsdram->RefreshErrorCallback = pCallback;
824 break;
825 default :
826 /* update return status */
827 status = HAL_ERROR;
828 break;
829 }
830 }
831 else if (hsdram->State == HAL_SDRAM_STATE_RESET)
832 {
833 switch (CallbackId)
834 {
835 case HAL_SDRAM_MSP_INIT_CB_ID :
836 hsdram->MspInitCallback = pCallback;
837 break;
838 case HAL_SDRAM_MSP_DEINIT_CB_ID :
839 hsdram->MspDeInitCallback = pCallback;
840 break;
841 default :
842 /* update return status */
843 status = HAL_ERROR;
844 break;
845 }
846 }
847 else
848 {
849 /* update return status */
850 status = HAL_ERROR;
851 }
852
853 /* Release Lock */
854 __HAL_UNLOCK(hsdram);
855 return status;
856 }
857
858 /**
859 * @brief Unregister a User SDRAM Callback
860 * SDRAM Callback is redirected to the weak (surcharged) predefined callback
861 * @param hsdram : SDRAM handle
862 * @param CallbackId : ID of the callback to be unregistered
863 * This parameter can be one of the following values:
864 * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID
865 * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID
866 * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID
867 * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID
868 * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID
869 * @retval status
870 */
HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef * hsdram,HAL_SDRAM_CallbackIDTypeDef CallbackId)871 HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId)
872 {
873 HAL_StatusTypeDef status = HAL_OK;
874 HAL_SDRAM_StateTypeDef state;
875
876 /* Process locked */
877 __HAL_LOCK(hsdram);
878
879 state = hsdram->State;
880 if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
881 {
882 switch (CallbackId)
883 {
884 case HAL_SDRAM_MSP_INIT_CB_ID :
885 hsdram->MspInitCallback = HAL_SDRAM_MspInit;
886 break;
887 case HAL_SDRAM_MSP_DEINIT_CB_ID :
888 hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
889 break;
890 case HAL_SDRAM_REFRESH_ERR_CB_ID :
891 hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
892 break;
893 case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
894 hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
895 break;
896 case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
897 hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
898 break;
899 default :
900 /* update return status */
901 status = HAL_ERROR;
902 break;
903 }
904 }
905 else if (hsdram->State == HAL_SDRAM_STATE_RESET)
906 {
907 switch (CallbackId)
908 {
909 case HAL_SDRAM_MSP_INIT_CB_ID :
910 hsdram->MspInitCallback = HAL_SDRAM_MspInit;
911 break;
912 case HAL_SDRAM_MSP_DEINIT_CB_ID :
913 hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
914 break;
915 default :
916 /* update return status */
917 status = HAL_ERROR;
918 break;
919 }
920 }
921 else
922 {
923 /* update return status */
924 status = HAL_ERROR;
925 }
926
927 /* Release Lock */
928 __HAL_UNLOCK(hsdram);
929 return status;
930 }
931
932 /**
933 * @brief Register a User SDRAM Callback for DMA transfers
934 * To be used instead of the weak (surcharged) predefined callback
935 * @param hsdram : SDRAM handle
936 * @param CallbackId : ID of the callback to be registered
937 * This parameter can be one of the following values:
938 * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID
939 * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID
940 * @param pCallback : pointer to the Callback function
941 * @retval status
942 */
HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef * hsdram,HAL_SDRAM_CallbackIDTypeDef CallbackId,pSDRAM_DmaCallbackTypeDef pCallback)943 HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
944 pSDRAM_DmaCallbackTypeDef pCallback)
945 {
946 HAL_StatusTypeDef status = HAL_OK;
947 HAL_SDRAM_StateTypeDef state;
948
949 if (pCallback == NULL)
950 {
951 return HAL_ERROR;
952 }
953
954 /* Process locked */
955 __HAL_LOCK(hsdram);
956
957 state = hsdram->State;
958 if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
959 {
960 switch (CallbackId)
961 {
962 case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
963 hsdram->DmaXferCpltCallback = pCallback;
964 break;
965 case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
966 hsdram->DmaXferErrorCallback = pCallback;
967 break;
968 default :
969 /* update return status */
970 status = HAL_ERROR;
971 break;
972 }
973 }
974 else
975 {
976 /* update return status */
977 status = HAL_ERROR;
978 }
979
980 /* Release Lock */
981 __HAL_UNLOCK(hsdram);
982 return status;
983 }
984 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
985
986 /**
987 * @}
988 */
989
990 /** @defgroup SDRAM_Exported_Functions_Group3 Control functions
991 * @brief management functions
992 *
993 @verbatim
994 ==============================================================================
995 ##### SDRAM Control functions #####
996 ==============================================================================
997 [..]
998 This subsection provides a set of functions allowing to control dynamically
999 the SDRAM interface.
1000
1001 @endverbatim
1002 * @{
1003 */
1004
1005 /**
1006 * @brief Enables dynamically SDRAM write protection.
1007 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1008 * the configuration information for SDRAM module.
1009 * @retval HAL status
1010 */
HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef * hsdram)1011 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
1012 {
1013 /* Check the SDRAM controller state */
1014 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
1015 {
1016 return HAL_BUSY;
1017 }
1018 else if (hsdram->State == HAL_SDRAM_STATE_READY)
1019 {
1020 /* Update the SDRAM state */
1021 hsdram->State = HAL_SDRAM_STATE_BUSY;
1022
1023 /* Enable write protection */
1024 (void)FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
1025
1026 /* Update the SDRAM state */
1027 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
1028 }
1029 else
1030 {
1031 return HAL_ERROR;
1032 }
1033
1034 return HAL_OK;
1035 }
1036
1037 /**
1038 * @brief Disables dynamically SDRAM write protection.
1039 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1040 * the configuration information for SDRAM module.
1041 * @retval HAL status
1042 */
HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef * hsdram)1043 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
1044 {
1045 HAL_SDRAM_StateTypeDef state = hsdram->State;
1046
1047 /* Check the SDRAM controller state */
1048 if (state == HAL_SDRAM_STATE_BUSY)
1049 {
1050 return HAL_BUSY;
1051 }
1052 else if (state == HAL_SDRAM_STATE_WRITE_PROTECTED)
1053 {
1054 /* Update the SDRAM state */
1055 hsdram->State = HAL_SDRAM_STATE_BUSY;
1056
1057 /* Disable write protection */
1058 (void)FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
1059
1060 /* Update the SDRAM state */
1061 hsdram->State = HAL_SDRAM_STATE_READY;
1062 }
1063 else
1064 {
1065 return HAL_ERROR;
1066 }
1067
1068 return HAL_OK;
1069 }
1070
1071 /**
1072 * @brief Sends Command to the SDRAM bank.
1073 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1074 * the configuration information for SDRAM module.
1075 * @param Command SDRAM command structure
1076 * @param Timeout Timeout duration
1077 * @retval HAL status
1078 */
HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef * hsdram,FMC_SDRAM_CommandTypeDef * Command,uint32_t Timeout)1079 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command,
1080 uint32_t Timeout)
1081 {
1082 HAL_SDRAM_StateTypeDef state = hsdram->State;
1083
1084 /* Check the SDRAM controller state */
1085 if (state == HAL_SDRAM_STATE_BUSY)
1086 {
1087 return HAL_BUSY;
1088 }
1089 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_PRECHARGED))
1090 {
1091 /* Update the SDRAM state */
1092 hsdram->State = HAL_SDRAM_STATE_BUSY;
1093
1094 /* Send SDRAM command */
1095 (void)FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
1096
1097 /* Update the SDRAM controller state state */
1098 if (Command->CommandMode == FMC_SDRAM_CMD_PALL)
1099 {
1100 hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
1101 }
1102 else
1103 {
1104 hsdram->State = HAL_SDRAM_STATE_READY;
1105 }
1106 }
1107 else
1108 {
1109 return HAL_ERROR;
1110 }
1111
1112 return HAL_OK;
1113 }
1114
1115 /**
1116 * @brief Programs the SDRAM Memory Refresh rate.
1117 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1118 * the configuration information for SDRAM module.
1119 * @param RefreshRate The SDRAM refresh rate value
1120 * @retval HAL status
1121 */
HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef * hsdram,uint32_t RefreshRate)1122 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
1123 {
1124 /* Check the SDRAM controller state */
1125 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
1126 {
1127 return HAL_BUSY;
1128 }
1129 else if (hsdram->State == HAL_SDRAM_STATE_READY)
1130 {
1131 /* Update the SDRAM state */
1132 hsdram->State = HAL_SDRAM_STATE_BUSY;
1133
1134 /* Program the refresh rate */
1135 (void)FMC_SDRAM_ProgramRefreshRate(hsdram->Instance, RefreshRate);
1136
1137 /* Update the SDRAM state */
1138 hsdram->State = HAL_SDRAM_STATE_READY;
1139 }
1140 else
1141 {
1142 return HAL_ERROR;
1143 }
1144
1145 return HAL_OK;
1146 }
1147
1148 /**
1149 * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
1150 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1151 * the configuration information for SDRAM module.
1152 * @param AutoRefreshNumber The SDRAM auto Refresh number
1153 * @retval HAL status
1154 */
HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef * hsdram,uint32_t AutoRefreshNumber)1155 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
1156 {
1157 /* Check the SDRAM controller state */
1158 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
1159 {
1160 return HAL_BUSY;
1161 }
1162 else if (hsdram->State == HAL_SDRAM_STATE_READY)
1163 {
1164 /* Update the SDRAM state */
1165 hsdram->State = HAL_SDRAM_STATE_BUSY;
1166
1167 /* Set the Auto-Refresh number */
1168 (void)FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance, AutoRefreshNumber);
1169
1170 /* Update the SDRAM state */
1171 hsdram->State = HAL_SDRAM_STATE_READY;
1172 }
1173 else
1174 {
1175 return HAL_ERROR;
1176 }
1177
1178 return HAL_OK;
1179 }
1180
1181 /**
1182 * @brief Returns the SDRAM memory current mode.
1183 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1184 * the configuration information for SDRAM module.
1185 * @retval The SDRAM memory mode.
1186 */
HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef * hsdram)1187 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
1188 {
1189 /* Return the SDRAM memory current mode */
1190 return (FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
1191 }
1192
1193 /**
1194 * @}
1195 */
1196
1197 /** @defgroup SDRAM_Exported_Functions_Group4 State functions
1198 * @brief Peripheral State functions
1199 *
1200 @verbatim
1201 ==============================================================================
1202 ##### SDRAM State functions #####
1203 ==============================================================================
1204 [..]
1205 This subsection permits to get in run-time the status of the SDRAM controller
1206 and the data flow.
1207
1208 @endverbatim
1209 * @{
1210 */
1211
1212 /**
1213 * @brief Returns the SDRAM state.
1214 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1215 * the configuration information for SDRAM module.
1216 * @retval HAL state
1217 */
HAL_SDRAM_GetState(SDRAM_HandleTypeDef * hsdram)1218 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
1219 {
1220 return hsdram->State;
1221 }
1222
1223 /**
1224 * @}
1225 */
1226
1227 /**
1228 * @}
1229 */
1230
1231 /**
1232 * @brief DMA SDRAM process complete callback.
1233 * @param hdma : DMA handle
1234 * @retval None
1235 */
SDRAM_DMACplt(DMA_HandleTypeDef * hdma)1236 static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma)
1237 {
1238 SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
1239
1240 /* Disable the DMA channel */
1241 __HAL_DMA_DISABLE(hdma);
1242
1243 /* Update the SDRAM controller state */
1244 hsdram->State = HAL_SDRAM_STATE_READY;
1245
1246 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
1247 hsdram->DmaXferCpltCallback(hdma);
1248 #else
1249 HAL_SDRAM_DMA_XferCpltCallback(hdma);
1250 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
1251 }
1252
1253 /**
1254 * @brief DMA SRAM process complete callback.
1255 * @param hdma : DMA handle
1256 * @retval None
1257 */
SDRAM_DMACpltProt(DMA_HandleTypeDef * hdma)1258 static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
1259 {
1260 SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
1261
1262 /* Disable the DMA channel */
1263 __HAL_DMA_DISABLE(hdma);
1264
1265 /* Update the SDRAM controller state */
1266 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
1267
1268 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
1269 hsdram->DmaXferCpltCallback(hdma);
1270 #else
1271 HAL_SDRAM_DMA_XferCpltCallback(hdma);
1272 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
1273 }
1274
1275 /**
1276 * @brief DMA SDRAM error callback.
1277 * @param hdma : DMA handle
1278 * @retval None
1279 */
SDRAM_DMAError(DMA_HandleTypeDef * hdma)1280 static void SDRAM_DMAError(DMA_HandleTypeDef *hdma)
1281 {
1282 SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
1283
1284 /* Disable the DMA channel */
1285 __HAL_DMA_DISABLE(hdma);
1286
1287 /* Update the SDRAM controller state */
1288 hsdram->State = HAL_SDRAM_STATE_ERROR;
1289
1290 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
1291 hsdram->DmaXferErrorCallback(hdma);
1292 #else
1293 HAL_SDRAM_DMA_XferErrorCallback(hdma);
1294 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
1295 }
1296
1297 /**
1298 * @}
1299 */
1300
1301 #endif /* HAL_SDRAM_MODULE_ENABLED */
1302
1303 /**
1304 * @}
1305 */
1306
1307
