1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_rcc.c
4 * @author MCD Application Team
5 * @brief RCC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Reset and Clock Control (RCC) peripheral:
8 * + Initialization and de-initialization functions
9 * + Peripheral Control functions
10 *
11 @verbatim
12 ==============================================================================
13 ##### RCC specific features #####
14 ==============================================================================
15 [..]
16 After reset the device is running from Internal High Speed oscillator
17 (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
18 and I-Cache are disabled, and all peripherals are off except internal
19 SRAM, Flash and JTAG.
20 (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
21 all peripherals mapped on these buses are running at HSI speed.
22 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
23 (+) All GPIOs are in input floating state, except the JTAG pins which
24 are assigned to be used for debug purpose.
25
26 [..]
27 Once the device started from reset, the user application has to:
28 (+) Configure the clock source to be used to drive the System clock
29 (if the application needs higher frequency/performance)
30 (+) Configure the System clock frequency and Flash settings
31 (+) Configure the AHB and APB buses prescalers
32 (+) Enable the clock for the peripheral(s) to be used
33 (+) Configure the clock source(s) for peripherals which clocks are not
34 derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
35
36 ##### RCC Limitations #####
37 ==============================================================================
38 [..]
39 A delay between an RCC peripheral clock enable and the effective peripheral
40 enabling should be taken into account in order to manage the peripheral read/write
41 from/to registers.
42 (+) This delay depends on the peripheral mapping.
43 (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
44 after the clock enable bit is set on the hardware register
45 (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
46 after the clock enable bit is set on the hardware register
47
48 [..]
49 Implemented Workaround:
50 (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
51 inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
52
53 @endverbatim
54 ******************************************************************************
55 * @attention
56 *
57 * Copyright (c) 2017 STMicroelectronics.
58 * All rights reserved.
59 *
60 * This software is licensed under terms that can be found in the LICENSE file in
61 * the root directory of this software component.
62 * If no LICENSE file comes with this software, it is provided AS-IS.
63 ******************************************************************************
64 */
65
66 /* Includes ------------------------------------------------------------------*/
67 #include "stm32f7xx_hal.h"
68
69 /** @addtogroup STM32F7xx_HAL_Driver
70 * @{
71 */
72
73 /** @defgroup RCC RCC
74 * @brief RCC HAL module driver
75 * @{
76 */
77
78 #ifdef HAL_RCC_MODULE_ENABLED
79
80 /* Private typedef -----------------------------------------------------------*/
81 /* Private define ------------------------------------------------------------*/
82 /* Private macro -------------------------------------------------------------*/
83 /** @defgroup RCC_Private_Macros RCC Private Macros
84 * @{
85 */
86
87 #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
88 #define MCO1_GPIO_PORT GPIOA
89 #define MCO1_PIN GPIO_PIN_8
90
91 #define MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
92 #define MCO2_GPIO_PORT GPIOC
93 #define MCO2_PIN GPIO_PIN_9
94
95 /**
96 * @}
97 */
98 /* Private variables ---------------------------------------------------------*/
99 /** @defgroup RCC_Private_Variables RCC Private Variables
100 * @{
101 */
102
103 /**
104 * @}
105 */
106
107 /* Private function prototypes -----------------------------------------------*/
108 /* Exported functions ---------------------------------------------------------*/
109
110 /** @defgroup RCC_Exported_Functions RCC Exported Functions
111 * @{
112 */
113
114 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
115 * @brief Initialization and Configuration functions
116 *
117 @verbatim
118 ===============================================================================
119 ##### Initialization and de-initialization functions #####
120 ===============================================================================
121 [..]
122 This section provides functions allowing to configure the internal/external oscillators
123 (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
124 and APB2).
125
126 [..] Internal/external clock and PLL configuration
127 (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
128 the PLL as System clock source.
129
130 (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
131 clock source.
132
133 (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
134 through the PLL as System clock source. Can be used also as RTC clock source.
135
136 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
137
138 (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
139 (++) The first output is used to generate the high speed system clock (up to 216 MHz)
140 (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
141 the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
142
143 (#) CSS (Clock security system), once enable using the function HAL_RCC_EnableCSS()
144 and if a HSE clock failure occurs(HSE used directly or through PLL as System
145 clock source), the System clock is automatically switched to HSI and an interrupt
146 is generated if enabled. The interrupt is linked to the Cortex-M7 NMI
147 (Non-Maskable Interrupt) exception vector.
148
149 (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
150 clock (through a configurable prescaler) on PA8 pin.
151
152 (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
153 clock (through a configurable prescaler) on PC9 pin.
154
155 [..] System, AHB and APB buses clocks configuration
156 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
157 HSE and PLL.
158 The AHB clock (HCLK) is derived from System clock through configurable
159 prescaler and used to clock the CPU, memory and peripherals mapped
160 on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
161 from AHB clock through configurable prescalers and used to clock
162 the peripherals mapped on these buses. You can use
163 "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
164
165 -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
166 (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
167 from an external clock mapped on the I2S_CKIN pin.
168 You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
169 (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or
170 from an external clock mapped on the I2S_CKIN pin.
171 You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
172 (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
173 divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()
174 macros to configure this clock.
175 (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
176 to work correctly, while the SDIO require a frequency equal or lower than
177 to 48. This clock is derived of the main PLL through PLLQ divider.
178 (+@) IWDG clock which is always the LSI clock.
179 @endverbatim
180 * @{
181 */
182
183 /**
184 * @brief Resets the RCC clock configuration to the default reset state.
185 * @note The default reset state of the clock configuration is given below:
186 * - HSI ON and used as system clock source
187 * - HSE, PLL, PLLI2S and PLLSAI OFF
188 * - AHB, APB1 and APB2 prescaler set to 1.
189 * - CSS, MCO1 and MCO2 OFF
190 * - All interrupts disabled
191 * @note This function doesn't modify the configuration of the
192 * - Peripheral clocks
193 * - LSI, LSE and RTC clocks
194 * @retval None
195 */
HAL_RCC_DeInit(void)196 HAL_StatusTypeDef HAL_RCC_DeInit(void)
197 {
198 uint32_t tickstart;
199
200 /* Get Start Tick */
201 tickstart = HAL_GetTick();
202
203 /* Set HSION bit to the reset value */
204 SET_BIT(RCC->CR, RCC_CR_HSION);
205
206 /* Wait till HSI is ready */
207 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)
208 {
209 if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
210 {
211 return HAL_TIMEOUT;
212 }
213 }
214
215 /* Set HSITRIM[4:0] bits to the reset value */
216 SET_BIT(RCC->CR, RCC_CR_HSITRIM_4);
217
218 /* Get Start Tick */
219 tickstart = HAL_GetTick();
220
221 /* Reset CFGR register */
222 CLEAR_REG(RCC->CFGR);
223
224 /* Wait till clock switch is ready */
225 while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET)
226 {
227 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
228 {
229 return HAL_TIMEOUT;
230 }
231 }
232
233 /* Get Start Tick */
234 tickstart = HAL_GetTick();
235
236 /* Clear HSEON, HSEBYP and CSSON bits */
237 CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON);
238
239 /* Wait till HSE is disabled */
240 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET)
241 {
242 if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
243 {
244 return HAL_TIMEOUT;
245 }
246 }
247
248 /* Get Start Tick */
249 tickstart = HAL_GetTick();
250
251 /* Clear PLLON bit */
252 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
253
254 /* Wait till PLL is disabled */
255 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)
256 {
257 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
258 {
259 return HAL_TIMEOUT;
260 }
261 }
262
263 /* Get Start Tick */
264 tickstart = HAL_GetTick();
265
266 /* Reset PLLI2SON bit */
267 CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
268
269 /* Wait till PLLI2S is disabled */
270 while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET)
271 {
272 if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
273 {
274 return HAL_TIMEOUT;
275 }
276 }
277
278 /* Get Start Tick */
279 tickstart = HAL_GetTick();
280
281 /* Reset PLLSAI bit */
282 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
283
284 /* Wait till PLLSAI is disabled */
285 while (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) != RESET)
286 {
287 if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
288 {
289 return HAL_TIMEOUT;
290 }
291 }
292
293 /* Once PLL, PLLI2S and PLLSAI are OFF, reset PLLCFGR register to default value */
294 RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | 0x20000000U;
295
296 /* Reset PLLI2SCFGR register to default value */
297 RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1;
298
299 /* Reset PLLSAICFGR register to default value */
300 RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2 | 0x20000000U;
301
302 /* Disable all interrupts */
303 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE | RCC_CIR_PLLI2SRDYIE | RCC_CIR_PLLSAIRDYIE);
304
305 /* Clear all interrupt flags */
306 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_PLLI2SRDYC | RCC_CIR_PLLSAIRDYC | RCC_CIR_CSSC);
307
308 /* Clear LSION bit */
309 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
310
311 /* Reset all CSR flags */
312 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
313
314 /* Update the SystemCoreClock global variable */
315 SystemCoreClock = HSI_VALUE;
316
317 /* Adapt Systick interrupt period */
318 if (HAL_InitTick(uwTickPrio) != HAL_OK)
319 {
320 return HAL_ERROR;
321 }
322 else
323 {
324 return HAL_OK;
325 }
326 }
327
328 /**
329 * @brief Initializes the RCC Oscillators according to the specified parameters in the
330 * RCC_OscInitTypeDef.
331 * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
332 * contains the configuration information for the RCC Oscillators.
333 * @note The PLL is not disabled when used as system clock.
334 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
335 * supported by this function. User should request a transition to LSE Off
336 * first and then LSE On or LSE Bypass.
337 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
338 * supported by this function. User should request a transition to HSE Off
339 * first and then HSE On or HSE Bypass.
340 * @retval HAL status
341 */
HAL_RCC_OscConfig(RCC_OscInitTypeDef * RCC_OscInitStruct)342 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
343 {
344 uint32_t tickstart;
345 uint32_t pll_config;
346 FlagStatus pwrclkchanged = RESET;
347
348 /* Check Null pointer */
349 if (RCC_OscInitStruct == NULL)
350 {
351 return HAL_ERROR;
352 }
353
354 /* Check the parameters */
355 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
356
357 /*------------------------------- HSE Configuration ------------------------*/
358 if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
359 {
360 /* Check the parameters */
361 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
362 /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
363 if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
364 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
365 {
366 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
367 {
368 return HAL_ERROR;
369 }
370 }
371 else
372 {
373 /* Set the new HSE configuration ---------------------------------------*/
374 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
375
376 /* Check the HSE State */
377 if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
378 {
379 /* Get Start Tick*/
380 tickstart = HAL_GetTick();
381
382 /* Wait till HSE is ready */
383 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
384 {
385 if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
386 {
387 return HAL_TIMEOUT;
388 }
389 }
390 }
391 else
392 {
393 /* Get Start Tick*/
394 tickstart = HAL_GetTick();
395
396 /* Wait till HSE is bypassed or disabled */
397 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
398 {
399 if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
400 {
401 return HAL_TIMEOUT;
402 }
403 }
404 }
405 }
406 }
407 /*----------------------------- HSI Configuration --------------------------*/
408 if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
409 {
410 /* Check the parameters */
411 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
412 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
413
414 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
415 if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
416 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
417 {
418 /* When HSI is used as system clock it will not disabled */
419 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
420 {
421 return HAL_ERROR;
422 }
423 /* Otherwise, just the calibration is allowed */
424 else
425 {
426 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
427 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
428 }
429 }
430 else
431 {
432 /* Check the HSI State */
433 if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
434 {
435 /* Enable the Internal High Speed oscillator (HSI). */
436 __HAL_RCC_HSI_ENABLE();
437
438 /* Get Start Tick*/
439 tickstart = HAL_GetTick();
440
441 /* Wait till HSI is ready */
442 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
443 {
444 if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
445 {
446 return HAL_TIMEOUT;
447 }
448 }
449
450 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
451 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
452 }
453 else
454 {
455 /* Disable the Internal High Speed oscillator (HSI). */
456 __HAL_RCC_HSI_DISABLE();
457
458 /* Get Start Tick*/
459 tickstart = HAL_GetTick();
460
461 /* Wait till HSI is ready */
462 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
463 {
464 if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
465 {
466 return HAL_TIMEOUT;
467 }
468 }
469 }
470 }
471 }
472 /*------------------------------ LSI Configuration -------------------------*/
473 if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
474 {
475 /* Check the parameters */
476 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
477
478 /* Check the LSI State */
479 if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
480 {
481 /* Enable the Internal Low Speed oscillator (LSI). */
482 __HAL_RCC_LSI_ENABLE();
483
484 /* Get Start Tick*/
485 tickstart = HAL_GetTick();
486
487 /* Wait till LSI is ready */
488 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
489 {
490 if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
491 {
492 return HAL_TIMEOUT;
493 }
494 }
495 }
496 else
497 {
498 /* Disable the Internal Low Speed oscillator (LSI). */
499 __HAL_RCC_LSI_DISABLE();
500
501 /* Get Start Tick*/
502 tickstart = HAL_GetTick();
503
504 /* Wait till LSI is ready */
505 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
506 {
507 if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
508 {
509 return HAL_TIMEOUT;
510 }
511 }
512 }
513 }
514 /*------------------------------ LSE Configuration -------------------------*/
515 if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
516 {
517 /* Check the parameters */
518 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
519
520 /* Update LSE configuration in Backup Domain control register */
521 /* Requires to enable write access to Backup Domain of necessary */
522 if (__HAL_RCC_PWR_IS_CLK_DISABLED())
523 {
524 /* Enable Power Clock*/
525 __HAL_RCC_PWR_CLK_ENABLE();
526 pwrclkchanged = SET;
527 }
528
529 if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
530 {
531 /* Enable write access to Backup domain */
532 PWR->CR1 |= PWR_CR1_DBP;
533
534 /* Wait for Backup domain Write protection disable */
535 tickstart = HAL_GetTick();
536
537 while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
538 {
539 if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
540 {
541 return HAL_TIMEOUT;
542 }
543 }
544 }
545
546 /* Set the new LSE configuration -----------------------------------------*/
547 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
548 /* Check the LSE State */
549 if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
550 {
551 /* Get Start Tick*/
552 tickstart = HAL_GetTick();
553
554 /* Wait till LSE is ready */
555 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
556 {
557 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
558 {
559 return HAL_TIMEOUT;
560 }
561 }
562 }
563 else
564 {
565 /* Get Start Tick*/
566 tickstart = HAL_GetTick();
567
568 /* Wait till LSE is ready */
569 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
570 {
571 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
572 {
573 return HAL_TIMEOUT;
574 }
575 }
576 }
577
578 /* Restore clock configuration if changed */
579 if (pwrclkchanged == SET)
580 {
581 __HAL_RCC_PWR_CLK_DISABLE();
582 }
583 }
584 /*-------------------------------- PLL Configuration -----------------------*/
585 /* Check the parameters */
586 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
587 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
588 {
589 /* Check if the PLL is used as system clock or not */
590 if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
591 {
592 if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
593 {
594 /* Check the parameters */
595 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
596 assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
597 assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
598 assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
599 assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
600 #if defined (RCC_PLLCFGR_PLLR)
601 assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
602 #endif
603
604 /* Disable the main PLL. */
605 __HAL_RCC_PLL_DISABLE();
606
607 /* Get Start Tick*/
608 tickstart = HAL_GetTick();
609
610 /* Wait till PLL is ready */
611 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
612 {
613 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
614 {
615 return HAL_TIMEOUT;
616 }
617 }
618
619 /* Configure the main PLL clock source, multiplication and division factors. */
620 #if defined (RCC_PLLCFGR_PLLR)
621 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
622 RCC_OscInitStruct->PLL.PLLM,
623 RCC_OscInitStruct->PLL.PLLN,
624 RCC_OscInitStruct->PLL.PLLP,
625 RCC_OscInitStruct->PLL.PLLQ,
626 RCC_OscInitStruct->PLL.PLLR);
627 #else
628 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
629 RCC_OscInitStruct->PLL.PLLM,
630 RCC_OscInitStruct->PLL.PLLN,
631 RCC_OscInitStruct->PLL.PLLP,
632 RCC_OscInitStruct->PLL.PLLQ);
633 #endif
634
635 /* Enable the main PLL. */
636 __HAL_RCC_PLL_ENABLE();
637
638 /* Get Start Tick*/
639 tickstart = HAL_GetTick();
640
641 /* Wait till PLL is ready */
642 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
643 {
644 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
645 {
646 return HAL_TIMEOUT;
647 }
648 }
649 }
650 else
651 {
652 /* Disable the main PLL. */
653 __HAL_RCC_PLL_DISABLE();
654
655 /* Get Start Tick*/
656 tickstart = HAL_GetTick();
657
658 /* Wait till PLL is ready */
659 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
660 {
661 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
662 {
663 return HAL_TIMEOUT;
664 }
665 }
666 }
667 }
668 else
669 {
670 /* Do not return HAL_ERROR if request repeats the current configuration */
671 pll_config = RCC->PLLCFGR;
672 #if defined (RCC_PLLCFGR_PLLR)
673 if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
674 (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
675 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
676 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
677 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
678 (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
679 (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
680 #else
681 if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
682 (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
683 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
684 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
685 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
686 (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
687 #endif
688 {
689 return HAL_ERROR;
690 }
691 }
692 }
693 return HAL_OK;
694 }
695
696 /**
697 * @brief Initializes the CPU, AHB and APB buses clocks according to the specified
698 * parameters in the RCC_ClkInitStruct.
699 * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
700 * contains the configuration information for the RCC peripheral.
701 * @param FLatency FLASH Latency, this parameter depend on device selected
702 *
703 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
704 * and updated by HAL_RCC_GetHCLKFreq() function called within this function
705 *
706 * @note The HSI is used (enabled by hardware) as system clock source after
707 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
708 * of failure of the HSE used directly or indirectly as system clock
709 * (if the Clock Security System CSS is enabled).
710 *
711 * @note A switch from one clock source to another occurs only if the target
712 * clock source is ready (clock stable after startup delay or PLL locked).
713 * If a clock source which is not yet ready is selected, the switch will
714 * occur when the clock source will be ready.
715 * You can use HAL_RCC_GetClockConfig() function to know which clock is
716 * currently used as system clock source.
717 * @note Depending on the device voltage range, the software has to set correctly
718 * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
719 * (for more details refer to section above "Initialization/de-initialization functions")
720 * @retval None
721 */
HAL_RCC_ClockConfig(RCC_ClkInitTypeDef * RCC_ClkInitStruct,uint32_t FLatency)722 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
723 {
724 uint32_t tickstart = 0;
725
726 /* Check Null pointer */
727 if (RCC_ClkInitStruct == NULL)
728 {
729 return HAL_ERROR;
730 }
731
732 /* Check the parameters */
733 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
734 assert_param(IS_FLASH_LATENCY(FLatency));
735
736 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
737 must be correctly programmed according to the frequency of the CPU clock
738 (HCLK) and the supply voltage of the device. */
739
740 /* Increasing the CPU frequency */
741 if (FLatency > __HAL_FLASH_GET_LATENCY())
742 {
743 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
744 __HAL_FLASH_SET_LATENCY(FLatency);
745
746 /* Check that the new number of wait states is taken into account to access the Flash
747 memory by reading the FLASH_ACR register */
748 if (__HAL_FLASH_GET_LATENCY() != FLatency)
749 {
750 return HAL_ERROR;
751 }
752 }
753
754 /*-------------------------- HCLK Configuration --------------------------*/
755 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
756 {
757 /* Set the highest APBx dividers in order to ensure that we do not go through
758 a non-spec phase whatever we decrease or increase HCLK. */
759 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
760 {
761 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
762 }
763
764 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
765 {
766 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
767 }
768
769 /* Set the new HCLK clock divider */
770 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
771 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
772 }
773
774 /*------------------------- SYSCLK Configuration ---------------------------*/
775 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
776 {
777 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
778
779 /* HSE is selected as System Clock Source */
780 if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
781 {
782 /* Check the HSE ready flag */
783 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
784 {
785 return HAL_ERROR;
786 }
787 }
788 /* PLL is selected as System Clock Source */
789 else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
790 {
791 /* Check the PLL ready flag */
792 if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
793 {
794 return HAL_ERROR;
795 }
796 }
797 /* HSI is selected as System Clock Source */
798 else
799 {
800 /* Check the HSI ready flag */
801 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
802 {
803 return HAL_ERROR;
804 }
805 }
806
807 __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
808
809 /* Get Start Tick*/
810 tickstart = HAL_GetTick();
811
812 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
813 {
814 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
815 {
816 return HAL_TIMEOUT;
817 }
818 }
819 }
820
821 /* Decreasing the number of wait states because of lower CPU frequency */
822 if (FLatency < __HAL_FLASH_GET_LATENCY())
823 {
824 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
825 __HAL_FLASH_SET_LATENCY(FLatency);
826
827 /* Check that the new number of wait states is taken into account to access the Flash
828 memory by reading the FLASH_ACR register */
829 if (__HAL_FLASH_GET_LATENCY() != FLatency)
830 {
831 return HAL_ERROR;
832 }
833 }
834
835 /*-------------------------- PCLK1 Configuration ---------------------------*/
836 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
837 {
838 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
839 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
840 }
841
842 /*-------------------------- PCLK2 Configuration ---------------------------*/
843 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
844 {
845 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
846 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
847 }
848
849 /* Update the SystemCoreClock global variable */
850 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
851
852 /* Configure the source of time base considering new system clocks settings*/
853 HAL_InitTick(uwTickPrio);
854
855 return HAL_OK;
856 }
857
858 /**
859 * @}
860 */
861
862 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
863 * @brief RCC clocks control functions
864 *
865 @verbatim
866 ===============================================================================
867 ##### Peripheral Control functions #####
868 ===============================================================================
869 [..]
870 This subsection provides a set of functions allowing to control the RCC Clocks
871 frequencies.
872
873 @endverbatim
874 * @{
875 */
876
877 /**
878 * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
879 * @note PA8/PC9 should be configured in alternate function mode.
880 * @param RCC_MCOx specifies the output direction for the clock source.
881 * This parameter can be one of the following values:
882 * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
883 * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
884 * @param RCC_MCOSource specifies the clock source to output.
885 * This parameter can be one of the following values:
886 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
887 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
888 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
889 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
890 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
891 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
892 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
893 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
894 * @param RCC_MCODiv specifies the MCOx prescaler.
895 * This parameter can be one of the following values:
896 * @arg RCC_MCODIV_1: no division applied to MCOx clock
897 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
898 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
899 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
900 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
901 * @retval None
902 */
HAL_RCC_MCOConfig(uint32_t RCC_MCOx,uint32_t RCC_MCOSource,uint32_t RCC_MCODiv)903 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
904 {
905 GPIO_InitTypeDef GPIO_InitStruct;
906 /* Check the parameters */
907 assert_param(IS_RCC_MCO(RCC_MCOx));
908 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
909 /* RCC_MCO1 */
910 if (RCC_MCOx == RCC_MCO1)
911 {
912 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
913
914 /* MCO1 Clock Enable */
915 MCO1_CLK_ENABLE();
916
917 /* Configure the MCO1 pin in alternate function mode */
918 GPIO_InitStruct.Pin = MCO1_PIN;
919 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
920 GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
921 GPIO_InitStruct.Pull = GPIO_NOPULL;
922 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
923 HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
924
925 /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
926 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
927 }
928 else
929 {
930 assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
931
932 /* MCO2 Clock Enable */
933 MCO2_CLK_ENABLE();
934
935 /* Configure the MCO2 pin in alternate function mode */
936 GPIO_InitStruct.Pin = MCO2_PIN;
937 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
938 GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
939 GPIO_InitStruct.Pull = GPIO_NOPULL;
940 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
941 HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
942
943 /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
944 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3)));
945 }
946 }
947
948 /**
949 * @brief Enables the Clock Security System.
950 * @note If a failure is detected on the HSE oscillator clock, this oscillator
951 * is automatically disabled and an interrupt is generated to inform the
952 * software about the failure (Clock Security System Interrupt, CSSI),
953 * allowing the MCU to perform rescue operations. The CSSI is linked to
954 * the Cortex-M7 NMI (Non-Maskable Interrupt) exception vector.
955 * @retval None
956 */
HAL_RCC_EnableCSS(void)957 void HAL_RCC_EnableCSS(void)
958 {
959 SET_BIT(RCC->CR, RCC_CR_CSSON);
960 }
961
962 /**
963 * @brief Disables the Clock Security System.
964 * @retval None
965 */
HAL_RCC_DisableCSS(void)966 void HAL_RCC_DisableCSS(void)
967 {
968 CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
969 }
970
971 /**
972 * @brief Returns the SYSCLK frequency
973 *
974 * @note The system frequency computed by this function is not the real
975 * frequency in the chip. It is calculated based on the predefined
976 * constant and the selected clock source:
977 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
978 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
979 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
980 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
981 * @note (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
982 * 16 MHz) but the real value may vary depending on the variations
983 * in voltage and temperature.
984 * @note (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
985 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
986 * frequency of the crystal used. Otherwise, this function may
987 * have wrong result.
988 *
989 * @note The result of this function could be not correct when using fractional
990 * value for HSE crystal.
991 *
992 * @note This function can be used by the user application to compute the
993 * baudrate for the communication peripherals or configure other parameters.
994 *
995 * @note Each time SYSCLK changes, this function must be called to update the
996 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
997 *
998 *
999 * @retval SYSCLK frequency
1000 */
HAL_RCC_GetSysClockFreq(void)1001 uint32_t HAL_RCC_GetSysClockFreq(void)
1002 {
1003 uint32_t pllm = 0, pllvco = 0, pllp = 0;
1004 uint32_t sysclockfreq = 0;
1005
1006 /* Get SYSCLK source -------------------------------------------------------*/
1007 switch (RCC->CFGR & RCC_CFGR_SWS)
1008 {
1009 case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
1010 {
1011 sysclockfreq = HSI_VALUE;
1012 break;
1013 }
1014 case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
1015 {
1016 sysclockfreq = HSE_VALUE;
1017 break;
1018 }
1019 case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
1020 {
1021 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1022 SYSCLK = PLL_VCO / PLLP */
1023 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
1024 if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
1025 {
1026 /* HSE used as PLL clock source */
1027 pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
1028 }
1029 else
1030 {
1031 /* HSI used as PLL clock source */
1032 pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
1033 }
1034 pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
1035
1036 sysclockfreq = pllvco / pllp;
1037 break;
1038 }
1039 default:
1040 {
1041 sysclockfreq = HSI_VALUE;
1042 break;
1043 }
1044 }
1045 return sysclockfreq;
1046 }
1047
1048 /**
1049 * @brief Returns the HCLK frequency
1050 * @note Each time HCLK changes, this function must be called to update the
1051 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
1052 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
1053 * @retval HCLK frequency
1054 */
HAL_RCC_GetHCLKFreq(void)1055 uint32_t HAL_RCC_GetHCLKFreq(void)
1056 {
1057 return SystemCoreClock;
1058 }
1059
1060 /**
1061 * @brief Returns the PCLK1 frequency
1062 * @note Each time PCLK1 changes, this function must be called to update the
1063 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
1064 * @retval PCLK1 frequency
1065 */
HAL_RCC_GetPCLK1Freq(void)1066 uint32_t HAL_RCC_GetPCLK1Freq(void)
1067 {
1068 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
1069 return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
1070 }
1071
1072 /**
1073 * @brief Returns the PCLK2 frequency
1074 * @note Each time PCLK2 changes, this function must be called to update the
1075 * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
1076 * @retval PCLK2 frequency
1077 */
HAL_RCC_GetPCLK2Freq(void)1078 uint32_t HAL_RCC_GetPCLK2Freq(void)
1079 {
1080 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
1081 return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
1082 }
1083
1084 /**
1085 * @brief Configures the RCC_OscInitStruct according to the internal
1086 * RCC configuration registers.
1087 * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
1088 * will be configured.
1089 * @retval None
1090 */
HAL_RCC_GetOscConfig(RCC_OscInitTypeDef * RCC_OscInitStruct)1091 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
1092 {
1093 /* Set all possible values for the Oscillator type parameter ---------------*/
1094 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
1095
1096 /* Get the HSE configuration -----------------------------------------------*/
1097 if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
1098 {
1099 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
1100 }
1101 else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
1102 {
1103 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
1104 }
1105 else
1106 {
1107 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
1108 }
1109
1110 /* Get the HSI configuration -----------------------------------------------*/
1111 if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
1112 {
1113 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
1114 }
1115 else
1116 {
1117 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
1118 }
1119
1120 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
1121
1122 /* Get the LSE configuration -----------------------------------------------*/
1123 if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
1124 {
1125 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
1126 }
1127 else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
1128 {
1129 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
1130 }
1131 else
1132 {
1133 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
1134 }
1135
1136 /* Get the LSI configuration -----------------------------------------------*/
1137 if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION)
1138 {
1139 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
1140 }
1141 else
1142 {
1143 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
1144 }
1145
1146 /* Get the PLL configuration -----------------------------------------------*/
1147 if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
1148 {
1149 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
1150 }
1151 else
1152 {
1153 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
1154 }
1155 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
1156 RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
1157 RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
1158 RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> RCC_PLLCFGR_PLLP_Pos);
1159 RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos);
1160 #if defined (RCC_PLLCFGR_PLLR)
1161 RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR));
1162 #endif
1163 }
1164
1165 /**
1166 * @brief Configures the RCC_ClkInitStruct according to the internal
1167 * RCC configuration registers.
1168 * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
1169 * will be configured.
1170 * @param pFLatency Pointer on the Flash Latency.
1171 * @retval None
1172 */
HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef * RCC_ClkInitStruct,uint32_t * pFLatency)1173 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
1174 {
1175 /* Set all possible values for the Clock type parameter --------------------*/
1176 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
1177
1178 /* Get the SYSCLK configuration --------------------------------------------*/
1179 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
1180
1181 /* Get the HCLK configuration ----------------------------------------------*/
1182 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
1183
1184 /* Get the APB1 configuration ----------------------------------------------*/
1185 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
1186
1187 /* Get the APB2 configuration ----------------------------------------------*/
1188 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
1189
1190 /* Get the Flash Wait State (Latency) configuration ------------------------*/
1191 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
1192 }
1193
1194 /**
1195 * @brief This function handles the RCC CSS interrupt request.
1196 * @note This API should be called under the NMI_Handler().
1197 * @retval None
1198 */
HAL_RCC_NMI_IRQHandler(void)1199 void HAL_RCC_NMI_IRQHandler(void)
1200 {
1201 /* Check RCC CSSF flag */
1202 if (__HAL_RCC_GET_IT(RCC_IT_CSS))
1203 {
1204 /* RCC Clock Security System interrupt user callback */
1205 HAL_RCC_CSSCallback();
1206
1207 /* Clear RCC CSS pending bit */
1208 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
1209 }
1210 }
1211
1212 /**
1213 * @brief RCC Clock Security System interrupt callback
1214 * @retval None
1215 */
HAL_RCC_CSSCallback(void)1216 __weak void HAL_RCC_CSSCallback(void)
1217 {
1218 /* NOTE : This function Should not be modified, when the callback is needed,
1219 the HAL_RCC_CSSCallback could be implemented in the user file
1220 */
1221 }
1222
1223 /**
1224 * @}
1225 */
1226
1227 /**
1228 * @}
1229 */
1230
1231 #endif /* HAL_RCC_MODULE_ENABLED */
1232 /**
1233 * @}
1234 */
1235
1236 /**
1237 * @}
1238 */
1239
1240
