1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_i2c.c
4 * @author MCD Application Team
5 * @brief I2C HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Inter Integrated Circuit (I2C) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral State and Errors functions
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2017 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 @verbatim
24 ==============================================================================
25 ##### How to use this driver #####
26 ==============================================================================
27 [..]
28 The I2C HAL driver can be used as follows:
29
30 (#) Declare a I2C_HandleTypeDef handle structure, for example:
31 I2C_HandleTypeDef hi2c;
32
33 (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
34 (##) Enable the I2Cx interface clock
35 (##) I2C pins configuration
36 (+++) Enable the clock for the I2C GPIOs
37 (+++) Configure I2C pins as alternate function open-drain
38 (##) NVIC configuration if you need to use interrupt process
39 (+++) Configure the I2Cx interrupt priority
40 (+++) Enable the NVIC I2C IRQ Channel
41 (##) DMA Configuration if you need to use DMA process
42 (+++) Declare a DMA_HandleTypeDef handle structure for
43 the transmit or receive stream
44 (+++) Enable the DMAx interface clock using
45 (+++) Configure the DMA handle parameters
46 (+++) Configure the DMA Tx or Rx stream
47 (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
48 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
49 the DMA Tx or Rx stream
50
51 (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
52 Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
53
54 (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
55 (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
56
57 (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
58
59 (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
60
61 *** Polling mode IO operation ***
62 =================================
63 [..]
64 (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
65 (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
66 (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
67 (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
68
69 *** Polling mode IO MEM operation ***
70 =====================================
71 [..]
72 (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
73 (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
74
75
76 *** Interrupt mode IO operation ***
77 ===================================
78 [..]
79 (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
80 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
81 add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
82 (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
83 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
84 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
85 (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
86 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
87 add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
88 (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
89 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
90 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
91 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
92 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
93 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
94 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
95 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
96 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
97 This action will inform Master to generate a Stop condition to discard the communication.
98
99
100 *** Interrupt mode or DMA mode IO sequential operation ***
101 ==========================================================
102 [..]
103 (@) These interfaces allow to manage a sequential transfer with a repeated start condition
104 when a direction change during transfer
105 [..]
106 (+) A specific option field manage the different steps of a sequential transfer
107 (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
108 (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in
109 no sequential mode
110 (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
111 and data to transfer without a final stop condition
112 (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with
113 start condition, address and data to transfer without a final stop condition,
114 an then permit a call the same master sequential interface several times
115 (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
116 or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
117 (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
118 and with new data to transfer if the direction change or manage only the new data to
119 transfer
120 if no direction change and without a final stop condition in both cases
121 (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
122 and with new data to transfer if the direction change or manage only the new data to
123 transfer
124 if no direction change and with a final stop condition in both cases
125 (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition
126 after several call of the same master sequential interface several times
127 (link with option I2C_FIRST_AND_NEXT_FRAME).
128 Usage can, transfer several bytes one by one using
129 HAL_I2C_Master_Seq_Transmit_IT
130 or HAL_I2C_Master_Seq_Receive_IT
131 or HAL_I2C_Master_Seq_Transmit_DMA
132 or HAL_I2C_Master_Seq_Receive_DMA
133 with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME.
134 Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or
135 Receive sequence permit to call the opposite interface Receive or Transmit
136 without stopping the communication and so generate a restart condition.
137 (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after
138 each call of the same master sequential
139 interface.
140 Usage can, transfer several bytes one by one with a restart with slave address between
141 each bytes using
142 HAL_I2C_Master_Seq_Transmit_IT
143 or HAL_I2C_Master_Seq_Receive_IT
144 or HAL_I2C_Master_Seq_Transmit_DMA
145 or HAL_I2C_Master_Seq_Receive_DMA
146 with option I2C_FIRST_FRAME then I2C_OTHER_FRAME.
147 Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic
148 generation of STOP condition.
149
150 (+) Different sequential I2C interfaces are listed below:
151 (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using
152 HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA()
153 (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and
154 users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
155 (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using
156 HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
157 (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
158 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
159 (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
160 (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
161 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
162 (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
163 HAL_I2C_DisableListen_IT()
164 (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can
165 add their own code to check the Address Match Code and the transmission direction request by master
166 (Write/Read).
167 (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can
168 add their own code by customization of function pointer HAL_I2C_ListenCpltCallback()
169 (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using
170 HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA()
171 (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and
172 users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
173 (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using
174 HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA()
175 (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
176 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
177 (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
178 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
179 (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
180 This action will inform Master to generate a Stop condition to discard the communication.
181
182 *** Interrupt mode IO MEM operation ***
183 =======================================
184 [..]
185 (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
186 HAL_I2C_Mem_Write_IT()
187 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
188 add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
189 (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
190 HAL_I2C_Mem_Read_IT()
191 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
192 add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
193 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
194 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
195
196 *** DMA mode IO operation ***
197 ==============================
198 [..]
199 (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
200 HAL_I2C_Master_Transmit_DMA()
201 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
202 add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
203 (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
204 HAL_I2C_Master_Receive_DMA()
205 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
206 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
207 (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
208 HAL_I2C_Slave_Transmit_DMA()
209 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
210 add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
211 (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
212 HAL_I2C_Slave_Receive_DMA()
213 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
214 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
215 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
216 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
217 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
218 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
219 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
220 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
221 This action will inform Master to generate a Stop condition to discard the communication.
222
223 *** DMA mode IO MEM operation ***
224 =================================
225 [..]
226 (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
227 HAL_I2C_Mem_Write_DMA()
228 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
229 add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
230 (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
231 HAL_I2C_Mem_Read_DMA()
232 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
233 add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
234 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
235 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
236
237
238 *** I2C HAL driver macros list ***
239 ==================================
240 [..]
241 Below the list of most used macros in I2C HAL driver.
242
243 (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
244 (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
245 (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
246 (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
247 (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
248 (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
249 (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
250
251 *** Callback registration ***
252 =============================================
253 [..]
254 The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
255 allows the user to configure dynamically the driver callbacks.
256 Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
257 to register an interrupt callback.
258 [..]
259 Function HAL_I2C_RegisterCallback() allows to register following callbacks:
260 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
261 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
262 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
263 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
264 (+) ListenCpltCallback : callback for end of listen mode.
265 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
266 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
267 (+) ErrorCallback : callback for error detection.
268 (+) AbortCpltCallback : callback for abort completion process.
269 (+) MspInitCallback : callback for Msp Init.
270 (+) MspDeInitCallback : callback for Msp DeInit.
271 This function takes as parameters the HAL peripheral handle, the Callback ID
272 and a pointer to the user callback function.
273 [..]
274 For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
275 [..]
276 Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
277 weak function.
278 HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
279 and the Callback ID.
280 This function allows to reset following callbacks:
281 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
282 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
283 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
284 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
285 (+) ListenCpltCallback : callback for end of listen mode.
286 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
287 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
288 (+) ErrorCallback : callback for error detection.
289 (+) AbortCpltCallback : callback for abort completion process.
290 (+) MspInitCallback : callback for Msp Init.
291 (+) MspDeInitCallback : callback for Msp DeInit.
292 [..]
293 For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
294 [..]
295 By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
296 all callbacks are set to the corresponding weak functions:
297 examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
298 Exception done for MspInit and MspDeInit functions that are
299 reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
300 these callbacks are null (not registered beforehand).
301 If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
302 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
303 [..]
304 Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
305 Exception done MspInit/MspDeInit functions that can be registered/unregistered
306 in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
307 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
308 Then, the user first registers the MspInit/MspDeInit user callbacks
309 using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
310 or HAL_I2C_Init() function.
311 [..]
312 When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
313 not defined, the callback registration feature is not available and all callbacks
314 are set to the corresponding weak functions.
315
316 [..]
317 (@) You can refer to the I2C HAL driver header file for more useful macros
318
319 @endverbatim
320 */
321
322 /* Includes ------------------------------------------------------------------*/
323 #include "stm32f7xx_hal.h"
324
325 /** @addtogroup STM32F7xx_HAL_Driver
326 * @{
327 */
328
329 /** @defgroup I2C I2C
330 * @brief I2C HAL module driver
331 * @{
332 */
333
334 #ifdef HAL_I2C_MODULE_ENABLED
335
336 /* Private typedef -----------------------------------------------------------*/
337 /* Private define ------------------------------------------------------------*/
338
339 /** @defgroup I2C_Private_Define I2C Private Define
340 * @{
341 */
342 #define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */
343 #define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */
344 #define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */
345 #define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */
346 #define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */
347 #define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */
348 #define I2C_TIMEOUT_TC (25U) /*!< 25 ms */
349 #define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */
350 #define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */
351 #define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */
352
353 #define MAX_NBYTE_SIZE 255U
354 #define SLAVE_ADDR_SHIFT 7U
355 #define SLAVE_ADDR_MSK 0x06U
356
357 /* Private define for @ref PreviousState usage */
358 #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
359 (uint32_t)HAL_I2C_STATE_BUSY_RX) & \
360 (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
361 /*!< Mask State define, keep only RX and TX bits */
362 #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
363 /*!< Default Value */
364 #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
365 (uint32_t)HAL_I2C_MODE_MASTER))
366 /*!< Master Busy TX, combinaison of State LSB and Mode enum */
367 #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
368 (uint32_t)HAL_I2C_MODE_MASTER))
369 /*!< Master Busy RX, combinaison of State LSB and Mode enum */
370 #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
371 (uint32_t)HAL_I2C_MODE_SLAVE))
372 /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
373 #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
374 (uint32_t)HAL_I2C_MODE_SLAVE))
375 /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
376 #define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
377 (uint32_t)HAL_I2C_MODE_MEM))
378 /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
379 #define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
380 (uint32_t)HAL_I2C_MODE_MEM))
381 /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
382
383
384 /* Private define to centralize the enable/disable of Interrupts */
385 #define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with
386 @ref I2C_XFER_LISTEN_IT */
387 #define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with
388 @ref I2C_XFER_LISTEN_IT */
389 #define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT
390 and @ref I2C_XFER_RX_IT */
391
392 #define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error
393 and NACK treatment */
394 #define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */
395 #define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */
396
397 /* Private define Sequential Transfer Options default/reset value */
398 #define I2C_NO_OPTION_FRAME (0xFFFF0000U)
399 /**
400 * @}
401 */
402
403 /* Private macro -------------------------------------------------------------*/
404 /* Macro to get remaining data to transfer on DMA side */
405 #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__)
406
407 /* Private variables ---------------------------------------------------------*/
408 /* Private function prototypes -----------------------------------------------*/
409
410 /** @defgroup I2C_Private_Functions I2C Private Functions
411 * @{
412 */
413 /* Private functions to handle DMA transfer */
414 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
415 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
416 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
417 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
418 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
419 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
420
421 /* Private functions to handle IT transfer */
422 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
423 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
424 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
425 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
426 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
427 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
428 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
429
430 /* Private functions to handle IT transfer */
431 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
432 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
433 uint32_t Tickstart);
434 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
435 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
436 uint32_t Tickstart);
437
438 /* Private functions for I2C transfer IRQ handler */
439 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
440 uint32_t ITSources);
441 static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
442 uint32_t ITSources);
443 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
444 uint32_t ITSources);
445 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
446 uint32_t ITSources);
447 static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
448 uint32_t ITSources);
449 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
450 uint32_t ITSources);
451
452 /* Private functions to handle flags during polling transfer */
453 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
454 uint32_t Timeout, uint32_t Tickstart);
455 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
456 uint32_t Tickstart);
457 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
458 uint32_t Tickstart);
459 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
460 uint32_t Tickstart);
461 static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
462 uint32_t Tickstart);
463
464 /* Private functions to centralize the enable/disable of Interrupts */
465 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
466 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
467
468 /* Private function to treat different error callback */
469 static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
470
471 /* Private function to flush TXDR register */
472 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
473
474 /* Private function to handle start, restart or stop a transfer */
475 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
476 uint32_t Request);
477
478 /* Private function to Convert Specific options */
479 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
480 /**
481 * @}
482 */
483
484 /* Exported functions --------------------------------------------------------*/
485
486 /** @defgroup I2C_Exported_Functions I2C Exported Functions
487 * @{
488 */
489
490 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
491 * @brief Initialization and Configuration functions
492 *
493 @verbatim
494 ===============================================================================
495 ##### Initialization and de-initialization functions #####
496 ===============================================================================
497 [..] This subsection provides a set of functions allowing to initialize and
498 deinitialize the I2Cx peripheral:
499
500 (+) User must Implement HAL_I2C_MspInit() function in which he configures
501 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
502
503 (+) Call the function HAL_I2C_Init() to configure the selected device with
504 the selected configuration:
505 (++) Clock Timing
506 (++) Own Address 1
507 (++) Addressing mode (Master, Slave)
508 (++) Dual Addressing mode
509 (++) Own Address 2
510 (++) Own Address 2 Mask
511 (++) General call mode
512 (++) Nostretch mode
513
514 (+) Call the function HAL_I2C_DeInit() to restore the default configuration
515 of the selected I2Cx peripheral.
516
517 @endverbatim
518 * @{
519 */
520
521 /**
522 * @brief Initializes the I2C according to the specified parameters
523 * in the I2C_InitTypeDef and initialize the associated handle.
524 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
525 * the configuration information for the specified I2C.
526 * @retval HAL status
527 */
HAL_I2C_Init(I2C_HandleTypeDef * hi2c)528 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
529 {
530 /* Check the I2C handle allocation */
531 if (hi2c == NULL)
532 {
533 return HAL_ERROR;
534 }
535
536 /* Check the parameters */
537 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
538 assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
539 assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
540 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
541 assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
542 assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
543 assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
544 assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
545
546 if (hi2c->State == HAL_I2C_STATE_RESET)
547 {
548 /* Allocate lock resource and initialize it */
549 hi2c->Lock = HAL_UNLOCKED;
550
551 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
552 /* Init the I2C Callback settings */
553 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
554 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
555 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
556 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
557 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
558 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
559 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
560 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
561 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
562 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
563
564 if (hi2c->MspInitCallback == NULL)
565 {
566 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
567 }
568
569 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
570 hi2c->MspInitCallback(hi2c);
571 #else
572 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
573 HAL_I2C_MspInit(hi2c);
574 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
575 }
576
577 hi2c->State = HAL_I2C_STATE_BUSY;
578
579 /* Disable the selected I2C peripheral */
580 __HAL_I2C_DISABLE(hi2c);
581
582 /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
583 /* Configure I2Cx: Frequency range */
584 hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
585
586 /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
587 /* Disable Own Address1 before set the Own Address1 configuration */
588 hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
589
590 /* Configure I2Cx: Own Address1 and ack own address1 mode */
591 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
592 {
593 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
594 }
595 else /* I2C_ADDRESSINGMODE_10BIT */
596 {
597 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
598 }
599
600 /*---------------------------- I2Cx CR2 Configuration ----------------------*/
601 /* Configure I2Cx: Addressing Master mode */
602 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
603 {
604 hi2c->Instance->CR2 = (I2C_CR2_ADD10);
605 }
606 /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
607 hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
608
609 /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
610 /* Disable Own Address2 before set the Own Address2 configuration */
611 hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
612
613 /* Configure I2Cx: Dual mode and Own Address2 */
614 hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
615 (hi2c->Init.OwnAddress2Masks << 8));
616
617 /*---------------------------- I2Cx CR1 Configuration ----------------------*/
618 /* Configure I2Cx: Generalcall and NoStretch mode */
619 hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
620
621 /* Enable the selected I2C peripheral */
622 __HAL_I2C_ENABLE(hi2c);
623
624 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
625 hi2c->State = HAL_I2C_STATE_READY;
626 hi2c->PreviousState = I2C_STATE_NONE;
627 hi2c->Mode = HAL_I2C_MODE_NONE;
628
629 return HAL_OK;
630 }
631
632 /**
633 * @brief DeInitialize the I2C peripheral.
634 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
635 * the configuration information for the specified I2C.
636 * @retval HAL status
637 */
HAL_I2C_DeInit(I2C_HandleTypeDef * hi2c)638 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
639 {
640 /* Check the I2C handle allocation */
641 if (hi2c == NULL)
642 {
643 return HAL_ERROR;
644 }
645
646 /* Check the parameters */
647 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
648
649 hi2c->State = HAL_I2C_STATE_BUSY;
650
651 /* Disable the I2C Peripheral Clock */
652 __HAL_I2C_DISABLE(hi2c);
653
654 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
655 if (hi2c->MspDeInitCallback == NULL)
656 {
657 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
658 }
659
660 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
661 hi2c->MspDeInitCallback(hi2c);
662 #else
663 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
664 HAL_I2C_MspDeInit(hi2c);
665 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
666
667 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
668 hi2c->State = HAL_I2C_STATE_RESET;
669 hi2c->PreviousState = I2C_STATE_NONE;
670 hi2c->Mode = HAL_I2C_MODE_NONE;
671
672 /* Release Lock */
673 __HAL_UNLOCK(hi2c);
674
675 return HAL_OK;
676 }
677
678 /**
679 * @brief Initialize the I2C MSP.
680 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
681 * the configuration information for the specified I2C.
682 * @retval None
683 */
HAL_I2C_MspInit(I2C_HandleTypeDef * hi2c)684 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
685 {
686 /* Prevent unused argument(s) compilation warning */
687 UNUSED(hi2c);
688
689 /* NOTE : This function should not be modified, when the callback is needed,
690 the HAL_I2C_MspInit could be implemented in the user file
691 */
692 }
693
694 /**
695 * @brief DeInitialize the I2C MSP.
696 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
697 * the configuration information for the specified I2C.
698 * @retval None
699 */
HAL_I2C_MspDeInit(I2C_HandleTypeDef * hi2c)700 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
701 {
702 /* Prevent unused argument(s) compilation warning */
703 UNUSED(hi2c);
704
705 /* NOTE : This function should not be modified, when the callback is needed,
706 the HAL_I2C_MspDeInit could be implemented in the user file
707 */
708 }
709
710 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
711 /**
712 * @brief Register a User I2C Callback
713 * To be used instead of the weak predefined callback
714 * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
715 * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
716 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
717 * the configuration information for the specified I2C.
718 * @param CallbackID ID of the callback to be registered
719 * This parameter can be one of the following values:
720 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
721 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
722 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
723 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
724 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
725 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
726 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
727 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
728 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
729 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
730 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
731 * @param pCallback pointer to the Callback function
732 * @retval HAL status
733 */
HAL_I2C_RegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID,pI2C_CallbackTypeDef pCallback)734 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
735 pI2C_CallbackTypeDef pCallback)
736 {
737 HAL_StatusTypeDef status = HAL_OK;
738
739 if (pCallback == NULL)
740 {
741 /* Update the error code */
742 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
743
744 return HAL_ERROR;
745 }
746
747 if (HAL_I2C_STATE_READY == hi2c->State)
748 {
749 switch (CallbackID)
750 {
751 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
752 hi2c->MasterTxCpltCallback = pCallback;
753 break;
754
755 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
756 hi2c->MasterRxCpltCallback = pCallback;
757 break;
758
759 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
760 hi2c->SlaveTxCpltCallback = pCallback;
761 break;
762
763 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
764 hi2c->SlaveRxCpltCallback = pCallback;
765 break;
766
767 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
768 hi2c->ListenCpltCallback = pCallback;
769 break;
770
771 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
772 hi2c->MemTxCpltCallback = pCallback;
773 break;
774
775 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
776 hi2c->MemRxCpltCallback = pCallback;
777 break;
778
779 case HAL_I2C_ERROR_CB_ID :
780 hi2c->ErrorCallback = pCallback;
781 break;
782
783 case HAL_I2C_ABORT_CB_ID :
784 hi2c->AbortCpltCallback = pCallback;
785 break;
786
787 case HAL_I2C_MSPINIT_CB_ID :
788 hi2c->MspInitCallback = pCallback;
789 break;
790
791 case HAL_I2C_MSPDEINIT_CB_ID :
792 hi2c->MspDeInitCallback = pCallback;
793 break;
794
795 default :
796 /* Update the error code */
797 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
798
799 /* Return error status */
800 status = HAL_ERROR;
801 break;
802 }
803 }
804 else if (HAL_I2C_STATE_RESET == hi2c->State)
805 {
806 switch (CallbackID)
807 {
808 case HAL_I2C_MSPINIT_CB_ID :
809 hi2c->MspInitCallback = pCallback;
810 break;
811
812 case HAL_I2C_MSPDEINIT_CB_ID :
813 hi2c->MspDeInitCallback = pCallback;
814 break;
815
816 default :
817 /* Update the error code */
818 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
819
820 /* Return error status */
821 status = HAL_ERROR;
822 break;
823 }
824 }
825 else
826 {
827 /* Update the error code */
828 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
829
830 /* Return error status */
831 status = HAL_ERROR;
832 }
833
834 return status;
835 }
836
837 /**
838 * @brief Unregister an I2C Callback
839 * I2C callback is redirected to the weak predefined callback
840 * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
841 * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
842 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
843 * the configuration information for the specified I2C.
844 * @param CallbackID ID of the callback to be unregistered
845 * This parameter can be one of the following values:
846 * This parameter can be one of the following values:
847 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
848 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
849 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
850 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
851 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
852 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
853 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
854 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
855 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
856 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
857 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
858 * @retval HAL status
859 */
HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID)860 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
861 {
862 HAL_StatusTypeDef status = HAL_OK;
863
864 if (HAL_I2C_STATE_READY == hi2c->State)
865 {
866 switch (CallbackID)
867 {
868 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
869 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
870 break;
871
872 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
873 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
874 break;
875
876 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
877 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
878 break;
879
880 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
881 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
882 break;
883
884 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
885 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
886 break;
887
888 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
889 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
890 break;
891
892 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
893 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
894 break;
895
896 case HAL_I2C_ERROR_CB_ID :
897 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
898 break;
899
900 case HAL_I2C_ABORT_CB_ID :
901 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
902 break;
903
904 case HAL_I2C_MSPINIT_CB_ID :
905 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
906 break;
907
908 case HAL_I2C_MSPDEINIT_CB_ID :
909 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
910 break;
911
912 default :
913 /* Update the error code */
914 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
915
916 /* Return error status */
917 status = HAL_ERROR;
918 break;
919 }
920 }
921 else if (HAL_I2C_STATE_RESET == hi2c->State)
922 {
923 switch (CallbackID)
924 {
925 case HAL_I2C_MSPINIT_CB_ID :
926 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
927 break;
928
929 case HAL_I2C_MSPDEINIT_CB_ID :
930 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
931 break;
932
933 default :
934 /* Update the error code */
935 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
936
937 /* Return error status */
938 status = HAL_ERROR;
939 break;
940 }
941 }
942 else
943 {
944 /* Update the error code */
945 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
946
947 /* Return error status */
948 status = HAL_ERROR;
949 }
950
951 return status;
952 }
953
954 /**
955 * @brief Register the Slave Address Match I2C Callback
956 * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
957 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
958 * the configuration information for the specified I2C.
959 * @param pCallback pointer to the Address Match Callback function
960 * @retval HAL status
961 */
HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef * hi2c,pI2C_AddrCallbackTypeDef pCallback)962 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
963 {
964 HAL_StatusTypeDef status = HAL_OK;
965
966 if (pCallback == NULL)
967 {
968 /* Update the error code */
969 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
970
971 return HAL_ERROR;
972 }
973
974 if (HAL_I2C_STATE_READY == hi2c->State)
975 {
976 hi2c->AddrCallback = pCallback;
977 }
978 else
979 {
980 /* Update the error code */
981 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
982
983 /* Return error status */
984 status = HAL_ERROR;
985 }
986
987 return status;
988 }
989
990 /**
991 * @brief UnRegister the Slave Address Match I2C Callback
992 * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
993 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
994 * the configuration information for the specified I2C.
995 * @retval HAL status
996 */
HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef * hi2c)997 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
998 {
999 HAL_StatusTypeDef status = HAL_OK;
1000
1001 if (HAL_I2C_STATE_READY == hi2c->State)
1002 {
1003 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
1004 }
1005 else
1006 {
1007 /* Update the error code */
1008 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
1009
1010 /* Return error status */
1011 status = HAL_ERROR;
1012 }
1013
1014 return status;
1015 }
1016
1017 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
1018
1019 /**
1020 * @}
1021 */
1022
1023 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
1024 * @brief Data transfers functions
1025 *
1026 @verbatim
1027 ===============================================================================
1028 ##### IO operation functions #####
1029 ===============================================================================
1030 [..]
1031 This subsection provides a set of functions allowing to manage the I2C data
1032 transfers.
1033
1034 (#) There are two modes of transfer:
1035 (++) Blocking mode : The communication is performed in the polling mode.
1036 The status of all data processing is returned by the same function
1037 after finishing transfer.
1038 (++) No-Blocking mode : The communication is performed using Interrupts
1039 or DMA. These functions return the status of the transfer startup.
1040 The end of the data processing will be indicated through the
1041 dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
1042 using DMA mode.
1043
1044 (#) Blocking mode functions are :
1045 (++) HAL_I2C_Master_Transmit()
1046 (++) HAL_I2C_Master_Receive()
1047 (++) HAL_I2C_Slave_Transmit()
1048 (++) HAL_I2C_Slave_Receive()
1049 (++) HAL_I2C_Mem_Write()
1050 (++) HAL_I2C_Mem_Read()
1051 (++) HAL_I2C_IsDeviceReady()
1052
1053 (#) No-Blocking mode functions with Interrupt are :
1054 (++) HAL_I2C_Master_Transmit_IT()
1055 (++) HAL_I2C_Master_Receive_IT()
1056 (++) HAL_I2C_Slave_Transmit_IT()
1057 (++) HAL_I2C_Slave_Receive_IT()
1058 (++) HAL_I2C_Mem_Write_IT()
1059 (++) HAL_I2C_Mem_Read_IT()
1060 (++) HAL_I2C_Master_Seq_Transmit_IT()
1061 (++) HAL_I2C_Master_Seq_Receive_IT()
1062 (++) HAL_I2C_Slave_Seq_Transmit_IT()
1063 (++) HAL_I2C_Slave_Seq_Receive_IT()
1064 (++) HAL_I2C_EnableListen_IT()
1065 (++) HAL_I2C_DisableListen_IT()
1066 (++) HAL_I2C_Master_Abort_IT()
1067
1068 (#) No-Blocking mode functions with DMA are :
1069 (++) HAL_I2C_Master_Transmit_DMA()
1070 (++) HAL_I2C_Master_Receive_DMA()
1071 (++) HAL_I2C_Slave_Transmit_DMA()
1072 (++) HAL_I2C_Slave_Receive_DMA()
1073 (++) HAL_I2C_Mem_Write_DMA()
1074 (++) HAL_I2C_Mem_Read_DMA()
1075 (++) HAL_I2C_Master_Seq_Transmit_DMA()
1076 (++) HAL_I2C_Master_Seq_Receive_DMA()
1077 (++) HAL_I2C_Slave_Seq_Transmit_DMA()
1078 (++) HAL_I2C_Slave_Seq_Receive_DMA()
1079
1080 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
1081 (++) HAL_I2C_MasterTxCpltCallback()
1082 (++) HAL_I2C_MasterRxCpltCallback()
1083 (++) HAL_I2C_SlaveTxCpltCallback()
1084 (++) HAL_I2C_SlaveRxCpltCallback()
1085 (++) HAL_I2C_MemTxCpltCallback()
1086 (++) HAL_I2C_MemRxCpltCallback()
1087 (++) HAL_I2C_AddrCallback()
1088 (++) HAL_I2C_ListenCpltCallback()
1089 (++) HAL_I2C_ErrorCallback()
1090 (++) HAL_I2C_AbortCpltCallback()
1091
1092 @endverbatim
1093 * @{
1094 */
1095
1096 /**
1097 * @brief Transmits in master mode an amount of data in blocking mode.
1098 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1099 * the configuration information for the specified I2C.
1100 * @param DevAddress Target device address: The device 7 bits address value
1101 * in datasheet must be shifted to the left before calling the interface
1102 * @param pData Pointer to data buffer
1103 * @param Size Amount of data to be sent
1104 * @param Timeout Timeout duration
1105 * @retval HAL status
1106 */
HAL_I2C_Master_Transmit(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1107 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1108 uint16_t Size, uint32_t Timeout)
1109 {
1110 uint32_t tickstart;
1111
1112 if (hi2c->State == HAL_I2C_STATE_READY)
1113 {
1114 /* Process Locked */
1115 __HAL_LOCK(hi2c);
1116
1117 /* Init tickstart for timeout management*/
1118 tickstart = HAL_GetTick();
1119
1120 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1121 {
1122 return HAL_ERROR;
1123 }
1124
1125 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1126 hi2c->Mode = HAL_I2C_MODE_MASTER;
1127 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1128
1129 /* Prepare transfer parameters */
1130 hi2c->pBuffPtr = pData;
1131 hi2c->XferCount = Size;
1132 hi2c->XferISR = NULL;
1133
1134 /* Send Slave Address */
1135 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1136 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1137 {
1138 hi2c->XferSize = MAX_NBYTE_SIZE;
1139 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1140 I2C_GENERATE_START_WRITE);
1141 }
1142 else
1143 {
1144 hi2c->XferSize = hi2c->XferCount;
1145 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1146 I2C_GENERATE_START_WRITE);
1147 }
1148
1149 while (hi2c->XferCount > 0U)
1150 {
1151 /* Wait until TXIS flag is set */
1152 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1153 {
1154 return HAL_ERROR;
1155 }
1156 /* Write data to TXDR */
1157 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1158
1159 /* Increment Buffer pointer */
1160 hi2c->pBuffPtr++;
1161
1162 hi2c->XferCount--;
1163 hi2c->XferSize--;
1164
1165 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
1166 {
1167 /* Wait until TCR flag is set */
1168 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1169 {
1170 return HAL_ERROR;
1171 }
1172
1173 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1174 {
1175 hi2c->XferSize = MAX_NBYTE_SIZE;
1176 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1177 I2C_NO_STARTSTOP);
1178 }
1179 else
1180 {
1181 hi2c->XferSize = hi2c->XferCount;
1182 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1183 I2C_NO_STARTSTOP);
1184 }
1185 }
1186 }
1187
1188 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1189 /* Wait until STOPF flag is set */
1190 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1191 {
1192 return HAL_ERROR;
1193 }
1194
1195 /* Clear STOP Flag */
1196 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1197
1198 /* Clear Configuration Register 2 */
1199 I2C_RESET_CR2(hi2c);
1200
1201 hi2c->State = HAL_I2C_STATE_READY;
1202 hi2c->Mode = HAL_I2C_MODE_NONE;
1203
1204 /* Process Unlocked */
1205 __HAL_UNLOCK(hi2c);
1206
1207 return HAL_OK;
1208 }
1209 else
1210 {
1211 return HAL_BUSY;
1212 }
1213 }
1214
1215 /**
1216 * @brief Receives in master mode an amount of data in blocking mode.
1217 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1218 * the configuration information for the specified I2C.
1219 * @param DevAddress Target device address: The device 7 bits address value
1220 * in datasheet must be shifted to the left before calling the interface
1221 * @param pData Pointer to data buffer
1222 * @param Size Amount of data to be sent
1223 * @param Timeout Timeout duration
1224 * @retval HAL status
1225 */
HAL_I2C_Master_Receive(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1226 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1227 uint16_t Size, uint32_t Timeout)
1228 {
1229 uint32_t tickstart;
1230
1231 if (hi2c->State == HAL_I2C_STATE_READY)
1232 {
1233 /* Process Locked */
1234 __HAL_LOCK(hi2c);
1235
1236 /* Init tickstart for timeout management*/
1237 tickstart = HAL_GetTick();
1238
1239 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1240 {
1241 return HAL_ERROR;
1242 }
1243
1244 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1245 hi2c->Mode = HAL_I2C_MODE_MASTER;
1246 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1247
1248 /* Prepare transfer parameters */
1249 hi2c->pBuffPtr = pData;
1250 hi2c->XferCount = Size;
1251 hi2c->XferISR = NULL;
1252
1253 /* Send Slave Address */
1254 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1255 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1256 {
1257 hi2c->XferSize = MAX_NBYTE_SIZE;
1258 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1259 I2C_GENERATE_START_READ);
1260 }
1261 else
1262 {
1263 hi2c->XferSize = hi2c->XferCount;
1264 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1265 I2C_GENERATE_START_READ);
1266 }
1267
1268 while (hi2c->XferCount > 0U)
1269 {
1270 /* Wait until RXNE flag is set */
1271 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1272 {
1273 return HAL_ERROR;
1274 }
1275
1276 /* Read data from RXDR */
1277 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1278
1279 /* Increment Buffer pointer */
1280 hi2c->pBuffPtr++;
1281
1282 hi2c->XferSize--;
1283 hi2c->XferCount--;
1284
1285 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
1286 {
1287 /* Wait until TCR flag is set */
1288 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1289 {
1290 return HAL_ERROR;
1291 }
1292
1293 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1294 {
1295 hi2c->XferSize = MAX_NBYTE_SIZE;
1296 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1297 I2C_NO_STARTSTOP);
1298 }
1299 else
1300 {
1301 hi2c->XferSize = hi2c->XferCount;
1302 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1303 I2C_NO_STARTSTOP);
1304 }
1305 }
1306 }
1307
1308 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1309 /* Wait until STOPF flag is set */
1310 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1311 {
1312 return HAL_ERROR;
1313 }
1314
1315 /* Clear STOP Flag */
1316 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1317
1318 /* Clear Configuration Register 2 */
1319 I2C_RESET_CR2(hi2c);
1320
1321 hi2c->State = HAL_I2C_STATE_READY;
1322 hi2c->Mode = HAL_I2C_MODE_NONE;
1323
1324 /* Process Unlocked */
1325 __HAL_UNLOCK(hi2c);
1326
1327 return HAL_OK;
1328 }
1329 else
1330 {
1331 return HAL_BUSY;
1332 }
1333 }
1334
1335 /**
1336 * @brief Transmits in slave mode an amount of data in blocking mode.
1337 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1338 * the configuration information for the specified I2C.
1339 * @param pData Pointer to data buffer
1340 * @param Size Amount of data to be sent
1341 * @param Timeout Timeout duration
1342 * @retval HAL status
1343 */
HAL_I2C_Slave_Transmit(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1344 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
1345 uint32_t Timeout)
1346 {
1347 uint32_t tickstart;
1348
1349 if (hi2c->State == HAL_I2C_STATE_READY)
1350 {
1351 if ((pData == NULL) || (Size == 0U))
1352 {
1353 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
1354 return HAL_ERROR;
1355 }
1356 /* Process Locked */
1357 __HAL_LOCK(hi2c);
1358
1359 /* Init tickstart for timeout management*/
1360 tickstart = HAL_GetTick();
1361
1362 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1363 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1364 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1365
1366 /* Prepare transfer parameters */
1367 hi2c->pBuffPtr = pData;
1368 hi2c->XferCount = Size;
1369 hi2c->XferISR = NULL;
1370
1371 /* Enable Address Acknowledge */
1372 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1373
1374 /* Wait until ADDR flag is set */
1375 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1376 {
1377 /* Disable Address Acknowledge */
1378 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1379 return HAL_ERROR;
1380 }
1381
1382 /* Clear ADDR flag */
1383 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1384
1385 /* If 10bit addressing mode is selected */
1386 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
1387 {
1388 /* Wait until ADDR flag is set */
1389 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1390 {
1391 /* Disable Address Acknowledge */
1392 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1393 return HAL_ERROR;
1394 }
1395
1396 /* Clear ADDR flag */
1397 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1398 }
1399
1400 /* Wait until DIR flag is set Transmitter mode */
1401 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
1402 {
1403 /* Disable Address Acknowledge */
1404 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1405 return HAL_ERROR;
1406 }
1407
1408 while (hi2c->XferCount > 0U)
1409 {
1410 /* Wait until TXIS flag is set */
1411 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1412 {
1413 /* Disable Address Acknowledge */
1414 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1415 return HAL_ERROR;
1416 }
1417
1418 /* Write data to TXDR */
1419 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1420
1421 /* Increment Buffer pointer */
1422 hi2c->pBuffPtr++;
1423
1424 hi2c->XferCount--;
1425 }
1426
1427 /* Wait until AF flag is set */
1428 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
1429 {
1430 /* Disable Address Acknowledge */
1431 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1432 return HAL_ERROR;
1433 }
1434
1435 /* Flush TX register */
1436 I2C_Flush_TXDR(hi2c);
1437
1438 /* Clear AF flag */
1439 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
1440
1441 /* Wait until STOP flag is set */
1442 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1443 {
1444 /* Disable Address Acknowledge */
1445 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1446
1447 return HAL_ERROR;
1448 }
1449
1450 /* Clear STOP flag */
1451 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1452
1453 /* Wait until BUSY flag is reset */
1454 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
1455 {
1456 /* Disable Address Acknowledge */
1457 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1458 return HAL_ERROR;
1459 }
1460
1461 /* Disable Address Acknowledge */
1462 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1463
1464 hi2c->State = HAL_I2C_STATE_READY;
1465 hi2c->Mode = HAL_I2C_MODE_NONE;
1466
1467 /* Process Unlocked */
1468 __HAL_UNLOCK(hi2c);
1469
1470 return HAL_OK;
1471 }
1472 else
1473 {
1474 return HAL_BUSY;
1475 }
1476 }
1477
1478 /**
1479 * @brief Receive in slave mode an amount of data in blocking mode
1480 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1481 * the configuration information for the specified I2C.
1482 * @param pData Pointer to data buffer
1483 * @param Size Amount of data to be sent
1484 * @param Timeout Timeout duration
1485 * @retval HAL status
1486 */
HAL_I2C_Slave_Receive(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1487 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
1488 uint32_t Timeout)
1489 {
1490 uint32_t tickstart;
1491
1492 if (hi2c->State == HAL_I2C_STATE_READY)
1493 {
1494 if ((pData == NULL) || (Size == 0U))
1495 {
1496 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
1497 return HAL_ERROR;
1498 }
1499 /* Process Locked */
1500 __HAL_LOCK(hi2c);
1501
1502 /* Init tickstart for timeout management*/
1503 tickstart = HAL_GetTick();
1504
1505 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1506 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1507 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1508
1509 /* Prepare transfer parameters */
1510 hi2c->pBuffPtr = pData;
1511 hi2c->XferCount = Size;
1512 hi2c->XferSize = hi2c->XferCount;
1513 hi2c->XferISR = NULL;
1514
1515 /* Enable Address Acknowledge */
1516 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1517
1518 /* Wait until ADDR flag is set */
1519 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1520 {
1521 /* Disable Address Acknowledge */
1522 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1523 return HAL_ERROR;
1524 }
1525
1526 /* Clear ADDR flag */
1527 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1528
1529 /* Wait until DIR flag is reset Receiver mode */
1530 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
1531 {
1532 /* Disable Address Acknowledge */
1533 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1534 return HAL_ERROR;
1535 }
1536
1537 while (hi2c->XferCount > 0U)
1538 {
1539 /* Wait until RXNE flag is set */
1540 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1541 {
1542 /* Disable Address Acknowledge */
1543 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1544
1545 /* Store Last receive data if any */
1546 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
1547 {
1548 /* Read data from RXDR */
1549 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1550
1551 /* Increment Buffer pointer */
1552 hi2c->pBuffPtr++;
1553
1554 hi2c->XferCount--;
1555 hi2c->XferSize--;
1556 }
1557
1558 return HAL_ERROR;
1559 }
1560
1561 /* Read data from RXDR */
1562 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1563
1564 /* Increment Buffer pointer */
1565 hi2c->pBuffPtr++;
1566
1567 hi2c->XferCount--;
1568 hi2c->XferSize--;
1569 }
1570
1571 /* Wait until STOP flag is set */
1572 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1573 {
1574 /* Disable Address Acknowledge */
1575 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1576 return HAL_ERROR;
1577 }
1578
1579 /* Clear STOP flag */
1580 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1581
1582 /* Wait until BUSY flag is reset */
1583 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
1584 {
1585 /* Disable Address Acknowledge */
1586 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1587 return HAL_ERROR;
1588 }
1589
1590 /* Disable Address Acknowledge */
1591 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1592
1593 hi2c->State = HAL_I2C_STATE_READY;
1594 hi2c->Mode = HAL_I2C_MODE_NONE;
1595
1596 /* Process Unlocked */
1597 __HAL_UNLOCK(hi2c);
1598
1599 return HAL_OK;
1600 }
1601 else
1602 {
1603 return HAL_BUSY;
1604 }
1605 }
1606
1607 /**
1608 * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
1609 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1610 * the configuration information for the specified I2C.
1611 * @param DevAddress Target device address: The device 7 bits address value
1612 * in datasheet must be shifted to the left before calling the interface
1613 * @param pData Pointer to data buffer
1614 * @param Size Amount of data to be sent
1615 * @retval HAL status
1616 */
HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1617 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1618 uint16_t Size)
1619 {
1620 uint32_t xfermode;
1621
1622 if (hi2c->State == HAL_I2C_STATE_READY)
1623 {
1624 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1625 {
1626 return HAL_BUSY;
1627 }
1628
1629 /* Process Locked */
1630 __HAL_LOCK(hi2c);
1631
1632 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1633 hi2c->Mode = HAL_I2C_MODE_MASTER;
1634 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1635
1636 /* Prepare transfer parameters */
1637 hi2c->pBuffPtr = pData;
1638 hi2c->XferCount = Size;
1639 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1640 hi2c->XferISR = I2C_Master_ISR_IT;
1641
1642 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1643 {
1644 hi2c->XferSize = MAX_NBYTE_SIZE;
1645 xfermode = I2C_RELOAD_MODE;
1646 }
1647 else
1648 {
1649 hi2c->XferSize = hi2c->XferCount;
1650 xfermode = I2C_AUTOEND_MODE;
1651 }
1652
1653 /* Send Slave Address */
1654 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1655 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
1656
1657 /* Process Unlocked */
1658 __HAL_UNLOCK(hi2c);
1659
1660 /* Note : The I2C interrupts must be enabled after unlocking current process
1661 to avoid the risk of I2C interrupt handle execution before current
1662 process unlock */
1663
1664 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1665 /* possible to enable all of these */
1666 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1667 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1668 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
1669
1670 return HAL_OK;
1671 }
1672 else
1673 {
1674 return HAL_BUSY;
1675 }
1676 }
1677
1678 /**
1679 * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
1680 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1681 * the configuration information for the specified I2C.
1682 * @param DevAddress Target device address: The device 7 bits address value
1683 * in datasheet must be shifted to the left before calling the interface
1684 * @param pData Pointer to data buffer
1685 * @param Size Amount of data to be sent
1686 * @retval HAL status
1687 */
HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1688 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1689 uint16_t Size)
1690 {
1691 uint32_t xfermode;
1692
1693 if (hi2c->State == HAL_I2C_STATE_READY)
1694 {
1695 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1696 {
1697 return HAL_BUSY;
1698 }
1699
1700 /* Process Locked */
1701 __HAL_LOCK(hi2c);
1702
1703 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1704 hi2c->Mode = HAL_I2C_MODE_MASTER;
1705 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1706
1707 /* Prepare transfer parameters */
1708 hi2c->pBuffPtr = pData;
1709 hi2c->XferCount = Size;
1710 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1711 hi2c->XferISR = I2C_Master_ISR_IT;
1712
1713 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1714 {
1715 hi2c->XferSize = MAX_NBYTE_SIZE;
1716 xfermode = I2C_RELOAD_MODE;
1717 }
1718 else
1719 {
1720 hi2c->XferSize = hi2c->XferCount;
1721 xfermode = I2C_AUTOEND_MODE;
1722 }
1723
1724 /* Send Slave Address */
1725 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1726 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
1727
1728 /* Process Unlocked */
1729 __HAL_UNLOCK(hi2c);
1730
1731 /* Note : The I2C interrupts must be enabled after unlocking current process
1732 to avoid the risk of I2C interrupt handle execution before current
1733 process unlock */
1734
1735 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1736 /* possible to enable all of these */
1737 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1738 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1739 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
1740
1741 return HAL_OK;
1742 }
1743 else
1744 {
1745 return HAL_BUSY;
1746 }
1747 }
1748
1749 /**
1750 * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
1751 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1752 * the configuration information for the specified I2C.
1753 * @param pData Pointer to data buffer
1754 * @param Size Amount of data to be sent
1755 * @retval HAL status
1756 */
HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1757 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1758 {
1759 if (hi2c->State == HAL_I2C_STATE_READY)
1760 {
1761 /* Process Locked */
1762 __HAL_LOCK(hi2c);
1763
1764 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1765 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1766 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1767
1768 /* Enable Address Acknowledge */
1769 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1770
1771 /* Prepare transfer parameters */
1772 hi2c->pBuffPtr = pData;
1773 hi2c->XferCount = Size;
1774 hi2c->XferSize = hi2c->XferCount;
1775 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1776 hi2c->XferISR = I2C_Slave_ISR_IT;
1777
1778 /* Process Unlocked */
1779 __HAL_UNLOCK(hi2c);
1780
1781 /* Note : The I2C interrupts must be enabled after unlocking current process
1782 to avoid the risk of I2C interrupt handle execution before current
1783 process unlock */
1784
1785 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1786 /* possible to enable all of these */
1787 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1788 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1789 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
1790
1791 return HAL_OK;
1792 }
1793 else
1794 {
1795 return HAL_BUSY;
1796 }
1797 }
1798
1799 /**
1800 * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
1801 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1802 * the configuration information for the specified I2C.
1803 * @param pData Pointer to data buffer
1804 * @param Size Amount of data to be sent
1805 * @retval HAL status
1806 */
HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1807 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1808 {
1809 if (hi2c->State == HAL_I2C_STATE_READY)
1810 {
1811 /* Process Locked */
1812 __HAL_LOCK(hi2c);
1813
1814 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1815 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1816 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1817
1818 /* Enable Address Acknowledge */
1819 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1820
1821 /* Prepare transfer parameters */
1822 hi2c->pBuffPtr = pData;
1823 hi2c->XferCount = Size;
1824 hi2c->XferSize = hi2c->XferCount;
1825 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1826 hi2c->XferISR = I2C_Slave_ISR_IT;
1827
1828 /* Process Unlocked */
1829 __HAL_UNLOCK(hi2c);
1830
1831 /* Note : The I2C interrupts must be enabled after unlocking current process
1832 to avoid the risk of I2C interrupt handle execution before current
1833 process unlock */
1834
1835 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1836 /* possible to enable all of these */
1837 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1838 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1839 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
1840
1841 return HAL_OK;
1842 }
1843 else
1844 {
1845 return HAL_BUSY;
1846 }
1847 }
1848
1849 /**
1850 * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
1851 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1852 * the configuration information for the specified I2C.
1853 * @param DevAddress Target device address: The device 7 bits address value
1854 * in datasheet must be shifted to the left before calling the interface
1855 * @param pData Pointer to data buffer
1856 * @param Size Amount of data to be sent
1857 * @retval HAL status
1858 */
HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1859 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1860 uint16_t Size)
1861 {
1862 uint32_t xfermode;
1863 HAL_StatusTypeDef dmaxferstatus;
1864
1865 if (hi2c->State == HAL_I2C_STATE_READY)
1866 {
1867 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1868 {
1869 return HAL_BUSY;
1870 }
1871
1872 /* Process Locked */
1873 __HAL_LOCK(hi2c);
1874
1875 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1876 hi2c->Mode = HAL_I2C_MODE_MASTER;
1877 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1878
1879 /* Prepare transfer parameters */
1880 hi2c->pBuffPtr = pData;
1881 hi2c->XferCount = Size;
1882 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1883 hi2c->XferISR = I2C_Master_ISR_DMA;
1884
1885 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1886 {
1887 hi2c->XferSize = MAX_NBYTE_SIZE;
1888 xfermode = I2C_RELOAD_MODE;
1889 }
1890 else
1891 {
1892 hi2c->XferSize = hi2c->XferCount;
1893 xfermode = I2C_AUTOEND_MODE;
1894 }
1895
1896 if (hi2c->XferSize > 0U)
1897 {
1898 if (hi2c->hdmatx != NULL)
1899 {
1900 /* Set the I2C DMA transfer complete callback */
1901 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
1902
1903 /* Set the DMA error callback */
1904 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
1905
1906 /* Set the unused DMA callbacks to NULL */
1907 hi2c->hdmatx->XferHalfCpltCallback = NULL;
1908 hi2c->hdmatx->XferAbortCallback = NULL;
1909
1910 /* Enable the DMA stream */
1911 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
1912 hi2c->XferSize);
1913 }
1914 else
1915 {
1916 /* Update I2C state */
1917 hi2c->State = HAL_I2C_STATE_READY;
1918 hi2c->Mode = HAL_I2C_MODE_NONE;
1919
1920 /* Update I2C error code */
1921 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
1922
1923 /* Process Unlocked */
1924 __HAL_UNLOCK(hi2c);
1925
1926 return HAL_ERROR;
1927 }
1928
1929 if (dmaxferstatus == HAL_OK)
1930 {
1931 /* Send Slave Address */
1932 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1933 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
1934
1935 /* Update XferCount value */
1936 hi2c->XferCount -= hi2c->XferSize;
1937
1938 /* Process Unlocked */
1939 __HAL_UNLOCK(hi2c);
1940
1941 /* Note : The I2C interrupts must be enabled after unlocking current process
1942 to avoid the risk of I2C interrupt handle execution before current
1943 process unlock */
1944 /* Enable ERR and NACK interrupts */
1945 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
1946
1947 /* Enable DMA Request */
1948 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
1949 }
1950 else
1951 {
1952 /* Update I2C state */
1953 hi2c->State = HAL_I2C_STATE_READY;
1954 hi2c->Mode = HAL_I2C_MODE_NONE;
1955
1956 /* Update I2C error code */
1957 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
1958
1959 /* Process Unlocked */
1960 __HAL_UNLOCK(hi2c);
1961
1962 return HAL_ERROR;
1963 }
1964 }
1965 else
1966 {
1967 /* Update Transfer ISR function pointer */
1968 hi2c->XferISR = I2C_Master_ISR_IT;
1969
1970 /* Send Slave Address */
1971 /* Set NBYTES to write and generate START condition */
1972 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1973 I2C_GENERATE_START_WRITE);
1974
1975 /* Process Unlocked */
1976 __HAL_UNLOCK(hi2c);
1977
1978 /* Note : The I2C interrupts must be enabled after unlocking current process
1979 to avoid the risk of I2C interrupt handle execution before current
1980 process unlock */
1981 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1982 /* possible to enable all of these */
1983 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1984 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1985 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
1986 }
1987
1988 return HAL_OK;
1989 }
1990 else
1991 {
1992 return HAL_BUSY;
1993 }
1994 }
1995
1996 /**
1997 * @brief Receive in master mode an amount of data in non-blocking mode with DMA
1998 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1999 * the configuration information for the specified I2C.
2000 * @param DevAddress Target device address: The device 7 bits address value
2001 * in datasheet must be shifted to the left before calling the interface
2002 * @param pData Pointer to data buffer
2003 * @param Size Amount of data to be sent
2004 * @retval HAL status
2005 */
HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)2006 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
2007 uint16_t Size)
2008 {
2009 uint32_t xfermode;
2010 HAL_StatusTypeDef dmaxferstatus;
2011
2012 if (hi2c->State == HAL_I2C_STATE_READY)
2013 {
2014 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2015 {
2016 return HAL_BUSY;
2017 }
2018
2019 /* Process Locked */
2020 __HAL_LOCK(hi2c);
2021
2022 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2023 hi2c->Mode = HAL_I2C_MODE_MASTER;
2024 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2025
2026 /* Prepare transfer parameters */
2027 hi2c->pBuffPtr = pData;
2028 hi2c->XferCount = Size;
2029 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2030 hi2c->XferISR = I2C_Master_ISR_DMA;
2031
2032 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2033 {
2034 hi2c->XferSize = MAX_NBYTE_SIZE;
2035 xfermode = I2C_RELOAD_MODE;
2036 }
2037 else
2038 {
2039 hi2c->XferSize = hi2c->XferCount;
2040 xfermode = I2C_AUTOEND_MODE;
2041 }
2042
2043 if (hi2c->XferSize > 0U)
2044 {
2045 if (hi2c->hdmarx != NULL)
2046 {
2047 /* Set the I2C DMA transfer complete callback */
2048 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
2049
2050 /* Set the DMA error callback */
2051 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2052
2053 /* Set the unused DMA callbacks to NULL */
2054 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2055 hi2c->hdmarx->XferAbortCallback = NULL;
2056
2057 /* Enable the DMA stream */
2058 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
2059 hi2c->XferSize);
2060 }
2061 else
2062 {
2063 /* Update I2C state */
2064 hi2c->State = HAL_I2C_STATE_READY;
2065 hi2c->Mode = HAL_I2C_MODE_NONE;
2066
2067 /* Update I2C error code */
2068 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2069
2070 /* Process Unlocked */
2071 __HAL_UNLOCK(hi2c);
2072
2073 return HAL_ERROR;
2074 }
2075
2076 if (dmaxferstatus == HAL_OK)
2077 {
2078 /* Send Slave Address */
2079 /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2080 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
2081
2082 /* Update XferCount value */
2083 hi2c->XferCount -= hi2c->XferSize;
2084
2085 /* Process Unlocked */
2086 __HAL_UNLOCK(hi2c);
2087
2088 /* Note : The I2C interrupts must be enabled after unlocking current process
2089 to avoid the risk of I2C interrupt handle execution before current
2090 process unlock */
2091 /* Enable ERR and NACK interrupts */
2092 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
2093
2094 /* Enable DMA Request */
2095 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2096 }
2097 else
2098 {
2099 /* Update I2C state */
2100 hi2c->State = HAL_I2C_STATE_READY;
2101 hi2c->Mode = HAL_I2C_MODE_NONE;
2102
2103 /* Update I2C error code */
2104 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2105
2106 /* Process Unlocked */
2107 __HAL_UNLOCK(hi2c);
2108
2109 return HAL_ERROR;
2110 }
2111 }
2112 else
2113 {
2114 /* Update Transfer ISR function pointer */
2115 hi2c->XferISR = I2C_Master_ISR_IT;
2116
2117 /* Send Slave Address */
2118 /* Set NBYTES to read and generate START condition */
2119 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2120 I2C_GENERATE_START_READ);
2121
2122 /* Process Unlocked */
2123 __HAL_UNLOCK(hi2c);
2124
2125 /* Note : The I2C interrupts must be enabled after unlocking current process
2126 to avoid the risk of I2C interrupt handle execution before current
2127 process unlock */
2128 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2129 /* possible to enable all of these */
2130 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2131 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2132 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2133 }
2134
2135 return HAL_OK;
2136 }
2137 else
2138 {
2139 return HAL_BUSY;
2140 }
2141 }
2142
2143 /**
2144 * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
2145 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2146 * the configuration information for the specified I2C.
2147 * @param pData Pointer to data buffer
2148 * @param Size Amount of data to be sent
2149 * @retval HAL status
2150 */
HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2151 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2152 {
2153 HAL_StatusTypeDef dmaxferstatus;
2154
2155 if (hi2c->State == HAL_I2C_STATE_READY)
2156 {
2157 if ((pData == NULL) || (Size == 0U))
2158 {
2159 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2160 return HAL_ERROR;
2161 }
2162 /* Process Locked */
2163 __HAL_LOCK(hi2c);
2164
2165 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2166 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2167 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2168
2169 /* Prepare transfer parameters */
2170 hi2c->pBuffPtr = pData;
2171 hi2c->XferCount = Size;
2172 hi2c->XferSize = hi2c->XferCount;
2173 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2174 hi2c->XferISR = I2C_Slave_ISR_DMA;
2175
2176 if (hi2c->hdmatx != NULL)
2177 {
2178 /* Set the I2C DMA transfer complete callback */
2179 hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
2180
2181 /* Set the DMA error callback */
2182 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2183
2184 /* Set the unused DMA callbacks to NULL */
2185 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2186 hi2c->hdmatx->XferAbortCallback = NULL;
2187
2188 /* Enable the DMA stream */
2189 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
2190 hi2c->XferSize);
2191 }
2192 else
2193 {
2194 /* Update I2C state */
2195 hi2c->State = HAL_I2C_STATE_LISTEN;
2196 hi2c->Mode = HAL_I2C_MODE_NONE;
2197
2198 /* Update I2C error code */
2199 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2200
2201 /* Process Unlocked */
2202 __HAL_UNLOCK(hi2c);
2203
2204 return HAL_ERROR;
2205 }
2206
2207 if (dmaxferstatus == HAL_OK)
2208 {
2209 /* Enable Address Acknowledge */
2210 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2211
2212 /* Process Unlocked */
2213 __HAL_UNLOCK(hi2c);
2214
2215 /* Note : The I2C interrupts must be enabled after unlocking current process
2216 to avoid the risk of I2C interrupt handle execution before current
2217 process unlock */
2218 /* Enable ERR, STOP, NACK, ADDR interrupts */
2219 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2220
2221 /* Enable DMA Request */
2222 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
2223 }
2224 else
2225 {
2226 /* Update I2C state */
2227 hi2c->State = HAL_I2C_STATE_LISTEN;
2228 hi2c->Mode = HAL_I2C_MODE_NONE;
2229
2230 /* Update I2C error code */
2231 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2232
2233 /* Process Unlocked */
2234 __HAL_UNLOCK(hi2c);
2235
2236 return HAL_ERROR;
2237 }
2238
2239 return HAL_OK;
2240 }
2241 else
2242 {
2243 return HAL_BUSY;
2244 }
2245 }
2246
2247 /**
2248 * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
2249 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2250 * the configuration information for the specified I2C.
2251 * @param pData Pointer to data buffer
2252 * @param Size Amount of data to be sent
2253 * @retval HAL status
2254 */
HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2255 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2256 {
2257 HAL_StatusTypeDef dmaxferstatus;
2258
2259 if (hi2c->State == HAL_I2C_STATE_READY)
2260 {
2261 if ((pData == NULL) || (Size == 0U))
2262 {
2263 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2264 return HAL_ERROR;
2265 }
2266 /* Process Locked */
2267 __HAL_LOCK(hi2c);
2268
2269 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2270 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2271 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2272
2273 /* Prepare transfer parameters */
2274 hi2c->pBuffPtr = pData;
2275 hi2c->XferCount = Size;
2276 hi2c->XferSize = hi2c->XferCount;
2277 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2278 hi2c->XferISR = I2C_Slave_ISR_DMA;
2279
2280 if (hi2c->hdmarx != NULL)
2281 {
2282 /* Set the I2C DMA transfer complete callback */
2283 hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
2284
2285 /* Set the DMA error callback */
2286 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2287
2288 /* Set the unused DMA callbacks to NULL */
2289 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2290 hi2c->hdmarx->XferAbortCallback = NULL;
2291
2292 /* Enable the DMA stream */
2293 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
2294 hi2c->XferSize);
2295 }
2296 else
2297 {
2298 /* Update I2C state */
2299 hi2c->State = HAL_I2C_STATE_LISTEN;
2300 hi2c->Mode = HAL_I2C_MODE_NONE;
2301
2302 /* Update I2C error code */
2303 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2304
2305 /* Process Unlocked */
2306 __HAL_UNLOCK(hi2c);
2307
2308 return HAL_ERROR;
2309 }
2310
2311 if (dmaxferstatus == HAL_OK)
2312 {
2313 /* Enable Address Acknowledge */
2314 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2315
2316 /* Process Unlocked */
2317 __HAL_UNLOCK(hi2c);
2318
2319 /* Note : The I2C interrupts must be enabled after unlocking current process
2320 to avoid the risk of I2C interrupt handle execution before current
2321 process unlock */
2322 /* Enable ERR, STOP, NACK, ADDR interrupts */
2323 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2324
2325 /* Enable DMA Request */
2326 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2327 }
2328 else
2329 {
2330 /* Update I2C state */
2331 hi2c->State = HAL_I2C_STATE_LISTEN;
2332 hi2c->Mode = HAL_I2C_MODE_NONE;
2333
2334 /* Update I2C error code */
2335 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2336
2337 /* Process Unlocked */
2338 __HAL_UNLOCK(hi2c);
2339
2340 return HAL_ERROR;
2341 }
2342
2343 return HAL_OK;
2344 }
2345 else
2346 {
2347 return HAL_BUSY;
2348 }
2349 }
2350 /**
2351 * @brief Write an amount of data in blocking mode to a specific memory address
2352 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2353 * the configuration information for the specified I2C.
2354 * @param DevAddress Target device address: The device 7 bits address value
2355 * in datasheet must be shifted to the left before calling the interface
2356 * @param MemAddress Internal memory address
2357 * @param MemAddSize Size of internal memory address
2358 * @param pData Pointer to data buffer
2359 * @param Size Amount of data to be sent
2360 * @param Timeout Timeout duration
2361 * @retval HAL status
2362 */
HAL_I2C_Mem_Write(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2363 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2364 uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2365 {
2366 uint32_t tickstart;
2367
2368 /* Check the parameters */
2369 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2370
2371 if (hi2c->State == HAL_I2C_STATE_READY)
2372 {
2373 if ((pData == NULL) || (Size == 0U))
2374 {
2375 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2376 return HAL_ERROR;
2377 }
2378
2379 /* Process Locked */
2380 __HAL_LOCK(hi2c);
2381
2382 /* Init tickstart for timeout management*/
2383 tickstart = HAL_GetTick();
2384
2385 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
2386 {
2387 return HAL_ERROR;
2388 }
2389
2390 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2391 hi2c->Mode = HAL_I2C_MODE_MEM;
2392 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2393
2394 /* Prepare transfer parameters */
2395 hi2c->pBuffPtr = pData;
2396 hi2c->XferCount = Size;
2397 hi2c->XferISR = NULL;
2398
2399 /* Send Slave Address and Memory Address */
2400 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2401 {
2402 /* Process Unlocked */
2403 __HAL_UNLOCK(hi2c);
2404 return HAL_ERROR;
2405 }
2406
2407 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
2408 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2409 {
2410 hi2c->XferSize = MAX_NBYTE_SIZE;
2411 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
2412 }
2413 else
2414 {
2415 hi2c->XferSize = hi2c->XferCount;
2416 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
2417 }
2418
2419 do
2420 {
2421 /* Wait until TXIS flag is set */
2422 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2423 {
2424 return HAL_ERROR;
2425 }
2426
2427 /* Write data to TXDR */
2428 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
2429
2430 /* Increment Buffer pointer */
2431 hi2c->pBuffPtr++;
2432
2433 hi2c->XferCount--;
2434 hi2c->XferSize--;
2435
2436 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
2437 {
2438 /* Wait until TCR flag is set */
2439 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
2440 {
2441 return HAL_ERROR;
2442 }
2443
2444 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2445 {
2446 hi2c->XferSize = MAX_NBYTE_SIZE;
2447 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
2448 I2C_NO_STARTSTOP);
2449 }
2450 else
2451 {
2452 hi2c->XferSize = hi2c->XferCount;
2453 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2454 I2C_NO_STARTSTOP);
2455 }
2456 }
2457
2458 } while (hi2c->XferCount > 0U);
2459
2460 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
2461 /* Wait until STOPF flag is reset */
2462 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2463 {
2464 return HAL_ERROR;
2465 }
2466
2467 /* Clear STOP Flag */
2468 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2469
2470 /* Clear Configuration Register 2 */
2471 I2C_RESET_CR2(hi2c);
2472
2473 hi2c->State = HAL_I2C_STATE_READY;
2474 hi2c->Mode = HAL_I2C_MODE_NONE;
2475
2476 /* Process Unlocked */
2477 __HAL_UNLOCK(hi2c);
2478
2479 return HAL_OK;
2480 }
2481 else
2482 {
2483 return HAL_BUSY;
2484 }
2485 }
2486
2487 /**
2488 * @brief Read an amount of data in blocking mode from a specific memory address
2489 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2490 * the configuration information for the specified I2C.
2491 * @param DevAddress Target device address: The device 7 bits address value
2492 * in datasheet must be shifted to the left before calling the interface
2493 * @param MemAddress Internal memory address
2494 * @param MemAddSize Size of internal memory address
2495 * @param pData Pointer to data buffer
2496 * @param Size Amount of data to be sent
2497 * @param Timeout Timeout duration
2498 * @retval HAL status
2499 */
HAL_I2C_Mem_Read(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2500 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2501 uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2502 {
2503 uint32_t tickstart;
2504
2505 /* Check the parameters */
2506 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2507
2508 if (hi2c->State == HAL_I2C_STATE_READY)
2509 {
2510 if ((pData == NULL) || (Size == 0U))
2511 {
2512 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2513 return HAL_ERROR;
2514 }
2515
2516 /* Process Locked */
2517 __HAL_LOCK(hi2c);
2518
2519 /* Init tickstart for timeout management*/
2520 tickstart = HAL_GetTick();
2521
2522 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
2523 {
2524 return HAL_ERROR;
2525 }
2526
2527 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2528 hi2c->Mode = HAL_I2C_MODE_MEM;
2529 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2530
2531 /* Prepare transfer parameters */
2532 hi2c->pBuffPtr = pData;
2533 hi2c->XferCount = Size;
2534 hi2c->XferISR = NULL;
2535
2536 /* Send Slave Address and Memory Address */
2537 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2538 {
2539 /* Process Unlocked */
2540 __HAL_UNLOCK(hi2c);
2541 return HAL_ERROR;
2542 }
2543
2544 /* Send Slave Address */
2545 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2546 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2547 {
2548 hi2c->XferSize = MAX_NBYTE_SIZE;
2549 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
2550 I2C_GENERATE_START_READ);
2551 }
2552 else
2553 {
2554 hi2c->XferSize = hi2c->XferCount;
2555 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2556 I2C_GENERATE_START_READ);
2557 }
2558
2559 do
2560 {
2561 /* Wait until RXNE flag is set */
2562 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
2563 {
2564 return HAL_ERROR;
2565 }
2566
2567 /* Read data from RXDR */
2568 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
2569
2570 /* Increment Buffer pointer */
2571 hi2c->pBuffPtr++;
2572
2573 hi2c->XferSize--;
2574 hi2c->XferCount--;
2575
2576 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
2577 {
2578 /* Wait until TCR flag is set */
2579 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
2580 {
2581 return HAL_ERROR;
2582 }
2583
2584 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2585 {
2586 hi2c->XferSize = MAX_NBYTE_SIZE;
2587 I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
2588 I2C_NO_STARTSTOP);
2589 }
2590 else
2591 {
2592 hi2c->XferSize = hi2c->XferCount;
2593 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2594 I2C_NO_STARTSTOP);
2595 }
2596 }
2597 } while (hi2c->XferCount > 0U);
2598
2599 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
2600 /* Wait until STOPF flag is reset */
2601 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2602 {
2603 return HAL_ERROR;
2604 }
2605
2606 /* Clear STOP Flag */
2607 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2608
2609 /* Clear Configuration Register 2 */
2610 I2C_RESET_CR2(hi2c);
2611
2612 hi2c->State = HAL_I2C_STATE_READY;
2613 hi2c->Mode = HAL_I2C_MODE_NONE;
2614
2615 /* Process Unlocked */
2616 __HAL_UNLOCK(hi2c);
2617
2618 return HAL_OK;
2619 }
2620 else
2621 {
2622 return HAL_BUSY;
2623 }
2624 }
2625 /**
2626 * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
2627 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2628 * the configuration information for the specified I2C.
2629 * @param DevAddress Target device address: The device 7 bits address value
2630 * in datasheet must be shifted to the left before calling the interface
2631 * @param MemAddress Internal memory address
2632 * @param MemAddSize Size of internal memory address
2633 * @param pData Pointer to data buffer
2634 * @param Size Amount of data to be sent
2635 * @retval HAL status
2636 */
HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2637 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2638 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2639 {
2640 /* Check the parameters */
2641 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2642
2643 if (hi2c->State == HAL_I2C_STATE_READY)
2644 {
2645 if ((pData == NULL) || (Size == 0U))
2646 {
2647 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2648 return HAL_ERROR;
2649 }
2650
2651 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2652 {
2653 return HAL_BUSY;
2654 }
2655
2656 /* Process Locked */
2657 __HAL_LOCK(hi2c);
2658
2659 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2660 hi2c->Mode = HAL_I2C_MODE_MEM;
2661 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2662
2663 /* Prepare transfer parameters */
2664 hi2c->pBuffPtr = pData;
2665 hi2c->XferCount = Size;
2666 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2667 hi2c->XferISR = I2C_Mem_ISR_IT;
2668 hi2c->Devaddress = DevAddress;
2669
2670 /* If Memory address size is 8Bit */
2671 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
2672 {
2673 /* Prefetch Memory Address */
2674 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
2675
2676 /* Reset Memaddress content */
2677 hi2c->Memaddress = 0xFFFFFFFFU;
2678 }
2679 /* If Memory address size is 16Bit */
2680 else
2681 {
2682 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
2683 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
2684
2685 /* Prepare Memaddress buffer for LSB part */
2686 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
2687 }
2688 /* Send Slave Address and Memory Address */
2689 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
2690
2691 /* Process Unlocked */
2692 __HAL_UNLOCK(hi2c);
2693
2694 /* Note : The I2C interrupts must be enabled after unlocking current process
2695 to avoid the risk of I2C interrupt handle execution before current
2696 process unlock */
2697
2698 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2699 /* possible to enable all of these */
2700 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2701 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2702 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2703
2704 return HAL_OK;
2705 }
2706 else
2707 {
2708 return HAL_BUSY;
2709 }
2710 }
2711
2712 /**
2713 * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
2714 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2715 * the configuration information for the specified I2C.
2716 * @param DevAddress Target device address: The device 7 bits address value
2717 * in datasheet must be shifted to the left before calling the interface
2718 * @param MemAddress Internal memory address
2719 * @param MemAddSize Size of internal memory address
2720 * @param pData Pointer to data buffer
2721 * @param Size Amount of data to be sent
2722 * @retval HAL status
2723 */
HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2724 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2725 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2726 {
2727 /* Check the parameters */
2728 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2729
2730 if (hi2c->State == HAL_I2C_STATE_READY)
2731 {
2732 if ((pData == NULL) || (Size == 0U))
2733 {
2734 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2735 return HAL_ERROR;
2736 }
2737
2738 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2739 {
2740 return HAL_BUSY;
2741 }
2742
2743 /* Process Locked */
2744 __HAL_LOCK(hi2c);
2745
2746 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2747 hi2c->Mode = HAL_I2C_MODE_MEM;
2748 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2749
2750 /* Prepare transfer parameters */
2751 hi2c->pBuffPtr = pData;
2752 hi2c->XferCount = Size;
2753 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2754 hi2c->XferISR = I2C_Mem_ISR_IT;
2755 hi2c->Devaddress = DevAddress;
2756
2757 /* If Memory address size is 8Bit */
2758 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
2759 {
2760 /* Prefetch Memory Address */
2761 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
2762
2763 /* Reset Memaddress content */
2764 hi2c->Memaddress = 0xFFFFFFFFU;
2765 }
2766 /* If Memory address size is 16Bit */
2767 else
2768 {
2769 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
2770 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
2771
2772 /* Prepare Memaddress buffer for LSB part */
2773 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
2774 }
2775 /* Send Slave Address and Memory Address */
2776 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
2777
2778 /* Process Unlocked */
2779 __HAL_UNLOCK(hi2c);
2780
2781 /* Note : The I2C interrupts must be enabled after unlocking current process
2782 to avoid the risk of I2C interrupt handle execution before current
2783 process unlock */
2784
2785 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
2786 /* possible to enable all of these */
2787 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2788 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2789 I2C_Enable_IRQ(hi2c, (I2C_XFER_TX_IT | I2C_XFER_RX_IT));
2790
2791 return HAL_OK;
2792 }
2793 else
2794 {
2795 return HAL_BUSY;
2796 }
2797 }
2798 /**
2799 * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
2800 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2801 * the configuration information for the specified I2C.
2802 * @param DevAddress Target device address: The device 7 bits address value
2803 * in datasheet must be shifted to the left before calling the interface
2804 * @param MemAddress Internal memory address
2805 * @param MemAddSize Size of internal memory address
2806 * @param pData Pointer to data buffer
2807 * @param Size Amount of data to be sent
2808 * @retval HAL status
2809 */
HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2810 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2811 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2812 {
2813 HAL_StatusTypeDef dmaxferstatus;
2814
2815 /* Check the parameters */
2816 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2817
2818 if (hi2c->State == HAL_I2C_STATE_READY)
2819 {
2820 if ((pData == NULL) || (Size == 0U))
2821 {
2822 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2823 return HAL_ERROR;
2824 }
2825
2826 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2827 {
2828 return HAL_BUSY;
2829 }
2830
2831 /* Process Locked */
2832 __HAL_LOCK(hi2c);
2833
2834 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2835 hi2c->Mode = HAL_I2C_MODE_MEM;
2836 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2837
2838 /* Prepare transfer parameters */
2839 hi2c->pBuffPtr = pData;
2840 hi2c->XferCount = Size;
2841 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2842 hi2c->XferISR = I2C_Mem_ISR_DMA;
2843 hi2c->Devaddress = DevAddress;
2844
2845 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2846 {
2847 hi2c->XferSize = MAX_NBYTE_SIZE;
2848 }
2849 else
2850 {
2851 hi2c->XferSize = hi2c->XferCount;
2852 }
2853
2854 /* If Memory address size is 8Bit */
2855 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
2856 {
2857 /* Prefetch Memory Address */
2858 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
2859
2860 /* Reset Memaddress content */
2861 hi2c->Memaddress = 0xFFFFFFFFU;
2862 }
2863 /* If Memory address size is 16Bit */
2864 else
2865 {
2866 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
2867 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
2868
2869 /* Prepare Memaddress buffer for LSB part */
2870 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
2871 }
2872
2873 if (hi2c->hdmatx != NULL)
2874 {
2875 /* Set the I2C DMA transfer complete callback */
2876 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
2877
2878 /* Set the DMA error callback */
2879 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2880
2881 /* Set the unused DMA callbacks to NULL */
2882 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2883 hi2c->hdmatx->XferAbortCallback = NULL;
2884
2885 /* Enable the DMA stream */
2886 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
2887 hi2c->XferSize);
2888 }
2889 else
2890 {
2891 /* Update I2C state */
2892 hi2c->State = HAL_I2C_STATE_READY;
2893 hi2c->Mode = HAL_I2C_MODE_NONE;
2894
2895 /* Update I2C error code */
2896 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2897
2898 /* Process Unlocked */
2899 __HAL_UNLOCK(hi2c);
2900
2901 return HAL_ERROR;
2902 }
2903
2904 if (dmaxferstatus == HAL_OK)
2905 {
2906 /* Send Slave Address and Memory Address */
2907 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
2908
2909 /* Process Unlocked */
2910 __HAL_UNLOCK(hi2c);
2911
2912 /* Note : The I2C interrupts must be enabled after unlocking current process
2913 to avoid the risk of I2C interrupt handle execution before current
2914 process unlock */
2915 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2916 /* possible to enable all of these */
2917 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2918 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2919 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2920 }
2921 else
2922 {
2923 /* Update I2C state */
2924 hi2c->State = HAL_I2C_STATE_READY;
2925 hi2c->Mode = HAL_I2C_MODE_NONE;
2926
2927 /* Update I2C error code */
2928 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2929
2930 /* Process Unlocked */
2931 __HAL_UNLOCK(hi2c);
2932
2933 return HAL_ERROR;
2934 }
2935
2936 return HAL_OK;
2937 }
2938 else
2939 {
2940 return HAL_BUSY;
2941 }
2942 }
2943
2944 /**
2945 * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
2946 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2947 * the configuration information for the specified I2C.
2948 * @param DevAddress Target device address: The device 7 bits address value
2949 * in datasheet must be shifted to the left before calling the interface
2950 * @param MemAddress Internal memory address
2951 * @param MemAddSize Size of internal memory address
2952 * @param pData Pointer to data buffer
2953 * @param Size Amount of data to be read
2954 * @retval HAL status
2955 */
HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2956 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2957 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2958 {
2959 HAL_StatusTypeDef dmaxferstatus;
2960
2961 /* Check the parameters */
2962 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2963
2964 if (hi2c->State == HAL_I2C_STATE_READY)
2965 {
2966 if ((pData == NULL) || (Size == 0U))
2967 {
2968 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2969 return HAL_ERROR;
2970 }
2971
2972 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2973 {
2974 return HAL_BUSY;
2975 }
2976
2977 /* Process Locked */
2978 __HAL_LOCK(hi2c);
2979
2980 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2981 hi2c->Mode = HAL_I2C_MODE_MEM;
2982 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2983
2984 /* Prepare transfer parameters */
2985 hi2c->pBuffPtr = pData;
2986 hi2c->XferCount = Size;
2987 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2988 hi2c->XferISR = I2C_Mem_ISR_DMA;
2989 hi2c->Devaddress = DevAddress;
2990
2991 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2992 {
2993 hi2c->XferSize = MAX_NBYTE_SIZE;
2994 }
2995 else
2996 {
2997 hi2c->XferSize = hi2c->XferCount;
2998 }
2999
3000 /* If Memory address size is 8Bit */
3001 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
3002 {
3003 /* Prefetch Memory Address */
3004 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3005
3006 /* Reset Memaddress content */
3007 hi2c->Memaddress = 0xFFFFFFFFU;
3008 }
3009 /* If Memory address size is 16Bit */
3010 else
3011 {
3012 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
3013 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
3014
3015 /* Prepare Memaddress buffer for LSB part */
3016 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
3017 }
3018
3019 if (hi2c->hdmarx != NULL)
3020 {
3021 /* Set the I2C DMA transfer complete callback */
3022 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
3023
3024 /* Set the DMA error callback */
3025 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3026
3027 /* Set the unused DMA callbacks to NULL */
3028 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3029 hi2c->hdmarx->XferAbortCallback = NULL;
3030
3031 /* Enable the DMA stream */
3032 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
3033 hi2c->XferSize);
3034 }
3035 else
3036 {
3037 /* Update I2C state */
3038 hi2c->State = HAL_I2C_STATE_READY;
3039 hi2c->Mode = HAL_I2C_MODE_NONE;
3040
3041 /* Update I2C error code */
3042 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3043
3044 /* Process Unlocked */
3045 __HAL_UNLOCK(hi2c);
3046
3047 return HAL_ERROR;
3048 }
3049
3050 if (dmaxferstatus == HAL_OK)
3051 {
3052 /* Send Slave Address and Memory Address */
3053 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
3054
3055 /* Process Unlocked */
3056 __HAL_UNLOCK(hi2c);
3057
3058 /* Note : The I2C interrupts must be enabled after unlocking current process
3059 to avoid the risk of I2C interrupt handle execution before current
3060 process unlock */
3061 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3062 /* possible to enable all of these */
3063 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3064 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3065 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3066 }
3067 else
3068 {
3069 /* Update I2C state */
3070 hi2c->State = HAL_I2C_STATE_READY;
3071 hi2c->Mode = HAL_I2C_MODE_NONE;
3072
3073 /* Update I2C error code */
3074 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3075
3076 /* Process Unlocked */
3077 __HAL_UNLOCK(hi2c);
3078
3079 return HAL_ERROR;
3080 }
3081
3082 return HAL_OK;
3083 }
3084 else
3085 {
3086 return HAL_BUSY;
3087 }
3088 }
3089
3090 /**
3091 * @brief Checks if target device is ready for communication.
3092 * @note This function is used with Memory devices
3093 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3094 * the configuration information for the specified I2C.
3095 * @param DevAddress Target device address: The device 7 bits address value
3096 * in datasheet must be shifted to the left before calling the interface
3097 * @param Trials Number of trials
3098 * @param Timeout Timeout duration
3099 * @retval HAL status
3100 */
HAL_I2C_IsDeviceReady(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Trials,uint32_t Timeout)3101 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
3102 uint32_t Timeout)
3103 {
3104 uint32_t tickstart;
3105
3106 __IO uint32_t I2C_Trials = 0UL;
3107
3108 FlagStatus tmp1;
3109 FlagStatus tmp2;
3110
3111 if (hi2c->State == HAL_I2C_STATE_READY)
3112 {
3113 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
3114 {
3115 return HAL_BUSY;
3116 }
3117
3118 /* Process Locked */
3119 __HAL_LOCK(hi2c);
3120
3121 hi2c->State = HAL_I2C_STATE_BUSY;
3122 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3123
3124 do
3125 {
3126 /* Generate Start */
3127 hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
3128
3129 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
3130 /* Wait until STOPF flag is set or a NACK flag is set*/
3131 tickstart = HAL_GetTick();
3132
3133 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
3134 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3135
3136 while ((tmp1 == RESET) && (tmp2 == RESET))
3137 {
3138 if (Timeout != HAL_MAX_DELAY)
3139 {
3140 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3141 {
3142 /* Update I2C state */
3143 hi2c->State = HAL_I2C_STATE_READY;
3144
3145 /* Update I2C error code */
3146 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3147
3148 /* Process Unlocked */
3149 __HAL_UNLOCK(hi2c);
3150
3151 return HAL_ERROR;
3152 }
3153 }
3154
3155 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
3156 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3157 }
3158
3159 /* Check if the NACKF flag has not been set */
3160 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
3161 {
3162 /* Wait until STOPF flag is reset */
3163 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3164 {
3165 return HAL_ERROR;
3166 }
3167
3168 /* Clear STOP Flag */
3169 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3170
3171 /* Device is ready */
3172 hi2c->State = HAL_I2C_STATE_READY;
3173
3174 /* Process Unlocked */
3175 __HAL_UNLOCK(hi2c);
3176
3177 return HAL_OK;
3178 }
3179 else
3180 {
3181 /* Wait until STOPF flag is reset */
3182 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3183 {
3184 return HAL_ERROR;
3185 }
3186
3187 /* Clear NACK Flag */
3188 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3189
3190 /* Clear STOP Flag, auto generated with autoend*/
3191 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3192 }
3193
3194 /* Check if the maximum allowed number of trials has been reached */
3195 if (I2C_Trials == Trials)
3196 {
3197 /* Generate Stop */
3198 hi2c->Instance->CR2 |= I2C_CR2_STOP;
3199
3200 /* Wait until STOPF flag is reset */
3201 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3202 {
3203 return HAL_ERROR;
3204 }
3205
3206 /* Clear STOP Flag */
3207 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3208 }
3209
3210 /* Increment Trials */
3211 I2C_Trials++;
3212 } while (I2C_Trials < Trials);
3213
3214 /* Update I2C state */
3215 hi2c->State = HAL_I2C_STATE_READY;
3216
3217 /* Update I2C error code */
3218 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3219
3220 /* Process Unlocked */
3221 __HAL_UNLOCK(hi2c);
3222
3223 return HAL_ERROR;
3224 }
3225 else
3226 {
3227 return HAL_BUSY;
3228 }
3229 }
3230
3231 /**
3232 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
3233 * @note This interface allow to manage repeated start condition when a direction change during transfer
3234 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3235 * the configuration information for the specified I2C.
3236 * @param DevAddress Target device address: The device 7 bits address value
3237 * in datasheet must be shifted to the left before calling the interface
3238 * @param pData Pointer to data buffer
3239 * @param Size Amount of data to be sent
3240 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3241 * @retval HAL status
3242 */
HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3243 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3244 uint16_t Size, uint32_t XferOptions)
3245 {
3246 uint32_t xfermode;
3247 uint32_t xferrequest = I2C_GENERATE_START_WRITE;
3248
3249 /* Check the parameters */
3250 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3251
3252 if (hi2c->State == HAL_I2C_STATE_READY)
3253 {
3254 /* Process Locked */
3255 __HAL_LOCK(hi2c);
3256
3257 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3258 hi2c->Mode = HAL_I2C_MODE_MASTER;
3259 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3260
3261 /* Prepare transfer parameters */
3262 hi2c->pBuffPtr = pData;
3263 hi2c->XferCount = Size;
3264 hi2c->XferOptions = XferOptions;
3265 hi2c->XferISR = I2C_Master_ISR_IT;
3266
3267 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3268 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3269 {
3270 hi2c->XferSize = MAX_NBYTE_SIZE;
3271 xfermode = I2C_RELOAD_MODE;
3272 }
3273 else
3274 {
3275 hi2c->XferSize = hi2c->XferCount;
3276 xfermode = hi2c->XferOptions;
3277 }
3278
3279 /* If transfer direction not change and there is no request to start another frame,
3280 do not generate Restart Condition */
3281 /* Mean Previous state is same as current state */
3282 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
3283 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3284 {
3285 xferrequest = I2C_NO_STARTSTOP;
3286 }
3287 else
3288 {
3289 /* Convert OTHER_xxx XferOptions if any */
3290 I2C_ConvertOtherXferOptions(hi2c);
3291
3292 /* Update xfermode accordingly if no reload is necessary */
3293 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3294 {
3295 xfermode = hi2c->XferOptions;
3296 }
3297 }
3298
3299 /* Send Slave Address and set NBYTES to write */
3300 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3301
3302 /* Process Unlocked */
3303 __HAL_UNLOCK(hi2c);
3304
3305 /* Note : The I2C interrupts must be enabled after unlocking current process
3306 to avoid the risk of I2C interrupt handle execution before current
3307 process unlock */
3308 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3309 /* possible to enable all of these */
3310 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3311 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3312 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3313
3314 return HAL_OK;
3315 }
3316 else
3317 {
3318 return HAL_BUSY;
3319 }
3320 }
3321
3322 /**
3323 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
3324 * @note This interface allow to manage repeated start condition when a direction change during transfer
3325 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3326 * the configuration information for the specified I2C.
3327 * @param DevAddress Target device address: The device 7 bits address value
3328 * in datasheet must be shifted to the left before calling the interface
3329 * @param pData Pointer to data buffer
3330 * @param Size Amount of data to be sent
3331 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3332 * @retval HAL status
3333 */
HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3334 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3335 uint16_t Size, uint32_t XferOptions)
3336 {
3337 uint32_t xfermode;
3338 uint32_t xferrequest = I2C_GENERATE_START_WRITE;
3339 HAL_StatusTypeDef dmaxferstatus;
3340
3341 /* Check the parameters */
3342 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3343
3344 if (hi2c->State == HAL_I2C_STATE_READY)
3345 {
3346 /* Process Locked */
3347 __HAL_LOCK(hi2c);
3348
3349 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3350 hi2c->Mode = HAL_I2C_MODE_MASTER;
3351 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3352
3353 /* Prepare transfer parameters */
3354 hi2c->pBuffPtr = pData;
3355 hi2c->XferCount = Size;
3356 hi2c->XferOptions = XferOptions;
3357 hi2c->XferISR = I2C_Master_ISR_DMA;
3358
3359 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3360 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3361 {
3362 hi2c->XferSize = MAX_NBYTE_SIZE;
3363 xfermode = I2C_RELOAD_MODE;
3364 }
3365 else
3366 {
3367 hi2c->XferSize = hi2c->XferCount;
3368 xfermode = hi2c->XferOptions;
3369 }
3370
3371 /* If transfer direction not change and there is no request to start another frame,
3372 do not generate Restart Condition */
3373 /* Mean Previous state is same as current state */
3374 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
3375 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3376 {
3377 xferrequest = I2C_NO_STARTSTOP;
3378 }
3379 else
3380 {
3381 /* Convert OTHER_xxx XferOptions if any */
3382 I2C_ConvertOtherXferOptions(hi2c);
3383
3384 /* Update xfermode accordingly if no reload is necessary */
3385 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3386 {
3387 xfermode = hi2c->XferOptions;
3388 }
3389 }
3390
3391 if (hi2c->XferSize > 0U)
3392 {
3393 if (hi2c->hdmatx != NULL)
3394 {
3395 /* Set the I2C DMA transfer complete callback */
3396 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
3397
3398 /* Set the DMA error callback */
3399 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3400
3401 /* Set the unused DMA callbacks to NULL */
3402 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3403 hi2c->hdmatx->XferAbortCallback = NULL;
3404
3405 /* Enable the DMA stream */
3406 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
3407 hi2c->XferSize);
3408 }
3409 else
3410 {
3411 /* Update I2C state */
3412 hi2c->State = HAL_I2C_STATE_READY;
3413 hi2c->Mode = HAL_I2C_MODE_NONE;
3414
3415 /* Update I2C error code */
3416 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3417
3418 /* Process Unlocked */
3419 __HAL_UNLOCK(hi2c);
3420
3421 return HAL_ERROR;
3422 }
3423
3424 if (dmaxferstatus == HAL_OK)
3425 {
3426 /* Send Slave Address and set NBYTES to write */
3427 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3428
3429 /* Update XferCount value */
3430 hi2c->XferCount -= hi2c->XferSize;
3431
3432 /* Process Unlocked */
3433 __HAL_UNLOCK(hi2c);
3434
3435 /* Note : The I2C interrupts must be enabled after unlocking current process
3436 to avoid the risk of I2C interrupt handle execution before current
3437 process unlock */
3438 /* Enable ERR and NACK interrupts */
3439 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
3440
3441 /* Enable DMA Request */
3442 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
3443 }
3444 else
3445 {
3446 /* Update I2C state */
3447 hi2c->State = HAL_I2C_STATE_READY;
3448 hi2c->Mode = HAL_I2C_MODE_NONE;
3449
3450 /* Update I2C error code */
3451 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3452
3453 /* Process Unlocked */
3454 __HAL_UNLOCK(hi2c);
3455
3456 return HAL_ERROR;
3457 }
3458 }
3459 else
3460 {
3461 /* Update Transfer ISR function pointer */
3462 hi2c->XferISR = I2C_Master_ISR_IT;
3463
3464 /* Send Slave Address */
3465 /* Set NBYTES to write and generate START condition */
3466 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
3467 I2C_GENERATE_START_WRITE);
3468
3469 /* Process Unlocked */
3470 __HAL_UNLOCK(hi2c);
3471
3472 /* Note : The I2C interrupts must be enabled after unlocking current process
3473 to avoid the risk of I2C interrupt handle execution before current
3474 process unlock */
3475 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3476 /* possible to enable all of these */
3477 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3478 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3479 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3480 }
3481
3482 return HAL_OK;
3483 }
3484 else
3485 {
3486 return HAL_BUSY;
3487 }
3488 }
3489
3490 /**
3491 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
3492 * @note This interface allow to manage repeated start condition when a direction change during transfer
3493 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3494 * the configuration information for the specified I2C.
3495 * @param DevAddress Target device address: The device 7 bits address value
3496 * in datasheet must be shifted to the left before calling the interface
3497 * @param pData Pointer to data buffer
3498 * @param Size Amount of data to be sent
3499 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3500 * @retval HAL status
3501 */
HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3502 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3503 uint16_t Size, uint32_t XferOptions)
3504 {
3505 uint32_t xfermode;
3506 uint32_t xferrequest = I2C_GENERATE_START_READ;
3507
3508 /* Check the parameters */
3509 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3510
3511 if (hi2c->State == HAL_I2C_STATE_READY)
3512 {
3513 /* Process Locked */
3514 __HAL_LOCK(hi2c);
3515
3516 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3517 hi2c->Mode = HAL_I2C_MODE_MASTER;
3518 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3519
3520 /* Prepare transfer parameters */
3521 hi2c->pBuffPtr = pData;
3522 hi2c->XferCount = Size;
3523 hi2c->XferOptions = XferOptions;
3524 hi2c->XferISR = I2C_Master_ISR_IT;
3525
3526 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3527 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3528 {
3529 hi2c->XferSize = MAX_NBYTE_SIZE;
3530 xfermode = I2C_RELOAD_MODE;
3531 }
3532 else
3533 {
3534 hi2c->XferSize = hi2c->XferCount;
3535 xfermode = hi2c->XferOptions;
3536 }
3537
3538 /* If transfer direction not change and there is no request to start another frame,
3539 do not generate Restart Condition */
3540 /* Mean Previous state is same as current state */
3541 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
3542 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3543 {
3544 xferrequest = I2C_NO_STARTSTOP;
3545 }
3546 else
3547 {
3548 /* Convert OTHER_xxx XferOptions if any */
3549 I2C_ConvertOtherXferOptions(hi2c);
3550
3551 /* Update xfermode accordingly if no reload is necessary */
3552 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3553 {
3554 xfermode = hi2c->XferOptions;
3555 }
3556 }
3557
3558 /* Send Slave Address and set NBYTES to read */
3559 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3560
3561 /* Process Unlocked */
3562 __HAL_UNLOCK(hi2c);
3563
3564 /* Note : The I2C interrupts must be enabled after unlocking current process
3565 to avoid the risk of I2C interrupt handle execution before current
3566 process unlock */
3567 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
3568
3569 return HAL_OK;
3570 }
3571 else
3572 {
3573 return HAL_BUSY;
3574 }
3575 }
3576
3577 /**
3578 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
3579 * @note This interface allow to manage repeated start condition when a direction change during transfer
3580 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3581 * the configuration information for the specified I2C.
3582 * @param DevAddress Target device address: The device 7 bits address value
3583 * in datasheet must be shifted to the left before calling the interface
3584 * @param pData Pointer to data buffer
3585 * @param Size Amount of data to be sent
3586 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3587 * @retval HAL status
3588 */
HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3589 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3590 uint16_t Size, uint32_t XferOptions)
3591 {
3592 uint32_t xfermode;
3593 uint32_t xferrequest = I2C_GENERATE_START_READ;
3594 HAL_StatusTypeDef dmaxferstatus;
3595
3596 /* Check the parameters */
3597 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3598
3599 if (hi2c->State == HAL_I2C_STATE_READY)
3600 {
3601 /* Process Locked */
3602 __HAL_LOCK(hi2c);
3603
3604 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3605 hi2c->Mode = HAL_I2C_MODE_MASTER;
3606 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3607
3608 /* Prepare transfer parameters */
3609 hi2c->pBuffPtr = pData;
3610 hi2c->XferCount = Size;
3611 hi2c->XferOptions = XferOptions;
3612 hi2c->XferISR = I2C_Master_ISR_DMA;
3613
3614 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3615 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3616 {
3617 hi2c->XferSize = MAX_NBYTE_SIZE;
3618 xfermode = I2C_RELOAD_MODE;
3619 }
3620 else
3621 {
3622 hi2c->XferSize = hi2c->XferCount;
3623 xfermode = hi2c->XferOptions;
3624 }
3625
3626 /* If transfer direction not change and there is no request to start another frame,
3627 do not generate Restart Condition */
3628 /* Mean Previous state is same as current state */
3629 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
3630 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3631 {
3632 xferrequest = I2C_NO_STARTSTOP;
3633 }
3634 else
3635 {
3636 /* Convert OTHER_xxx XferOptions if any */
3637 I2C_ConvertOtherXferOptions(hi2c);
3638
3639 /* Update xfermode accordingly if no reload is necessary */
3640 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3641 {
3642 xfermode = hi2c->XferOptions;
3643 }
3644 }
3645
3646 if (hi2c->XferSize > 0U)
3647 {
3648 if (hi2c->hdmarx != NULL)
3649 {
3650 /* Set the I2C DMA transfer complete callback */
3651 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
3652
3653 /* Set the DMA error callback */
3654 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3655
3656 /* Set the unused DMA callbacks to NULL */
3657 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3658 hi2c->hdmarx->XferAbortCallback = NULL;
3659
3660 /* Enable the DMA stream */
3661 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
3662 hi2c->XferSize);
3663 }
3664 else
3665 {
3666 /* Update I2C state */
3667 hi2c->State = HAL_I2C_STATE_READY;
3668 hi2c->Mode = HAL_I2C_MODE_NONE;
3669
3670 /* Update I2C error code */
3671 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3672
3673 /* Process Unlocked */
3674 __HAL_UNLOCK(hi2c);
3675
3676 return HAL_ERROR;
3677 }
3678
3679 if (dmaxferstatus == HAL_OK)
3680 {
3681 /* Send Slave Address and set NBYTES to read */
3682 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3683
3684 /* Update XferCount value */
3685 hi2c->XferCount -= hi2c->XferSize;
3686
3687 /* Process Unlocked */
3688 __HAL_UNLOCK(hi2c);
3689
3690 /* Note : The I2C interrupts must be enabled after unlocking current process
3691 to avoid the risk of I2C interrupt handle execution before current
3692 process unlock */
3693 /* Enable ERR and NACK interrupts */
3694 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
3695
3696 /* Enable DMA Request */
3697 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
3698 }
3699 else
3700 {
3701 /* Update I2C state */
3702 hi2c->State = HAL_I2C_STATE_READY;
3703 hi2c->Mode = HAL_I2C_MODE_NONE;
3704
3705 /* Update I2C error code */
3706 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3707
3708 /* Process Unlocked */
3709 __HAL_UNLOCK(hi2c);
3710
3711 return HAL_ERROR;
3712 }
3713 }
3714 else
3715 {
3716 /* Update Transfer ISR function pointer */
3717 hi2c->XferISR = I2C_Master_ISR_IT;
3718
3719 /* Send Slave Address */
3720 /* Set NBYTES to read and generate START condition */
3721 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
3722 I2C_GENERATE_START_READ);
3723
3724 /* Process Unlocked */
3725 __HAL_UNLOCK(hi2c);
3726
3727 /* Note : The I2C interrupts must be enabled after unlocking current process
3728 to avoid the risk of I2C interrupt handle execution before current
3729 process unlock */
3730 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3731 /* possible to enable all of these */
3732 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3733 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3734 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3735 }
3736
3737 return HAL_OK;
3738 }
3739 else
3740 {
3741 return HAL_BUSY;
3742 }
3743 }
3744
3745 /**
3746 * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
3747 * @note This interface allow to manage repeated start condition when a direction change during transfer
3748 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3749 * the configuration information for the specified I2C.
3750 * @param pData Pointer to data buffer
3751 * @param Size Amount of data to be sent
3752 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3753 * @retval HAL status
3754 */
HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3755 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
3756 uint32_t XferOptions)
3757 {
3758 /* Declaration of tmp to prevent undefined behavior of volatile usage */
3759 FlagStatus tmp;
3760
3761 /* Check the parameters */
3762 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3763
3764 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
3765 {
3766 if ((pData == NULL) || (Size == 0U))
3767 {
3768 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3769 return HAL_ERROR;
3770 }
3771
3772 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
3773 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
3774
3775 /* Process Locked */
3776 __HAL_LOCK(hi2c);
3777
3778 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
3779 /* and then toggle the HAL slave RX state to TX state */
3780 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
3781 {
3782 /* Disable associated Interrupts */
3783 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
3784
3785 /* Abort DMA Xfer if any */
3786 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
3787 {
3788 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
3789
3790 if (hi2c->hdmarx != NULL)
3791 {
3792 /* Set the I2C DMA Abort callback :
3793 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
3794 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
3795
3796 /* Abort DMA RX */
3797 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
3798 {
3799 /* Call Directly XferAbortCallback function in case of error */
3800 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
3801 }
3802 }
3803 }
3804 }
3805
3806 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
3807 hi2c->Mode = HAL_I2C_MODE_SLAVE;
3808 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3809
3810 /* Enable Address Acknowledge */
3811 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
3812
3813 /* Prepare transfer parameters */
3814 hi2c->pBuffPtr = pData;
3815 hi2c->XferCount = Size;
3816 hi2c->XferSize = hi2c->XferCount;
3817 hi2c->XferOptions = XferOptions;
3818 hi2c->XferISR = I2C_Slave_ISR_IT;
3819
3820 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
3821 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
3822 {
3823 /* Clear ADDR flag after prepare the transfer parameters */
3824 /* This action will generate an acknowledge to the Master */
3825 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
3826 }
3827
3828 /* Process Unlocked */
3829 __HAL_UNLOCK(hi2c);
3830
3831 /* Note : The I2C interrupts must be enabled after unlocking current process
3832 to avoid the risk of I2C interrupt handle execution before current
3833 process unlock */
3834 /* REnable ADDR interrupt */
3835 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
3836
3837 return HAL_OK;
3838 }
3839 else
3840 {
3841 return HAL_ERROR;
3842 }
3843 }
3844
3845 /**
3846 * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
3847 * @note This interface allow to manage repeated start condition when a direction change during transfer
3848 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3849 * the configuration information for the specified I2C.
3850 * @param pData Pointer to data buffer
3851 * @param Size Amount of data to be sent
3852 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3853 * @retval HAL status
3854 */
HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3855 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
3856 uint32_t XferOptions)
3857 {
3858 /* Declaration of tmp to prevent undefined behavior of volatile usage */
3859 FlagStatus tmp;
3860 HAL_StatusTypeDef dmaxferstatus;
3861
3862 /* Check the parameters */
3863 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3864
3865 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
3866 {
3867 if ((pData == NULL) || (Size == 0U))
3868 {
3869 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3870 return HAL_ERROR;
3871 }
3872
3873 /* Process Locked */
3874 __HAL_LOCK(hi2c);
3875
3876 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
3877 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
3878
3879 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
3880 /* and then toggle the HAL slave RX state to TX state */
3881 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
3882 {
3883 /* Disable associated Interrupts */
3884 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
3885
3886 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
3887 {
3888 /* Abort DMA Xfer if any */
3889 if (hi2c->hdmarx != NULL)
3890 {
3891 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
3892
3893 /* Set the I2C DMA Abort callback :
3894 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
3895 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
3896
3897 /* Abort DMA RX */
3898 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
3899 {
3900 /* Call Directly XferAbortCallback function in case of error */
3901 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
3902 }
3903 }
3904 }
3905 }
3906 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
3907 {
3908 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
3909 {
3910 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
3911
3912 /* Abort DMA Xfer if any */
3913 if (hi2c->hdmatx != NULL)
3914 {
3915 /* Set the I2C DMA Abort callback :
3916 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
3917 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
3918
3919 /* Abort DMA TX */
3920 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
3921 {
3922 /* Call Directly XferAbortCallback function in case of error */
3923 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
3924 }
3925 }
3926 }
3927 }
3928 else
3929 {
3930 /* Nothing to do */
3931 }
3932
3933 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
3934 hi2c->Mode = HAL_I2C_MODE_SLAVE;
3935 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3936
3937 /* Enable Address Acknowledge */
3938 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
3939
3940 /* Prepare transfer parameters */
3941 hi2c->pBuffPtr = pData;
3942 hi2c->XferCount = Size;
3943 hi2c->XferSize = hi2c->XferCount;
3944 hi2c->XferOptions = XferOptions;
3945 hi2c->XferISR = I2C_Slave_ISR_DMA;
3946
3947 if (hi2c->hdmatx != NULL)
3948 {
3949 /* Set the I2C DMA transfer complete callback */
3950 hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
3951
3952 /* Set the DMA error callback */
3953 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3954
3955 /* Set the unused DMA callbacks to NULL */
3956 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3957 hi2c->hdmatx->XferAbortCallback = NULL;
3958
3959 /* Enable the DMA stream */
3960 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
3961 hi2c->XferSize);
3962 }
3963 else
3964 {
3965 /* Update I2C state */
3966 hi2c->State = HAL_I2C_STATE_LISTEN;
3967 hi2c->Mode = HAL_I2C_MODE_NONE;
3968
3969 /* Update I2C error code */
3970 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3971
3972 /* Process Unlocked */
3973 __HAL_UNLOCK(hi2c);
3974
3975 return HAL_ERROR;
3976 }
3977
3978 if (dmaxferstatus == HAL_OK)
3979 {
3980 /* Update XferCount value */
3981 hi2c->XferCount -= hi2c->XferSize;
3982
3983 /* Reset XferSize */
3984 hi2c->XferSize = 0;
3985 }
3986 else
3987 {
3988 /* Update I2C state */
3989 hi2c->State = HAL_I2C_STATE_LISTEN;
3990 hi2c->Mode = HAL_I2C_MODE_NONE;
3991
3992 /* Update I2C error code */
3993 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3994
3995 /* Process Unlocked */
3996 __HAL_UNLOCK(hi2c);
3997
3998 return HAL_ERROR;
3999 }
4000
4001 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4002 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
4003 {
4004 /* Clear ADDR flag after prepare the transfer parameters */
4005 /* This action will generate an acknowledge to the Master */
4006 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4007 }
4008
4009 /* Process Unlocked */
4010 __HAL_UNLOCK(hi2c);
4011
4012 /* Enable DMA Request */
4013 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
4014
4015 /* Note : The I2C interrupts must be enabled after unlocking current process
4016 to avoid the risk of I2C interrupt handle execution before current
4017 process unlock */
4018 /* Enable ERR, STOP, NACK, ADDR interrupts */
4019 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4020
4021 return HAL_OK;
4022 }
4023 else
4024 {
4025 return HAL_ERROR;
4026 }
4027 }
4028
4029 /**
4030 * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
4031 * @note This interface allow to manage repeated start condition when a direction change during transfer
4032 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4033 * the configuration information for the specified I2C.
4034 * @param pData Pointer to data buffer
4035 * @param Size Amount of data to be sent
4036 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4037 * @retval HAL status
4038 */
HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4039 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4040 uint32_t XferOptions)
4041 {
4042 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4043 FlagStatus tmp;
4044
4045 /* Check the parameters */
4046 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4047
4048 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4049 {
4050 if ((pData == NULL) || (Size == 0U))
4051 {
4052 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4053 return HAL_ERROR;
4054 }
4055
4056 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4057 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
4058
4059 /* Process Locked */
4060 __HAL_LOCK(hi2c);
4061
4062 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4063 /* and then toggle the HAL slave TX state to RX state */
4064 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4065 {
4066 /* Disable associated Interrupts */
4067 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4068
4069 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4070 {
4071 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4072
4073 /* Abort DMA Xfer if any */
4074 if (hi2c->hdmatx != NULL)
4075 {
4076 /* Set the I2C DMA Abort callback :
4077 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4078 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4079
4080 /* Abort DMA TX */
4081 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4082 {
4083 /* Call Directly XferAbortCallback function in case of error */
4084 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4085 }
4086 }
4087 }
4088 }
4089
4090 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4091 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4092 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4093
4094 /* Enable Address Acknowledge */
4095 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4096
4097 /* Prepare transfer parameters */
4098 hi2c->pBuffPtr = pData;
4099 hi2c->XferCount = Size;
4100 hi2c->XferSize = hi2c->XferCount;
4101 hi2c->XferOptions = XferOptions;
4102 hi2c->XferISR = I2C_Slave_ISR_IT;
4103
4104 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4105 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
4106 {
4107 /* Clear ADDR flag after prepare the transfer parameters */
4108 /* This action will generate an acknowledge to the Master */
4109 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4110 }
4111
4112 /* Process Unlocked */
4113 __HAL_UNLOCK(hi2c);
4114
4115 /* Note : The I2C interrupts must be enabled after unlocking current process
4116 to avoid the risk of I2C interrupt handle execution before current
4117 process unlock */
4118 /* REnable ADDR interrupt */
4119 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
4120
4121 return HAL_OK;
4122 }
4123 else
4124 {
4125 return HAL_ERROR;
4126 }
4127 }
4128
4129 /**
4130 * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
4131 * @note This interface allow to manage repeated start condition when a direction change during transfer
4132 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4133 * the configuration information for the specified I2C.
4134 * @param pData Pointer to data buffer
4135 * @param Size Amount of data to be sent
4136 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4137 * @retval HAL status
4138 */
HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4139 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4140 uint32_t XferOptions)
4141 {
4142 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4143 FlagStatus tmp;
4144 HAL_StatusTypeDef dmaxferstatus;
4145
4146 /* Check the parameters */
4147 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4148
4149 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4150 {
4151 if ((pData == NULL) || (Size == 0U))
4152 {
4153 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4154 return HAL_ERROR;
4155 }
4156
4157 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4158 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
4159
4160 /* Process Locked */
4161 __HAL_LOCK(hi2c);
4162
4163 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4164 /* and then toggle the HAL slave TX state to RX state */
4165 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4166 {
4167 /* Disable associated Interrupts */
4168 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4169
4170 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4171 {
4172 /* Abort DMA Xfer if any */
4173 if (hi2c->hdmatx != NULL)
4174 {
4175 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4176
4177 /* Set the I2C DMA Abort callback :
4178 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4179 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4180
4181 /* Abort DMA TX */
4182 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4183 {
4184 /* Call Directly XferAbortCallback function in case of error */
4185 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4186 }
4187 }
4188 }
4189 }
4190 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4191 {
4192 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4193 {
4194 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4195
4196 /* Abort DMA Xfer if any */
4197 if (hi2c->hdmarx != NULL)
4198 {
4199 /* Set the I2C DMA Abort callback :
4200 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4201 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4202
4203 /* Abort DMA RX */
4204 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4205 {
4206 /* Call Directly XferAbortCallback function in case of error */
4207 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4208 }
4209 }
4210 }
4211 }
4212 else
4213 {
4214 /* Nothing to do */
4215 }
4216
4217 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4218 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4219 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4220
4221 /* Enable Address Acknowledge */
4222 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4223
4224 /* Prepare transfer parameters */
4225 hi2c->pBuffPtr = pData;
4226 hi2c->XferCount = Size;
4227 hi2c->XferSize = hi2c->XferCount;
4228 hi2c->XferOptions = XferOptions;
4229 hi2c->XferISR = I2C_Slave_ISR_DMA;
4230
4231 if (hi2c->hdmarx != NULL)
4232 {
4233 /* Set the I2C DMA transfer complete callback */
4234 hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
4235
4236 /* Set the DMA error callback */
4237 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4238
4239 /* Set the unused DMA callbacks to NULL */
4240 hi2c->hdmarx->XferHalfCpltCallback = NULL;
4241 hi2c->hdmarx->XferAbortCallback = NULL;
4242
4243 /* Enable the DMA stream */
4244 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR,
4245 (uint32_t)pData, hi2c->XferSize);
4246 }
4247 else
4248 {
4249 /* Update I2C state */
4250 hi2c->State = HAL_I2C_STATE_LISTEN;
4251 hi2c->Mode = HAL_I2C_MODE_NONE;
4252
4253 /* Update I2C error code */
4254 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4255
4256 /* Process Unlocked */
4257 __HAL_UNLOCK(hi2c);
4258
4259 return HAL_ERROR;
4260 }
4261
4262 if (dmaxferstatus == HAL_OK)
4263 {
4264 /* Update XferCount value */
4265 hi2c->XferCount -= hi2c->XferSize;
4266
4267 /* Reset XferSize */
4268 hi2c->XferSize = 0;
4269 }
4270 else
4271 {
4272 /* Update I2C state */
4273 hi2c->State = HAL_I2C_STATE_LISTEN;
4274 hi2c->Mode = HAL_I2C_MODE_NONE;
4275
4276 /* Update I2C error code */
4277 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4278
4279 /* Process Unlocked */
4280 __HAL_UNLOCK(hi2c);
4281
4282 return HAL_ERROR;
4283 }
4284
4285 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4286 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
4287 {
4288 /* Clear ADDR flag after prepare the transfer parameters */
4289 /* This action will generate an acknowledge to the Master */
4290 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4291 }
4292
4293 /* Process Unlocked */
4294 __HAL_UNLOCK(hi2c);
4295
4296 /* Enable DMA Request */
4297 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
4298
4299 /* Note : The I2C interrupts must be enabled after unlocking current process
4300 to avoid the risk of I2C interrupt handle execution before current
4301 process unlock */
4302 /* REnable ADDR interrupt */
4303 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
4304
4305 return HAL_OK;
4306 }
4307 else
4308 {
4309 return HAL_ERROR;
4310 }
4311 }
4312
4313 /**
4314 * @brief Enable the Address listen mode with Interrupt.
4315 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4316 * the configuration information for the specified I2C.
4317 * @retval HAL status
4318 */
HAL_I2C_EnableListen_IT(I2C_HandleTypeDef * hi2c)4319 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
4320 {
4321 if (hi2c->State == HAL_I2C_STATE_READY)
4322 {
4323 hi2c->State = HAL_I2C_STATE_LISTEN;
4324 hi2c->XferISR = I2C_Slave_ISR_IT;
4325
4326 /* Enable the Address Match interrupt */
4327 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4328
4329 return HAL_OK;
4330 }
4331 else
4332 {
4333 return HAL_BUSY;
4334 }
4335 }
4336
4337 /**
4338 * @brief Disable the Address listen mode with Interrupt.
4339 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4340 * the configuration information for the specified I2C
4341 * @retval HAL status
4342 */
HAL_I2C_DisableListen_IT(I2C_HandleTypeDef * hi2c)4343 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
4344 {
4345 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4346 uint32_t tmp;
4347
4348 /* Disable Address listen mode only if a transfer is not ongoing */
4349 if (hi2c->State == HAL_I2C_STATE_LISTEN)
4350 {
4351 tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
4352 hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
4353 hi2c->State = HAL_I2C_STATE_READY;
4354 hi2c->Mode = HAL_I2C_MODE_NONE;
4355 hi2c->XferISR = NULL;
4356
4357 /* Disable the Address Match interrupt */
4358 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4359
4360 return HAL_OK;
4361 }
4362 else
4363 {
4364 return HAL_BUSY;
4365 }
4366 }
4367
4368 /**
4369 * @brief Abort a master I2C IT or DMA process communication with Interrupt.
4370 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4371 * the configuration information for the specified I2C.
4372 * @param DevAddress Target device address: The device 7 bits address value
4373 * in datasheet must be shifted to the left before calling the interface
4374 * @retval HAL status
4375 */
HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress)4376 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
4377 {
4378 if (hi2c->Mode == HAL_I2C_MODE_MASTER)
4379 {
4380 /* Process Locked */
4381 __HAL_LOCK(hi2c);
4382
4383 /* Disable Interrupts and Store Previous state */
4384 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
4385 {
4386 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4387 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
4388 }
4389 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
4390 {
4391 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
4392 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
4393 }
4394 else
4395 {
4396 /* Do nothing */
4397 }
4398
4399 /* Set State at HAL_I2C_STATE_ABORT */
4400 hi2c->State = HAL_I2C_STATE_ABORT;
4401
4402 /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
4403 /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
4404 I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
4405
4406 /* Process Unlocked */
4407 __HAL_UNLOCK(hi2c);
4408
4409 /* Note : The I2C interrupts must be enabled after unlocking current process
4410 to avoid the risk of I2C interrupt handle execution before current
4411 process unlock */
4412 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
4413
4414 return HAL_OK;
4415 }
4416 else
4417 {
4418 /* Wrong usage of abort function */
4419 /* This function should be used only in case of abort monitored by master device */
4420 return HAL_ERROR;
4421 }
4422 }
4423
4424 /**
4425 * @}
4426 */
4427
4428 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
4429 * @{
4430 */
4431
4432 /**
4433 * @brief This function handles I2C event interrupt request.
4434 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4435 * the configuration information for the specified I2C.
4436 * @retval None
4437 */
HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef * hi2c)4438 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
4439 {
4440 /* Get current IT Flags and IT sources value */
4441 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
4442 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
4443
4444 /* I2C events treatment -------------------------------------*/
4445 if (hi2c->XferISR != NULL)
4446 {
4447 hi2c->XferISR(hi2c, itflags, itsources);
4448 }
4449 }
4450
4451 /**
4452 * @brief This function handles I2C error interrupt request.
4453 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4454 * the configuration information for the specified I2C.
4455 * @retval None
4456 */
HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef * hi2c)4457 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
4458 {
4459 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
4460 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
4461 uint32_t tmperror;
4462
4463 /* I2C Bus error interrupt occurred ------------------------------------*/
4464 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
4465 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4466 {
4467 hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
4468
4469 /* Clear BERR flag */
4470 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
4471 }
4472
4473 /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
4474 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
4475 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4476 {
4477 hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
4478
4479 /* Clear OVR flag */
4480 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
4481 }
4482
4483 /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
4484 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
4485 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4486 {
4487 hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
4488
4489 /* Clear ARLO flag */
4490 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
4491 }
4492
4493 /* Store current volatile hi2c->ErrorCode, misra rule */
4494 tmperror = hi2c->ErrorCode;
4495
4496 /* Call the Error Callback in case of Error detected */
4497 if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
4498 {
4499 I2C_ITError(hi2c, tmperror);
4500 }
4501 }
4502
4503 /**
4504 * @brief Master Tx Transfer completed callback.
4505 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4506 * the configuration information for the specified I2C.
4507 * @retval None
4508 */
HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef * hi2c)4509 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
4510 {
4511 /* Prevent unused argument(s) compilation warning */
4512 UNUSED(hi2c);
4513
4514 /* NOTE : This function should not be modified, when the callback is needed,
4515 the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
4516 */
4517 }
4518
4519 /**
4520 * @brief Master Rx Transfer completed callback.
4521 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4522 * the configuration information for the specified I2C.
4523 * @retval None
4524 */
HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef * hi2c)4525 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
4526 {
4527 /* Prevent unused argument(s) compilation warning */
4528 UNUSED(hi2c);
4529
4530 /* NOTE : This function should not be modified, when the callback is needed,
4531 the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
4532 */
4533 }
4534
4535 /** @brief Slave Tx Transfer completed callback.
4536 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4537 * the configuration information for the specified I2C.
4538 * @retval None
4539 */
HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef * hi2c)4540 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
4541 {
4542 /* Prevent unused argument(s) compilation warning */
4543 UNUSED(hi2c);
4544
4545 /* NOTE : This function should not be modified, when the callback is needed,
4546 the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
4547 */
4548 }
4549
4550 /**
4551 * @brief Slave Rx Transfer completed callback.
4552 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4553 * the configuration information for the specified I2C.
4554 * @retval None
4555 */
HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef * hi2c)4556 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
4557 {
4558 /* Prevent unused argument(s) compilation warning */
4559 UNUSED(hi2c);
4560
4561 /* NOTE : This function should not be modified, when the callback is needed,
4562 the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
4563 */
4564 }
4565
4566 /**
4567 * @brief Slave Address Match callback.
4568 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4569 * the configuration information for the specified I2C.
4570 * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
4571 * @param AddrMatchCode Address Match Code
4572 * @retval None
4573 */
HAL_I2C_AddrCallback(I2C_HandleTypeDef * hi2c,uint8_t TransferDirection,uint16_t AddrMatchCode)4574 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
4575 {
4576 /* Prevent unused argument(s) compilation warning */
4577 UNUSED(hi2c);
4578 UNUSED(TransferDirection);
4579 UNUSED(AddrMatchCode);
4580
4581 /* NOTE : This function should not be modified, when the callback is needed,
4582 the HAL_I2C_AddrCallback() could be implemented in the user file
4583 */
4584 }
4585
4586 /**
4587 * @brief Listen Complete callback.
4588 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4589 * the configuration information for the specified I2C.
4590 * @retval None
4591 */
HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef * hi2c)4592 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
4593 {
4594 /* Prevent unused argument(s) compilation warning */
4595 UNUSED(hi2c);
4596
4597 /* NOTE : This function should not be modified, when the callback is needed,
4598 the HAL_I2C_ListenCpltCallback() could be implemented in the user file
4599 */
4600 }
4601
4602 /**
4603 * @brief Memory Tx Transfer completed callback.
4604 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4605 * the configuration information for the specified I2C.
4606 * @retval None
4607 */
HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef * hi2c)4608 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
4609 {
4610 /* Prevent unused argument(s) compilation warning */
4611 UNUSED(hi2c);
4612
4613 /* NOTE : This function should not be modified, when the callback is needed,
4614 the HAL_I2C_MemTxCpltCallback could be implemented in the user file
4615 */
4616 }
4617
4618 /**
4619 * @brief Memory Rx Transfer completed callback.
4620 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4621 * the configuration information for the specified I2C.
4622 * @retval None
4623 */
HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef * hi2c)4624 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
4625 {
4626 /* Prevent unused argument(s) compilation warning */
4627 UNUSED(hi2c);
4628
4629 /* NOTE : This function should not be modified, when the callback is needed,
4630 the HAL_I2C_MemRxCpltCallback could be implemented in the user file
4631 */
4632 }
4633
4634 /**
4635 * @brief I2C error callback.
4636 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4637 * the configuration information for the specified I2C.
4638 * @retval None
4639 */
HAL_I2C_ErrorCallback(I2C_HandleTypeDef * hi2c)4640 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
4641 {
4642 /* Prevent unused argument(s) compilation warning */
4643 UNUSED(hi2c);
4644
4645 /* NOTE : This function should not be modified, when the callback is needed,
4646 the HAL_I2C_ErrorCallback could be implemented in the user file
4647 */
4648 }
4649
4650 /**
4651 * @brief I2C abort callback.
4652 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4653 * the configuration information for the specified I2C.
4654 * @retval None
4655 */
HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef * hi2c)4656 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
4657 {
4658 /* Prevent unused argument(s) compilation warning */
4659 UNUSED(hi2c);
4660
4661 /* NOTE : This function should not be modified, when the callback is needed,
4662 the HAL_I2C_AbortCpltCallback could be implemented in the user file
4663 */
4664 }
4665
4666 /**
4667 * @}
4668 */
4669
4670 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
4671 * @brief Peripheral State, Mode and Error functions
4672 *
4673 @verbatim
4674 ===============================================================================
4675 ##### Peripheral State, Mode and Error functions #####
4676 ===============================================================================
4677 [..]
4678 This subsection permit to get in run-time the status of the peripheral
4679 and the data flow.
4680
4681 @endverbatim
4682 * @{
4683 */
4684
4685 /**
4686 * @brief Return the I2C handle state.
4687 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4688 * the configuration information for the specified I2C.
4689 * @retval HAL state
4690 */
HAL_I2C_GetState(I2C_HandleTypeDef * hi2c)4691 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
4692 {
4693 /* Return I2C handle state */
4694 return hi2c->State;
4695 }
4696
4697 /**
4698 * @brief Returns the I2C Master, Slave, Memory or no mode.
4699 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4700 * the configuration information for I2C module
4701 * @retval HAL mode
4702 */
HAL_I2C_GetMode(I2C_HandleTypeDef * hi2c)4703 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
4704 {
4705 return hi2c->Mode;
4706 }
4707
4708 /**
4709 * @brief Return the I2C error code.
4710 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4711 * the configuration information for the specified I2C.
4712 * @retval I2C Error Code
4713 */
HAL_I2C_GetError(I2C_HandleTypeDef * hi2c)4714 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
4715 {
4716 return hi2c->ErrorCode;
4717 }
4718
4719 /**
4720 * @}
4721 */
4722
4723 /**
4724 * @}
4725 */
4726
4727 /** @addtogroup I2C_Private_Functions
4728 * @{
4729 */
4730
4731 /**
4732 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
4733 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4734 * the configuration information for the specified I2C.
4735 * @param ITFlags Interrupt flags to handle.
4736 * @param ITSources Interrupt sources enabled.
4737 * @retval HAL status
4738 */
I2C_Master_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)4739 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
4740 uint32_t ITSources)
4741 {
4742 uint16_t devaddress;
4743 uint32_t tmpITFlags = ITFlags;
4744
4745 /* Process Locked */
4746 __HAL_LOCK(hi2c);
4747
4748 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
4749 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
4750 {
4751 /* Clear NACK Flag */
4752 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4753
4754 /* Set corresponding Error Code */
4755 /* No need to generate STOP, it is automatically done */
4756 /* Error callback will be send during stop flag treatment */
4757 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
4758
4759 /* Flush TX register */
4760 I2C_Flush_TXDR(hi2c);
4761 }
4762 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
4763 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
4764 {
4765 /* Remove RXNE flag on temporary variable as read done */
4766 tmpITFlags &= ~I2C_FLAG_RXNE;
4767
4768 /* Read data from RXDR */
4769 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
4770
4771 /* Increment Buffer pointer */
4772 hi2c->pBuffPtr++;
4773
4774 hi2c->XferSize--;
4775 hi2c->XferCount--;
4776 }
4777 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
4778 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
4779 {
4780 /* Write data to TXDR */
4781 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
4782
4783 /* Increment Buffer pointer */
4784 hi2c->pBuffPtr++;
4785
4786 hi2c->XferSize--;
4787 hi2c->XferCount--;
4788 }
4789 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
4790 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
4791 {
4792 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
4793 {
4794 devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
4795
4796 if (hi2c->XferCount > MAX_NBYTE_SIZE)
4797 {
4798 hi2c->XferSize = MAX_NBYTE_SIZE;
4799 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
4800 }
4801 else
4802 {
4803 hi2c->XferSize = hi2c->XferCount;
4804 if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
4805 {
4806 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
4807 hi2c->XferOptions, I2C_NO_STARTSTOP);
4808 }
4809 else
4810 {
4811 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
4812 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
4813 }
4814 }
4815 }
4816 else
4817 {
4818 /* Call TxCpltCallback() if no stop mode is set */
4819 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
4820 {
4821 /* Call I2C Master Sequential complete process */
4822 I2C_ITMasterSeqCplt(hi2c);
4823 }
4824 else
4825 {
4826 /* Wrong size Status regarding TCR flag event */
4827 /* Call the corresponding callback to inform upper layer of End of Transfer */
4828 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
4829 }
4830 }
4831 }
4832 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
4833 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
4834 {
4835 if (hi2c->XferCount == 0U)
4836 {
4837 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
4838 {
4839 /* Generate a stop condition in case of no transfer option */
4840 if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
4841 {
4842 /* Generate Stop */
4843 hi2c->Instance->CR2 |= I2C_CR2_STOP;
4844 }
4845 else
4846 {
4847 /* Call I2C Master Sequential complete process */
4848 I2C_ITMasterSeqCplt(hi2c);
4849 }
4850 }
4851 }
4852 else
4853 {
4854 /* Wrong size Status regarding TC flag event */
4855 /* Call the corresponding callback to inform upper layer of End of Transfer */
4856 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
4857 }
4858 }
4859 else
4860 {
4861 /* Nothing to do */
4862 }
4863
4864 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
4865 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
4866 {
4867 /* Call I2C Master complete process */
4868 I2C_ITMasterCplt(hi2c, tmpITFlags);
4869 }
4870
4871 /* Process Unlocked */
4872 __HAL_UNLOCK(hi2c);
4873
4874 return HAL_OK;
4875 }
4876
4877 /**
4878 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt.
4879 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4880 * the configuration information for the specified I2C.
4881 * @param ITFlags Interrupt flags to handle.
4882 * @param ITSources Interrupt sources enabled.
4883 * @retval HAL status
4884 */
I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)4885 static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
4886 uint32_t ITSources)
4887 {
4888 uint32_t direction = I2C_GENERATE_START_WRITE;
4889 uint32_t tmpITFlags = ITFlags;
4890
4891 /* Process Locked */
4892 __HAL_LOCK(hi2c);
4893
4894 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
4895 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
4896 {
4897 /* Clear NACK Flag */
4898 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4899
4900 /* Set corresponding Error Code */
4901 /* No need to generate STOP, it is automatically done */
4902 /* Error callback will be send during stop flag treatment */
4903 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
4904
4905 /* Flush TX register */
4906 I2C_Flush_TXDR(hi2c);
4907 }
4908 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
4909 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
4910 {
4911 /* Remove RXNE flag on temporary variable as read done */
4912 tmpITFlags &= ~I2C_FLAG_RXNE;
4913
4914 /* Read data from RXDR */
4915 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
4916
4917 /* Increment Buffer pointer */
4918 hi2c->pBuffPtr++;
4919
4920 hi2c->XferSize--;
4921 hi2c->XferCount--;
4922 }
4923 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
4924 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
4925 {
4926 if (hi2c->Memaddress == 0xFFFFFFFFU)
4927 {
4928 /* Write data to TXDR */
4929 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
4930
4931 /* Increment Buffer pointer */
4932 hi2c->pBuffPtr++;
4933
4934 hi2c->XferSize--;
4935 hi2c->XferCount--;
4936 }
4937 else
4938 {
4939 /* Write LSB part of Memory Address */
4940 hi2c->Instance->TXDR = hi2c->Memaddress;
4941
4942 /* Reset Memaddress content */
4943 hi2c->Memaddress = 0xFFFFFFFFU;
4944 }
4945 }
4946 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
4947 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
4948 {
4949 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
4950 {
4951 if (hi2c->XferCount > MAX_NBYTE_SIZE)
4952 {
4953 hi2c->XferSize = MAX_NBYTE_SIZE;
4954 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
4955 I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
4956 }
4957 else
4958 {
4959 hi2c->XferSize = hi2c->XferCount;
4960 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
4961 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
4962 }
4963 }
4964 else
4965 {
4966 /* Wrong size Status regarding TCR flag event */
4967 /* Call the corresponding callback to inform upper layer of End of Transfer */
4968 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
4969 }
4970 }
4971 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
4972 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
4973 {
4974 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
4975 {
4976 direction = I2C_GENERATE_START_READ;
4977 }
4978
4979 if (hi2c->XferCount > MAX_NBYTE_SIZE)
4980 {
4981 hi2c->XferSize = MAX_NBYTE_SIZE;
4982
4983 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
4984 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
4985 I2C_RELOAD_MODE, direction);
4986 }
4987 else
4988 {
4989 hi2c->XferSize = hi2c->XferCount;
4990
4991 /* Set NBYTES to write and generate RESTART */
4992 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
4993 I2C_AUTOEND_MODE, direction);
4994 }
4995 }
4996 else
4997 {
4998 /* Nothing to do */
4999 }
5000
5001 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5002 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5003 {
5004 /* Call I2C Master complete process */
5005 I2C_ITMasterCplt(hi2c, tmpITFlags);
5006 }
5007
5008 /* Process Unlocked */
5009 __HAL_UNLOCK(hi2c);
5010
5011 return HAL_OK;
5012 }
5013
5014 /**
5015 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
5016 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5017 * the configuration information for the specified I2C.
5018 * @param ITFlags Interrupt flags to handle.
5019 * @param ITSources Interrupt sources enabled.
5020 * @retval HAL status
5021 */
I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5022 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5023 uint32_t ITSources)
5024 {
5025 uint32_t tmpoptions = hi2c->XferOptions;
5026 uint32_t tmpITFlags = ITFlags;
5027
5028 /* Process locked */
5029 __HAL_LOCK(hi2c);
5030
5031 /* Check if STOPF is set */
5032 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5033 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5034 {
5035 /* Call I2C Slave complete process */
5036 I2C_ITSlaveCplt(hi2c, tmpITFlags);
5037 }
5038
5039 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
5040 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5041 {
5042 /* Check that I2C transfer finished */
5043 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
5044 /* Mean XferCount == 0*/
5045 /* So clear Flag NACKF only */
5046 if (hi2c->XferCount == 0U)
5047 {
5048 if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
5049 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
5050 Warning[Pa134]: left and right operands are identical */
5051 {
5052 /* Call I2C Listen complete process */
5053 I2C_ITListenCplt(hi2c, tmpITFlags);
5054 }
5055 else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
5056 {
5057 /* Clear NACK Flag */
5058 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5059
5060 /* Flush TX register */
5061 I2C_Flush_TXDR(hi2c);
5062
5063 /* Last Byte is Transmitted */
5064 /* Call I2C Slave Sequential complete process */
5065 I2C_ITSlaveSeqCplt(hi2c);
5066 }
5067 else
5068 {
5069 /* Clear NACK Flag */
5070 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5071 }
5072 }
5073 else
5074 {
5075 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
5076 /* Clear NACK Flag */
5077 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5078
5079 /* Set ErrorCode corresponding to a Non-Acknowledge */
5080 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5081
5082 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
5083 {
5084 /* Call the corresponding callback to inform upper layer of End of Transfer */
5085 I2C_ITError(hi2c, hi2c->ErrorCode);
5086 }
5087 }
5088 }
5089 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
5090 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
5091 {
5092 if (hi2c->XferCount > 0U)
5093 {
5094 /* Read data from RXDR */
5095 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
5096
5097 /* Increment Buffer pointer */
5098 hi2c->pBuffPtr++;
5099
5100 hi2c->XferSize--;
5101 hi2c->XferCount--;
5102 }
5103
5104 if ((hi2c->XferCount == 0U) && \
5105 (tmpoptions != I2C_NO_OPTION_FRAME))
5106 {
5107 /* Call I2C Slave Sequential complete process */
5108 I2C_ITSlaveSeqCplt(hi2c);
5109 }
5110 }
5111 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
5112 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
5113 {
5114 I2C_ITAddrCplt(hi2c, tmpITFlags);
5115 }
5116 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
5117 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5118 {
5119 /* Write data to TXDR only if XferCount not reach "0" */
5120 /* A TXIS flag can be set, during STOP treatment */
5121 /* Check if all Data have already been sent */
5122 /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
5123 if (hi2c->XferCount > 0U)
5124 {
5125 /* Write data to TXDR */
5126 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
5127
5128 /* Increment Buffer pointer */
5129 hi2c->pBuffPtr++;
5130
5131 hi2c->XferCount--;
5132 hi2c->XferSize--;
5133 }
5134 else
5135 {
5136 if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
5137 {
5138 /* Last Byte is Transmitted */
5139 /* Call I2C Slave Sequential complete process */
5140 I2C_ITSlaveSeqCplt(hi2c);
5141 }
5142 }
5143 }
5144 else
5145 {
5146 /* Nothing to do */
5147 }
5148
5149 /* Process Unlocked */
5150 __HAL_UNLOCK(hi2c);
5151
5152 return HAL_OK;
5153 }
5154
5155 /**
5156 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
5157 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5158 * the configuration information for the specified I2C.
5159 * @param ITFlags Interrupt flags to handle.
5160 * @param ITSources Interrupt sources enabled.
5161 * @retval HAL status
5162 */
I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5163 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5164 uint32_t ITSources)
5165 {
5166 uint16_t devaddress;
5167 uint32_t xfermode;
5168
5169 /* Process Locked */
5170 __HAL_LOCK(hi2c);
5171
5172 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5173 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5174 {
5175 /* Clear NACK Flag */
5176 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5177
5178 /* Set corresponding Error Code */
5179 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5180
5181 /* No need to generate STOP, it is automatically done */
5182 /* But enable STOP interrupt, to treat it */
5183 /* Error callback will be send during stop flag treatment */
5184 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
5185
5186 /* Flush TX register */
5187 I2C_Flush_TXDR(hi2c);
5188 }
5189 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
5190 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5191 {
5192 /* Disable TC interrupt */
5193 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
5194
5195 if (hi2c->XferCount != 0U)
5196 {
5197 /* Recover Slave address */
5198 devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
5199
5200 /* Prepare the new XferSize to transfer */
5201 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5202 {
5203 hi2c->XferSize = MAX_NBYTE_SIZE;
5204 xfermode = I2C_RELOAD_MODE;
5205 }
5206 else
5207 {
5208 hi2c->XferSize = hi2c->XferCount;
5209 if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
5210 {
5211 xfermode = hi2c->XferOptions;
5212 }
5213 else
5214 {
5215 xfermode = I2C_AUTOEND_MODE;
5216 }
5217 }
5218
5219 /* Set the new XferSize in Nbytes register */
5220 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
5221
5222 /* Update XferCount value */
5223 hi2c->XferCount -= hi2c->XferSize;
5224
5225 /* Enable DMA Request */
5226 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5227 {
5228 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5229 }
5230 else
5231 {
5232 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5233 }
5234 }
5235 else
5236 {
5237 /* Call TxCpltCallback() if no stop mode is set */
5238 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5239 {
5240 /* Call I2C Master Sequential complete process */
5241 I2C_ITMasterSeqCplt(hi2c);
5242 }
5243 else
5244 {
5245 /* Wrong size Status regarding TCR flag event */
5246 /* Call the corresponding callback to inform upper layer of End of Transfer */
5247 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5248 }
5249 }
5250 }
5251 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
5252 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5253 {
5254 if (hi2c->XferCount == 0U)
5255 {
5256 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5257 {
5258 /* Generate a stop condition in case of no transfer option */
5259 if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
5260 {
5261 /* Generate Stop */
5262 hi2c->Instance->CR2 |= I2C_CR2_STOP;
5263 }
5264 else
5265 {
5266 /* Call I2C Master Sequential complete process */
5267 I2C_ITMasterSeqCplt(hi2c);
5268 }
5269 }
5270 }
5271 else
5272 {
5273 /* Wrong size Status regarding TC flag event */
5274 /* Call the corresponding callback to inform upper layer of End of Transfer */
5275 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5276 }
5277 }
5278 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5279 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5280 {
5281 /* Call I2C Master complete process */
5282 I2C_ITMasterCplt(hi2c, ITFlags);
5283 }
5284 else
5285 {
5286 /* Nothing to do */
5287 }
5288
5289 /* Process Unlocked */
5290 __HAL_UNLOCK(hi2c);
5291
5292 return HAL_OK;
5293 }
5294
5295 /**
5296 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA.
5297 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5298 * the configuration information for the specified I2C.
5299 * @param ITFlags Interrupt flags to handle.
5300 * @param ITSources Interrupt sources enabled.
5301 * @retval HAL status
5302 */
I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5303 static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5304 uint32_t ITSources)
5305 {
5306 uint32_t direction = I2C_GENERATE_START_WRITE;
5307
5308 /* Process Locked */
5309 __HAL_LOCK(hi2c);
5310
5311 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5312 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5313 {
5314 /* Clear NACK Flag */
5315 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5316
5317 /* Set corresponding Error Code */
5318 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5319
5320 /* No need to generate STOP, it is automatically done */
5321 /* But enable STOP interrupt, to treat it */
5322 /* Error callback will be send during stop flag treatment */
5323 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
5324
5325 /* Flush TX register */
5326 I2C_Flush_TXDR(hi2c);
5327 }
5328 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \
5329 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5330 {
5331 /* Write LSB part of Memory Address */
5332 hi2c->Instance->TXDR = hi2c->Memaddress;
5333
5334 /* Reset Memaddress content */
5335 hi2c->Memaddress = 0xFFFFFFFFU;
5336 }
5337 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
5338 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5339 {
5340 /* Enable only Error interrupt */
5341 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
5342
5343 if (hi2c->XferCount != 0U)
5344 {
5345 /* Prepare the new XferSize to transfer */
5346 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5347 {
5348 hi2c->XferSize = MAX_NBYTE_SIZE;
5349 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5350 I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
5351 }
5352 else
5353 {
5354 hi2c->XferSize = hi2c->XferCount;
5355 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5356 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5357 }
5358
5359 /* Update XferCount value */
5360 hi2c->XferCount -= hi2c->XferSize;
5361
5362 /* Enable DMA Request */
5363 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5364 {
5365 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5366 }
5367 else
5368 {
5369 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5370 }
5371 }
5372 else
5373 {
5374 /* Wrong size Status regarding TCR flag event */
5375 /* Call the corresponding callback to inform upper layer of End of Transfer */
5376 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5377 }
5378 }
5379 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
5380 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5381 {
5382 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5383 {
5384 direction = I2C_GENERATE_START_READ;
5385 }
5386
5387 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5388 {
5389 hi2c->XferSize = MAX_NBYTE_SIZE;
5390
5391 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
5392 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5393 I2C_RELOAD_MODE, direction);
5394 }
5395 else
5396 {
5397 hi2c->XferSize = hi2c->XferCount;
5398
5399 /* Set NBYTES to write and generate RESTART */
5400 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5401 I2C_AUTOEND_MODE, direction);
5402 }
5403
5404 /* Update XferCount value */
5405 hi2c->XferCount -= hi2c->XferSize;
5406
5407 /* Enable DMA Request */
5408 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5409 {
5410 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5411 }
5412 else
5413 {
5414 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5415 }
5416 }
5417 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5418 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5419 {
5420 /* Call I2C Master complete process */
5421 I2C_ITMasterCplt(hi2c, ITFlags);
5422 }
5423 else
5424 {
5425 /* Nothing to do */
5426 }
5427
5428 /* Process Unlocked */
5429 __HAL_UNLOCK(hi2c);
5430
5431 return HAL_OK;
5432 }
5433
5434 /**
5435 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
5436 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5437 * the configuration information for the specified I2C.
5438 * @param ITFlags Interrupt flags to handle.
5439 * @param ITSources Interrupt sources enabled.
5440 * @retval HAL status
5441 */
I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5442 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5443 uint32_t ITSources)
5444 {
5445 uint32_t tmpoptions = hi2c->XferOptions;
5446 uint32_t treatdmanack = 0U;
5447 HAL_I2C_StateTypeDef tmpstate;
5448
5449 /* Process locked */
5450 __HAL_LOCK(hi2c);
5451
5452 /* Check if STOPF is set */
5453 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5454 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5455 {
5456 /* Call I2C Slave complete process */
5457 I2C_ITSlaveCplt(hi2c, ITFlags);
5458 }
5459
5460 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5461 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5462 {
5463 /* Check that I2C transfer finished */
5464 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
5465 /* Mean XferCount == 0 */
5466 /* So clear Flag NACKF only */
5467 if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
5468 (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
5469 {
5470 /* Split check of hdmarx, for MISRA compliance */
5471 if (hi2c->hdmarx != NULL)
5472 {
5473 if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
5474 {
5475 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
5476 {
5477 treatdmanack = 1U;
5478 }
5479 }
5480 }
5481
5482 /* Split check of hdmatx, for MISRA compliance */
5483 if (hi2c->hdmatx != NULL)
5484 {
5485 if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
5486 {
5487 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
5488 {
5489 treatdmanack = 1U;
5490 }
5491 }
5492 }
5493
5494 if (treatdmanack == 1U)
5495 {
5496 if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
5497 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
5498 Warning[Pa134]: left and right operands are identical */
5499 {
5500 /* Call I2C Listen complete process */
5501 I2C_ITListenCplt(hi2c, ITFlags);
5502 }
5503 else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
5504 {
5505 /* Clear NACK Flag */
5506 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5507
5508 /* Flush TX register */
5509 I2C_Flush_TXDR(hi2c);
5510
5511 /* Last Byte is Transmitted */
5512 /* Call I2C Slave Sequential complete process */
5513 I2C_ITSlaveSeqCplt(hi2c);
5514 }
5515 else
5516 {
5517 /* Clear NACK Flag */
5518 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5519 }
5520 }
5521 else
5522 {
5523 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
5524 /* Clear NACK Flag */
5525 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5526
5527 /* Set ErrorCode corresponding to a Non-Acknowledge */
5528 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5529
5530 /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
5531 tmpstate = hi2c->State;
5532
5533 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
5534 {
5535 if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
5536 {
5537 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
5538 }
5539 else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
5540 {
5541 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
5542 }
5543 else
5544 {
5545 /* Do nothing */
5546 }
5547
5548 /* Call the corresponding callback to inform upper layer of End of Transfer */
5549 I2C_ITError(hi2c, hi2c->ErrorCode);
5550 }
5551 }
5552 }
5553 else
5554 {
5555 /* Only Clear NACK Flag, no DMA treatment is pending */
5556 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5557 }
5558 }
5559 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
5560 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
5561 {
5562 I2C_ITAddrCplt(hi2c, ITFlags);
5563 }
5564 else
5565 {
5566 /* Nothing to do */
5567 }
5568
5569 /* Process Unlocked */
5570 __HAL_UNLOCK(hi2c);
5571
5572 return HAL_OK;
5573 }
5574
5575 /**
5576 * @brief Master sends target device address followed by internal memory address for write request.
5577 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5578 * the configuration information for the specified I2C.
5579 * @param DevAddress Target device address: The device 7 bits address value
5580 * in datasheet must be shifted to the left before calling the interface
5581 * @param MemAddress Internal memory address
5582 * @param MemAddSize Size of internal memory address
5583 * @param Timeout Timeout duration
5584 * @param Tickstart Tick start value
5585 * @retval HAL status
5586 */
I2C_RequestMemoryWrite(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)5587 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
5588 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
5589 uint32_t Tickstart)
5590 {
5591 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
5592
5593 /* Wait until TXIS flag is set */
5594 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5595 {
5596 return HAL_ERROR;
5597 }
5598
5599 /* If Memory address size is 8Bit */
5600 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
5601 {
5602 /* Send Memory Address */
5603 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5604 }
5605 /* If Memory address size is 16Bit */
5606 else
5607 {
5608 /* Send MSB of Memory Address */
5609 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
5610
5611 /* Wait until TXIS flag is set */
5612 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5613 {
5614 return HAL_ERROR;
5615 }
5616
5617 /* Send LSB of Memory Address */
5618 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5619 }
5620
5621 /* Wait until TCR flag is set */
5622 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
5623 {
5624 return HAL_ERROR;
5625 }
5626
5627 return HAL_OK;
5628 }
5629
5630 /**
5631 * @brief Master sends target device address followed by internal memory address for read request.
5632 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5633 * the configuration information for the specified I2C.
5634 * @param DevAddress Target device address: The device 7 bits address value
5635 * in datasheet must be shifted to the left before calling the interface
5636 * @param MemAddress Internal memory address
5637 * @param MemAddSize Size of internal memory address
5638 * @param Timeout Timeout duration
5639 * @param Tickstart Tick start value
5640 * @retval HAL status
5641 */
I2C_RequestMemoryRead(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)5642 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
5643 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
5644 uint32_t Tickstart)
5645 {
5646 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
5647
5648 /* Wait until TXIS flag is set */
5649 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5650 {
5651 return HAL_ERROR;
5652 }
5653
5654 /* If Memory address size is 8Bit */
5655 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
5656 {
5657 /* Send Memory Address */
5658 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5659 }
5660 /* If Memory address size is 16Bit */
5661 else
5662 {
5663 /* Send MSB of Memory Address */
5664 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
5665
5666 /* Wait until TXIS flag is set */
5667 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5668 {
5669 return HAL_ERROR;
5670 }
5671
5672 /* Send LSB of Memory Address */
5673 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5674 }
5675
5676 /* Wait until TC flag is set */
5677 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
5678 {
5679 return HAL_ERROR;
5680 }
5681
5682 return HAL_OK;
5683 }
5684
5685 /**
5686 * @brief I2C Address complete process callback.
5687 * @param hi2c I2C handle.
5688 * @param ITFlags Interrupt flags to handle.
5689 * @retval None
5690 */
I2C_ITAddrCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)5691 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
5692 {
5693 uint8_t transferdirection;
5694 uint16_t slaveaddrcode;
5695 uint16_t ownadd1code;
5696 uint16_t ownadd2code;
5697
5698 /* Prevent unused argument(s) compilation warning */
5699 UNUSED(ITFlags);
5700
5701 /* In case of Listen state, need to inform upper layer of address match code event */
5702 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
5703 {
5704 transferdirection = I2C_GET_DIR(hi2c);
5705 slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
5706 ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);
5707 ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
5708
5709 /* If 10bits addressing mode is selected */
5710 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
5711 {
5712 if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
5713 {
5714 slaveaddrcode = ownadd1code;
5715 hi2c->AddrEventCount++;
5716 if (hi2c->AddrEventCount == 2U)
5717 {
5718 /* Reset Address Event counter */
5719 hi2c->AddrEventCount = 0U;
5720
5721 /* Clear ADDR flag */
5722 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
5723
5724 /* Process Unlocked */
5725 __HAL_UNLOCK(hi2c);
5726
5727 /* Call Slave Addr callback */
5728 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5729 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
5730 #else
5731 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
5732 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5733 }
5734 }
5735 else
5736 {
5737 slaveaddrcode = ownadd2code;
5738
5739 /* Disable ADDR Interrupts */
5740 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
5741
5742 /* Process Unlocked */
5743 __HAL_UNLOCK(hi2c);
5744
5745 /* Call Slave Addr callback */
5746 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5747 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
5748 #else
5749 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
5750 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5751 }
5752 }
5753 /* else 7 bits addressing mode is selected */
5754 else
5755 {
5756 /* Disable ADDR Interrupts */
5757 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
5758
5759 /* Process Unlocked */
5760 __HAL_UNLOCK(hi2c);
5761
5762 /* Call Slave Addr callback */
5763 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5764 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
5765 #else
5766 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
5767 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5768 }
5769 }
5770 /* Else clear address flag only */
5771 else
5772 {
5773 /* Clear ADDR flag */
5774 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
5775
5776 /* Process Unlocked */
5777 __HAL_UNLOCK(hi2c);
5778 }
5779 }
5780
5781 /**
5782 * @brief I2C Master sequential complete process.
5783 * @param hi2c I2C handle.
5784 * @retval None
5785 */
I2C_ITMasterSeqCplt(I2C_HandleTypeDef * hi2c)5786 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
5787 {
5788 /* Reset I2C handle mode */
5789 hi2c->Mode = HAL_I2C_MODE_NONE;
5790
5791 /* No Generate Stop, to permit restart mode */
5792 /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
5793 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5794 {
5795 hi2c->State = HAL_I2C_STATE_READY;
5796 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
5797 hi2c->XferISR = NULL;
5798
5799 /* Disable Interrupts */
5800 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5801
5802 /* Process Unlocked */
5803 __HAL_UNLOCK(hi2c);
5804
5805 /* Call the corresponding callback to inform upper layer of End of Transfer */
5806 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5807 hi2c->MasterTxCpltCallback(hi2c);
5808 #else
5809 HAL_I2C_MasterTxCpltCallback(hi2c);
5810 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5811 }
5812 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
5813 else
5814 {
5815 hi2c->State = HAL_I2C_STATE_READY;
5816 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
5817 hi2c->XferISR = NULL;
5818
5819 /* Disable Interrupts */
5820 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
5821
5822 /* Process Unlocked */
5823 __HAL_UNLOCK(hi2c);
5824
5825 /* Call the corresponding callback to inform upper layer of End of Transfer */
5826 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5827 hi2c->MasterRxCpltCallback(hi2c);
5828 #else
5829 HAL_I2C_MasterRxCpltCallback(hi2c);
5830 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5831 }
5832 }
5833
5834 /**
5835 * @brief I2C Slave sequential complete process.
5836 * @param hi2c I2C handle.
5837 * @retval None
5838 */
I2C_ITSlaveSeqCplt(I2C_HandleTypeDef * hi2c)5839 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
5840 {
5841 uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
5842
5843 /* Reset I2C handle mode */
5844 hi2c->Mode = HAL_I2C_MODE_NONE;
5845
5846 /* If a DMA is ongoing, Update handle size context */
5847 if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
5848 {
5849 /* Disable DMA Request */
5850 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
5851 }
5852 else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
5853 {
5854 /* Disable DMA Request */
5855 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
5856 }
5857 else
5858 {
5859 /* Do nothing */
5860 }
5861
5862 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
5863 {
5864 /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
5865 hi2c->State = HAL_I2C_STATE_LISTEN;
5866 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
5867
5868 /* Disable Interrupts */
5869 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5870
5871 /* Process Unlocked */
5872 __HAL_UNLOCK(hi2c);
5873
5874 /* Call the corresponding callback to inform upper layer of End of Transfer */
5875 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5876 hi2c->SlaveTxCpltCallback(hi2c);
5877 #else
5878 HAL_I2C_SlaveTxCpltCallback(hi2c);
5879 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5880 }
5881
5882 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
5883 {
5884 /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
5885 hi2c->State = HAL_I2C_STATE_LISTEN;
5886 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
5887
5888 /* Disable Interrupts */
5889 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
5890
5891 /* Process Unlocked */
5892 __HAL_UNLOCK(hi2c);
5893
5894 /* Call the corresponding callback to inform upper layer of End of Transfer */
5895 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5896 hi2c->SlaveRxCpltCallback(hi2c);
5897 #else
5898 HAL_I2C_SlaveRxCpltCallback(hi2c);
5899 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5900 }
5901 else
5902 {
5903 /* Nothing to do */
5904 }
5905 }
5906
5907 /**
5908 * @brief I2C Master complete process.
5909 * @param hi2c I2C handle.
5910 * @param ITFlags Interrupt flags to handle.
5911 * @retval None
5912 */
I2C_ITMasterCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)5913 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
5914 {
5915 uint32_t tmperror;
5916 uint32_t tmpITFlags = ITFlags;
5917 __IO uint32_t tmpreg;
5918
5919 /* Clear STOP Flag */
5920 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
5921
5922 /* Disable Interrupts and Store Previous state */
5923 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5924 {
5925 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5926 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
5927 }
5928 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5929 {
5930 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
5931 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
5932 }
5933 else
5934 {
5935 /* Do nothing */
5936 }
5937
5938 /* Clear Configuration Register 2 */
5939 I2C_RESET_CR2(hi2c);
5940
5941 /* Reset handle parameters */
5942 hi2c->XferISR = NULL;
5943 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
5944
5945 if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
5946 {
5947 /* Clear NACK Flag */
5948 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5949
5950 /* Set acknowledge error code */
5951 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5952 }
5953
5954 /* Fetch Last receive data if any */
5955 if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
5956 {
5957 /* Read data from RXDR */
5958 tmpreg = (uint8_t)hi2c->Instance->RXDR;
5959 UNUSED(tmpreg);
5960 }
5961
5962 /* Flush TX register */
5963 I2C_Flush_TXDR(hi2c);
5964
5965 /* Store current volatile hi2c->ErrorCode, misra rule */
5966 tmperror = hi2c->ErrorCode;
5967
5968 /* Call the corresponding callback to inform upper layer of End of Transfer */
5969 if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
5970 {
5971 /* Call the corresponding callback to inform upper layer of End of Transfer */
5972 I2C_ITError(hi2c, hi2c->ErrorCode);
5973 }
5974 /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
5975 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5976 {
5977 hi2c->State = HAL_I2C_STATE_READY;
5978 hi2c->PreviousState = I2C_STATE_NONE;
5979
5980 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5981 {
5982 hi2c->Mode = HAL_I2C_MODE_NONE;
5983
5984 /* Process Unlocked */
5985 __HAL_UNLOCK(hi2c);
5986
5987 /* Call the corresponding callback to inform upper layer of End of Transfer */
5988 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5989 hi2c->MemTxCpltCallback(hi2c);
5990 #else
5991 HAL_I2C_MemTxCpltCallback(hi2c);
5992 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5993 }
5994 else
5995 {
5996 hi2c->Mode = HAL_I2C_MODE_NONE;
5997
5998 /* Process Unlocked */
5999 __HAL_UNLOCK(hi2c);
6000
6001 /* Call the corresponding callback to inform upper layer of End of Transfer */
6002 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6003 hi2c->MasterTxCpltCallback(hi2c);
6004 #else
6005 HAL_I2C_MasterTxCpltCallback(hi2c);
6006 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6007 }
6008 }
6009 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
6010 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6011 {
6012 hi2c->State = HAL_I2C_STATE_READY;
6013 hi2c->PreviousState = I2C_STATE_NONE;
6014
6015 if (hi2c->Mode == HAL_I2C_MODE_MEM)
6016 {
6017 hi2c->Mode = HAL_I2C_MODE_NONE;
6018
6019 /* Process Unlocked */
6020 __HAL_UNLOCK(hi2c);
6021
6022 /* Call the corresponding callback to inform upper layer of End of Transfer */
6023 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6024 hi2c->MemRxCpltCallback(hi2c);
6025 #else
6026 HAL_I2C_MemRxCpltCallback(hi2c);
6027 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6028 }
6029 else
6030 {
6031 hi2c->Mode = HAL_I2C_MODE_NONE;
6032
6033 /* Process Unlocked */
6034 __HAL_UNLOCK(hi2c);
6035
6036 /* Call the corresponding callback to inform upper layer of End of Transfer */
6037 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6038 hi2c->MasterRxCpltCallback(hi2c);
6039 #else
6040 HAL_I2C_MasterRxCpltCallback(hi2c);
6041 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6042 }
6043 }
6044 else
6045 {
6046 /* Nothing to do */
6047 }
6048 }
6049
6050 /**
6051 * @brief I2C Slave complete process.
6052 * @param hi2c I2C handle.
6053 * @param ITFlags Interrupt flags to handle.
6054 * @retval None
6055 */
I2C_ITSlaveCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6056 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6057 {
6058 uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
6059 uint32_t tmpITFlags = ITFlags;
6060 HAL_I2C_StateTypeDef tmpstate = hi2c->State;
6061
6062 /* Clear STOP Flag */
6063 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6064
6065 /* Disable Interrupts and Store Previous state */
6066 if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
6067 {
6068 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
6069 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6070 }
6071 else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
6072 {
6073 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
6074 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6075 }
6076 else
6077 {
6078 /* Do nothing */
6079 }
6080
6081 /* Disable Address Acknowledge */
6082 hi2c->Instance->CR2 |= I2C_CR2_NACK;
6083
6084 /* Clear Configuration Register 2 */
6085 I2C_RESET_CR2(hi2c);
6086
6087 /* Flush TX register */
6088 I2C_Flush_TXDR(hi2c);
6089
6090 /* If a DMA is ongoing, Update handle size context */
6091 if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
6092 {
6093 /* Disable DMA Request */
6094 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6095
6096 if (hi2c->hdmatx != NULL)
6097 {
6098 hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
6099 }
6100 }
6101 else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
6102 {
6103 /* Disable DMA Request */
6104 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6105
6106 if (hi2c->hdmarx != NULL)
6107 {
6108 hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
6109 }
6110 }
6111 else
6112 {
6113 /* Do nothing */
6114 }
6115
6116 /* Store Last receive data if any */
6117 if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
6118 {
6119 /* Remove RXNE flag on temporary variable as read done */
6120 tmpITFlags &= ~I2C_FLAG_RXNE;
6121
6122 /* Read data from RXDR */
6123 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
6124
6125 /* Increment Buffer pointer */
6126 hi2c->pBuffPtr++;
6127
6128 if ((hi2c->XferSize > 0U))
6129 {
6130 hi2c->XferSize--;
6131 hi2c->XferCount--;
6132 }
6133 }
6134
6135 /* All data are not transferred, so set error code accordingly */
6136 if (hi2c->XferCount != 0U)
6137 {
6138 /* Set ErrorCode corresponding to a Non-Acknowledge */
6139 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6140 }
6141
6142 hi2c->Mode = HAL_I2C_MODE_NONE;
6143 hi2c->XferISR = NULL;
6144
6145 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
6146 {
6147 /* Call the corresponding callback to inform upper layer of End of Transfer */
6148 I2C_ITError(hi2c, hi2c->ErrorCode);
6149
6150 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6151 if (hi2c->State == HAL_I2C_STATE_LISTEN)
6152 {
6153 /* Call I2C Listen complete process */
6154 I2C_ITListenCplt(hi2c, tmpITFlags);
6155 }
6156 }
6157 else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
6158 {
6159 /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
6160 I2C_ITSlaveSeqCplt(hi2c);
6161
6162 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6163 hi2c->State = HAL_I2C_STATE_READY;
6164 hi2c->PreviousState = I2C_STATE_NONE;
6165
6166 /* Process Unlocked */
6167 __HAL_UNLOCK(hi2c);
6168
6169 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6170 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6171 hi2c->ListenCpltCallback(hi2c);
6172 #else
6173 HAL_I2C_ListenCpltCallback(hi2c);
6174 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6175 }
6176 /* Call the corresponding callback to inform upper layer of End of Transfer */
6177 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6178 {
6179 hi2c->State = HAL_I2C_STATE_READY;
6180 hi2c->PreviousState = I2C_STATE_NONE;
6181
6182 /* Process Unlocked */
6183 __HAL_UNLOCK(hi2c);
6184
6185 /* Call the corresponding callback to inform upper layer of End of Transfer */
6186 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6187 hi2c->SlaveRxCpltCallback(hi2c);
6188 #else
6189 HAL_I2C_SlaveRxCpltCallback(hi2c);
6190 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6191 }
6192 else
6193 {
6194 hi2c->State = HAL_I2C_STATE_READY;
6195 hi2c->PreviousState = I2C_STATE_NONE;
6196
6197 /* Process Unlocked */
6198 __HAL_UNLOCK(hi2c);
6199
6200 /* Call the corresponding callback to inform upper layer of End of Transfer */
6201 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6202 hi2c->SlaveTxCpltCallback(hi2c);
6203 #else
6204 HAL_I2C_SlaveTxCpltCallback(hi2c);
6205 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6206 }
6207 }
6208
6209 /**
6210 * @brief I2C Listen complete process.
6211 * @param hi2c I2C handle.
6212 * @param ITFlags Interrupt flags to handle.
6213 * @retval None
6214 */
I2C_ITListenCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6215 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6216 {
6217 /* Reset handle parameters */
6218 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6219 hi2c->PreviousState = I2C_STATE_NONE;
6220 hi2c->State = HAL_I2C_STATE_READY;
6221 hi2c->Mode = HAL_I2C_MODE_NONE;
6222 hi2c->XferISR = NULL;
6223
6224 /* Store Last receive data if any */
6225 if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
6226 {
6227 /* Read data from RXDR */
6228 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
6229
6230 /* Increment Buffer pointer */
6231 hi2c->pBuffPtr++;
6232
6233 if ((hi2c->XferSize > 0U))
6234 {
6235 hi2c->XferSize--;
6236 hi2c->XferCount--;
6237
6238 /* Set ErrorCode corresponding to a Non-Acknowledge */
6239 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6240 }
6241 }
6242
6243 /* Disable all Interrupts*/
6244 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6245
6246 /* Clear NACK Flag */
6247 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6248
6249 /* Process Unlocked */
6250 __HAL_UNLOCK(hi2c);
6251
6252 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6253 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6254 hi2c->ListenCpltCallback(hi2c);
6255 #else
6256 HAL_I2C_ListenCpltCallback(hi2c);
6257 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6258 }
6259
6260 /**
6261 * @brief I2C interrupts error process.
6262 * @param hi2c I2C handle.
6263 * @param ErrorCode Error code to handle.
6264 * @retval None
6265 */
I2C_ITError(I2C_HandleTypeDef * hi2c,uint32_t ErrorCode)6266 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
6267 {
6268 HAL_I2C_StateTypeDef tmpstate = hi2c->State;
6269 uint32_t tmppreviousstate;
6270
6271 /* Reset handle parameters */
6272 hi2c->Mode = HAL_I2C_MODE_NONE;
6273 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6274 hi2c->XferCount = 0U;
6275
6276 /* Set new error code */
6277 hi2c->ErrorCode |= ErrorCode;
6278
6279 /* Disable Interrupts */
6280 if ((tmpstate == HAL_I2C_STATE_LISTEN) ||
6281 (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
6282 (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
6283 {
6284 /* Disable all interrupts, except interrupts related to LISTEN state */
6285 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6286
6287 /* keep HAL_I2C_STATE_LISTEN if set */
6288 hi2c->State = HAL_I2C_STATE_LISTEN;
6289 hi2c->XferISR = I2C_Slave_ISR_IT;
6290 }
6291 else
6292 {
6293 /* Disable all interrupts */
6294 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6295
6296 /* If state is an abort treatment on going, don't change state */
6297 /* This change will be do later */
6298 if (hi2c->State != HAL_I2C_STATE_ABORT)
6299 {
6300 /* Set HAL_I2C_STATE_READY */
6301 hi2c->State = HAL_I2C_STATE_READY;
6302 }
6303 hi2c->XferISR = NULL;
6304 }
6305
6306 /* Abort DMA TX transfer if any */
6307 tmppreviousstate = hi2c->PreviousState;
6308 if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
6309 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
6310 {
6311 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
6312 {
6313 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6314 }
6315
6316 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
6317 {
6318 /* Set the I2C DMA Abort callback :
6319 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6320 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
6321
6322 /* Process Unlocked */
6323 __HAL_UNLOCK(hi2c);
6324
6325 /* Abort DMA TX */
6326 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
6327 {
6328 /* Call Directly XferAbortCallback function in case of error */
6329 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
6330 }
6331 }
6332 else
6333 {
6334 I2C_TreatErrorCallback(hi2c);
6335 }
6336 }
6337 /* Abort DMA RX transfer if any */
6338 else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
6339 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
6340 {
6341 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
6342 {
6343 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6344 }
6345
6346 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
6347 {
6348 /* Set the I2C DMA Abort callback :
6349 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6350 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
6351
6352 /* Process Unlocked */
6353 __HAL_UNLOCK(hi2c);
6354
6355 /* Abort DMA RX */
6356 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
6357 {
6358 /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
6359 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
6360 }
6361 }
6362 else
6363 {
6364 I2C_TreatErrorCallback(hi2c);
6365 }
6366 }
6367 else
6368 {
6369 I2C_TreatErrorCallback(hi2c);
6370 }
6371 }
6372
6373 /**
6374 * @brief I2C Error callback treatment.
6375 * @param hi2c I2C handle.
6376 * @retval None
6377 */
I2C_TreatErrorCallback(I2C_HandleTypeDef * hi2c)6378 static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
6379 {
6380 if (hi2c->State == HAL_I2C_STATE_ABORT)
6381 {
6382 hi2c->State = HAL_I2C_STATE_READY;
6383 hi2c->PreviousState = I2C_STATE_NONE;
6384
6385 /* Process Unlocked */
6386 __HAL_UNLOCK(hi2c);
6387
6388 /* Call the corresponding callback to inform upper layer of End of Transfer */
6389 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6390 hi2c->AbortCpltCallback(hi2c);
6391 #else
6392 HAL_I2C_AbortCpltCallback(hi2c);
6393 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6394 }
6395 else
6396 {
6397 hi2c->PreviousState = I2C_STATE_NONE;
6398
6399 /* Process Unlocked */
6400 __HAL_UNLOCK(hi2c);
6401
6402 /* Call the corresponding callback to inform upper layer of End of Transfer */
6403 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6404 hi2c->ErrorCallback(hi2c);
6405 #else
6406 HAL_I2C_ErrorCallback(hi2c);
6407 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6408 }
6409 }
6410
6411 /**
6412 * @brief I2C Tx data register flush process.
6413 * @param hi2c I2C handle.
6414 * @retval None
6415 */
I2C_Flush_TXDR(I2C_HandleTypeDef * hi2c)6416 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
6417 {
6418 /* If a pending TXIS flag is set */
6419 /* Write a dummy data in TXDR to clear it */
6420 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
6421 {
6422 hi2c->Instance->TXDR = 0x00U;
6423 }
6424
6425 /* Flush TX register if not empty */
6426 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
6427 {
6428 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
6429 }
6430 }
6431
6432 /**
6433 * @brief DMA I2C master transmit process complete callback.
6434 * @param hdma DMA handle
6435 * @retval None
6436 */
I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef * hdma)6437 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
6438 {
6439 /* Derogation MISRAC2012-Rule-11.5 */
6440 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6441
6442 /* Disable DMA Request */
6443 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6444
6445 /* If last transfer, enable STOP interrupt */
6446 if (hi2c->XferCount == 0U)
6447 {
6448 /* Enable STOP interrupt */
6449 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
6450 }
6451 /* else prepare a new DMA transfer and enable TCReload interrupt */
6452 else
6453 {
6454 /* Update Buffer pointer */
6455 hi2c->pBuffPtr += hi2c->XferSize;
6456
6457 /* Set the XferSize to transfer */
6458 if (hi2c->XferCount > MAX_NBYTE_SIZE)
6459 {
6460 hi2c->XferSize = MAX_NBYTE_SIZE;
6461 }
6462 else
6463 {
6464 hi2c->XferSize = hi2c->XferCount;
6465 }
6466
6467 /* Enable the DMA stream */
6468 if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
6469 hi2c->XferSize) != HAL_OK)
6470 {
6471 /* Call the corresponding callback to inform upper layer of End of Transfer */
6472 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6473 }
6474 else
6475 {
6476 /* Enable TC interrupts */
6477 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
6478 }
6479 }
6480 }
6481
6482 /**
6483 * @brief DMA I2C slave transmit process complete callback.
6484 * @param hdma DMA handle
6485 * @retval None
6486 */
I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef * hdma)6487 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
6488 {
6489 /* Derogation MISRAC2012-Rule-11.5 */
6490 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6491 uint32_t tmpoptions = hi2c->XferOptions;
6492
6493 if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
6494 {
6495 /* Disable DMA Request */
6496 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6497
6498 /* Last Byte is Transmitted */
6499 /* Call I2C Slave Sequential complete process */
6500 I2C_ITSlaveSeqCplt(hi2c);
6501 }
6502 else
6503 {
6504 /* No specific action, Master fully manage the generation of STOP condition */
6505 /* Mean that this generation can arrive at any time, at the end or during DMA process */
6506 /* So STOP condition should be manage through Interrupt treatment */
6507 }
6508 }
6509
6510 /**
6511 * @brief DMA I2C master receive process complete callback.
6512 * @param hdma DMA handle
6513 * @retval None
6514 */
I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef * hdma)6515 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
6516 {
6517 /* Derogation MISRAC2012-Rule-11.5 */
6518 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6519
6520 /* Disable DMA Request */
6521 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6522
6523 /* If last transfer, enable STOP interrupt */
6524 if (hi2c->XferCount == 0U)
6525 {
6526 /* Enable STOP interrupt */
6527 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
6528 }
6529 /* else prepare a new DMA transfer and enable TCReload interrupt */
6530 else
6531 {
6532 /* Update Buffer pointer */
6533 hi2c->pBuffPtr += hi2c->XferSize;
6534
6535 /* Set the XferSize to transfer */
6536 if (hi2c->XferCount > MAX_NBYTE_SIZE)
6537 {
6538 hi2c->XferSize = MAX_NBYTE_SIZE;
6539 }
6540 else
6541 {
6542 hi2c->XferSize = hi2c->XferCount;
6543 }
6544
6545 /* Enable the DMA stream */
6546 if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
6547 hi2c->XferSize) != HAL_OK)
6548 {
6549 /* Call the corresponding callback to inform upper layer of End of Transfer */
6550 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6551 }
6552 else
6553 {
6554 /* Enable TC interrupts */
6555 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
6556 }
6557 }
6558 }
6559
6560 /**
6561 * @brief DMA I2C slave receive process complete callback.
6562 * @param hdma DMA handle
6563 * @retval None
6564 */
I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef * hdma)6565 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
6566 {
6567 /* Derogation MISRAC2012-Rule-11.5 */
6568 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6569 uint32_t tmpoptions = hi2c->XferOptions;
6570
6571 if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \
6572 (tmpoptions != I2C_NO_OPTION_FRAME))
6573 {
6574 /* Disable DMA Request */
6575 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6576
6577 /* Call I2C Slave Sequential complete process */
6578 I2C_ITSlaveSeqCplt(hi2c);
6579 }
6580 else
6581 {
6582 /* No specific action, Master fully manage the generation of STOP condition */
6583 /* Mean that this generation can arrive at any time, at the end or during DMA process */
6584 /* So STOP condition should be manage through Interrupt treatment */
6585 }
6586 }
6587
6588 /**
6589 * @brief DMA I2C communication error callback.
6590 * @param hdma DMA handle
6591 * @retval None
6592 */
I2C_DMAError(DMA_HandleTypeDef * hdma)6593 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
6594 {
6595 uint32_t treatdmaerror = 0U;
6596 /* Derogation MISRAC2012-Rule-11.5 */
6597 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6598
6599 if (hi2c->hdmatx != NULL)
6600 {
6601 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
6602 {
6603 treatdmaerror = 1U;
6604 }
6605 }
6606
6607 if (hi2c->hdmarx != NULL)
6608 {
6609 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
6610 {
6611 treatdmaerror = 1U;
6612 }
6613 }
6614
6615 /* Check if a FIFO error is detected, if true normal use case, so no specific action to perform */
6616 if (!((HAL_DMA_GetError(hdma) == HAL_DMA_ERROR_FE)) && (treatdmaerror != 0U))
6617 {
6618 /* Disable Acknowledge */
6619 hi2c->Instance->CR2 |= I2C_CR2_NACK;
6620
6621 /* Call the corresponding callback to inform upper layer of End of Transfer */
6622 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6623 }
6624 }
6625
6626 /**
6627 * @brief DMA I2C communication abort callback
6628 * (To be called at end of DMA Abort procedure).
6629 * @param hdma DMA handle.
6630 * @retval None
6631 */
I2C_DMAAbort(DMA_HandleTypeDef * hdma)6632 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
6633 {
6634 /* Derogation MISRAC2012-Rule-11.5 */
6635 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6636
6637 /* Reset AbortCpltCallback */
6638 if (hi2c->hdmatx != NULL)
6639 {
6640 hi2c->hdmatx->XferAbortCallback = NULL;
6641 }
6642 if (hi2c->hdmarx != NULL)
6643 {
6644 hi2c->hdmarx->XferAbortCallback = NULL;
6645 }
6646
6647 I2C_TreatErrorCallback(hi2c);
6648 }
6649
6650 /**
6651 * @brief This function handles I2C Communication Timeout. It waits
6652 * until a flag is no longer in the specified status.
6653 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6654 * the configuration information for the specified I2C.
6655 * @param Flag Specifies the I2C flag to check.
6656 * @param Status The actual Flag status (SET or RESET).
6657 * @param Timeout Timeout duration
6658 * @param Tickstart Tick start value
6659 * @retval HAL status
6660 */
I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Flag,FlagStatus Status,uint32_t Timeout,uint32_t Tickstart)6661 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
6662 uint32_t Timeout, uint32_t Tickstart)
6663 {
6664 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
6665 {
6666 /* Check for the Timeout */
6667 if (Timeout != HAL_MAX_DELAY)
6668 {
6669 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6670 {
6671 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6672 hi2c->State = HAL_I2C_STATE_READY;
6673 hi2c->Mode = HAL_I2C_MODE_NONE;
6674
6675 /* Process Unlocked */
6676 __HAL_UNLOCK(hi2c);
6677 return HAL_ERROR;
6678 }
6679 }
6680 }
6681 return HAL_OK;
6682 }
6683
6684 /**
6685 * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.
6686 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6687 * the configuration information for the specified I2C.
6688 * @param Timeout Timeout duration
6689 * @param Tickstart Tick start value
6690 * @retval HAL status
6691 */
I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)6692 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
6693 uint32_t Tickstart)
6694 {
6695 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
6696 {
6697 /* Check if an error is detected */
6698 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
6699 {
6700 return HAL_ERROR;
6701 }
6702
6703 /* Check for the Timeout */
6704 if (Timeout != HAL_MAX_DELAY)
6705 {
6706 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6707 {
6708 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6709 hi2c->State = HAL_I2C_STATE_READY;
6710 hi2c->Mode = HAL_I2C_MODE_NONE;
6711
6712 /* Process Unlocked */
6713 __HAL_UNLOCK(hi2c);
6714
6715 return HAL_ERROR;
6716 }
6717 }
6718 }
6719 return HAL_OK;
6720 }
6721
6722 /**
6723 * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
6724 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6725 * the configuration information for the specified I2C.
6726 * @param Timeout Timeout duration
6727 * @param Tickstart Tick start value
6728 * @retval HAL status
6729 */
I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)6730 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
6731 uint32_t Tickstart)
6732 {
6733 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
6734 {
6735 /* Check if an error is detected */
6736 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
6737 {
6738 return HAL_ERROR;
6739 }
6740
6741 /* Check for the Timeout */
6742 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6743 {
6744 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6745 hi2c->State = HAL_I2C_STATE_READY;
6746 hi2c->Mode = HAL_I2C_MODE_NONE;
6747
6748 /* Process Unlocked */
6749 __HAL_UNLOCK(hi2c);
6750
6751 return HAL_ERROR;
6752 }
6753 }
6754 return HAL_OK;
6755 }
6756
6757 /**
6758 * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
6759 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6760 * the configuration information for the specified I2C.
6761 * @param Timeout Timeout duration
6762 * @param Tickstart Tick start value
6763 * @retval HAL status
6764 */
I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)6765 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
6766 uint32_t Tickstart)
6767 {
6768 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
6769 {
6770 /* Check if an error is detected */
6771 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
6772 {
6773 return HAL_ERROR;
6774 }
6775
6776 /* Check if a STOPF is detected */
6777 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
6778 {
6779 /* Check if an RXNE is pending */
6780 /* Store Last receive data if any */
6781 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
6782 {
6783 /* Return HAL_OK */
6784 /* The Reading of data from RXDR will be done in caller function */
6785 return HAL_OK;
6786 }
6787 else
6788 {
6789 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
6790 {
6791 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6792 hi2c->ErrorCode = HAL_I2C_ERROR_AF;
6793 }
6794 else
6795 {
6796 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
6797 }
6798
6799 /* Clear STOP Flag */
6800 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6801
6802 /* Clear Configuration Register 2 */
6803 I2C_RESET_CR2(hi2c);
6804
6805 hi2c->State = HAL_I2C_STATE_READY;
6806 hi2c->Mode = HAL_I2C_MODE_NONE;
6807
6808 /* Process Unlocked */
6809 __HAL_UNLOCK(hi2c);
6810
6811 return HAL_ERROR;
6812 }
6813 }
6814
6815 /* Check for the Timeout */
6816 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6817 {
6818 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6819 hi2c->State = HAL_I2C_STATE_READY;
6820
6821 /* Process Unlocked */
6822 __HAL_UNLOCK(hi2c);
6823
6824 return HAL_ERROR;
6825 }
6826 }
6827 return HAL_OK;
6828 }
6829
6830 /**
6831 * @brief This function handles errors detection during an I2C Communication.
6832 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6833 * the configuration information for the specified I2C.
6834 * @param Timeout Timeout duration
6835 * @param Tickstart Tick start value
6836 * @retval HAL status
6837 */
I2C_IsErrorOccurred(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)6838 static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
6839 {
6840 HAL_StatusTypeDef status = HAL_OK;
6841 uint32_t itflag = hi2c->Instance->ISR;
6842 uint32_t error_code = 0;
6843 uint32_t tickstart = Tickstart;
6844 uint32_t tmp1;
6845 HAL_I2C_ModeTypeDef tmp2;
6846
6847 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
6848 {
6849 /* Clear NACKF Flag */
6850 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6851
6852 /* Wait until STOP Flag is set or timeout occurred */
6853 /* AutoEnd should be initiate after AF */
6854 while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
6855 {
6856 /* Check for the Timeout */
6857 if (Timeout != HAL_MAX_DELAY)
6858 {
6859 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
6860 {
6861 tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
6862 tmp2 = hi2c->Mode;
6863
6864 /* In case of I2C still busy, try to regenerate a STOP manually */
6865 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
6866 (tmp1 != I2C_CR2_STOP) && \
6867 (tmp2 != HAL_I2C_MODE_SLAVE))
6868 {
6869 /* Generate Stop */
6870 hi2c->Instance->CR2 |= I2C_CR2_STOP;
6871
6872 /* Update Tick with new reference */
6873 tickstart = HAL_GetTick();
6874 }
6875
6876 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
6877 {
6878 /* Check for the Timeout */
6879 if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
6880 {
6881 error_code |=HAL_I2C_ERROR_TIMEOUT;
6882
6883 status = HAL_ERROR;
6884
6885 break;
6886 }
6887 }
6888 }
6889 }
6890 }
6891
6892 /* In case STOP Flag is detected, clear it */
6893 if (status == HAL_OK)
6894 {
6895 /* Clear STOP Flag */
6896 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6897 }
6898
6899 error_code |= HAL_I2C_ERROR_AF;
6900
6901 status = HAL_ERROR;
6902 }
6903
6904 /* Refresh Content of Status register */
6905 itflag = hi2c->Instance->ISR;
6906
6907 /* Then verify if an additional errors occurs */
6908 /* Check if a Bus error occurred */
6909 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
6910 {
6911 error_code |= HAL_I2C_ERROR_BERR;
6912
6913 /* Clear BERR flag */
6914 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
6915
6916 status = HAL_ERROR;
6917 }
6918
6919 /* Check if an Over-Run/Under-Run error occurred */
6920 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
6921 {
6922 error_code |= HAL_I2C_ERROR_OVR;
6923
6924 /* Clear OVR flag */
6925 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
6926
6927 status = HAL_ERROR;
6928 }
6929
6930 /* Check if an Arbitration Loss error occurred */
6931 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
6932 {
6933 error_code |= HAL_I2C_ERROR_ARLO;
6934
6935 /* Clear ARLO flag */
6936 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
6937
6938 status = HAL_ERROR;
6939 }
6940
6941 if (status != HAL_OK)
6942 {
6943 /* Flush TX register */
6944 I2C_Flush_TXDR(hi2c);
6945
6946 /* Clear Configuration Register 2 */
6947 I2C_RESET_CR2(hi2c);
6948
6949 hi2c->ErrorCode |= error_code;
6950 hi2c->State = HAL_I2C_STATE_READY;
6951 hi2c->Mode = HAL_I2C_MODE_NONE;
6952
6953 /* Process Unlocked */
6954 __HAL_UNLOCK(hi2c);
6955 }
6956
6957 return status;
6958 }
6959
6960 /**
6961 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
6962 * @param hi2c I2C handle.
6963 * @param DevAddress Specifies the slave address to be programmed.
6964 * @param Size Specifies the number of bytes to be programmed.
6965 * This parameter must be a value between 0 and 255.
6966 * @param Mode New state of the I2C START condition generation.
6967 * This parameter can be one of the following values:
6968 * @arg @ref I2C_RELOAD_MODE Enable Reload mode .
6969 * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
6970 * @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
6971 * @param Request New state of the I2C START condition generation.
6972 * This parameter can be one of the following values:
6973 * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
6974 * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
6975 * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
6976 * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
6977 * @retval None
6978 */
I2C_TransferConfig(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t Size,uint32_t Mode,uint32_t Request)6979 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
6980 uint32_t Request)
6981 {
6982 /* Check the parameters */
6983 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
6984 assert_param(IS_TRANSFER_MODE(Mode));
6985 assert_param(IS_TRANSFER_REQUEST(Request));
6986
6987 /* Declaration of tmp to prevent undefined behavior of volatile usage */
6988 uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
6989 (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
6990 (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
6991
6992 /* update CR2 register */
6993 MODIFY_REG(hi2c->Instance->CR2, \
6994 ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
6995 (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
6996 I2C_CR2_START | I2C_CR2_STOP)), tmp);
6997 }
6998
6999 /**
7000 * @brief Manage the enabling of Interrupts.
7001 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7002 * the configuration information for the specified I2C.
7003 * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
7004 * @retval None
7005 */
I2C_Enable_IRQ(I2C_HandleTypeDef * hi2c,uint16_t InterruptRequest)7006 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
7007 {
7008 uint32_t tmpisr = 0U;
7009
7010 if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
7011 (hi2c->XferISR == I2C_Slave_ISR_DMA))
7012 {
7013 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7014 {
7015 /* Enable ERR, STOP, NACK and ADDR interrupts */
7016 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7017 }
7018
7019 if (InterruptRequest == I2C_XFER_ERROR_IT)
7020 {
7021 /* Enable ERR and NACK interrupts */
7022 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7023 }
7024
7025 if (InterruptRequest == I2C_XFER_CPLT_IT)
7026 {
7027 /* Enable STOP interrupts */
7028 tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
7029 }
7030
7031 if (InterruptRequest == I2C_XFER_RELOAD_IT)
7032 {
7033 /* Enable TC interrupts */
7034 tmpisr |= I2C_IT_TCI;
7035 }
7036 }
7037 else
7038 {
7039 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7040 {
7041 /* Enable ERR, STOP, NACK, and ADDR interrupts */
7042 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7043 }
7044
7045 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7046 {
7047 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
7048 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
7049 }
7050
7051 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7052 {
7053 /* Enable ERR, TC, STOP, NACK and TXI interrupts */
7054 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
7055 }
7056
7057 if (InterruptRequest == I2C_XFER_ERROR_IT)
7058 {
7059 /* Enable ERR and NACK interrupts */
7060 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7061 }
7062
7063 if (InterruptRequest == I2C_XFER_CPLT_IT)
7064 {
7065 /* Enable STOP interrupts */
7066 tmpisr |= I2C_IT_STOPI;
7067 }
7068 }
7069
7070 /* Enable interrupts only at the end */
7071 /* to avoid the risk of I2C interrupt handle execution before */
7072 /* all interrupts requested done */
7073 __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
7074 }
7075
7076 /**
7077 * @brief Manage the disabling of Interrupts.
7078 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7079 * the configuration information for the specified I2C.
7080 * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
7081 * @retval None
7082 */
I2C_Disable_IRQ(I2C_HandleTypeDef * hi2c,uint16_t InterruptRequest)7083 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
7084 {
7085 uint32_t tmpisr = 0U;
7086
7087 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7088 {
7089 /* Disable TC and TXI interrupts */
7090 tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
7091
7092 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
7093 {
7094 /* Disable NACK and STOP interrupts */
7095 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7096 }
7097 }
7098
7099 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7100 {
7101 /* Disable TC and RXI interrupts */
7102 tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
7103
7104 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
7105 {
7106 /* Disable NACK and STOP interrupts */
7107 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7108 }
7109 }
7110
7111 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7112 {
7113 /* Disable ADDR, NACK and STOP interrupts */
7114 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7115 }
7116
7117 if (InterruptRequest == I2C_XFER_ERROR_IT)
7118 {
7119 /* Enable ERR and NACK interrupts */
7120 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7121 }
7122
7123 if (InterruptRequest == I2C_XFER_CPLT_IT)
7124 {
7125 /* Enable STOP interrupts */
7126 tmpisr |= I2C_IT_STOPI;
7127 }
7128
7129 if (InterruptRequest == I2C_XFER_RELOAD_IT)
7130 {
7131 /* Enable TC interrupts */
7132 tmpisr |= I2C_IT_TCI;
7133 }
7134
7135 /* Disable interrupts only at the end */
7136 /* to avoid a breaking situation like at "t" time */
7137 /* all disable interrupts request are not done */
7138 __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
7139 }
7140
7141 /**
7142 * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
7143 * @param hi2c I2C handle.
7144 * @retval None
7145 */
I2C_ConvertOtherXferOptions(I2C_HandleTypeDef * hi2c)7146 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
7147 {
7148 /* if user set XferOptions to I2C_OTHER_FRAME */
7149 /* it request implicitly to generate a restart condition */
7150 /* set XferOptions to I2C_FIRST_FRAME */
7151 if (hi2c->XferOptions == I2C_OTHER_FRAME)
7152 {
7153 hi2c->XferOptions = I2C_FIRST_FRAME;
7154 }
7155 /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
7156 /* it request implicitly to generate a restart condition */
7157 /* then generate a stop condition at the end of transfer */
7158 /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */
7159 else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
7160 {
7161 hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
7162 }
7163 else
7164 {
7165 /* Nothing to do */
7166 }
7167 }
7168
7169 /**
7170 * @}
7171 */
7172
7173 #endif /* HAL_I2C_MODULE_ENABLED */
7174 /**
7175 * @}
7176 */
7177
7178 /**
7179 * @}
7180 */
7181
