1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_adc.c
4 * @author MCD Application Team
5 * @brief This file provides firmware functions to manage the following
6 * functionalities of the Analog to Digital Converter (ADC) peripheral:
7 * + Initialization and de-initialization functions
8 * + Peripheral Control functions
9 * + Peripheral State functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2017 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software is licensed under terms that can be found in the LICENSE file
18 * in the root directory of this software component.
19 * If no LICENSE file comes with this software, it is provided AS-IS.
20 *
21 ******************************************************************************
22 @verbatim
23 ==============================================================================
24 ##### ADC Peripheral features #####
25 ==============================================================================
26 [..]
27 (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
28 (#) Interrupt generation at the end of conversion, end of injected conversion,
29 and in case of analog watchdog or overrun events
30 (#) Single and continuous conversion modes.
31 (#) Scan mode for automatic conversion of channel 0 to channel x.
32 (#) Data alignment with in-built data coherency.
33 (#) Channel-wise programmable sampling time.
34 (#) External trigger option with configurable polarity for both regular and
35 injected conversion.
36 (#) Dual/Triple mode (on devices with 2 ADCs or more).
37 (#) Configurable DMA data storage in Dual/Triple ADC mode.
38 (#) Configurable delay between conversions in Dual/Triple interleaved mode.
39 (#) ADC conversion type (refer to the datasheets).
40 (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
41 slower speed.
42 (#) ADC input range: VREF(minus) = VIN = VREF(plus).
43 (#) DMA request generation during regular channel conversion.
44
45
46 ##### How to use this driver #####
47 ==============================================================================
48 [..]
49 (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
50 (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
51 (##) ADC pins configuration
52 (+++) Enable the clock for the ADC GPIOs using the following function:
53 __HAL_RCC_GPIOx_CLK_ENABLE()
54 (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
55 (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
56 (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
57 (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
58 (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
59 (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
60 (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
61 (+++) Configure and enable two DMA streams stream for managing data
62 transfer from peripheral to memory (output stream)
63 (+++) Associate the initialized DMA handle to the CRYP DMA handle
64 using __HAL_LINKDMA()
65 (+++) Configure the priority and enable the NVIC for the transfer complete
66 interrupt on the two DMA Streams. The output stream should have higher
67 priority than the input stream.
68
69 *** Configuration of ADC, groups regular/injected, channels parameters ***
70 ==============================================================================
71 [..]
72 (#) Configure the ADC parameters (resolution, data alignment, ...)
73 and regular group parameters (conversion trigger, sequencer, ...)
74 using function HAL_ADC_Init().
75
76 (#) Configure the channels for regular group parameters (channel number,
77 channel rank into sequencer, ..., into regular group)
78 using function HAL_ADC_ConfigChannel().
79
80 (#) Optionally, configure the injected group parameters (conversion trigger,
81 sequencer, ..., of injected group)
82 and the channels for injected group parameters (channel number,
83 channel rank into sequencer, ..., into injected group)
84 using function HAL_ADCEx_InjectedConfigChannel().
85
86 (#) Optionally, configure the analog watchdog parameters (channels
87 monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig().
88
89 (#) Optionally, for devices with several ADC instances: configure the
90 multimode parameters using function HAL_ADCEx_MultiModeConfigChannel().
91
92 *** Execution of ADC conversions ***
93 ==============================================================================
94 [..]
95 (#) ADC driver can be used among three modes: polling, interruption,
96 transfer by DMA.
97
98 *** Polling mode IO operation ***
99 =================================
100 [..]
101 (+) Start the ADC peripheral using HAL_ADC_Start()
102 (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
103 user can specify the value of timeout according to his end application
104 (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
105 (+) Stop the ADC peripheral using HAL_ADC_Stop()
106
107 *** Interrupt mode IO operation ***
108 ===================================
109 [..]
110 (+) Start the ADC peripheral using HAL_ADC_Start_IT()
111 (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
112 (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can
113 add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
114 (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can
115 add his own code by customization of function pointer HAL_ADC_ErrorCallback
116 (+) Stop the ADC peripheral using HAL_ADC_Stop_IT()
117
118 *** DMA mode IO operation ***
119 ==============================
120 [..]
121 (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length
122 of data to be transferred at each end of conversion
123 (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can
124 add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
125 (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can
126 add his own code by customization of function pointer HAL_ADC_ErrorCallback
127 (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA()
128
129 *** ADC HAL driver macros list ***
130 =============================================
131 [..]
132 Below the list of most used macros in ADC HAL driver.
133
134 (+) __HAL_ADC_ENABLE : Enable the ADC peripheral
135 (+) __HAL_ADC_DISABLE : Disable the ADC peripheral
136 (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt
137 (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt
138 (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled
139 (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags
140 (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status
141 (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register
142
143 *** Callback functions ***
144 ==============================
145 [..]
146 (@) Callback functions must be implemented in user program:
147 (+@) HAL_ADC_ErrorCallback()
148 (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
149 (+@) HAL_ADC_ConvCpltCallback()
150 (+@) HAL_ADC_ConvHalfCpltCallback
151
152 (@) You can refer to the ADC HAL driver header file for more useful macros
153
154 *** Deinitialization of ADC ***
155 ==============================================================================
156 [..]
157 (#) Disable the ADC interface
158 (++) ADC clock can be hard reset and disabled at RCC top level.
159 (++) Hard reset of ADC peripherals
160 using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET().
161 (++) ADC clock disable using the equivalent macro/functions as configuration step.
162 (+++) Example:
163 Into HAL_ADC_MspDeInit() (recommended code location) or with
164 other device clock parameters configuration:
165 (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);
166 (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
167 (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)
168 (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
169
170 (#) ADC pins configuration
171 (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE()
172
173 (#) Optionally, in case of usage of ADC with interruptions:
174 (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn)
175
176 (#) Optionally, in case of usage of DMA:
177 (++) Deinitialize the DMA using function HAL_DMA_DeInit().
178 (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)
179
180 *** Callback registration ***
181 ==============================================================================
182 [..]
183
184 The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
185 allows the user to configure dynamically the driver callbacks.
186 Use Functions HAL_ADC_RegisterCallback()
187 to register an interrupt callback.
188 [..]
189
190 Function HAL_ADC_RegisterCallback() allows to register following callbacks:
191 (+) ConvCpltCallback : ADC conversion complete callback
192 (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
193 (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
194 (+) ErrorCallback : ADC error callback
195 (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
196 (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
197 (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
198 (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
199 (+) EndOfSamplingCallback : ADC end of sampling callback
200 (+) MspInitCallback : ADC Msp Init callback
201 (+) MspDeInitCallback : ADC Msp DeInit callback
202 This function takes as parameters the HAL peripheral handle, the Callback ID
203 and a pointer to the user callback function.
204 [..]
205
206 Use function HAL_ADC_UnRegisterCallback to reset a callback to the default
207 weak function.
208 [..]
209
210 HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
211 and the Callback ID.
212 This function allows to reset following callbacks:
213 (+) ConvCpltCallback : ADC conversion complete callback
214 (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
215 (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
216 (+) ErrorCallback : ADC error callback
217 (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
218 (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
219 (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
220 (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
221 (+) EndOfSamplingCallback : ADC end of sampling callback
222 (+) MspInitCallback : ADC Msp Init callback
223 (+) MspDeInitCallback : ADC Msp DeInit callback
224 [..]
225
226 By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET
227 all callbacks are set to the corresponding weak functions:
228 examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback().
229 Exception done for MspInit and MspDeInit functions that are
230 reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when
231 these callbacks are null (not registered beforehand).
232 [..]
233
234 If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit()
235 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
236 [..]
237
238 Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only.
239 Exception done MspInit/MspDeInit functions that can be registered/unregistered
240 in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state,
241 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
242 [..]
243
244 Then, the user first registers the MspInit/MspDeInit user callbacks
245 using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit()
246 or HAL_ADC_Init() function.
247 [..]
248
249 When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
250 not defined, the callback registration feature is not available and all callbacks
251 are set to the corresponding weak functions.
252
253 @endverbatim
254 ******************************************************************************
255 */
256
257 /* Includes ------------------------------------------------------------------*/
258 #include "stm32f7xx_hal.h"
259
260 /** @addtogroup STM32F7xx_HAL_Driver
261 * @{
262 */
263
264 /** @defgroup ADC ADC
265 * @brief ADC driver modules
266 * @{
267 */
268
269 #ifdef HAL_ADC_MODULE_ENABLED
270
271 /* Private typedef -----------------------------------------------------------*/
272 /* Private define ------------------------------------------------------------*/
273 /* Private macro -------------------------------------------------------------*/
274 /* Private variables ---------------------------------------------------------*/
275 /** @addtogroup ADC_Private_Functions
276 * @{
277 */
278 /* Private function prototypes -----------------------------------------------*/
279 static void ADC_Init(ADC_HandleTypeDef* hadc);
280 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
281 static void ADC_DMAError(DMA_HandleTypeDef *hdma);
282 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
283 /**
284 * @}
285 */
286
287 /* Exported functions --------------------------------------------------------*/
288 /** @defgroup ADC_Exported_Functions ADC Exported Functions
289 * @{
290 */
291
292 /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
293 * @brief Initialization and Configuration functions
294 *
295 @verbatim
296 ===============================================================================
297 ##### Initialization and de-initialization functions #####
298 ===============================================================================
299 [..] This section provides functions allowing to:
300 (+) Initialize and configure the ADC.
301 (+) De-initialize the ADC.
302
303 @endverbatim
304 * @{
305 */
306
307 /**
308 * @brief Initializes the ADCx peripheral according to the specified parameters
309 * in the ADC_InitStruct and initializes the ADC MSP.
310 *
311 * @note This function is used to configure the global features of the ADC (
312 * ClockPrescaler, Resolution, Data Alignment and number of conversion), however,
313 * the rest of the configuration parameters are specific to the regular
314 * channels group (scan mode activation, continuous mode activation,
315 * External trigger source and edge, DMA continuous request after the
316 * last transfer and End of conversion selection).
317 *
318 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
319 * the configuration information for the specified ADC.
320 * @retval HAL status
321 */
HAL_ADC_Init(ADC_HandleTypeDef * hadc)322 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
323 {
324 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
325
326 /* Check ADC handle */
327 if(hadc == NULL)
328 {
329 return HAL_ERROR;
330 }
331
332 /* Check the parameters */
333 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
334 assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
335 assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
336 assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
337 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
338 assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv));
339 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
340 assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
341 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
342 assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
343 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
344
345 if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
346 {
347 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
348 }
349
350 if(hadc->State == HAL_ADC_STATE_RESET)
351 {
352 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
353 /* Init the ADC Callback settings */
354 hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */
355 hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */
356 hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */
357 hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */
358 hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */
359 if (hadc->MspInitCallback == NULL)
360 {
361 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
362 }
363
364 /* Init the low level hardware */
365 hadc->MspInitCallback(hadc);
366 #else
367 /* Init the low level hardware */
368 HAL_ADC_MspInit(hadc);
369 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
370
371 /* Initialize ADC error code */
372 ADC_CLEAR_ERRORCODE(hadc);
373
374 /* Allocate lock resource and initialize it */
375 hadc->Lock = HAL_UNLOCKED;
376 }
377
378 /* Configuration of ADC parameters if previous preliminary actions are */
379 /* correctly completed. */
380 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
381 {
382 /* Set ADC state */
383 ADC_STATE_CLR_SET(hadc->State,
384 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
385 HAL_ADC_STATE_BUSY_INTERNAL);
386
387 /* Set ADC parameters */
388 ADC_Init(hadc);
389
390 /* Set ADC error code to none */
391 ADC_CLEAR_ERRORCODE(hadc);
392
393 /* Set the ADC state */
394 ADC_STATE_CLR_SET(hadc->State,
395 HAL_ADC_STATE_BUSY_INTERNAL,
396 HAL_ADC_STATE_READY);
397 }
398 else
399 {
400 tmp_hal_status = HAL_ERROR;
401 }
402
403 /* Release Lock */
404 __HAL_UNLOCK(hadc);
405
406 /* Return function status */
407 return tmp_hal_status;
408 }
409
410 /**
411 * @brief Deinitializes the ADCx peripheral registers to their default reset values.
412 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
413 * the configuration information for the specified ADC.
414 * @retval HAL status
415 */
HAL_ADC_DeInit(ADC_HandleTypeDef * hadc)416 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
417 {
418 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
419
420 /* Check ADC handle */
421 if(hadc == NULL)
422 {
423 return HAL_ERROR;
424 }
425
426 /* Check the parameters */
427 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
428
429 /* Set ADC state */
430 SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
431
432 /* Stop potential conversion on going, on regular and injected groups */
433 /* Disable ADC peripheral */
434 __HAL_ADC_DISABLE(hadc);
435
436 /* Configuration of ADC parameters if previous preliminary actions are */
437 /* correctly completed. */
438 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
439 {
440 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
441 if (hadc->MspDeInitCallback == NULL)
442 {
443 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
444 }
445
446 /* DeInit the low level hardware: RCC clock, NVIC */
447 hadc->MspDeInitCallback(hadc);
448 #else
449 /* DeInit the low level hardware: RCC clock, NVIC */
450 HAL_ADC_MspDeInit(hadc);
451 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
452
453 /* Set ADC error code to none */
454 ADC_CLEAR_ERRORCODE(hadc);
455
456 /* Set ADC state */
457 hadc->State = HAL_ADC_STATE_RESET;
458 }
459
460 /* Process unlocked */
461 __HAL_UNLOCK(hadc);
462
463 /* Return function status */
464 return tmp_hal_status;
465 }
466
467 /**
468 * @brief Initializes the ADC MSP.
469 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
470 * the configuration information for the specified ADC.
471 * @retval None
472 */
HAL_ADC_MspInit(ADC_HandleTypeDef * hadc)473 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
474 {
475 /* Prevent unused argument(s) compilation warning */
476 UNUSED(hadc);
477 /* NOTE : This function Should not be modified, when the callback is needed,
478 the HAL_ADC_MspInit could be implemented in the user file
479 */
480 }
481
482 /**
483 * @brief DeInitializes the ADC MSP.
484 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
485 * the configuration information for the specified ADC.
486 * @retval None
487 */
HAL_ADC_MspDeInit(ADC_HandleTypeDef * hadc)488 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
489 {
490 /* Prevent unused argument(s) compilation warning */
491 UNUSED(hadc);
492 /* NOTE : This function Should not be modified, when the callback is needed,
493 the HAL_ADC_MspDeInit could be implemented in the user file
494 */
495 }
496
497 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
498 /**
499 * @brief Register a User ADC Callback
500 * To be used instead of the weak predefined callback
501 * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
502 * the configuration information for the specified ADC.
503 * @param CallbackID ID of the callback to be registered
504 * This parameter can be one of the following values:
505 * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
506 * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
507 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
508 * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
509 * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
510 * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
511 * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
512 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
513 * @param pCallback pointer to the Callback function
514 * @retval HAL status
515 */
HAL_ADC_RegisterCallback(ADC_HandleTypeDef * hadc,HAL_ADC_CallbackIDTypeDef CallbackID,pADC_CallbackTypeDef pCallback)516 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
517 {
518 HAL_StatusTypeDef status = HAL_OK;
519
520 if (pCallback == NULL)
521 {
522 /* Update the error code */
523 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
524
525 return HAL_ERROR;
526 }
527
528 if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
529 {
530 switch (CallbackID)
531 {
532 case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
533 hadc->ConvCpltCallback = pCallback;
534 break;
535
536 case HAL_ADC_CONVERSION_HALF_CB_ID :
537 hadc->ConvHalfCpltCallback = pCallback;
538 break;
539
540 case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
541 hadc->LevelOutOfWindowCallback = pCallback;
542 break;
543
544 case HAL_ADC_ERROR_CB_ID :
545 hadc->ErrorCallback = pCallback;
546 break;
547
548 case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
549 hadc->InjectedConvCpltCallback = pCallback;
550 break;
551
552 case HAL_ADC_MSPINIT_CB_ID :
553 hadc->MspInitCallback = pCallback;
554 break;
555
556 case HAL_ADC_MSPDEINIT_CB_ID :
557 hadc->MspDeInitCallback = pCallback;
558 break;
559
560 default :
561 /* Update the error code */
562 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
563
564 /* Return error status */
565 status = HAL_ERROR;
566 break;
567 }
568 }
569 else if (HAL_ADC_STATE_RESET == hadc->State)
570 {
571 switch (CallbackID)
572 {
573 case HAL_ADC_MSPINIT_CB_ID :
574 hadc->MspInitCallback = pCallback;
575 break;
576
577 case HAL_ADC_MSPDEINIT_CB_ID :
578 hadc->MspDeInitCallback = pCallback;
579 break;
580
581 default :
582 /* Update the error code */
583 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
584
585 /* Return error status */
586 status = HAL_ERROR;
587 break;
588 }
589 }
590 else
591 {
592 /* Update the error code */
593 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
594
595 /* Return error status */
596 status = HAL_ERROR;
597 }
598
599 return status;
600 }
601
602 /**
603 * @brief Unregister a ADC Callback
604 * ADC callback is redirected to the weak predefined callback
605 * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
606 * the configuration information for the specified ADC.
607 * @param CallbackID ID of the callback to be unregistered
608 * This parameter can be one of the following values:
609 * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
610 * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
611 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
612 * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
613 * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
614 * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
615 * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
616 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
617 * @retval HAL status
618 */
HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef * hadc,HAL_ADC_CallbackIDTypeDef CallbackID)619 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
620 {
621 HAL_StatusTypeDef status = HAL_OK;
622
623 if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
624 {
625 switch (CallbackID)
626 {
627 case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
628 hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
629 break;
630
631 case HAL_ADC_CONVERSION_HALF_CB_ID :
632 hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
633 break;
634
635 case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
636 hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
637 break;
638
639 case HAL_ADC_ERROR_CB_ID :
640 hadc->ErrorCallback = HAL_ADC_ErrorCallback;
641 break;
642
643 case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
644 hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
645 break;
646
647 case HAL_ADC_MSPINIT_CB_ID :
648 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
649 break;
650
651 case HAL_ADC_MSPDEINIT_CB_ID :
652 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
653 break;
654
655 default :
656 /* Update the error code */
657 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
658
659 /* Return error status */
660 status = HAL_ERROR;
661 break;
662 }
663 }
664 else if (HAL_ADC_STATE_RESET == hadc->State)
665 {
666 switch (CallbackID)
667 {
668 case HAL_ADC_MSPINIT_CB_ID :
669 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
670 break;
671
672 case HAL_ADC_MSPDEINIT_CB_ID :
673 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
674 break;
675
676 default :
677 /* Update the error code */
678 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
679
680 /* Return error status */
681 status = HAL_ERROR;
682 break;
683 }
684 }
685 else
686 {
687 /* Update the error code */
688 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
689
690 /* Return error status */
691 status = HAL_ERROR;
692 }
693
694 return status;
695 }
696
697 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
698
699
700 /**
701 * @}
702 */
703
704 /** @defgroup ADC_Exported_Functions_Group2 IO operation functions
705 * @brief IO operation functions
706 *
707 @verbatim
708 ===============================================================================
709 ##### IO operation functions #####
710 ===============================================================================
711 [..] This section provides functions allowing to:
712 (+) Start conversion of regular channel.
713 (+) Stop conversion of regular channel.
714 (+) Start conversion of regular channel and enable interrupt.
715 (+) Stop conversion of regular channel and disable interrupt.
716 (+) Start conversion of regular channel and enable DMA transfer.
717 (+) Stop conversion of regular channel and disable DMA transfer.
718 (+) Handle ADC interrupt request.
719
720 @endverbatim
721 * @{
722 */
723
724 /**
725 * @brief Enables ADC and starts conversion of the regular channels.
726 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
727 * the configuration information for the specified ADC.
728 * @retval HAL status
729 */
HAL_ADC_Start(ADC_HandleTypeDef * hadc)730 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
731 {
732 __IO uint32_t counter = 0;
733
734 /* Check the parameters */
735 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
736 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
737
738 /* Process locked */
739 __HAL_LOCK(hadc);
740
741 /* Enable the ADC peripheral */
742 /* Check if ADC peripheral is disabled in order to enable it and wait during
743 Tstab time the ADC's stabilization */
744 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
745 {
746 /* Enable the Peripheral */
747 __HAL_ADC_ENABLE(hadc);
748
749 /* Delay for ADC stabilization time */
750 /* Compute number of CPU cycles to wait for */
751 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
752 while(counter != 0)
753 {
754 counter--;
755 }
756 }
757
758 /* Start conversion if ADC is effectively enabled */
759 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
760 {
761 /* Set ADC state */
762 /* - Clear state bitfield related to regular group conversion results */
763 /* - Set state bitfield related to regular group operation */
764 ADC_STATE_CLR_SET(hadc->State,
765 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
766 HAL_ADC_STATE_REG_BUSY);
767
768 /* If conversions on group regular are also triggering group injected, */
769 /* update ADC state. */
770 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
771 {
772 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
773 }
774
775 /* State machine update: Check if an injected conversion is ongoing */
776 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
777 {
778 /* Reset ADC error code fields related to conversions on group regular */
779 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
780 }
781 else
782 {
783 /* Reset ADC all error code fields */
784 ADC_CLEAR_ERRORCODE(hadc);
785 }
786
787 /* Process unlocked */
788 /* Unlock before starting ADC conversions: in case of potential */
789 /* interruption, to let the process to ADC IRQ Handler. */
790 __HAL_UNLOCK(hadc);
791
792 /* Clear regular group conversion flag and overrun flag */
793 /* (To ensure of no unknown state from potential previous ADC operations) */
794 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
795
796 /* Check if Multimode enabled */
797 if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
798 {
799 /* if no external trigger present enable software conversion of regular channels */
800 if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
801 {
802 /* Enable the selected ADC software conversion for regular group */
803 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
804 }
805 }
806 else
807 {
808 /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
809 if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
810 {
811 /* Enable the selected ADC software conversion for regular group */
812 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
813 }
814
815 /* if dual mode is selected, ADC3 works independently. */
816 /* check if the mode selected is not triple */
817 if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) )
818 {
819 /* if instance of handle correspond to ADC3 and no external trigger present enable software conversion of regular channels */
820 if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
821 {
822 /* Enable the selected ADC software conversion for regular group */
823 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
824 }
825 }
826 }
827 }
828 else
829 {
830 /* Update ADC state machine to error */
831 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
832
833 /* Set ADC error code to ADC IP internal error */
834 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
835 }
836
837 /* Return function status */
838 return HAL_OK;
839 }
840
841 /**
842 * @brief Disables ADC and stop conversion of regular channels.
843 *
844 * @note Caution: This function will stop also injected channels.
845 *
846 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
847 * the configuration information for the specified ADC.
848 *
849 * @retval HAL status.
850 */
HAL_ADC_Stop(ADC_HandleTypeDef * hadc)851 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
852 {
853 /* Check the parameters */
854 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
855
856 /* Process locked */
857 __HAL_LOCK(hadc);
858
859 /* Stop potential conversion on going, on regular and injected groups */
860 /* Disable ADC peripheral */
861 __HAL_ADC_DISABLE(hadc);
862
863 /* Check if ADC is effectively disabled */
864 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
865 {
866 /* Set ADC state */
867 ADC_STATE_CLR_SET(hadc->State,
868 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
869 HAL_ADC_STATE_READY);
870 }
871
872 /* Process unlocked */
873 __HAL_UNLOCK(hadc);
874
875 /* Return function status */
876 return HAL_OK;
877 }
878
879 /**
880 * @brief Poll for regular conversion complete
881 * @note ADC conversion flags EOS (end of sequence) and EOC (end of
882 * conversion) are cleared by this function.
883 * @note This function cannot be used in a particular setup: ADC configured
884 * in DMA mode and polling for end of each conversion (ADC init
885 * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
886 * In this case, DMA resets the flag EOC and polling cannot be
887 * performed on each conversion. Nevertheless, polling can still
888 * be performed on the complete sequence.
889 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
890 * the configuration information for the specified ADC.
891 * @param Timeout Timeout value in millisecond.
892 * @retval HAL status
893 */
HAL_ADC_PollForConversion(ADC_HandleTypeDef * hadc,uint32_t Timeout)894 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
895 {
896 uint32_t tickstart = 0;
897
898 /* Verification that ADC configuration is compliant with polling for */
899 /* each conversion: */
900 /* Particular case is ADC configured in DMA mode and ADC sequencer with */
901 /* several ranks and polling for end of each conversion. */
902 /* For code simplicity sake, this particular case is generalized to */
903 /* ADC configured in DMA mode and polling for end of each conversion. */
904 if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
905 HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) )
906 {
907 /* Update ADC state machine to error */
908 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
909
910 /* Process unlocked */
911 __HAL_UNLOCK(hadc);
912
913 return HAL_ERROR;
914 }
915
916 /* Get tick */
917 tickstart = HAL_GetTick();
918
919 /* Check End of conversion flag */
920 while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
921 {
922 /* Check if timeout is disabled (set to infinite wait) */
923 if(Timeout != HAL_MAX_DELAY)
924 {
925 if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
926 {
927 /* New check to avoid false timeout detection in case of preemption */
928 if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
929 {
930 /* Update ADC state machine to timeout */
931 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
932
933 /* Process unlocked */
934 __HAL_UNLOCK(hadc);
935
936 return HAL_TIMEOUT;
937 }
938 }
939 }
940 }
941
942 /* Clear regular group conversion flag */
943 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
944
945 /* Update ADC state machine */
946 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
947
948 /* Determine whether any further conversion upcoming on group regular */
949 /* by external trigger, continuous mode or scan sequence on going. */
950 /* Note: On STM32F7, there is no independent flag of end of sequence. */
951 /* The test of scan sequence on going is done either with scan */
952 /* sequence disabled or with end of conversion flag set to */
953 /* of end of sequence. */
954 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
955 (hadc->Init.ContinuousConvMode == DISABLE) &&
956 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
957 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
958 {
959 /* Set ADC state */
960 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
961
962 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
963 {
964 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
965 }
966 }
967
968 /* Return ADC state */
969 return HAL_OK;
970 }
971
972 /**
973 * @brief Poll for conversion event
974 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
975 * the configuration information for the specified ADC.
976 * @param EventType the ADC event type.
977 * This parameter can be one of the following values:
978 * @arg ADC_AWD_EVENT: ADC Analog watch Dog event.
979 * @arg ADC_OVR_EVENT: ADC Overrun event.
980 * @param Timeout Timeout value in millisecond.
981 * @retval HAL status
982 */
HAL_ADC_PollForEvent(ADC_HandleTypeDef * hadc,uint32_t EventType,uint32_t Timeout)983 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
984 {
985 uint32_t tickstart = 0;
986
987 /* Check the parameters */
988 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
989 assert_param(IS_ADC_EVENT_TYPE(EventType));
990
991 /* Get tick */
992 tickstart = HAL_GetTick();
993
994 /* Check selected event flag */
995 while(!(__HAL_ADC_GET_FLAG(hadc,EventType)))
996 {
997 /* Check for the Timeout */
998 if(Timeout != HAL_MAX_DELAY)
999 {
1000 if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
1001 {
1002 /* New check to avoid false timeout detection in case of preemption */
1003 if(!(__HAL_ADC_GET_FLAG(hadc,EventType)))
1004 {
1005 /* Update ADC state machine to timeout */
1006 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
1007
1008 /* Process unlocked */
1009 __HAL_UNLOCK(hadc);
1010
1011 return HAL_TIMEOUT;
1012 }
1013 }
1014 }
1015 }
1016
1017 /* Analog watchdog (level out of window) event */
1018 if(EventType == ADC_AWD_EVENT)
1019 {
1020 /* Set ADC state */
1021 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
1022
1023 /* Clear ADC analog watchdog flag */
1024 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
1025 }
1026 /* Overrun event */
1027 else
1028 {
1029 /* Set ADC state */
1030 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
1031 /* Set ADC error code to overrun */
1032 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
1033
1034 /* Clear ADC overrun flag */
1035 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1036 }
1037
1038 /* Return ADC state */
1039 return HAL_OK;
1040 }
1041
1042
1043 /**
1044 * @brief Enables the interrupt and starts ADC conversion of regular channels.
1045 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1046 * the configuration information for the specified ADC.
1047 * @retval HAL status.
1048 */
HAL_ADC_Start_IT(ADC_HandleTypeDef * hadc)1049 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
1050 {
1051 __IO uint32_t counter = 0;
1052
1053 /* Check the parameters */
1054 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
1055 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
1056
1057 /* Process locked */
1058 __HAL_LOCK(hadc);
1059
1060 /* Enable the ADC peripheral */
1061 /* Check if ADC peripheral is disabled in order to enable it and wait during
1062 Tstab time the ADC's stabilization */
1063 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
1064 {
1065 /* Enable the Peripheral */
1066 __HAL_ADC_ENABLE(hadc);
1067
1068 /* Delay for ADC stabilization time */
1069 /* Compute number of CPU cycles to wait for */
1070 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
1071 while(counter != 0)
1072 {
1073 counter--;
1074 }
1075 }
1076
1077 /* Start conversion if ADC is effectively enabled */
1078 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
1079 {
1080 /* Set ADC state */
1081 /* - Clear state bitfield related to regular group conversion results */
1082 /* - Set state bitfield related to regular group operation */
1083 ADC_STATE_CLR_SET(hadc->State,
1084 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
1085 HAL_ADC_STATE_REG_BUSY);
1086
1087 /* If conversions on group regular are also triggering group injected, */
1088 /* update ADC state. */
1089 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
1090 {
1091 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1092 }
1093
1094 /* State machine update: Check if an injected conversion is ongoing */
1095 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1096 {
1097 /* Reset ADC error code fields related to conversions on group regular */
1098 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
1099 }
1100 else
1101 {
1102 /* Reset ADC all error code fields */
1103 ADC_CLEAR_ERRORCODE(hadc);
1104 }
1105
1106 /* Process unlocked */
1107 /* Unlock before starting ADC conversions: in case of potential */
1108 /* interruption, to let the process to ADC IRQ Handler. */
1109 __HAL_UNLOCK(hadc);
1110
1111 /* Clear regular group conversion flag and overrun flag */
1112 /* (To ensure of no unknown state from potential previous ADC operations) */
1113 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
1114
1115 /* Enable end of conversion interrupt for regular group */
1116 __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
1117
1118 /* Check if Multimode enabled */
1119 if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
1120 {
1121 /* if no external trigger present enable software conversion of regular channels */
1122 if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
1123 {
1124 /* Enable the selected ADC software conversion for regular group */
1125 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
1126 }
1127 }
1128 else
1129 {
1130 /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
1131 if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
1132 {
1133 /* Enable the selected ADC software conversion for regular group */
1134 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
1135 }
1136
1137 /* if dual mode is selected, ADC3 works independently. */
1138 /* check if the mode selected is not triple */
1139 if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) )
1140 {
1141 /* if instance of handle correspond to ADC3 and no external trigger present enable software conversion of regular channels */
1142 if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
1143 {
1144 /* Enable the selected ADC software conversion for regular group */
1145 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
1146 }
1147 }
1148 }
1149 }
1150 else
1151 {
1152 /* Update ADC state machine to error */
1153 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
1154
1155 /* Set ADC error code to ADC IP internal error */
1156 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
1157 }
1158
1159 /* Return function status */
1160 return HAL_OK;
1161 }
1162
1163 /**
1164 * @brief Disables the interrupt and stop ADC conversion of regular channels.
1165 *
1166 * @note Caution: This function will stop also injected channels.
1167 *
1168 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1169 * the configuration information for the specified ADC.
1170 * @retval HAL status.
1171 */
HAL_ADC_Stop_IT(ADC_HandleTypeDef * hadc)1172 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
1173 {
1174 /* Check the parameters */
1175 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1176
1177 /* Process locked */
1178 __HAL_LOCK(hadc);
1179
1180 /* Stop potential conversion on going, on regular and injected groups */
1181 /* Disable ADC peripheral */
1182 __HAL_ADC_DISABLE(hadc);
1183
1184 /* Check if ADC is effectively disabled */
1185 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
1186 {
1187 /* Disable ADC end of conversion interrupt for regular group */
1188 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
1189
1190 /* Set ADC state */
1191 ADC_STATE_CLR_SET(hadc->State,
1192 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1193 HAL_ADC_STATE_READY);
1194 }
1195
1196 /* Process unlocked */
1197 __HAL_UNLOCK(hadc);
1198
1199 /* Return function status */
1200 return HAL_OK;
1201 }
1202
1203 /**
1204 * @brief Handles ADC interrupt request
1205 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1206 * the configuration information for the specified ADC.
1207 * @retval None
1208 */
HAL_ADC_IRQHandler(ADC_HandleTypeDef * hadc)1209 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
1210 {
1211 uint32_t tmp1 = 0, tmp2 = 0;
1212
1213 uint32_t tmp_sr = hadc->Instance->SR;
1214 uint32_t tmp_cr1 = hadc->Instance->CR1;
1215
1216 /* Check the parameters */
1217 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
1218 assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
1219 assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
1220
1221 tmp1 = tmp_sr & ADC_FLAG_EOC;
1222 tmp2 = tmp_cr1 & ADC_IT_EOC;
1223
1224 /* Check End of conversion flag for regular channels */
1225 if(tmp1 && tmp2)
1226 {
1227 /* Update state machine on conversion status if not in error state */
1228 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
1229 {
1230 /* Set ADC state */
1231 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
1232 }
1233
1234 /* Determine whether any further conversion upcoming on group regular */
1235 /* by external trigger, continuous mode or scan sequence on going. */
1236 /* Note: On STM32F7, there is no independent flag of end of sequence. */
1237 /* The test of scan sequence on going is done either with scan */
1238 /* sequence disabled or with end of conversion flag set to */
1239 /* of end of sequence. */
1240 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
1241 (hadc->Init.ContinuousConvMode == DISABLE) &&
1242 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
1243 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
1244 {
1245 /* Disable ADC end of single conversion interrupt on group regular */
1246 /* Note: Overrun interrupt was enabled with EOC interrupt in */
1247 /* HAL_ADC_Start_IT(), but is not disabled here because can be used */
1248 /* by overrun IRQ process below. */
1249 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
1250
1251 /* Set ADC state */
1252 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1253
1254 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1255 {
1256 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
1257 }
1258 }
1259
1260 /* Conversion complete callback */
1261 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1262 hadc->ConvCpltCallback(hadc);
1263 #else
1264 HAL_ADC_ConvCpltCallback(hadc);
1265 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1266
1267 /* Clear regular group conversion flag */
1268 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
1269 }
1270
1271 tmp1 = tmp_sr & ADC_FLAG_JEOC;
1272 tmp2 = tmp_cr1 & ADC_IT_JEOC;
1273 /* Check End of conversion flag for injected channels */
1274 if(tmp1 && tmp2)
1275 {
1276 /* Update state machine on conversion status if not in error state */
1277 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
1278 {
1279 /* Set ADC state */
1280 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
1281 }
1282
1283 /* Determine whether any further conversion upcoming on group injected */
1284 /* by external trigger, scan sequence on going or by automatic injected */
1285 /* conversion from group regular (same conditions as group regular */
1286 /* interruption disabling above). */
1287 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
1288 (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
1289 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) &&
1290 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
1291 (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
1292 (hadc->Init.ContinuousConvMode == DISABLE))))
1293 {
1294 /* Disable ADC end of single conversion interrupt on group injected */
1295 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
1296
1297 /* Set ADC state */
1298 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
1299
1300 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
1301 {
1302 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
1303 }
1304 }
1305
1306 /* Conversion complete callback */
1307 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1308 hadc->InjectedConvCpltCallback(hadc);
1309 #else
1310 HAL_ADCEx_InjectedConvCpltCallback(hadc);
1311 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1312
1313 /* Clear injected group conversion flag */
1314 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
1315 }
1316
1317 tmp1 = tmp_sr & ADC_FLAG_AWD;
1318 tmp2 = tmp_cr1 & ADC_IT_AWD;
1319 /* Check Analog watchdog flag */
1320 if(tmp1 && tmp2)
1321 {
1322 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
1323 {
1324 /* Set ADC state */
1325 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
1326
1327 /* Level out of window callback */
1328 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1329 hadc->LevelOutOfWindowCallback(hadc);
1330 #else
1331 HAL_ADC_LevelOutOfWindowCallback(hadc);
1332 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1333
1334
1335 /* Clear the ADC analog watchdog flag */
1336 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
1337 }
1338 }
1339
1340 tmp1 = tmp_sr & ADC_FLAG_OVR;
1341 tmp2 = tmp_cr1 & ADC_IT_OVR;
1342 /* Check Overrun flag */
1343 if(tmp1 && tmp2)
1344 {
1345 /* Note: On STM32F7, ADC overrun can be set through other parameters */
1346 /* refer to description of parameter "EOCSelection" for more */
1347 /* details. */
1348
1349 /* Set ADC error code to overrun */
1350 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
1351
1352 /* Clear ADC overrun flag */
1353 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1354
1355 /* Error callback */
1356 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1357 hadc->ErrorCallback(hadc);
1358 #else
1359 HAL_ADC_ErrorCallback(hadc);
1360 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1361
1362 /* Clear the Overrun flag */
1363 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1364 }
1365 }
1366
1367 /**
1368 * @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral
1369 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1370 * the configuration information for the specified ADC.
1371 * @param pData The destination Buffer address.
1372 * @param Length The length of data to be transferred from ADC peripheral to memory.
1373 * @retval HAL status
1374 */
HAL_ADC_Start_DMA(ADC_HandleTypeDef * hadc,uint32_t * pData,uint32_t Length)1375 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
1376 {
1377 __IO uint32_t counter = 0;
1378
1379 /* Check the parameters */
1380 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
1381 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
1382
1383 /* Process locked */
1384 __HAL_LOCK(hadc);
1385
1386 /* Enable the ADC peripheral */
1387 /* Check if ADC peripheral is disabled in order to enable it and wait during
1388 Tstab time the ADC's stabilization */
1389 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
1390 {
1391 /* Enable the Peripheral */
1392 __HAL_ADC_ENABLE(hadc);
1393
1394 /* Delay for ADC stabilization time */
1395 /* Compute number of CPU cycles to wait for */
1396 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
1397 while(counter != 0)
1398 {
1399 counter--;
1400 }
1401 }
1402
1403 /* Start conversion if ADC is effectively enabled */
1404 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
1405 {
1406 /* Set ADC state */
1407 /* - Clear state bitfield related to regular group conversion results */
1408 /* - Set state bitfield related to regular group operation */
1409 ADC_STATE_CLR_SET(hadc->State,
1410 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
1411 HAL_ADC_STATE_REG_BUSY);
1412
1413 /* If conversions on group regular are also triggering group injected, */
1414 /* update ADC state. */
1415 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
1416 {
1417 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1418 }
1419
1420 /* State machine update: Check if an injected conversion is ongoing */
1421 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1422 {
1423 /* Reset ADC error code fields related to conversions on group regular */
1424 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
1425 }
1426 else
1427 {
1428 /* Reset ADC all error code fields */
1429 ADC_CLEAR_ERRORCODE(hadc);
1430 }
1431
1432 /* Process unlocked */
1433 /* Unlock before starting ADC conversions: in case of potential */
1434 /* interruption, to let the process to ADC IRQ Handler. */
1435 __HAL_UNLOCK(hadc);
1436
1437 /* Set the DMA transfer complete callback */
1438 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
1439
1440 /* Set the DMA half transfer complete callback */
1441 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
1442
1443 /* Set the DMA error callback */
1444 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
1445
1446
1447 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
1448 /* start (in case of SW start): */
1449
1450 /* Clear regular group conversion flag and overrun flag */
1451 /* (To ensure of no unknown state from potential previous ADC operations) */
1452 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
1453
1454 /* Enable ADC overrun interrupt */
1455 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
1456
1457 /* Enable ADC DMA mode */
1458 hadc->Instance->CR2 |= ADC_CR2_DMA;
1459
1460 /* Start the DMA channel */
1461 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
1462
1463 /* Check if Multimode enabled */
1464 if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
1465 {
1466 /* if no external trigger present enable software conversion of regular channels */
1467 if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
1468 {
1469 /* Enable the selected ADC software conversion for regular group */
1470 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
1471 }
1472 }
1473 else
1474 {
1475 /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
1476 if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
1477 {
1478 /* Enable the selected ADC software conversion for regular group */
1479 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
1480 }
1481 /* if dual mode is selected, ADC3 works independently. */
1482 /* check if the mode selected is not triple */
1483 if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) )
1484 {
1485 /* if instance of handle correspond to ADC3 and no external trigger present enable software conversion of regular channels */
1486 if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
1487 {
1488 /* Enable the selected ADC software conversion for regular group */
1489 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
1490 }
1491 }
1492 }
1493 }
1494 else
1495 {
1496 /* Update ADC state machine to error */
1497 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
1498
1499 /* Set ADC error code to ADC IP internal error */
1500 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
1501 }
1502
1503 /* Return function status */
1504 return HAL_OK;
1505 }
1506
1507 /**
1508 * @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral
1509 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1510 * the configuration information for the specified ADC.
1511 * @retval HAL status
1512 */
HAL_ADC_Stop_DMA(ADC_HandleTypeDef * hadc)1513 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
1514 {
1515 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1516
1517 /* Check the parameters */
1518 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1519
1520 /* Process locked */
1521 __HAL_LOCK(hadc);
1522
1523 /* Stop potential conversion on going, on regular and injected groups */
1524 /* Disable ADC peripheral */
1525 __HAL_ADC_DISABLE(hadc);
1526
1527 /* Check if ADC is effectively disabled */
1528 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
1529 {
1530 /* Disable the selected ADC DMA mode */
1531 hadc->Instance->CR2 &= ~ADC_CR2_DMA;
1532
1533 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
1534 /* DMA transfer is on going) */
1535 if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
1536 {
1537 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
1538
1539 /* Check if DMA channel effectively disabled */
1540 if (tmp_hal_status != HAL_OK)
1541 {
1542 /* Update ADC state machine to error */
1543 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
1544 }
1545 }
1546
1547 /* Disable ADC overrun interrupt */
1548 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
1549
1550 /* Set ADC state */
1551 ADC_STATE_CLR_SET(hadc->State,
1552 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1553 HAL_ADC_STATE_READY);
1554 }
1555
1556 /* Process unlocked */
1557 __HAL_UNLOCK(hadc);
1558
1559 /* Return function status */
1560 return tmp_hal_status;
1561 }
1562
1563 /**
1564 * @brief Gets the converted value from data register of regular channel.
1565 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1566 * the configuration information for the specified ADC.
1567 * @retval Converted value
1568 */
HAL_ADC_GetValue(ADC_HandleTypeDef * hadc)1569 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
1570 {
1571 /* Return the selected ADC converted value */
1572 return hadc->Instance->DR;
1573 }
1574
1575 /**
1576 * @brief Regular conversion complete callback in non blocking mode
1577 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1578 * the configuration information for the specified ADC.
1579 * @retval None
1580 */
HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef * hadc)1581 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
1582 {
1583 /* Prevent unused argument(s) compilation warning */
1584 UNUSED(hadc);
1585 /* NOTE : This function Should not be modified, when the callback is needed,
1586 the HAL_ADC_ConvCpltCallback could be implemented in the user file
1587 */
1588 }
1589
1590 /**
1591 * @brief Regular conversion half DMA transfer callback in non blocking mode
1592 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1593 * the configuration information for the specified ADC.
1594 * @retval None
1595 */
HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef * hadc)1596 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
1597 {
1598 /* Prevent unused argument(s) compilation warning */
1599 UNUSED(hadc);
1600 /* NOTE : This function Should not be modified, when the callback is needed,
1601 the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file
1602 */
1603 }
1604
1605 /**
1606 * @brief Analog watchdog callback in non blocking mode
1607 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1608 * the configuration information for the specified ADC.
1609 * @retval None
1610 */
HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef * hadc)1611 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
1612 {
1613 /* Prevent unused argument(s) compilation warning */
1614 UNUSED(hadc);
1615 /* NOTE : This function Should not be modified, when the callback is needed,
1616 the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file
1617 */
1618 }
1619
1620 /**
1621 * @brief Error ADC callback.
1622 * @note In case of error due to overrun when using ADC with DMA transfer
1623 * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
1624 * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
1625 * - If needed, restart a new ADC conversion using function
1626 * "HAL_ADC_Start_DMA()"
1627 * (this function is also clearing overrun flag)
1628 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1629 * the configuration information for the specified ADC.
1630 * @retval None
1631 */
HAL_ADC_ErrorCallback(ADC_HandleTypeDef * hadc)1632 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
1633 {
1634 /* Prevent unused argument(s) compilation warning */
1635 UNUSED(hadc);
1636 /* NOTE : This function Should not be modified, when the callback is needed,
1637 the HAL_ADC_ErrorCallback could be implemented in the user file
1638 */
1639 }
1640
1641 /**
1642 * @}
1643 */
1644
1645 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
1646 * @brief Peripheral Control functions
1647 *
1648 @verbatim
1649 ===============================================================================
1650 ##### Peripheral Control functions #####
1651 ===============================================================================
1652 [..] This section provides functions allowing to:
1653 (+) Configure regular channels.
1654 (+) Configure injected channels.
1655 (+) Configure multimode.
1656 (+) Configure the analog watch dog.
1657
1658 @endverbatim
1659 * @{
1660 */
1661
1662 /**
1663 * @brief Configures for the selected ADC regular channel its corresponding
1664 * rank in the sequencer and its sample time.
1665 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1666 * the configuration information for the specified ADC.
1667 * @param sConfig ADC configuration structure.
1668 * @retval HAL status
1669 */
HAL_ADC_ConfigChannel(ADC_HandleTypeDef * hadc,ADC_ChannelConfTypeDef * sConfig)1670 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
1671 {
1672 __IO uint32_t counter = 0;
1673
1674 /* Check the parameters */
1675 assert_param(IS_ADC_CHANNEL(sConfig->Channel));
1676 assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
1677 assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
1678
1679 /* Process locked */
1680 __HAL_LOCK(hadc);
1681
1682 /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
1683 if ((sConfig->Channel > ADC_CHANNEL_9) && (sConfig->Channel != ADC_INTERNAL_NONE))
1684 {
1685 /* Clear the old sample time */
1686 hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
1687
1688 if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
1689 {
1690 /* Set the new sample time */
1691 hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, ADC_CHANNEL_18);
1692 }
1693 else
1694 {
1695 /* Set the new sample time */
1696 hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
1697 }
1698 }
1699 else /* ADC_Channel include in ADC_Channel_[0..9] */
1700 {
1701 /* Clear the old sample time */
1702 hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
1703
1704 /* Set the new sample time */
1705 hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
1706 }
1707
1708 /* For Rank 1 to 6 */
1709 if (sConfig->Rank < 7)
1710 {
1711 /* Clear the old SQx bits for the selected rank */
1712 hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
1713
1714 /* Set the SQx bits for the selected rank */
1715 hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
1716 }
1717 /* For Rank 7 to 12 */
1718 else if (sConfig->Rank < 13)
1719 {
1720 /* Clear the old SQx bits for the selected rank */
1721 hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
1722
1723 /* Set the SQx bits for the selected rank */
1724 hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
1725 }
1726 /* For Rank 13 to 16 */
1727 else
1728 {
1729 /* Clear the old SQx bits for the selected rank */
1730 hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
1731
1732 /* Set the SQx bits for the selected rank */
1733 hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
1734 }
1735
1736 /* if no internal channel selected */
1737 if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_INTERNAL_NONE))
1738 {
1739 /* Disable the VBAT & TSVREFE channel*/
1740 ADC->CCR &= ~(ADC_CCR_VBATE | ADC_CCR_TSVREFE);
1741 }
1742
1743 /* if ADC1 Channel_18 is selected enable VBAT Channel */
1744 if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
1745 {
1746 /* Disable the TEMPSENSOR channel as it is multiplixed with the VBAT channel */
1747 ADC->CCR &= ~ADC_CCR_TSVREFE;
1748
1749 /* Enable the VBAT channel*/
1750 ADC->CCR |= ADC_CCR_VBATE;
1751 }
1752
1753 /* if ADC1 Channel_18 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
1754 if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))
1755 {
1756 /* Disable the VBAT channel as it is multiplixed with TEMPSENSOR channel */
1757 ADC->CCR &= ~ADC_CCR_VBATE;
1758
1759 /* Enable the TSVREFE channel*/
1760 ADC->CCR |= ADC_CCR_TSVREFE;
1761
1762 if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
1763 {
1764 /* Delay for temperature sensor stabilization time */
1765 /* Compute number of CPU cycles to wait for */
1766 counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
1767 while(counter != 0)
1768 {
1769 counter--;
1770 }
1771 }
1772 }
1773
1774 /* Process unlocked */
1775 __HAL_UNLOCK(hadc);
1776
1777 /* Return function status */
1778 return HAL_OK;
1779 }
1780
1781 /**
1782 * @brief Configures the analog watchdog.
1783 * @note Analog watchdog thresholds can be modified while ADC conversion
1784 * is on going.
1785 * In this case, some constraints must be taken into account:
1786 * the programmed threshold values are effective from the next
1787 * ADC EOC (end of unitary conversion).
1788 * Considering that registers write delay may happen due to
1789 * bus activity, this might cause an uncertainty on the
1790 * effective timing of the new programmed threshold values.
1791 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1792 * the configuration information for the specified ADC.
1793 * @param AnalogWDGConfig pointer to an ADC_AnalogWDGConfTypeDef structure
1794 * that contains the configuration information of ADC analog watchdog.
1795 * @retval HAL status
1796 */
HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef * hadc,ADC_AnalogWDGConfTypeDef * AnalogWDGConfig)1797 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
1798 {
1799 #ifdef USE_FULL_ASSERT
1800 uint32_t tmp = 0;
1801 #endif /* USE_FULL_ASSERT */
1802
1803 /* Check the parameters */
1804 assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode));
1805 assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
1806 assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
1807
1808 #ifdef USE_FULL_ASSERT
1809 tmp = ADC_GET_RESOLUTION(hadc);
1810 assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold));
1811 assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold));
1812 #endif /* USE_FULL_ASSERT */
1813
1814 /* Process locked */
1815 __HAL_LOCK(hadc);
1816
1817 if(AnalogWDGConfig->ITMode == ENABLE)
1818 {
1819 /* Enable the ADC Analog watchdog interrupt */
1820 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
1821 }
1822 else
1823 {
1824 /* Disable the ADC Analog watchdog interrupt */
1825 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
1826 }
1827
1828 /* Clear AWDEN, JAWDEN and AWDSGL bits */
1829 hadc->Instance->CR1 &= ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN);
1830
1831 /* Set the analog watchdog enable mode */
1832 hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode;
1833
1834 /* Set the high threshold */
1835 hadc->Instance->HTR = AnalogWDGConfig->HighThreshold;
1836
1837 /* Set the low threshold */
1838 hadc->Instance->LTR = AnalogWDGConfig->LowThreshold;
1839
1840 /* Clear the Analog watchdog channel select bits */
1841 hadc->Instance->CR1 &= ~ADC_CR1_AWDCH;
1842
1843 /* Set the Analog watchdog channel */
1844 hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel));
1845
1846 /* Process unlocked */
1847 __HAL_UNLOCK(hadc);
1848
1849 /* Return function status */
1850 return HAL_OK;
1851 }
1852
1853 /**
1854 * @}
1855 */
1856
1857 /** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions
1858 * @brief ADC Peripheral State functions
1859 *
1860 @verbatim
1861 ===============================================================================
1862 ##### Peripheral State and errors functions #####
1863 ===============================================================================
1864 [..]
1865 This subsection provides functions allowing to
1866 (+) Check the ADC state
1867 (+) Check the ADC Error
1868
1869 @endverbatim
1870 * @{
1871 */
1872
1873 /**
1874 * @brief return the ADC state
1875 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1876 * the configuration information for the specified ADC.
1877 * @retval HAL state
1878 */
HAL_ADC_GetState(ADC_HandleTypeDef * hadc)1879 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
1880 {
1881 /* Return ADC state */
1882 return hadc->State;
1883 }
1884
1885 /**
1886 * @brief Return the ADC error code
1887 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1888 * the configuration information for the specified ADC.
1889 * @retval ADC Error Code
1890 */
HAL_ADC_GetError(ADC_HandleTypeDef * hadc)1891 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
1892 {
1893 return hadc->ErrorCode;
1894 }
1895
1896 /**
1897 * @}
1898 */
1899
1900 /**
1901 * @}
1902 */
1903
1904 /* Private functions ---------------------------------------------------------*/
1905
1906 /** @defgroup ADC_Private_Functions ADC Private Functions
1907 * @{
1908 */
1909
1910 /**
1911 * @brief Initializes the ADCx peripheral according to the specified parameters
1912 * in the ADC_InitStruct without initializing the ADC MSP.
1913 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1914 * the configuration information for the specified ADC.
1915 * @retval None
1916 */
ADC_Init(ADC_HandleTypeDef * hadc)1917 static void ADC_Init(ADC_HandleTypeDef* hadc)
1918 {
1919 /* Set ADC parameters */
1920 /* Set the ADC clock prescaler */
1921 ADC->CCR &= ~(ADC_CCR_ADCPRE);
1922 ADC->CCR |= hadc->Init.ClockPrescaler;
1923
1924 /* Set ADC scan mode */
1925 hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
1926 hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
1927
1928 /* Set ADC resolution */
1929 hadc->Instance->CR1 &= ~(ADC_CR1_RES);
1930 hadc->Instance->CR1 |= hadc->Init.Resolution;
1931
1932 /* Set ADC data alignment */
1933 hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
1934 hadc->Instance->CR2 |= hadc->Init.DataAlign;
1935
1936 /* Enable external trigger if trigger selection is different of software */
1937 /* start. */
1938 /* Note: This configuration keeps the hardware feature of parameter */
1939 /* ExternalTrigConvEdge "trigger edge none" equivalent to */
1940 /* software start. */
1941 if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
1942 {
1943 /* Select external trigger to start conversion */
1944 hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
1945 hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
1946
1947 /* Select external trigger polarity */
1948 hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
1949 hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
1950 }
1951 else
1952 {
1953 /* Reset the external trigger */
1954 hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
1955 hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
1956 }
1957
1958 /* Enable or disable ADC continuous conversion mode */
1959 hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
1960 hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode);
1961
1962 if(hadc->Init.DiscontinuousConvMode != DISABLE)
1963 {
1964 assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
1965
1966 /* Enable the selected ADC regular discontinuous mode */
1967 hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;
1968
1969 /* Set the number of channels to be converted in discontinuous mode */
1970 hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);
1971 hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
1972 }
1973 else
1974 {
1975 /* Disable the selected ADC regular discontinuous mode */
1976 hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);
1977 }
1978
1979 /* Set ADC number of conversion */
1980 hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
1981 hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion);
1982
1983 /* Enable or disable ADC DMA continuous request */
1984 hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
1985 hadc->Instance->CR2 |= ADC_CR2_DMAContReq((uint32_t)hadc->Init.DMAContinuousRequests);
1986
1987 /* Enable or disable ADC end of conversion selection */
1988 hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
1989 hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
1990 }
1991
1992 /**
1993 * @brief DMA transfer complete callback.
1994 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1995 * the configuration information for the specified DMA module.
1996 * @retval None
1997 */
ADC_DMAConvCplt(DMA_HandleTypeDef * hdma)1998 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
1999 {
2000 /* Retrieve ADC handle corresponding to current DMA handle */
2001 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2002
2003 /* Update state machine on conversion status if not in error state */
2004 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
2005 {
2006 /* Update ADC state machine */
2007 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
2008
2009 /* Determine whether any further conversion upcoming on group regular */
2010 /* by external trigger, continuous mode or scan sequence on going. */
2011 /* Note: On STM32F7, there is no independent flag of end of sequence. */
2012 /* The test of scan sequence on going is done either with scan */
2013 /* sequence disabled or with end of conversion flag set to */
2014 /* of end of sequence. */
2015 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
2016 (hadc->Init.ContinuousConvMode == DISABLE) &&
2017 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
2018 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
2019 {
2020 /* Disable ADC end of single conversion interrupt on group regular */
2021 /* Note: Overrun interrupt was enabled with EOC interrupt in */
2022 /* HAL_ADC_Start_IT(), but is not disabled here because can be used */
2023 /* by overrun IRQ process below. */
2024 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
2025
2026 /* Set ADC state */
2027 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
2028
2029 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
2030 {
2031 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
2032 }
2033 }
2034
2035 /* Conversion complete callback */
2036 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2037 hadc->ConvCpltCallback(hadc);
2038 #else
2039 HAL_ADC_ConvCpltCallback(hadc);
2040 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2041 }
2042 else /* DMA and-or internal error occurred */
2043 {
2044 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
2045 {
2046 /* Call HAL ADC Error Callback function */
2047 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2048 hadc->ErrorCallback(hadc);
2049 #else
2050 HAL_ADC_ErrorCallback(hadc);
2051 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2052 }
2053 else
2054 {
2055 /* Call DMA error callback */
2056 hadc->DMA_Handle->XferErrorCallback(hdma);
2057 }
2058 }
2059 }
2060
2061 /**
2062 * @brief DMA half transfer complete callback.
2063 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2064 * the configuration information for the specified DMA module.
2065 * @retval None
2066 */
ADC_DMAHalfConvCplt(DMA_HandleTypeDef * hdma)2067 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
2068 {
2069 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2070 /* Half conversion callback */
2071 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2072 hadc->ConvHalfCpltCallback(hadc);
2073 #else
2074 HAL_ADC_ConvHalfCpltCallback(hadc);
2075 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2076 }
2077
2078 /**
2079 * @brief DMA error callback
2080 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2081 * the configuration information for the specified DMA module.
2082 * @retval None
2083 */
ADC_DMAError(DMA_HandleTypeDef * hdma)2084 static void ADC_DMAError(DMA_HandleTypeDef *hdma)
2085 {
2086 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2087 hadc->State= HAL_ADC_STATE_ERROR_DMA;
2088 /* Set ADC error code to DMA error */
2089 hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
2090 /* Error callback */
2091 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2092 hadc->ErrorCallback(hadc);
2093 #else
2094 HAL_ADC_ErrorCallback(hadc);
2095 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2096 }
2097
2098 /**
2099 * @}
2100 */
2101
2102 /**
2103 * @}
2104 */
2105
2106 #endif /* HAL_ADC_MODULE_ENABLED */
2107 /**
2108 * @}
2109 */
2110
2111 /**
2112 * @}
2113 */
2114
2115
