1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32F7xx_LL_TIM_H
21 #define __STM32F7xx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f7xx.h"
29
30 /** @addtogroup STM32F7xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM6) || defined (TIM7)
35
36 /** @defgroup TIM_LL TIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
43 * @{
44 */
45 static const uint8_t OFFSET_TAB_CCMRx[] =
46 {
47 0x00U, /* 0: TIMx_CH1 */
48 0x00U, /* 1: TIMx_CH1N */
49 0x00U, /* 2: TIMx_CH2 */
50 0x00U, /* 3: TIMx_CH2N */
51 0x04U, /* 4: TIMx_CH3 */
52 0x04U, /* 5: TIMx_CH3N */
53 0x04U, /* 6: TIMx_CH4 */
54 0x3CU, /* 7: TIMx_CH5 */
55 0x3CU /* 8: TIMx_CH6 */
56 };
57
58 static const uint8_t SHIFT_TAB_OCxx[] =
59 {
60 0U, /* 0: OC1M, OC1FE, OC1PE */
61 0U, /* 1: - NA */
62 8U, /* 2: OC2M, OC2FE, OC2PE */
63 0U, /* 3: - NA */
64 0U, /* 4: OC3M, OC3FE, OC3PE */
65 0U, /* 5: - NA */
66 8U, /* 6: OC4M, OC4FE, OC4PE */
67 0U, /* 7: OC5M, OC5FE, OC5PE */
68 8U /* 8: OC6M, OC6FE, OC6PE */
69 };
70
71 static const uint8_t SHIFT_TAB_ICxx[] =
72 {
73 0U, /* 0: CC1S, IC1PSC, IC1F */
74 0U, /* 1: - NA */
75 8U, /* 2: CC2S, IC2PSC, IC2F */
76 0U, /* 3: - NA */
77 0U, /* 4: CC3S, IC3PSC, IC3F */
78 0U, /* 5: - NA */
79 8U, /* 6: CC4S, IC4PSC, IC4F */
80 0U, /* 7: - NA */
81 0U /* 8: - NA */
82 };
83
84 static const uint8_t SHIFT_TAB_CCxP[] =
85 {
86 0U, /* 0: CC1P */
87 2U, /* 1: CC1NP */
88 4U, /* 2: CC2P */
89 6U, /* 3: CC2NP */
90 8U, /* 4: CC3P */
91 10U, /* 5: CC3NP */
92 12U, /* 6: CC4P */
93 16U, /* 7: CC5P */
94 20U /* 8: CC6P */
95 };
96
97 static const uint8_t SHIFT_TAB_OISx[] =
98 {
99 0U, /* 0: OIS1 */
100 1U, /* 1: OIS1N */
101 2U, /* 2: OIS2 */
102 3U, /* 3: OIS2N */
103 4U, /* 4: OIS3 */
104 5U, /* 5: OIS3N */
105 6U, /* 6: OIS4 */
106 8U, /* 7: OIS5 */
107 10U /* 8: OIS6 */
108 };
109 /**
110 * @}
111 */
112
113 /* Private constants ---------------------------------------------------------*/
114 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
115 * @{
116 */
117
118 #if defined(TIM_BREAK_INPUT_SUPPORT)
119 /* Defines used for the bit position in the register and perform offsets */
120 #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
121
122 /* Generic bit definitions for TIMx_AF1 register */
123 #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
124 #endif /* TIM_BREAK_INPUT_SUPPORT */
125
126 /* Remap mask definitions */
127 #define TIMx_OR_RMP_SHIFT 16U
128 #define TIMx_OR_RMP_MASK 0x0000FFFFU
129 #define TIM2_OR_RMP_MASK (TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT)
130 #define TIM5_OR_RMP_MASK (TIM5_OR_TI4_RMP << TIMx_OR_RMP_SHIFT)
131 #define TIM11_OR_RMP_MASK (TIM11_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
132
133 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
134 #define DT_DELAY_1 ((uint8_t)0x7F)
135 #define DT_DELAY_2 ((uint8_t)0x3F)
136 #define DT_DELAY_3 ((uint8_t)0x1F)
137 #define DT_DELAY_4 ((uint8_t)0x1F)
138
139 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
140 #define DT_RANGE_1 ((uint8_t)0x00)
141 #define DT_RANGE_2 ((uint8_t)0x80)
142 #define DT_RANGE_3 ((uint8_t)0xC0)
143 #define DT_RANGE_4 ((uint8_t)0xE0)
144
145
146 /**
147 * @}
148 */
149
150 /* Private macros ------------------------------------------------------------*/
151 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
152 * @{
153 */
154 /** @brief Convert channel id into channel index.
155 * @param __CHANNEL__ This parameter can be one of the following values:
156 * @arg @ref LL_TIM_CHANNEL_CH1
157 * @arg @ref LL_TIM_CHANNEL_CH1N
158 * @arg @ref LL_TIM_CHANNEL_CH2
159 * @arg @ref LL_TIM_CHANNEL_CH2N
160 * @arg @ref LL_TIM_CHANNEL_CH3
161 * @arg @ref LL_TIM_CHANNEL_CH3N
162 * @arg @ref LL_TIM_CHANNEL_CH4
163 * @arg @ref LL_TIM_CHANNEL_CH5
164 * @arg @ref LL_TIM_CHANNEL_CH6
165 * @retval none
166 */
167 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
168 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
169 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
170 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
171 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
172 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
173 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
174 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
175 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
176
177 /** @brief Calculate the deadtime sampling period(in ps).
178 * @param __TIMCLK__ timer input clock frequency (in Hz).
179 * @param __CKD__ This parameter can be one of the following values:
180 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
181 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
182 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
183 * @retval none
184 */
185 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
186 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
187 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
188 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
189 /**
190 * @}
191 */
192
193
194 /* Exported types ------------------------------------------------------------*/
195 #if defined(USE_FULL_LL_DRIVER)
196 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
197 * @{
198 */
199
200 /**
201 * @brief TIM Time Base configuration structure definition.
202 */
203 typedef struct
204 {
205 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
206 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
207
208 This feature can be modified afterwards using unitary function
209 @ref LL_TIM_SetPrescaler().*/
210
211 uint32_t CounterMode; /*!< Specifies the counter mode.
212 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
213
214 This feature can be modified afterwards using unitary function
215 @ref LL_TIM_SetCounterMode().*/
216
217 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
218 Auto-Reload Register at the next update event.
219 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
220 Some timer instances may support 32 bits counters. In that case this parameter must
221 be a number between 0x0000 and 0xFFFFFFFF.
222
223 This feature can be modified afterwards using unitary function
224 @ref LL_TIM_SetAutoReload().*/
225
226 uint32_t ClockDivision; /*!< Specifies the clock division.
227 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
228
229 This feature can be modified afterwards using unitary function
230 @ref LL_TIM_SetClockDivision().*/
231
232 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
233 reaches zero, an update event is generated and counting restarts
234 from the RCR value (N).
235 This means in PWM mode that (N+1) corresponds to:
236 - the number of PWM periods in edge-aligned mode
237 - the number of half PWM period in center-aligned mode
238 GP timers: this parameter must be a number between Min_Data = 0x00 and
239 Max_Data = 0xFF.
240 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
241 Max_Data = 0xFFFF.
242
243 This feature can be modified afterwards using unitary function
244 @ref LL_TIM_SetRepetitionCounter().*/
245 } LL_TIM_InitTypeDef;
246
247 /**
248 * @brief TIM Output Compare configuration structure definition.
249 */
250 typedef struct
251 {
252 uint32_t OCMode; /*!< Specifies the output mode.
253 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
254
255 This feature can be modified afterwards using unitary function
256 @ref LL_TIM_OC_SetMode().*/
257
258 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
259 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
260
261 This feature can be modified afterwards using unitary functions
262 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
263
264 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
265 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
266
267 This feature can be modified afterwards using unitary functions
268 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
269
270 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
271 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
272
273 This feature can be modified afterwards using unitary function
274 LL_TIM_OC_SetCompareCHx (x=1..6).*/
275
276 uint32_t OCPolarity; /*!< Specifies the output polarity.
277 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
278
279 This feature can be modified afterwards using unitary function
280 @ref LL_TIM_OC_SetPolarity().*/
281
282 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
283 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
284
285 This feature can be modified afterwards using unitary function
286 @ref LL_TIM_OC_SetPolarity().*/
287
288
289 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
290 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
291
292 This feature can be modified afterwards using unitary function
293 @ref LL_TIM_OC_SetIdleState().*/
294
295 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
296 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
297
298 This feature can be modified afterwards using unitary function
299 @ref LL_TIM_OC_SetIdleState().*/
300 } LL_TIM_OC_InitTypeDef;
301
302 /**
303 * @brief TIM Input Capture configuration structure definition.
304 */
305
306 typedef struct
307 {
308
309 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
310 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
311
312 This feature can be modified afterwards using unitary function
313 @ref LL_TIM_IC_SetPolarity().*/
314
315 uint32_t ICActiveInput; /*!< Specifies the input.
316 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
317
318 This feature can be modified afterwards using unitary function
319 @ref LL_TIM_IC_SetActiveInput().*/
320
321 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
322 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
323
324 This feature can be modified afterwards using unitary function
325 @ref LL_TIM_IC_SetPrescaler().*/
326
327 uint32_t ICFilter; /*!< Specifies the input capture filter.
328 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
329
330 This feature can be modified afterwards using unitary function
331 @ref LL_TIM_IC_SetFilter().*/
332 } LL_TIM_IC_InitTypeDef;
333
334
335 /**
336 * @brief TIM Encoder interface configuration structure definition.
337 */
338 typedef struct
339 {
340 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
341 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
342
343 This feature can be modified afterwards using unitary function
344 @ref LL_TIM_SetEncoderMode().*/
345
346 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
347 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
348
349 This feature can be modified afterwards using unitary function
350 @ref LL_TIM_IC_SetPolarity().*/
351
352 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
353 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
354
355 This feature can be modified afterwards using unitary function
356 @ref LL_TIM_IC_SetActiveInput().*/
357
358 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
359 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
360
361 This feature can be modified afterwards using unitary function
362 @ref LL_TIM_IC_SetPrescaler().*/
363
364 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
365 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
366
367 This feature can be modified afterwards using unitary function
368 @ref LL_TIM_IC_SetFilter().*/
369
370 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
371 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
372
373 This feature can be modified afterwards using unitary function
374 @ref LL_TIM_IC_SetPolarity().*/
375
376 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
377 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
378
379 This feature can be modified afterwards using unitary function
380 @ref LL_TIM_IC_SetActiveInput().*/
381
382 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
383 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
384
385 This feature can be modified afterwards using unitary function
386 @ref LL_TIM_IC_SetPrescaler().*/
387
388 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
389 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
390
391 This feature can be modified afterwards using unitary function
392 @ref LL_TIM_IC_SetFilter().*/
393
394 } LL_TIM_ENCODER_InitTypeDef;
395
396 /**
397 * @brief TIM Hall sensor interface configuration structure definition.
398 */
399 typedef struct
400 {
401
402 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
403 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
404
405 This feature can be modified afterwards using unitary function
406 @ref LL_TIM_IC_SetPolarity().*/
407
408 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
409 Prescaler must be set to get a maximum counter period longer than the
410 time interval between 2 consecutive changes on the Hall inputs.
411 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
412
413 This feature can be modified afterwards using unitary function
414 @ref LL_TIM_IC_SetPrescaler().*/
415
416 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
417 This parameter can be a value of
418 @ref TIM_LL_EC_IC_FILTER.
419
420 This feature can be modified afterwards using unitary function
421 @ref LL_TIM_IC_SetFilter().*/
422
423 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
424 A positive pulse (TRGO event) is generated with a programmable delay every time
425 a change occurs on the Hall inputs.
426 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
427
428 This feature can be modified afterwards using unitary function
429 @ref LL_TIM_OC_SetCompareCH2().*/
430 } LL_TIM_HALLSENSOR_InitTypeDef;
431
432 /**
433 * @brief BDTR (Break and Dead Time) structure definition
434 */
435 typedef struct
436 {
437 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
438 This parameter can be a value of @ref TIM_LL_EC_OSSR
439
440 This feature can be modified afterwards using unitary function
441 @ref LL_TIM_SetOffStates()
442
443 @note This bit-field cannot be modified as long as LOCK level 2 has been
444 programmed. */
445
446 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
447 This parameter can be a value of @ref TIM_LL_EC_OSSI
448
449 This feature can be modified afterwards using unitary function
450 @ref LL_TIM_SetOffStates()
451
452 @note This bit-field cannot be modified as long as LOCK level 2 has been
453 programmed. */
454
455 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
456 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
457
458 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
459 register has been written, their content is frozen until the next reset.*/
460
461 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
462 switching-on of the outputs.
463 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
464
465 This feature can be modified afterwards using unitary function
466 @ref LL_TIM_OC_SetDeadTime()
467
468 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
469 programmed. */
470
471 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
472 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
473
474 This feature can be modified afterwards using unitary functions
475 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
476
477 @note This bit-field can not be modified as long as LOCK level 1 has been
478 programmed. */
479
480 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
481 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
482
483 This feature can be modified afterwards using unitary function
484 @ref LL_TIM_ConfigBRK()
485
486 @note This bit-field can not be modified as long as LOCK level 1 has been
487 programmed. */
488
489 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
490 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
491
492 This feature can be modified afterwards using unitary function
493 @ref LL_TIM_ConfigBRK()
494
495 @note This bit-field can not be modified as long as LOCK level 1 has been
496 programmed. */
497
498 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
499 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
500
501 This feature can be modified afterwards using unitary functions
502 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
503
504 @note This bit-field can not be modified as long as LOCK level 1 has been
505 programmed. */
506
507 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
508 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
509
510 This feature can be modified afterwards using unitary function
511 @ref LL_TIM_ConfigBRK2()
512
513 @note This bit-field can not be modified as long as LOCK level 1 has been
514 programmed. */
515
516 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
517 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
518
519 This feature can be modified afterwards using unitary function
520 @ref LL_TIM_ConfigBRK2()
521
522 @note This bit-field can not be modified as long as LOCK level 1 has been
523 programmed. */
524
525 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
526 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
527
528 This feature can be modified afterwards using unitary functions
529 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
530
531 @note This bit-field can not be modified as long as LOCK level 1 has been
532 programmed. */
533 } LL_TIM_BDTR_InitTypeDef;
534
535 /**
536 * @}
537 */
538 #endif /* USE_FULL_LL_DRIVER */
539
540 /* Exported constants --------------------------------------------------------*/
541 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
542 * @{
543 */
544
545 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
546 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
547 * @{
548 */
549 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
550 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
551 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
552 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
553 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
554 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
555 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
556 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
557 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
558 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
559 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
560 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
561 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
562 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
563 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
564 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
565 /**
566 * @}
567 */
568
569 #if defined(USE_FULL_LL_DRIVER)
570 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
571 * @{
572 */
573 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
574 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
575 /**
576 * @}
577 */
578
579 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
580 * @{
581 */
582 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
583 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
584 /**
585 * @}
586 */
587
588 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
589 * @{
590 */
591 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
592 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
593 /**
594 * @}
595 */
596 #endif /* USE_FULL_LL_DRIVER */
597
598 /** @defgroup TIM_LL_EC_IT IT Defines
599 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
600 * @{
601 */
602 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
603 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
604 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
605 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
606 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
607 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
608 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
609 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
610 /**
611 * @}
612 */
613
614 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
615 * @{
616 */
617 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
618 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
619 /**
620 * @}
621 */
622
623 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
624 * @{
625 */
626 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
627 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
628 /**
629 * @}
630 */
631
632 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
633 * @{
634 */
635 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
636 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
637 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
638 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
639 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
640 /**
641 * @}
642 */
643
644 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
645 * @{
646 */
647 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
648 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
649 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
650 /**
651 * @}
652 */
653
654 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
655 * @{
656 */
657 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
658 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
659 /**
660 * @}
661 */
662
663 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
664 * @{
665 */
666 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
667 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
668 /**
669 * @}
670 */
671
672 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
673 * @{
674 */
675 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
676 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
677 /**
678 * @}
679 */
680
681 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
682 * @{
683 */
684 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
685 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
686 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
687 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
688 /**
689 * @}
690 */
691
692 /** @defgroup TIM_LL_EC_CHANNEL Channel
693 * @{
694 */
695 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
696 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
697 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
698 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
699 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
700 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
701 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
702 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
703 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
704 /**
705 * @}
706 */
707
708 #if defined(USE_FULL_LL_DRIVER)
709 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
710 * @{
711 */
712 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
713 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
714 /**
715 * @}
716 */
717 #endif /* USE_FULL_LL_DRIVER */
718
719 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
720 * @{
721 */
722 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
723 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
724 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
725 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
726 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
727 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
728 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
729 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
730 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
731 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
732 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
733 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
734 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
735 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
736 /**
737 * @}
738 */
739
740 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
741 * @{
742 */
743 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
744 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
745 /**
746 * @}
747 */
748
749 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
750 * @{
751 */
752 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
753 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
754 /**
755 * @}
756 */
757
758 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
759 * @{
760 */
761 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
762 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
763 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
764 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
765 /**
766 * @}
767 */
768
769 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
770 * @{
771 */
772 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
773 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
774 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
775 /**
776 * @}
777 */
778
779 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
780 * @{
781 */
782 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
783 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
784 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
785 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
786 /**
787 * @}
788 */
789
790 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
791 * @{
792 */
793 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
794 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
795 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
796 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
797 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
798 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
799 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
800 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
801 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
802 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
803 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
804 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
805 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
806 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
807 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
808 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
809 /**
810 * @}
811 */
812
813 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
814 * @{
815 */
816 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
817 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
818 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
819 /**
820 * @}
821 */
822
823 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
824 * @{
825 */
826 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
827 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
828 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
829 /**
830 * @}
831 */
832
833 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
834 * @{
835 */
836 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
837 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
838 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
839 /**
840 * @}
841 */
842
843 /** @defgroup TIM_LL_EC_TRGO Trigger Output
844 * @{
845 */
846 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
847 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
848 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
849 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
850 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
851 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
852 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
853 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
854 /**
855 * @}
856 */
857
858 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
859 * @{
860 */
861 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
862 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
863 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
864 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
865 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
866 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
867 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
868 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
869 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
870 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
871 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
872 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
873 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
874 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
875 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
876 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
877 /**
878 * @}
879 */
880
881 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
882 * @{
883 */
884 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
885 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
886 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
887 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
888 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
889 /**
890 * @}
891 */
892
893 /** @defgroup TIM_LL_EC_TS Trigger Selection
894 * @{
895 */
896 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
897 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
898 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
899 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
900 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
901 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
902 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
903 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
904 /**
905 * @}
906 */
907
908 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
909 * @{
910 */
911 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
912 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
913 /**
914 * @}
915 */
916
917 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
918 * @{
919 */
920 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
921 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
922 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
923 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
924 /**
925 * @}
926 */
927
928 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
929 * @{
930 */
931 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
932 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
933 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
934 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
935 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
936 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
937 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
938 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
939 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
940 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
941 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
942 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
943 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
944 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
945 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
946 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
947 /**
948 * @}
949 */
950
951
952 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
953 * @{
954 */
955 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
956 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
957 /**
958 * @}
959 */
960
961 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
962 * @{
963 */
964 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
965 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
966 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
967 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
968 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
969 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
970 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
971 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
972 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
973 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
974 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
975 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
976 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
977 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
978 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
979 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
980 /**
981 * @}
982 */
983
984 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
985 * @{
986 */
987 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
988 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
989 /**
990 * @}
991 */
992
993 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
994 * @{
995 */
996 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
997 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
998 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
999 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
1000 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
1001 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
1002 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1003 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1004 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1005 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1006 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1007 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1008 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1009 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1010 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1011 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1012 /**
1013 * @}
1014 */
1015
1016 /** @defgroup TIM_LL_EC_OSSI OSSI
1017 * @{
1018 */
1019 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1020 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1021 /**
1022 * @}
1023 */
1024
1025 /** @defgroup TIM_LL_EC_OSSR OSSR
1026 * @{
1027 */
1028 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1029 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1030 /**
1031 * @}
1032 */
1033
1034 #if defined(TIM_BREAK_INPUT_SUPPORT)
1035 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1036 * @{
1037 */
1038 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1039 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1040 /**
1041 * @}
1042 */
1043
1044 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1045 * @{
1046 */
1047 #define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE /*!< BKIN input from AF controller */
1048 #define LL_TIM_BKIN_SOURCE_DF1BK TIM1_AF1_BKDF1BKE /*!< internal signal: DFSDM1 break output */
1049 /**
1050 * @}
1051 */
1052
1053 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1054 * @{
1055 */
1056 #define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /*!< BRK BKIN input is active low */
1057 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1058 /**
1059 * @}
1060 */
1061 #endif /* TIM_BREAK_INPUT_SUPPORT */
1062
1063 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1064 * @{
1065 */
1066 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1067 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1068 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1069 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1070 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1071 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1072 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1073 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1074 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1075 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1076 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1077 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1078 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1079 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1080 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1081 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1082 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1083 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1084 #define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_OR register is the DMA base address for DMA burst */
1085 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1086 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1087 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1088 #if defined(TIM1_AF1_BKINE)&&defined(TIM1_AF2_BKINE)
1089 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
1090 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
1091 #endif /* TIM1_AF1_BKINE && TIM1_AF2_BKINE */
1092 /**
1093 * @}
1094 */
1095
1096 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1097 * @{
1098 */
1099 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1100 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1101 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1102 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1103 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1104 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1105 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1106 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1107 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1108 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1109 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1110 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1111 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1112 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1113 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1114 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1115 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1116 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1117 /**
1118 * @}
1119 */
1120
1121
1122 /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP_TIM8 TIM2 Internal Trigger1 Remap TIM8
1123 * @{
1124 */
1125 #define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR_RMP_MASK /*!< TIM2_ITR1 is connected to TIM8_TRGO */
1126 #define LL_TIM_TIM2_ITR1_RMP_ETH_PTP (TIM2_OR_ITR1_RMP_0 | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to ETH_PTP */
1127 #define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM2_OR_ITR1_RMP_1 | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_FS SOF */
1128 #define LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF (TIM2_OR_ITR1_RMP | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_HS SOF */
1129 /**
1130 * @}
1131 */
1132
1133 /** @defgroup TIM_LL_EC_TIM5_TI4_RMP TIM5 External Input Ch4 Remap
1134 * @{
1135 */
1136 #define LL_TIM_TIM5_TI4_RMP_GPIO TIM5_OR_RMP_MASK /*!< TIM5 channel 4 is connected to GPIO */
1137 #define LL_TIM_TIM5_TI4_RMP_LSI (TIM5_OR_TI4_RMP_0 | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to LSI internal clock */
1138 #define LL_TIM_TIM5_TI4_RMP_LSE (TIM5_OR_TI4_RMP_1 | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to LSE */
1139 #define LL_TIM_TIM5_TI4_RMP_RTC (TIM5_OR_TI4_RMP | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to RTC wakeup interrupt */
1140 /**
1141 * @}
1142 */
1143
1144 /** @defgroup TIM_LL_EC_TIM11_TI1_RMP TIM11 External Input Capture 1 Remap
1145 * @{
1146 */
1147 #define LL_TIM_TIM11_TI1_RMP_GPIO TIM11_OR_RMP_MASK /*!< TIM11 channel 1 is connected to GPIO */
1148 #define LL_TIM_TIM11_TI1_RMP_SPDIFRX (TIM11_OR_TI1_RMP_0 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to SPDIFRX */
1149 #define LL_TIM_TIM11_TI1_RMP_HSE (TIM11_OR_TI1_RMP_1 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to HSE */
1150 #define LL_TIM_TIM11_TI1_RMP_MCO1 (TIM11_OR_TI1_RMP | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to MCO1 */
1151 /**
1152 * @}
1153 */
1154
1155 /**
1156 * @}
1157 */
1158
1159 /**
1160 * @}
1161 */
1162
1163 /* Exported macro ------------------------------------------------------------*/
1164 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1165 * @{
1166 */
1167
1168 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1169 * @{
1170 */
1171 /**
1172 * @brief Write a value in TIM register.
1173 * @param __INSTANCE__ TIM Instance
1174 * @param __REG__ Register to be written
1175 * @param __VALUE__ Value to be written in the register
1176 * @retval None
1177 */
1178 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1179
1180 /**
1181 * @brief Read a value in TIM register.
1182 * @param __INSTANCE__ TIM Instance
1183 * @param __REG__ Register to be read
1184 * @retval Register value
1185 */
1186 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1187 /**
1188 * @}
1189 */
1190
1191 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
1192 * @{
1193 */
1194
1195 /**
1196 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1197 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1198 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1199 * to TIMx_CNT register bit 31)
1200 * @param __CNT__ Counter value
1201 * @retval UIF status bit
1202 */
1203 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1204 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1205
1206 /**
1207 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1208 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1209 * @param __TIMCLK__ timer input clock frequency (in Hz)
1210 * @param __CKD__ This parameter can be one of the following values:
1211 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1212 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1213 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1214 * @param __DT__ deadtime duration (in ns)
1215 * @retval DTG[0:7]
1216 */
1217 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1218 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1219 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1220 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1221 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1222 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1223 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1224 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1225 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1226 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1227 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1228 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1229 0U)
1230
1231 /**
1232 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1233 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1234 * @param __TIMCLK__ timer input clock frequency (in Hz)
1235 * @param __CNTCLK__ counter clock frequency (in Hz)
1236 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1237 */
1238 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1239 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1240
1241 /**
1242 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1243 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1244 * @param __TIMCLK__ timer input clock frequency (in Hz)
1245 * @param __PSC__ prescaler
1246 * @param __FREQ__ output signal frequency (in Hz)
1247 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1248 */
1249 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1250 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1251
1252 /**
1253 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1254 * active/inactive delay.
1255 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1256 * @param __TIMCLK__ timer input clock frequency (in Hz)
1257 * @param __PSC__ prescaler
1258 * @param __DELAY__ timer output compare active/inactive delay (in us)
1259 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1260 */
1261 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1262 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1263 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1264
1265 /**
1266 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1267 * (when the timer operates in one pulse mode).
1268 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1269 * @param __TIMCLK__ timer input clock frequency (in Hz)
1270 * @param __PSC__ prescaler
1271 * @param __DELAY__ timer output compare active/inactive delay (in us)
1272 * @param __PULSE__ pulse duration (in us)
1273 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1274 */
1275 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1276 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1277 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1278
1279 /**
1280 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1281 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1282 * @param __ICPSC__ This parameter can be one of the following values:
1283 * @arg @ref LL_TIM_ICPSC_DIV1
1284 * @arg @ref LL_TIM_ICPSC_DIV2
1285 * @arg @ref LL_TIM_ICPSC_DIV4
1286 * @arg @ref LL_TIM_ICPSC_DIV8
1287 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1288 */
1289 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1290 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1291
1292
1293 /**
1294 * @}
1295 */
1296
1297
1298 /**
1299 * @}
1300 */
1301
1302 /* Exported functions --------------------------------------------------------*/
1303 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1304 * @{
1305 */
1306
1307 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1308 * @{
1309 */
1310 /**
1311 * @brief Enable timer counter.
1312 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1313 * @param TIMx Timer instance
1314 * @retval None
1315 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1316 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1317 {
1318 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1319 }
1320
1321 /**
1322 * @brief Disable timer counter.
1323 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1324 * @param TIMx Timer instance
1325 * @retval None
1326 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1327 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1328 {
1329 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1330 }
1331
1332 /**
1333 * @brief Indicates whether the timer counter is enabled.
1334 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1335 * @param TIMx Timer instance
1336 * @retval State of bit (1 or 0).
1337 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)1338 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
1339 {
1340 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1341 }
1342
1343 /**
1344 * @brief Enable update event generation.
1345 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1346 * @param TIMx Timer instance
1347 * @retval None
1348 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1349 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1350 {
1351 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1352 }
1353
1354 /**
1355 * @brief Disable update event generation.
1356 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1357 * @param TIMx Timer instance
1358 * @retval None
1359 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1360 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1361 {
1362 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1363 }
1364
1365 /**
1366 * @brief Indicates whether update event generation is enabled.
1367 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1368 * @param TIMx Timer instance
1369 * @retval Inverted state of bit (0 or 1).
1370 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)1371 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
1372 {
1373 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1374 }
1375
1376 /**
1377 * @brief Set update event source
1378 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1379 * generate an update interrupt or DMA request if enabled:
1380 * - Counter overflow/underflow
1381 * - Setting the UG bit
1382 * - Update generation through the slave mode controller
1383 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1384 * overflow/underflow generates an update interrupt or DMA request if enabled.
1385 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1386 * @param TIMx Timer instance
1387 * @param UpdateSource This parameter can be one of the following values:
1388 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1389 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1390 * @retval None
1391 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1392 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1393 {
1394 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1395 }
1396
1397 /**
1398 * @brief Get actual event update source
1399 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1400 * @param TIMx Timer instance
1401 * @retval Returned value can be one of the following values:
1402 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1403 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1404 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)1405 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
1406 {
1407 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1408 }
1409
1410 /**
1411 * @brief Set one pulse mode (one shot v.s. repetitive).
1412 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1413 * @param TIMx Timer instance
1414 * @param OnePulseMode This parameter can be one of the following values:
1415 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1416 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1417 * @retval None
1418 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1419 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1420 {
1421 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1422 }
1423
1424 /**
1425 * @brief Get actual one pulse mode.
1426 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1427 * @param TIMx Timer instance
1428 * @retval Returned value can be one of the following values:
1429 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1430 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1431 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)1432 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
1433 {
1434 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1435 }
1436
1437 /**
1438 * @brief Set the timer counter counting mode.
1439 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1440 * check whether or not the counter mode selection feature is supported
1441 * by a timer instance.
1442 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1443 * requires a timer reset to avoid unexpected direction
1444 * due to DIR bit readonly in center aligned mode.
1445 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1446 * CR1 CMS LL_TIM_SetCounterMode
1447 * @param TIMx Timer instance
1448 * @param CounterMode This parameter can be one of the following values:
1449 * @arg @ref LL_TIM_COUNTERMODE_UP
1450 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1451 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1452 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1453 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1454 * @retval None
1455 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1456 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1457 {
1458 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1459 }
1460
1461 /**
1462 * @brief Get actual counter mode.
1463 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1464 * check whether or not the counter mode selection feature is supported
1465 * by a timer instance.
1466 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1467 * CR1 CMS LL_TIM_GetCounterMode
1468 * @param TIMx Timer instance
1469 * @retval Returned value can be one of the following values:
1470 * @arg @ref LL_TIM_COUNTERMODE_UP
1471 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1472 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1473 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1474 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1475 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)1476 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
1477 {
1478 uint32_t counter_mode;
1479
1480 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1481
1482 if (counter_mode == 0U)
1483 {
1484 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1485 }
1486
1487 return counter_mode;
1488 }
1489
1490 /**
1491 * @brief Enable auto-reload (ARR) preload.
1492 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1493 * @param TIMx Timer instance
1494 * @retval None
1495 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1496 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1497 {
1498 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1499 }
1500
1501 /**
1502 * @brief Disable auto-reload (ARR) preload.
1503 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1504 * @param TIMx Timer instance
1505 * @retval None
1506 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1507 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1508 {
1509 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1510 }
1511
1512 /**
1513 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1514 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1515 * @param TIMx Timer instance
1516 * @retval State of bit (1 or 0).
1517 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)1518 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
1519 {
1520 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1521 }
1522
1523 /**
1524 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1525 * (when supported) and the digital filters.
1526 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1527 * whether or not the clock division feature is supported by the timer
1528 * instance.
1529 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1530 * @param TIMx Timer instance
1531 * @param ClockDivision This parameter can be one of the following values:
1532 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1533 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1534 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1535 * @retval None
1536 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1537 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1538 {
1539 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1540 }
1541
1542 /**
1543 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1544 * generators (when supported) and the digital filters.
1545 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1546 * whether or not the clock division feature is supported by the timer
1547 * instance.
1548 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1549 * @param TIMx Timer instance
1550 * @retval Returned value can be one of the following values:
1551 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1552 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1553 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1554 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)1555 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
1556 {
1557 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1558 }
1559
1560 /**
1561 * @brief Set the counter value.
1562 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1563 * whether or not a timer instance supports a 32 bits counter.
1564 * @rmtoll CNT CNT LL_TIM_SetCounter
1565 * @param TIMx Timer instance
1566 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1567 * @retval None
1568 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1569 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1570 {
1571 WRITE_REG(TIMx->CNT, Counter);
1572 }
1573
1574 /**
1575 * @brief Get the counter value.
1576 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1577 * whether or not a timer instance supports a 32 bits counter.
1578 * @rmtoll CNT CNT LL_TIM_GetCounter
1579 * @param TIMx Timer instance
1580 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1581 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)1582 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
1583 {
1584 return (uint32_t)(READ_REG(TIMx->CNT));
1585 }
1586
1587 /**
1588 * @brief Get the current direction of the counter
1589 * @rmtoll CR1 DIR LL_TIM_GetDirection
1590 * @param TIMx Timer instance
1591 * @retval Returned value can be one of the following values:
1592 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1593 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1594 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)1595 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
1596 {
1597 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1598 }
1599
1600 /**
1601 * @brief Set the prescaler value.
1602 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1603 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1604 * prescaler ratio is taken into account at the next update event.
1605 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1606 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1607 * @param TIMx Timer instance
1608 * @param Prescaler between Min_Data=0 and Max_Data=65535
1609 * @retval None
1610 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1611 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1612 {
1613 WRITE_REG(TIMx->PSC, Prescaler);
1614 }
1615
1616 /**
1617 * @brief Get the prescaler value.
1618 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1619 * @param TIMx Timer instance
1620 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1621 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)1622 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
1623 {
1624 return (uint32_t)(READ_REG(TIMx->PSC));
1625 }
1626
1627 /**
1628 * @brief Set the auto-reload value.
1629 * @note The counter is blocked while the auto-reload value is null.
1630 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1631 * whether or not a timer instance supports a 32 bits counter.
1632 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1633 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1634 * @param TIMx Timer instance
1635 * @param AutoReload between Min_Data=0 and Max_Data=65535
1636 * @retval None
1637 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1638 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1639 {
1640 WRITE_REG(TIMx->ARR, AutoReload);
1641 }
1642
1643 /**
1644 * @brief Get the auto-reload value.
1645 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1646 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1647 * whether or not a timer instance supports a 32 bits counter.
1648 * @param TIMx Timer instance
1649 * @retval Auto-reload value
1650 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)1651 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
1652 {
1653 return (uint32_t)(READ_REG(TIMx->ARR));
1654 }
1655
1656 /**
1657 * @brief Set the repetition counter value.
1658 * @note For advanced timer instances RepetitionCounter can be up to 65535.
1659 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1660 * whether or not a timer instance supports a repetition counter.
1661 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1662 * @param TIMx Timer instance
1663 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
1664 * @retval None
1665 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)1666 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1667 {
1668 WRITE_REG(TIMx->RCR, RepetitionCounter);
1669 }
1670
1671 /**
1672 * @brief Get the repetition counter value.
1673 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1674 * whether or not a timer instance supports a repetition counter.
1675 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1676 * @param TIMx Timer instance
1677 * @retval Repetition counter value
1678 */
LL_TIM_GetRepetitionCounter(const TIM_TypeDef * TIMx)1679 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
1680 {
1681 return (uint32_t)(READ_REG(TIMx->RCR));
1682 }
1683
1684 /**
1685 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1686 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
1687 * in an atomic way.
1688 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
1689 * @param TIMx Timer instance
1690 * @retval None
1691 */
LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)1692 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
1693 {
1694 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1695 }
1696
1697 /**
1698 * @brief Disable update interrupt flag (UIF) remapping.
1699 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
1700 * @param TIMx Timer instance
1701 * @retval None
1702 */
LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)1703 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
1704 {
1705 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1706 }
1707
1708 /**
1709 * @brief Indicate whether update interrupt flag (UIF) copy is set.
1710 * @param Counter Counter value
1711 * @retval State of bit (1 or 0).
1712 */
LL_TIM_IsActiveUIFCPY(const uint32_t Counter)1713 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
1714 {
1715 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
1716 }
1717
1718 /**
1719 * @}
1720 */
1721
1722 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1723 * @{
1724 */
1725 /**
1726 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1727 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1728 * they are updated only when a commutation event (COM) occurs.
1729 * @note Only on channels that have a complementary output.
1730 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1731 * whether or not a timer instance is able to generate a commutation event.
1732 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1733 * @param TIMx Timer instance
1734 * @retval None
1735 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)1736 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1737 {
1738 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1739 }
1740
1741 /**
1742 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1743 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1744 * whether or not a timer instance is able to generate a commutation event.
1745 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1746 * @param TIMx Timer instance
1747 * @retval None
1748 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)1749 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1750 {
1751 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1752 }
1753
1754 /**
1755 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1756 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1757 * whether or not a timer instance is able to generate a commutation event.
1758 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1759 * @param TIMx Timer instance
1760 * @param CCUpdateSource This parameter can be one of the following values:
1761 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1762 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1763 * @retval None
1764 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)1765 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1766 {
1767 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1768 }
1769
1770 /**
1771 * @brief Set the trigger of the capture/compare DMA request.
1772 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1773 * @param TIMx Timer instance
1774 * @param DMAReqTrigger This parameter can be one of the following values:
1775 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1776 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1777 * @retval None
1778 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)1779 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1780 {
1781 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1782 }
1783
1784 /**
1785 * @brief Get actual trigger of the capture/compare DMA request.
1786 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1787 * @param TIMx Timer instance
1788 * @retval Returned value can be one of the following values:
1789 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1790 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1791 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)1792 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
1793 {
1794 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1795 }
1796
1797 /**
1798 * @brief Set the lock level to freeze the
1799 * configuration of several capture/compare parameters.
1800 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1801 * the lock mechanism is supported by a timer instance.
1802 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1803 * @param TIMx Timer instance
1804 * @param LockLevel This parameter can be one of the following values:
1805 * @arg @ref LL_TIM_LOCKLEVEL_OFF
1806 * @arg @ref LL_TIM_LOCKLEVEL_1
1807 * @arg @ref LL_TIM_LOCKLEVEL_2
1808 * @arg @ref LL_TIM_LOCKLEVEL_3
1809 * @retval None
1810 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)1811 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1812 {
1813 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1814 }
1815
1816 /**
1817 * @brief Enable capture/compare channels.
1818 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1819 * CCER CC1NE LL_TIM_CC_EnableChannel\n
1820 * CCER CC2E LL_TIM_CC_EnableChannel\n
1821 * CCER CC2NE LL_TIM_CC_EnableChannel\n
1822 * CCER CC3E LL_TIM_CC_EnableChannel\n
1823 * CCER CC3NE LL_TIM_CC_EnableChannel\n
1824 * CCER CC4E LL_TIM_CC_EnableChannel\n
1825 * CCER CC5E LL_TIM_CC_EnableChannel\n
1826 * CCER CC6E LL_TIM_CC_EnableChannel
1827 * @param TIMx Timer instance
1828 * @param Channels This parameter can be a combination of the following values:
1829 * @arg @ref LL_TIM_CHANNEL_CH1
1830 * @arg @ref LL_TIM_CHANNEL_CH1N
1831 * @arg @ref LL_TIM_CHANNEL_CH2
1832 * @arg @ref LL_TIM_CHANNEL_CH2N
1833 * @arg @ref LL_TIM_CHANNEL_CH3
1834 * @arg @ref LL_TIM_CHANNEL_CH3N
1835 * @arg @ref LL_TIM_CHANNEL_CH4
1836 * @arg @ref LL_TIM_CHANNEL_CH5
1837 * @arg @ref LL_TIM_CHANNEL_CH6
1838 * @retval None
1839 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1840 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1841 {
1842 SET_BIT(TIMx->CCER, Channels);
1843 }
1844
1845 /**
1846 * @brief Disable capture/compare channels.
1847 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
1848 * CCER CC1NE LL_TIM_CC_DisableChannel\n
1849 * CCER CC2E LL_TIM_CC_DisableChannel\n
1850 * CCER CC2NE LL_TIM_CC_DisableChannel\n
1851 * CCER CC3E LL_TIM_CC_DisableChannel\n
1852 * CCER CC3NE LL_TIM_CC_DisableChannel\n
1853 * CCER CC4E LL_TIM_CC_DisableChannel\n
1854 * CCER CC5E LL_TIM_CC_DisableChannel\n
1855 * CCER CC6E LL_TIM_CC_DisableChannel
1856 * @param TIMx Timer instance
1857 * @param Channels This parameter can be a combination of the following values:
1858 * @arg @ref LL_TIM_CHANNEL_CH1
1859 * @arg @ref LL_TIM_CHANNEL_CH1N
1860 * @arg @ref LL_TIM_CHANNEL_CH2
1861 * @arg @ref LL_TIM_CHANNEL_CH2N
1862 * @arg @ref LL_TIM_CHANNEL_CH3
1863 * @arg @ref LL_TIM_CHANNEL_CH3N
1864 * @arg @ref LL_TIM_CHANNEL_CH4
1865 * @arg @ref LL_TIM_CHANNEL_CH5
1866 * @arg @ref LL_TIM_CHANNEL_CH6
1867 * @retval None
1868 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1869 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1870 {
1871 CLEAR_BIT(TIMx->CCER, Channels);
1872 }
1873
1874 /**
1875 * @brief Indicate whether channel(s) is(are) enabled.
1876 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
1877 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
1878 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
1879 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
1880 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
1881 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
1882 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
1883 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
1884 * CCER CC6E LL_TIM_CC_IsEnabledChannel
1885 * @param TIMx Timer instance
1886 * @param Channels This parameter can be a combination of the following values:
1887 * @arg @ref LL_TIM_CHANNEL_CH1
1888 * @arg @ref LL_TIM_CHANNEL_CH1N
1889 * @arg @ref LL_TIM_CHANNEL_CH2
1890 * @arg @ref LL_TIM_CHANNEL_CH2N
1891 * @arg @ref LL_TIM_CHANNEL_CH3
1892 * @arg @ref LL_TIM_CHANNEL_CH3N
1893 * @arg @ref LL_TIM_CHANNEL_CH4
1894 * @arg @ref LL_TIM_CHANNEL_CH5
1895 * @arg @ref LL_TIM_CHANNEL_CH6
1896 * @retval State of bit (1 or 0).
1897 */
LL_TIM_CC_IsEnabledChannel(TIM_TypeDef * TIMx,uint32_t Channels)1898 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1899 {
1900 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
1901 }
1902
1903 /**
1904 * @}
1905 */
1906
1907 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
1908 * @{
1909 */
1910 /**
1911 * @brief Configure an output channel.
1912 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
1913 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
1914 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
1915 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
1916 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
1917 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
1918 * CCER CC1P LL_TIM_OC_ConfigOutput\n
1919 * CCER CC2P LL_TIM_OC_ConfigOutput\n
1920 * CCER CC3P LL_TIM_OC_ConfigOutput\n
1921 * CCER CC4P LL_TIM_OC_ConfigOutput\n
1922 * CCER CC5P LL_TIM_OC_ConfigOutput\n
1923 * CCER CC6P LL_TIM_OC_ConfigOutput\n
1924 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
1925 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
1926 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
1927 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
1928 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
1929 * CR2 OIS6 LL_TIM_OC_ConfigOutput
1930 * @param TIMx Timer instance
1931 * @param Channel This parameter can be one of the following values:
1932 * @arg @ref LL_TIM_CHANNEL_CH1
1933 * @arg @ref LL_TIM_CHANNEL_CH2
1934 * @arg @ref LL_TIM_CHANNEL_CH3
1935 * @arg @ref LL_TIM_CHANNEL_CH4
1936 * @arg @ref LL_TIM_CHANNEL_CH5
1937 * @arg @ref LL_TIM_CHANNEL_CH6
1938 * @param Configuration This parameter must be a combination of all the following values:
1939 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
1940 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
1941 * @retval None
1942 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)1943 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
1944 {
1945 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1946 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1947 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
1948 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
1949 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
1950 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
1951 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
1952 }
1953
1954 /**
1955 * @brief Define the behavior of the output reference signal OCxREF from which
1956 * OCx and OCxN (when relevant) are derived.
1957 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
1958 * CCMR1 OC2M LL_TIM_OC_SetMode\n
1959 * CCMR2 OC3M LL_TIM_OC_SetMode\n
1960 * CCMR2 OC4M LL_TIM_OC_SetMode\n
1961 * CCMR3 OC5M LL_TIM_OC_SetMode\n
1962 * CCMR3 OC6M LL_TIM_OC_SetMode
1963 * @param TIMx Timer instance
1964 * @param Channel This parameter can be one of the following values:
1965 * @arg @ref LL_TIM_CHANNEL_CH1
1966 * @arg @ref LL_TIM_CHANNEL_CH2
1967 * @arg @ref LL_TIM_CHANNEL_CH3
1968 * @arg @ref LL_TIM_CHANNEL_CH4
1969 * @arg @ref LL_TIM_CHANNEL_CH5
1970 * @arg @ref LL_TIM_CHANNEL_CH6
1971 * @param Mode This parameter can be one of the following values:
1972 * @arg @ref LL_TIM_OCMODE_FROZEN
1973 * @arg @ref LL_TIM_OCMODE_ACTIVE
1974 * @arg @ref LL_TIM_OCMODE_INACTIVE
1975 * @arg @ref LL_TIM_OCMODE_TOGGLE
1976 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
1977 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
1978 * @arg @ref LL_TIM_OCMODE_PWM1
1979 * @arg @ref LL_TIM_OCMODE_PWM2
1980 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
1981 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
1982 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
1983 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
1984 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
1985 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
1986 * @retval None
1987 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)1988 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
1989 {
1990 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1991 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1992 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
1993 }
1994
1995 /**
1996 * @brief Get the output compare mode of an output channel.
1997 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
1998 * CCMR1 OC2M LL_TIM_OC_GetMode\n
1999 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2000 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2001 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2002 * CCMR3 OC6M LL_TIM_OC_GetMode
2003 * @param TIMx Timer instance
2004 * @param Channel This parameter can be one of the following values:
2005 * @arg @ref LL_TIM_CHANNEL_CH1
2006 * @arg @ref LL_TIM_CHANNEL_CH2
2007 * @arg @ref LL_TIM_CHANNEL_CH3
2008 * @arg @ref LL_TIM_CHANNEL_CH4
2009 * @arg @ref LL_TIM_CHANNEL_CH5
2010 * @arg @ref LL_TIM_CHANNEL_CH6
2011 * @retval Returned value can be one of the following values:
2012 * @arg @ref LL_TIM_OCMODE_FROZEN
2013 * @arg @ref LL_TIM_OCMODE_ACTIVE
2014 * @arg @ref LL_TIM_OCMODE_INACTIVE
2015 * @arg @ref LL_TIM_OCMODE_TOGGLE
2016 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2017 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2018 * @arg @ref LL_TIM_OCMODE_PWM1
2019 * @arg @ref LL_TIM_OCMODE_PWM2
2020 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2021 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2022 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2023 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2024 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2025 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2026 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)2027 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
2028 {
2029 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2030 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2031 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2032 }
2033
2034 /**
2035 * @brief Set the polarity of an output channel.
2036 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2037 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2038 * CCER CC2P LL_TIM_OC_SetPolarity\n
2039 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2040 * CCER CC3P LL_TIM_OC_SetPolarity\n
2041 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2042 * CCER CC4P LL_TIM_OC_SetPolarity\n
2043 * CCER CC5P LL_TIM_OC_SetPolarity\n
2044 * CCER CC6P LL_TIM_OC_SetPolarity
2045 * @param TIMx Timer instance
2046 * @param Channel This parameter can be one of the following values:
2047 * @arg @ref LL_TIM_CHANNEL_CH1
2048 * @arg @ref LL_TIM_CHANNEL_CH1N
2049 * @arg @ref LL_TIM_CHANNEL_CH2
2050 * @arg @ref LL_TIM_CHANNEL_CH2N
2051 * @arg @ref LL_TIM_CHANNEL_CH3
2052 * @arg @ref LL_TIM_CHANNEL_CH3N
2053 * @arg @ref LL_TIM_CHANNEL_CH4
2054 * @arg @ref LL_TIM_CHANNEL_CH5
2055 * @arg @ref LL_TIM_CHANNEL_CH6
2056 * @param Polarity This parameter can be one of the following values:
2057 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2058 * @arg @ref LL_TIM_OCPOLARITY_LOW
2059 * @retval None
2060 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)2061 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2062 {
2063 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2064 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2065 }
2066
2067 /**
2068 * @brief Get the polarity of an output channel.
2069 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2070 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2071 * CCER CC2P LL_TIM_OC_GetPolarity\n
2072 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2073 * CCER CC3P LL_TIM_OC_GetPolarity\n
2074 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2075 * CCER CC4P LL_TIM_OC_GetPolarity\n
2076 * CCER CC5P LL_TIM_OC_GetPolarity\n
2077 * CCER CC6P LL_TIM_OC_GetPolarity
2078 * @param TIMx Timer instance
2079 * @param Channel This parameter can be one of the following values:
2080 * @arg @ref LL_TIM_CHANNEL_CH1
2081 * @arg @ref LL_TIM_CHANNEL_CH1N
2082 * @arg @ref LL_TIM_CHANNEL_CH2
2083 * @arg @ref LL_TIM_CHANNEL_CH2N
2084 * @arg @ref LL_TIM_CHANNEL_CH3
2085 * @arg @ref LL_TIM_CHANNEL_CH3N
2086 * @arg @ref LL_TIM_CHANNEL_CH4
2087 * @arg @ref LL_TIM_CHANNEL_CH5
2088 * @arg @ref LL_TIM_CHANNEL_CH6
2089 * @retval Returned value can be one of the following values:
2090 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2091 * @arg @ref LL_TIM_OCPOLARITY_LOW
2092 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2093 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2094 {
2095 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2096 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2097 }
2098
2099 /**
2100 * @brief Set the IDLE state of an output channel
2101 * @note This function is significant only for the timer instances
2102 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2103 * can be used to check whether or not a timer instance provides
2104 * a break input.
2105 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2106 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2107 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2108 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2109 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2110 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2111 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2112 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2113 * CR2 OIS6 LL_TIM_OC_SetIdleState
2114 * @param TIMx Timer instance
2115 * @param Channel This parameter can be one of the following values:
2116 * @arg @ref LL_TIM_CHANNEL_CH1
2117 * @arg @ref LL_TIM_CHANNEL_CH1N
2118 * @arg @ref LL_TIM_CHANNEL_CH2
2119 * @arg @ref LL_TIM_CHANNEL_CH2N
2120 * @arg @ref LL_TIM_CHANNEL_CH3
2121 * @arg @ref LL_TIM_CHANNEL_CH3N
2122 * @arg @ref LL_TIM_CHANNEL_CH4
2123 * @arg @ref LL_TIM_CHANNEL_CH5
2124 * @arg @ref LL_TIM_CHANNEL_CH6
2125 * @param IdleState This parameter can be one of the following values:
2126 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2127 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2128 * @retval None
2129 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)2130 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2131 {
2132 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2133 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2134 }
2135
2136 /**
2137 * @brief Get the IDLE state of an output channel
2138 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2139 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2140 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2141 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2142 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2143 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2144 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2145 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2146 * CR2 OIS6 LL_TIM_OC_GetIdleState
2147 * @param TIMx Timer instance
2148 * @param Channel This parameter can be one of the following values:
2149 * @arg @ref LL_TIM_CHANNEL_CH1
2150 * @arg @ref LL_TIM_CHANNEL_CH1N
2151 * @arg @ref LL_TIM_CHANNEL_CH2
2152 * @arg @ref LL_TIM_CHANNEL_CH2N
2153 * @arg @ref LL_TIM_CHANNEL_CH3
2154 * @arg @ref LL_TIM_CHANNEL_CH3N
2155 * @arg @ref LL_TIM_CHANNEL_CH4
2156 * @arg @ref LL_TIM_CHANNEL_CH5
2157 * @arg @ref LL_TIM_CHANNEL_CH6
2158 * @retval Returned value can be one of the following values:
2159 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2160 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2161 */
LL_TIM_OC_GetIdleState(const TIM_TypeDef * TIMx,uint32_t Channel)2162 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
2163 {
2164 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2165 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2166 }
2167
2168 /**
2169 * @brief Enable fast mode for the output channel.
2170 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2171 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2172 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2173 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2174 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2175 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2176 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2177 * @param TIMx Timer instance
2178 * @param Channel This parameter can be one of the following values:
2179 * @arg @ref LL_TIM_CHANNEL_CH1
2180 * @arg @ref LL_TIM_CHANNEL_CH2
2181 * @arg @ref LL_TIM_CHANNEL_CH3
2182 * @arg @ref LL_TIM_CHANNEL_CH4
2183 * @arg @ref LL_TIM_CHANNEL_CH5
2184 * @arg @ref LL_TIM_CHANNEL_CH6
2185 * @retval None
2186 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)2187 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2188 {
2189 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2190 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2191 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2192
2193 }
2194
2195 /**
2196 * @brief Disable fast mode for the output channel.
2197 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2198 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2199 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2200 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2201 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2202 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2203 * @param TIMx Timer instance
2204 * @param Channel This parameter can be one of the following values:
2205 * @arg @ref LL_TIM_CHANNEL_CH1
2206 * @arg @ref LL_TIM_CHANNEL_CH2
2207 * @arg @ref LL_TIM_CHANNEL_CH3
2208 * @arg @ref LL_TIM_CHANNEL_CH4
2209 * @arg @ref LL_TIM_CHANNEL_CH5
2210 * @arg @ref LL_TIM_CHANNEL_CH6
2211 * @retval None
2212 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)2213 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2214 {
2215 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2216 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2217 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2218
2219 }
2220
2221 /**
2222 * @brief Indicates whether fast mode is enabled for the output channel.
2223 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2224 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2225 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2226 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2227 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2228 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2229 * @param TIMx Timer instance
2230 * @param Channel This parameter can be one of the following values:
2231 * @arg @ref LL_TIM_CHANNEL_CH1
2232 * @arg @ref LL_TIM_CHANNEL_CH2
2233 * @arg @ref LL_TIM_CHANNEL_CH3
2234 * @arg @ref LL_TIM_CHANNEL_CH4
2235 * @arg @ref LL_TIM_CHANNEL_CH5
2236 * @arg @ref LL_TIM_CHANNEL_CH6
2237 * @retval State of bit (1 or 0).
2238 */
LL_TIM_OC_IsEnabledFast(TIM_TypeDef * TIMx,uint32_t Channel)2239 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
2240 {
2241 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2242 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2243 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2244 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2245 }
2246
2247 /**
2248 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2249 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2250 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2251 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2252 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2253 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2254 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2255 * @param TIMx Timer instance
2256 * @param Channel This parameter can be one of the following values:
2257 * @arg @ref LL_TIM_CHANNEL_CH1
2258 * @arg @ref LL_TIM_CHANNEL_CH2
2259 * @arg @ref LL_TIM_CHANNEL_CH3
2260 * @arg @ref LL_TIM_CHANNEL_CH4
2261 * @arg @ref LL_TIM_CHANNEL_CH5
2262 * @arg @ref LL_TIM_CHANNEL_CH6
2263 * @retval None
2264 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2265 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2266 {
2267 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2268 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2269 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2270 }
2271
2272 /**
2273 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2274 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2275 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2276 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2277 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2278 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2279 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2280 * @param TIMx Timer instance
2281 * @param Channel This parameter can be one of the following values:
2282 * @arg @ref LL_TIM_CHANNEL_CH1
2283 * @arg @ref LL_TIM_CHANNEL_CH2
2284 * @arg @ref LL_TIM_CHANNEL_CH3
2285 * @arg @ref LL_TIM_CHANNEL_CH4
2286 * @arg @ref LL_TIM_CHANNEL_CH5
2287 * @arg @ref LL_TIM_CHANNEL_CH6
2288 * @retval None
2289 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2290 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2291 {
2292 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2293 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2294 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2295 }
2296
2297 /**
2298 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2299 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2300 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2301 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2302 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2303 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2304 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2305 * @param TIMx Timer instance
2306 * @param Channel This parameter can be one of the following values:
2307 * @arg @ref LL_TIM_CHANNEL_CH1
2308 * @arg @ref LL_TIM_CHANNEL_CH2
2309 * @arg @ref LL_TIM_CHANNEL_CH3
2310 * @arg @ref LL_TIM_CHANNEL_CH4
2311 * @arg @ref LL_TIM_CHANNEL_CH5
2312 * @arg @ref LL_TIM_CHANNEL_CH6
2313 * @retval State of bit (1 or 0).
2314 */
LL_TIM_OC_IsEnabledPreload(TIM_TypeDef * TIMx,uint32_t Channel)2315 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
2316 {
2317 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2318 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2319 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2320 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2321 }
2322
2323 /**
2324 * @brief Enable clearing the output channel on an external event.
2325 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2326 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2327 * or not a timer instance can clear the OCxREF signal on an external event.
2328 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2329 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2330 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2331 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2332 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2333 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2334 * @param TIMx Timer instance
2335 * @param Channel This parameter can be one of the following values:
2336 * @arg @ref LL_TIM_CHANNEL_CH1
2337 * @arg @ref LL_TIM_CHANNEL_CH2
2338 * @arg @ref LL_TIM_CHANNEL_CH3
2339 * @arg @ref LL_TIM_CHANNEL_CH4
2340 * @arg @ref LL_TIM_CHANNEL_CH5
2341 * @arg @ref LL_TIM_CHANNEL_CH6
2342 * @retval None
2343 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2344 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2345 {
2346 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2347 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2348 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2349 }
2350
2351 /**
2352 * @brief Disable clearing the output channel on an external event.
2353 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2354 * or not a timer instance can clear the OCxREF signal on an external event.
2355 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2356 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2357 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2358 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2359 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2360 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2361 * @param TIMx Timer instance
2362 * @param Channel This parameter can be one of the following values:
2363 * @arg @ref LL_TIM_CHANNEL_CH1
2364 * @arg @ref LL_TIM_CHANNEL_CH2
2365 * @arg @ref LL_TIM_CHANNEL_CH3
2366 * @arg @ref LL_TIM_CHANNEL_CH4
2367 * @arg @ref LL_TIM_CHANNEL_CH5
2368 * @arg @ref LL_TIM_CHANNEL_CH6
2369 * @retval None
2370 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2371 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2372 {
2373 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2374 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2375 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2376 }
2377
2378 /**
2379 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2380 * @note This function enables clearing the output channel on an external event.
2381 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2382 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2383 * or not a timer instance can clear the OCxREF signal on an external event.
2384 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2385 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2386 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2387 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2388 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2389 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2390 * @param TIMx Timer instance
2391 * @param Channel This parameter can be one of the following values:
2392 * @arg @ref LL_TIM_CHANNEL_CH1
2393 * @arg @ref LL_TIM_CHANNEL_CH2
2394 * @arg @ref LL_TIM_CHANNEL_CH3
2395 * @arg @ref LL_TIM_CHANNEL_CH4
2396 * @arg @ref LL_TIM_CHANNEL_CH5
2397 * @arg @ref LL_TIM_CHANNEL_CH6
2398 * @retval State of bit (1 or 0).
2399 */
LL_TIM_OC_IsEnabledClear(TIM_TypeDef * TIMx,uint32_t Channel)2400 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
2401 {
2402 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2403 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2404 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2405 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2406 }
2407
2408 /**
2409 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
2410 * the Ocx and OCxN signals).
2411 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2412 * dead-time insertion feature is supported by a timer instance.
2413 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2414 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2415 * @param TIMx Timer instance
2416 * @param DeadTime between Min_Data=0 and Max_Data=255
2417 * @retval None
2418 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2419 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2420 {
2421 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2422 }
2423
2424 /**
2425 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2426 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2427 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2428 * whether or not a timer instance supports a 32 bits counter.
2429 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2430 * output channel 1 is supported by a timer instance.
2431 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2432 * @param TIMx Timer instance
2433 * @param CompareValue between Min_Data=0 and Max_Data=65535
2434 * @retval None
2435 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2436 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2437 {
2438 WRITE_REG(TIMx->CCR1, CompareValue);
2439 }
2440
2441 /**
2442 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2443 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2444 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2445 * whether or not a timer instance supports a 32 bits counter.
2446 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2447 * output channel 2 is supported by a timer instance.
2448 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2449 * @param TIMx Timer instance
2450 * @param CompareValue between Min_Data=0 and Max_Data=65535
2451 * @retval None
2452 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2453 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2454 {
2455 WRITE_REG(TIMx->CCR2, CompareValue);
2456 }
2457
2458 /**
2459 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2460 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2461 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2462 * whether or not a timer instance supports a 32 bits counter.
2463 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2464 * output channel is supported by a timer instance.
2465 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2466 * @param TIMx Timer instance
2467 * @param CompareValue between Min_Data=0 and Max_Data=65535
2468 * @retval None
2469 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2470 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2471 {
2472 WRITE_REG(TIMx->CCR3, CompareValue);
2473 }
2474
2475 /**
2476 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2477 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2478 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2479 * whether or not a timer instance supports a 32 bits counter.
2480 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2481 * output channel 4 is supported by a timer instance.
2482 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2483 * @param TIMx Timer instance
2484 * @param CompareValue between Min_Data=0 and Max_Data=65535
2485 * @retval None
2486 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2487 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2488 {
2489 WRITE_REG(TIMx->CCR4, CompareValue);
2490 }
2491
2492 /**
2493 * @brief Set compare value for output channel 5 (TIMx_CCR5).
2494 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2495 * output channel 5 is supported by a timer instance.
2496 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2497 * @param TIMx Timer instance
2498 * @param CompareValue between Min_Data=0 and Max_Data=65535
2499 * @retval None
2500 */
LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx,uint32_t CompareValue)2501 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
2502 {
2503 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
2504 }
2505
2506 /**
2507 * @brief Set compare value for output channel 6 (TIMx_CCR6).
2508 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2509 * output channel 6 is supported by a timer instance.
2510 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2511 * @param TIMx Timer instance
2512 * @param CompareValue between Min_Data=0 and Max_Data=65535
2513 * @retval None
2514 */
LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx,uint32_t CompareValue)2515 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
2516 {
2517 WRITE_REG(TIMx->CCR6, CompareValue);
2518 }
2519
2520 /**
2521 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2522 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2523 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2524 * whether or not a timer instance supports a 32 bits counter.
2525 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2526 * output channel 1 is supported by a timer instance.
2527 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2528 * @param TIMx Timer instance
2529 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2530 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)2531 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
2532 {
2533 return (uint32_t)(READ_REG(TIMx->CCR1));
2534 }
2535
2536 /**
2537 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2538 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2539 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2540 * whether or not a timer instance supports a 32 bits counter.
2541 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2542 * output channel 2 is supported by a timer instance.
2543 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2544 * @param TIMx Timer instance
2545 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2546 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)2547 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
2548 {
2549 return (uint32_t)(READ_REG(TIMx->CCR2));
2550 }
2551
2552 /**
2553 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2554 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2555 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2556 * whether or not a timer instance supports a 32 bits counter.
2557 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2558 * output channel 3 is supported by a timer instance.
2559 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2560 * @param TIMx Timer instance
2561 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2562 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)2563 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
2564 {
2565 return (uint32_t)(READ_REG(TIMx->CCR3));
2566 }
2567
2568 /**
2569 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2570 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2571 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2572 * whether or not a timer instance supports a 32 bits counter.
2573 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2574 * output channel 4 is supported by a timer instance.
2575 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2576 * @param TIMx Timer instance
2577 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2578 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)2579 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
2580 {
2581 return (uint32_t)(READ_REG(TIMx->CCR4));
2582 }
2583
2584 /**
2585 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
2586 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2587 * output channel 5 is supported by a timer instance.
2588 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2589 * @param TIMx Timer instance
2590 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2591 */
LL_TIM_OC_GetCompareCH5(const TIM_TypeDef * TIMx)2592 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
2593 {
2594 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
2595 }
2596
2597 /**
2598 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
2599 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2600 * output channel 6 is supported by a timer instance.
2601 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2602 * @param TIMx Timer instance
2603 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2604 */
LL_TIM_OC_GetCompareCH6(const TIM_TypeDef * TIMx)2605 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
2606 {
2607 return (uint32_t)(READ_REG(TIMx->CCR6));
2608 }
2609
2610 /**
2611 * @brief Select on which reference signal the OC5REF is combined to.
2612 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
2613 * whether or not a timer instance supports the combined 3-phase PWM mode.
2614 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2615 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2616 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2617 * @param TIMx Timer instance
2618 * @param GroupCH5 This parameter can be a combination of the following values:
2619 * @arg @ref LL_TIM_GROUPCH5_NONE
2620 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
2621 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
2622 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
2623 * @retval None
2624 */
LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx,uint32_t GroupCH5)2625 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
2626 {
2627 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
2628 }
2629
2630 /**
2631 * @}
2632 */
2633
2634 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2635 * @{
2636 */
2637 /**
2638 * @brief Configure input channel.
2639 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2640 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2641 * CCMR1 IC1F LL_TIM_IC_Config\n
2642 * CCMR1 CC2S LL_TIM_IC_Config\n
2643 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2644 * CCMR1 IC2F LL_TIM_IC_Config\n
2645 * CCMR2 CC3S LL_TIM_IC_Config\n
2646 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2647 * CCMR2 IC3F LL_TIM_IC_Config\n
2648 * CCMR2 CC4S LL_TIM_IC_Config\n
2649 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2650 * CCMR2 IC4F LL_TIM_IC_Config\n
2651 * CCER CC1P LL_TIM_IC_Config\n
2652 * CCER CC1NP LL_TIM_IC_Config\n
2653 * CCER CC2P LL_TIM_IC_Config\n
2654 * CCER CC2NP LL_TIM_IC_Config\n
2655 * CCER CC3P LL_TIM_IC_Config\n
2656 * CCER CC3NP LL_TIM_IC_Config\n
2657 * CCER CC4P LL_TIM_IC_Config\n
2658 * CCER CC4NP LL_TIM_IC_Config
2659 * @param TIMx Timer instance
2660 * @param Channel This parameter can be one of the following values:
2661 * @arg @ref LL_TIM_CHANNEL_CH1
2662 * @arg @ref LL_TIM_CHANNEL_CH2
2663 * @arg @ref LL_TIM_CHANNEL_CH3
2664 * @arg @ref LL_TIM_CHANNEL_CH4
2665 * @param Configuration This parameter must be a combination of all the following values:
2666 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2667 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2668 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2669 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2670 * @retval None
2671 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2672 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2673 {
2674 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2675 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2676 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2677 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
2678 << SHIFT_TAB_ICxx[iChannel]);
2679 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2680 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2681 }
2682
2683 /**
2684 * @brief Set the active input.
2685 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2686 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2687 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2688 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2689 * @param TIMx Timer instance
2690 * @param Channel This parameter can be one of the following values:
2691 * @arg @ref LL_TIM_CHANNEL_CH1
2692 * @arg @ref LL_TIM_CHANNEL_CH2
2693 * @arg @ref LL_TIM_CHANNEL_CH3
2694 * @arg @ref LL_TIM_CHANNEL_CH4
2695 * @param ICActiveInput This parameter can be one of the following values:
2696 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2697 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2698 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2699 * @retval None
2700 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)2701 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2702 {
2703 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2704 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2705 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2706 }
2707
2708 /**
2709 * @brief Get the current active input.
2710 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2711 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2712 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2713 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2714 * @param TIMx Timer instance
2715 * @param Channel This parameter can be one of the following values:
2716 * @arg @ref LL_TIM_CHANNEL_CH1
2717 * @arg @ref LL_TIM_CHANNEL_CH2
2718 * @arg @ref LL_TIM_CHANNEL_CH3
2719 * @arg @ref LL_TIM_CHANNEL_CH4
2720 * @retval Returned value can be one of the following values:
2721 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2722 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2723 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2724 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)2725 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
2726 {
2727 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2728 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2729 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2730 }
2731
2732 /**
2733 * @brief Set the prescaler of input channel.
2734 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2735 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2736 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2737 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2738 * @param TIMx Timer instance
2739 * @param Channel This parameter can be one of the following values:
2740 * @arg @ref LL_TIM_CHANNEL_CH1
2741 * @arg @ref LL_TIM_CHANNEL_CH2
2742 * @arg @ref LL_TIM_CHANNEL_CH3
2743 * @arg @ref LL_TIM_CHANNEL_CH4
2744 * @param ICPrescaler This parameter can be one of the following values:
2745 * @arg @ref LL_TIM_ICPSC_DIV1
2746 * @arg @ref LL_TIM_ICPSC_DIV2
2747 * @arg @ref LL_TIM_ICPSC_DIV4
2748 * @arg @ref LL_TIM_ICPSC_DIV8
2749 * @retval None
2750 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)2751 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2752 {
2753 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2754 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2755 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2756 }
2757
2758 /**
2759 * @brief Get the current prescaler value acting on an input channel.
2760 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2761 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2762 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2763 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2764 * @param TIMx Timer instance
2765 * @param Channel This parameter can be one of the following values:
2766 * @arg @ref LL_TIM_CHANNEL_CH1
2767 * @arg @ref LL_TIM_CHANNEL_CH2
2768 * @arg @ref LL_TIM_CHANNEL_CH3
2769 * @arg @ref LL_TIM_CHANNEL_CH4
2770 * @retval Returned value can be one of the following values:
2771 * @arg @ref LL_TIM_ICPSC_DIV1
2772 * @arg @ref LL_TIM_ICPSC_DIV2
2773 * @arg @ref LL_TIM_ICPSC_DIV4
2774 * @arg @ref LL_TIM_ICPSC_DIV8
2775 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)2776 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
2777 {
2778 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2779 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2780 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2781 }
2782
2783 /**
2784 * @brief Set the input filter duration.
2785 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
2786 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
2787 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
2788 * CCMR2 IC4F LL_TIM_IC_SetFilter
2789 * @param TIMx Timer instance
2790 * @param Channel This parameter can be one of the following values:
2791 * @arg @ref LL_TIM_CHANNEL_CH1
2792 * @arg @ref LL_TIM_CHANNEL_CH2
2793 * @arg @ref LL_TIM_CHANNEL_CH3
2794 * @arg @ref LL_TIM_CHANNEL_CH4
2795 * @param ICFilter This parameter can be one of the following values:
2796 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2797 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2798 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2799 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2800 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2801 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2802 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2803 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2804 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2805 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2806 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2807 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2808 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2809 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2810 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2811 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2812 * @retval None
2813 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)2814 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
2815 {
2816 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2817 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2818 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2819 }
2820
2821 /**
2822 * @brief Get the input filter duration.
2823 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
2824 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
2825 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
2826 * CCMR2 IC4F LL_TIM_IC_GetFilter
2827 * @param TIMx Timer instance
2828 * @param Channel This parameter can be one of the following values:
2829 * @arg @ref LL_TIM_CHANNEL_CH1
2830 * @arg @ref LL_TIM_CHANNEL_CH2
2831 * @arg @ref LL_TIM_CHANNEL_CH3
2832 * @arg @ref LL_TIM_CHANNEL_CH4
2833 * @retval Returned value can be one of the following values:
2834 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2835 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2836 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2837 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2838 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2839 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2840 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2841 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2842 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2843 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2844 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2845 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2846 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2847 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2848 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2849 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2850 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)2851 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
2852 {
2853 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2854 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2855 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2856 }
2857
2858 /**
2859 * @brief Set the input channel polarity.
2860 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
2861 * CCER CC1NP LL_TIM_IC_SetPolarity\n
2862 * CCER CC2P LL_TIM_IC_SetPolarity\n
2863 * CCER CC2NP LL_TIM_IC_SetPolarity\n
2864 * CCER CC3P LL_TIM_IC_SetPolarity\n
2865 * CCER CC3NP LL_TIM_IC_SetPolarity\n
2866 * CCER CC4P LL_TIM_IC_SetPolarity\n
2867 * CCER CC4NP LL_TIM_IC_SetPolarity
2868 * @param TIMx Timer instance
2869 * @param Channel This parameter can be one of the following values:
2870 * @arg @ref LL_TIM_CHANNEL_CH1
2871 * @arg @ref LL_TIM_CHANNEL_CH2
2872 * @arg @ref LL_TIM_CHANNEL_CH3
2873 * @arg @ref LL_TIM_CHANNEL_CH4
2874 * @param ICPolarity This parameter can be one of the following values:
2875 * @arg @ref LL_TIM_IC_POLARITY_RISING
2876 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2877 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2878 * @retval None
2879 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)2880 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
2881 {
2882 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2883 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2884 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
2885 }
2886
2887 /**
2888 * @brief Get the current input channel polarity.
2889 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
2890 * CCER CC1NP LL_TIM_IC_GetPolarity\n
2891 * CCER CC2P LL_TIM_IC_GetPolarity\n
2892 * CCER CC2NP LL_TIM_IC_GetPolarity\n
2893 * CCER CC3P LL_TIM_IC_GetPolarity\n
2894 * CCER CC3NP LL_TIM_IC_GetPolarity\n
2895 * CCER CC4P LL_TIM_IC_GetPolarity\n
2896 * CCER CC4NP LL_TIM_IC_GetPolarity
2897 * @param TIMx Timer instance
2898 * @param Channel This parameter can be one of the following values:
2899 * @arg @ref LL_TIM_CHANNEL_CH1
2900 * @arg @ref LL_TIM_CHANNEL_CH2
2901 * @arg @ref LL_TIM_CHANNEL_CH3
2902 * @arg @ref LL_TIM_CHANNEL_CH4
2903 * @retval Returned value can be one of the following values:
2904 * @arg @ref LL_TIM_IC_POLARITY_RISING
2905 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2906 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2907 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2908 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2909 {
2910 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2911 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
2912 SHIFT_TAB_CCxP[iChannel]);
2913 }
2914
2915 /**
2916 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
2917 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2918 * a timer instance provides an XOR input.
2919 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
2920 * @param TIMx Timer instance
2921 * @retval None
2922 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)2923 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
2924 {
2925 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
2926 }
2927
2928 /**
2929 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
2930 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2931 * a timer instance provides an XOR input.
2932 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
2933 * @param TIMx Timer instance
2934 * @retval None
2935 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)2936 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
2937 {
2938 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
2939 }
2940
2941 /**
2942 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
2943 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2944 * a timer instance provides an XOR input.
2945 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
2946 * @param TIMx Timer instance
2947 * @retval State of bit (1 or 0).
2948 */
LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef * TIMx)2949 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
2950 {
2951 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
2952 }
2953
2954 /**
2955 * @brief Get captured value for input channel 1.
2956 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2957 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2958 * whether or not a timer instance supports a 32 bits counter.
2959 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2960 * input channel 1 is supported by a timer instance.
2961 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
2962 * @param TIMx Timer instance
2963 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2964 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)2965 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
2966 {
2967 return (uint32_t)(READ_REG(TIMx->CCR1));
2968 }
2969
2970 /**
2971 * @brief Get captured value for input channel 2.
2972 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2973 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2974 * whether or not a timer instance supports a 32 bits counter.
2975 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2976 * input channel 2 is supported by a timer instance.
2977 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
2978 * @param TIMx Timer instance
2979 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2980 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)2981 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
2982 {
2983 return (uint32_t)(READ_REG(TIMx->CCR2));
2984 }
2985
2986 /**
2987 * @brief Get captured value for input channel 3.
2988 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2989 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2990 * whether or not a timer instance supports a 32 bits counter.
2991 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2992 * input channel 3 is supported by a timer instance.
2993 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
2994 * @param TIMx Timer instance
2995 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2996 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)2997 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
2998 {
2999 return (uint32_t)(READ_REG(TIMx->CCR3));
3000 }
3001
3002 /**
3003 * @brief Get captured value for input channel 4.
3004 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3005 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3006 * whether or not a timer instance supports a 32 bits counter.
3007 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3008 * input channel 4 is supported by a timer instance.
3009 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3010 * @param TIMx Timer instance
3011 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3012 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)3013 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
3014 {
3015 return (uint32_t)(READ_REG(TIMx->CCR4));
3016 }
3017
3018 /**
3019 * @}
3020 */
3021
3022 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3023 * @{
3024 */
3025 /**
3026 * @brief Enable external clock mode 2.
3027 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3028 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3029 * whether or not a timer instance supports external clock mode2.
3030 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3031 * @param TIMx Timer instance
3032 * @retval None
3033 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)3034 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3035 {
3036 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3037 }
3038
3039 /**
3040 * @brief Disable external clock mode 2.
3041 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3042 * whether or not a timer instance supports external clock mode2.
3043 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3044 * @param TIMx Timer instance
3045 * @retval None
3046 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)3047 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3048 {
3049 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3050 }
3051
3052 /**
3053 * @brief Indicate whether external clock mode 2 is enabled.
3054 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3055 * whether or not a timer instance supports external clock mode2.
3056 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3057 * @param TIMx Timer instance
3058 * @retval State of bit (1 or 0).
3059 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)3060 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
3061 {
3062 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3063 }
3064
3065 /**
3066 * @brief Set the clock source of the counter clock.
3067 * @note when selected clock source is external clock mode 1, the timer input
3068 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3069 * function. This timer input must be configured by calling
3070 * the @ref LL_TIM_IC_Config() function.
3071 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3072 * whether or not a timer instance supports external clock mode1.
3073 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3074 * whether or not a timer instance supports external clock mode2.
3075 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3076 * SMCR ECE LL_TIM_SetClockSource
3077 * @param TIMx Timer instance
3078 * @param ClockSource This parameter can be one of the following values:
3079 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3080 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3081 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3082 * @retval None
3083 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)3084 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3085 {
3086 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3087 }
3088
3089 /**
3090 * @brief Set the encoder interface mode.
3091 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3092 * whether or not a timer instance supports the encoder mode.
3093 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3094 * @param TIMx Timer instance
3095 * @param EncoderMode This parameter can be one of the following values:
3096 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3097 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3098 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3099 * @retval None
3100 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)3101 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3102 {
3103 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3104 }
3105
3106 /**
3107 * @}
3108 */
3109
3110 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3111 * @{
3112 */
3113 /**
3114 * @brief Set the trigger output (TRGO) used for timer synchronization .
3115 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3116 * whether or not a timer instance can operate as a master timer.
3117 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3118 * @param TIMx Timer instance
3119 * @param TimerSynchronization This parameter can be one of the following values:
3120 * @arg @ref LL_TIM_TRGO_RESET
3121 * @arg @ref LL_TIM_TRGO_ENABLE
3122 * @arg @ref LL_TIM_TRGO_UPDATE
3123 * @arg @ref LL_TIM_TRGO_CC1IF
3124 * @arg @ref LL_TIM_TRGO_OC1REF
3125 * @arg @ref LL_TIM_TRGO_OC2REF
3126 * @arg @ref LL_TIM_TRGO_OC3REF
3127 * @arg @ref LL_TIM_TRGO_OC4REF
3128 * @retval None
3129 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)3130 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3131 {
3132 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3133 }
3134
3135 /**
3136 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3137 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3138 * whether or not a timer instance can be used for ADC synchronization.
3139 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3140 * @param TIMx Timer Instance
3141 * @param ADCSynchronization This parameter can be one of the following values:
3142 * @arg @ref LL_TIM_TRGO2_RESET
3143 * @arg @ref LL_TIM_TRGO2_ENABLE
3144 * @arg @ref LL_TIM_TRGO2_UPDATE
3145 * @arg @ref LL_TIM_TRGO2_CC1F
3146 * @arg @ref LL_TIM_TRGO2_OC1
3147 * @arg @ref LL_TIM_TRGO2_OC2
3148 * @arg @ref LL_TIM_TRGO2_OC3
3149 * @arg @ref LL_TIM_TRGO2_OC4
3150 * @arg @ref LL_TIM_TRGO2_OC5
3151 * @arg @ref LL_TIM_TRGO2_OC6
3152 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3153 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3154 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3155 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3156 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3157 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3158 * @retval None
3159 */
LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx,uint32_t ADCSynchronization)3160 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3161 {
3162 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3163 }
3164
3165 /**
3166 * @brief Set the synchronization mode of a slave timer.
3167 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3168 * a timer instance can operate as a slave timer.
3169 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3170 * @param TIMx Timer instance
3171 * @param SlaveMode This parameter can be one of the following values:
3172 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3173 * @arg @ref LL_TIM_SLAVEMODE_RESET
3174 * @arg @ref LL_TIM_SLAVEMODE_GATED
3175 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3176 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3177 * @retval None
3178 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)3179 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3180 {
3181 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3182 }
3183
3184 /**
3185 * @brief Set the selects the trigger input to be used to synchronize the counter.
3186 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3187 * a timer instance can operate as a slave timer.
3188 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3189 * @param TIMx Timer instance
3190 * @param TriggerInput This parameter can be one of the following values:
3191 * @arg @ref LL_TIM_TS_ITR0
3192 * @arg @ref LL_TIM_TS_ITR1
3193 * @arg @ref LL_TIM_TS_ITR2
3194 * @arg @ref LL_TIM_TS_ITR3
3195 * @arg @ref LL_TIM_TS_TI1F_ED
3196 * @arg @ref LL_TIM_TS_TI1FP1
3197 * @arg @ref LL_TIM_TS_TI2FP2
3198 * @arg @ref LL_TIM_TS_ETRF
3199 * @retval None
3200 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)3201 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3202 {
3203 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3204 }
3205
3206 /**
3207 * @brief Enable the Master/Slave mode.
3208 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3209 * a timer instance can operate as a slave timer.
3210 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3211 * @param TIMx Timer instance
3212 * @retval None
3213 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)3214 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3215 {
3216 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3217 }
3218
3219 /**
3220 * @brief Disable the Master/Slave mode.
3221 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3222 * a timer instance can operate as a slave timer.
3223 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3224 * @param TIMx Timer instance
3225 * @retval None
3226 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)3227 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3228 {
3229 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3230 }
3231
3232 /**
3233 * @brief Indicates whether the Master/Slave mode is enabled.
3234 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3235 * a timer instance can operate as a slave timer.
3236 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3237 * @param TIMx Timer instance
3238 * @retval State of bit (1 or 0).
3239 */
LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef * TIMx)3240 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
3241 {
3242 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
3243 }
3244
3245 /**
3246 * @brief Configure the external trigger (ETR) input.
3247 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3248 * a timer instance provides an external trigger input.
3249 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3250 * SMCR ETPS LL_TIM_ConfigETR\n
3251 * SMCR ETF LL_TIM_ConfigETR
3252 * @param TIMx Timer instance
3253 * @param ETRPolarity This parameter can be one of the following values:
3254 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3255 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3256 * @param ETRPrescaler This parameter can be one of the following values:
3257 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3258 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3259 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3260 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3261 * @param ETRFilter This parameter can be one of the following values:
3262 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3263 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3264 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3265 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3266 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3267 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3268 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3269 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3270 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3271 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3272 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3273 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3274 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3275 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3276 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3277 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3278 * @retval None
3279 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)3280 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3281 uint32_t ETRFilter)
3282 {
3283 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3284 }
3285
3286 /**
3287 * @}
3288 */
3289
3290 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
3291 * @{
3292 */
3293 /**
3294 * @brief Enable the break function.
3295 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3296 * a timer instance provides a break input.
3297 * @rmtoll BDTR BKE LL_TIM_EnableBRK
3298 * @param TIMx Timer instance
3299 * @retval None
3300 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)3301 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
3302 {
3303 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3304 }
3305
3306 /**
3307 * @brief Disable the break function.
3308 * @rmtoll BDTR BKE LL_TIM_DisableBRK
3309 * @param TIMx Timer instance
3310 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3311 * a timer instance provides a break input.
3312 * @retval None
3313 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)3314 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
3315 {
3316 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3317 }
3318
3319 /**
3320 * @brief Configure the break input.
3321 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3322 * a timer instance provides a break input.
3323 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
3324 * BDTR BKF LL_TIM_ConfigBRK
3325 * @param TIMx Timer instance
3326 * @param BreakPolarity This parameter can be one of the following values:
3327 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3328 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3329 * @param BreakFilter This parameter can be one of the following values:
3330 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
3331 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
3332 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
3333 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
3334 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
3335 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
3336 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
3337 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
3338 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
3339 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
3340 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
3341 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
3342 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
3343 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
3344 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
3345 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
3346 * @retval None
3347 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakFilter)3348 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
3349 uint32_t BreakFilter)
3350 {
3351 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
3352 }
3353
3354 /**
3355 * @brief Enable the break 2 function.
3356 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3357 * a timer instance provides a second break input.
3358 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
3359 * @param TIMx Timer instance
3360 * @retval None
3361 */
LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)3362 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
3363 {
3364 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3365 }
3366
3367 /**
3368 * @brief Disable the break 2 function.
3369 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3370 * a timer instance provides a second break input.
3371 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
3372 * @param TIMx Timer instance
3373 * @retval None
3374 */
LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)3375 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
3376 {
3377 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3378 }
3379
3380 /**
3381 * @brief Configure the break 2 input.
3382 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3383 * a timer instance provides a second break input.
3384 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
3385 * BDTR BK2F LL_TIM_ConfigBRK2
3386 * @param TIMx Timer instance
3387 * @param Break2Polarity This parameter can be one of the following values:
3388 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
3389 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
3390 * @param Break2Filter This parameter can be one of the following values:
3391 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
3392 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
3393 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
3394 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
3395 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
3396 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
3397 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
3398 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
3399 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
3400 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
3401 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
3402 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
3403 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
3404 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
3405 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
3406 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
3407 * @retval None
3408 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter)3409 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
3410 {
3411 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
3412 }
3413
3414 /**
3415 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
3416 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3417 * a timer instance provides a break input.
3418 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
3419 * BDTR OSSR LL_TIM_SetOffStates
3420 * @param TIMx Timer instance
3421 * @param OffStateIdle This parameter can be one of the following values:
3422 * @arg @ref LL_TIM_OSSI_DISABLE
3423 * @arg @ref LL_TIM_OSSI_ENABLE
3424 * @param OffStateRun This parameter can be one of the following values:
3425 * @arg @ref LL_TIM_OSSR_DISABLE
3426 * @arg @ref LL_TIM_OSSR_ENABLE
3427 * @retval None
3428 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)3429 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
3430 {
3431 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
3432 }
3433
3434 /**
3435 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
3436 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3437 * a timer instance provides a break input.
3438 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
3439 * @param TIMx Timer instance
3440 * @retval None
3441 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)3442 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
3443 {
3444 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3445 }
3446
3447 /**
3448 * @brief Disable automatic output (MOE can be set only by software).
3449 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3450 * a timer instance provides a break input.
3451 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
3452 * @param TIMx Timer instance
3453 * @retval None
3454 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)3455 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
3456 {
3457 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3458 }
3459
3460 /**
3461 * @brief Indicate whether automatic output is enabled.
3462 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3463 * a timer instance provides a break input.
3464 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
3465 * @param TIMx Timer instance
3466 * @retval State of bit (1 or 0).
3467 */
LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef * TIMx)3468 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
3469 {
3470 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
3471 }
3472
3473 /**
3474 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
3475 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3476 * software and is reset in case of break or break2 event
3477 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3478 * a timer instance provides a break input.
3479 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
3480 * @param TIMx Timer instance
3481 * @retval None
3482 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)3483 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
3484 {
3485 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3486 }
3487
3488 /**
3489 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
3490 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3491 * software and is reset in case of break or break2 event.
3492 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3493 * a timer instance provides a break input.
3494 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
3495 * @param TIMx Timer instance
3496 * @retval None
3497 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)3498 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
3499 {
3500 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3501 }
3502
3503 /**
3504 * @brief Indicates whether outputs are enabled.
3505 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3506 * a timer instance provides a break input.
3507 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
3508 * @param TIMx Timer instance
3509 * @retval State of bit (1 or 0).
3510 */
LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef * TIMx)3511 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
3512 {
3513 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
3514 }
3515
3516 #if defined(TIM_BREAK_INPUT_SUPPORT)
3517 /**
3518 * @brief Enable the signals connected to the designated timer break input.
3519 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3520 * or not a timer instance allows for break input selection.
3521 * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
3522 * AF1 BKDFBKE LL_TIM_EnableBreakInputSource\n
3523 * AF2 BK2INE LL_TIM_EnableBreakInputSource\n
3524 * AF2 BK2DFBKE LL_TIM_EnableBreakInputSource
3525 * @param TIMx Timer instance
3526 * @param BreakInput This parameter can be one of the following values:
3527 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3528 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3529 * @param Source This parameter can be one of the following values:
3530 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3531 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
3532 * @retval None
3533 */
LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3534 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3535 {
3536 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3537 SET_BIT(*pReg, Source);
3538 }
3539
3540 /**
3541 * @brief Disable the signals connected to the designated timer break input.
3542 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3543 * or not a timer instance allows for break input selection.
3544 * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
3545 * AF1 BKDFBKE LL_TIM_DisableBreakInputSource\n
3546 * AF2 BK2INE LL_TIM_DisableBreakInputSource\n
3547 * AF2 BK2DFBKE LL_TIM_DisableBreakInputSource
3548 * @param TIMx Timer instance
3549 * @param BreakInput This parameter can be one of the following values:
3550 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3551 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3552 * @param Source This parameter can be one of the following values:
3553 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3554 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
3555 * @retval None
3556 */
LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3557 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3558 {
3559 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3560 CLEAR_BIT(*pReg, Source);
3561 }
3562
3563 /**
3564 * @brief Set the polarity of the break signal for the timer break input.
3565 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3566 * or not a timer instance allows for break input selection.
3567 * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
3568 * AF1 BKDFBKP LL_TIM_SetBreakInputSourcePolarity\n
3569 * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
3570 * AF2 BK2DFBKP LL_TIM_SetBreakInputSourcePolarity
3571 * @param TIMx Timer instance
3572 * @param BreakInput This parameter can be one of the following values:
3573 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3574 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3575 * @param Source This parameter can be one of the following values:
3576 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3577 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
3578 * @param Polarity This parameter can be one of the following values:
3579 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
3580 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
3581 * @retval None
3582 */
LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source,uint32_t Polarity)3583 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
3584 uint32_t Polarity)
3585 {
3586 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3587 MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
3588 }
3589 #endif /* TIM_BREAK_INPUT_SUPPORT */
3590 /**
3591 * @}
3592 */
3593
3594 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
3595 * @{
3596 */
3597 /**
3598 * @brief Configures the timer DMA burst feature.
3599 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
3600 * not a timer instance supports the DMA burst mode.
3601 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
3602 * DCR DBA LL_TIM_ConfigDMABurst
3603 * @param TIMx Timer instance
3604 * @param DMABurstBaseAddress This parameter can be one of the following values:
3605 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
3606 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
3607 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
3608 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
3609 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
3610 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
3611 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
3612 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
3613 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
3614 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
3615 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
3616 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
3617 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
3618 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
3619 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
3620 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
3621 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
3622 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
3623 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR
3624 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
3625 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
3626 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
3627 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 (*)
3628 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 (*)
3629 * (*) value not defined in all devices
3630 * @param DMABurstLength This parameter can be one of the following values:
3631 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
3632 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
3633 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
3634 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
3635 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
3636 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
3637 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
3638 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
3639 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
3640 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
3641 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
3642 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
3643 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
3644 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
3645 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
3646 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
3647 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
3648 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
3649 * @retval None
3650 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)3651 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
3652 {
3653 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
3654 }
3655
3656 /**
3657 * @}
3658 */
3659
3660 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3661 * @{
3662 */
3663 /**
3664 * @brief Remap TIM inputs (input channel, internal/external triggers).
3665 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3666 * a some timer inputs can be remapped.
3667 * @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n
3668 * TIM5_OR TI4_RMP LL_TIM_SetRemap\n
3669 * TIM11_OR TI1_RMP LL_TIM_SetRemap
3670 * @param TIMx Timer instance
3671 * @param Remap Remap param depends on the TIMx. Description available only
3672 * in CHM version of the User Manual (not in .pdf).
3673 * Otherwise see Reference Manual description of OR registers.
3674 *
3675 * Below description summarizes "Timer Instance" and "Remap" param combinations:
3676 *
3677 * TIM2: one of the following values
3678 *
3679 * ITR1_RMP can be one of the following values
3680 * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
3681 * @arg @ref LL_TIM_TIM2_ITR1_RMP_ETH_PTP
3682 * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
3683 * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF
3684 *
3685 * TIM5: one of the following values
3686 *
3687 * @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO
3688 * @arg @ref LL_TIM_TIM5_TI4_RMP_LSI
3689 * @arg @ref LL_TIM_TIM5_TI4_RMP_LSE
3690 * @arg @ref LL_TIM_TIM5_TI4_RMP_RTC
3691 *
3692 * TIM11: one of the following values
3693 *
3694 * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO
3695 * @arg @ref LL_TIM_TIM11_TI1_RMP_SPDIFRX
3696 * @arg @ref LL_TIM_TIM11_TI1_RMP_HSE
3697 * @arg @ref LL_TIM_TIM11_TI1_RMP_MCO1
3698 *
3699 * @retval None
3700 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)3701 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
3702 {
3703 MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
3704 }
3705
3706 /**
3707 * @}
3708 */
3709
3710 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
3711 * @{
3712 */
3713 /**
3714 * @brief Clear the update interrupt flag (UIF).
3715 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
3716 * @param TIMx Timer instance
3717 * @retval None
3718 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)3719 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
3720 {
3721 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
3722 }
3723
3724 /**
3725 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
3726 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
3727 * @param TIMx Timer instance
3728 * @retval State of bit (1 or 0).
3729 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)3730 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
3731 {
3732 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
3733 }
3734
3735 /**
3736 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
3737 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
3738 * @param TIMx Timer instance
3739 * @retval None
3740 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)3741 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
3742 {
3743 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
3744 }
3745
3746 /**
3747 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
3748 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
3749 * @param TIMx Timer instance
3750 * @retval State of bit (1 or 0).
3751 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)3752 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
3753 {
3754 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
3755 }
3756
3757 /**
3758 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
3759 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
3760 * @param TIMx Timer instance
3761 * @retval None
3762 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)3763 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
3764 {
3765 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
3766 }
3767
3768 /**
3769 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
3770 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
3771 * @param TIMx Timer instance
3772 * @retval State of bit (1 or 0).
3773 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)3774 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
3775 {
3776 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
3777 }
3778
3779 /**
3780 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
3781 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
3782 * @param TIMx Timer instance
3783 * @retval None
3784 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)3785 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
3786 {
3787 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
3788 }
3789
3790 /**
3791 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
3792 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
3793 * @param TIMx Timer instance
3794 * @retval State of bit (1 or 0).
3795 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)3796 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
3797 {
3798 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
3799 }
3800
3801 /**
3802 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
3803 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
3804 * @param TIMx Timer instance
3805 * @retval None
3806 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)3807 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
3808 {
3809 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
3810 }
3811
3812 /**
3813 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
3814 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
3815 * @param TIMx Timer instance
3816 * @retval State of bit (1 or 0).
3817 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)3818 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
3819 {
3820 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
3821 }
3822
3823 /**
3824 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
3825 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
3826 * @param TIMx Timer instance
3827 * @retval None
3828 */
LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)3829 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
3830 {
3831 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
3832 }
3833
3834 /**
3835 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
3836 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
3837 * @param TIMx Timer instance
3838 * @retval State of bit (1 or 0).
3839 */
LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef * TIMx)3840 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
3841 {
3842 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
3843 }
3844
3845 /**
3846 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
3847 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
3848 * @param TIMx Timer instance
3849 * @retval None
3850 */
LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)3851 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
3852 {
3853 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
3854 }
3855
3856 /**
3857 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
3858 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
3859 * @param TIMx Timer instance
3860 * @retval State of bit (1 or 0).
3861 */
LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef * TIMx)3862 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
3863 {
3864 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
3865 }
3866
3867 /**
3868 * @brief Clear the commutation interrupt flag (COMIF).
3869 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
3870 * @param TIMx Timer instance
3871 * @retval None
3872 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)3873 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
3874 {
3875 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
3876 }
3877
3878 /**
3879 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
3880 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
3881 * @param TIMx Timer instance
3882 * @retval State of bit (1 or 0).
3883 */
LL_TIM_IsActiveFlag_COM(const TIM_TypeDef * TIMx)3884 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
3885 {
3886 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
3887 }
3888
3889 /**
3890 * @brief Clear the trigger interrupt flag (TIF).
3891 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
3892 * @param TIMx Timer instance
3893 * @retval None
3894 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)3895 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
3896 {
3897 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
3898 }
3899
3900 /**
3901 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
3902 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
3903 * @param TIMx Timer instance
3904 * @retval State of bit (1 or 0).
3905 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)3906 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
3907 {
3908 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
3909 }
3910
3911 /**
3912 * @brief Clear the break interrupt flag (BIF).
3913 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
3914 * @param TIMx Timer instance
3915 * @retval None
3916 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)3917 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
3918 {
3919 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
3920 }
3921
3922 /**
3923 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
3924 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
3925 * @param TIMx Timer instance
3926 * @retval State of bit (1 or 0).
3927 */
LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef * TIMx)3928 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
3929 {
3930 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
3931 }
3932
3933 /**
3934 * @brief Clear the break 2 interrupt flag (B2IF).
3935 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
3936 * @param TIMx Timer instance
3937 * @retval None
3938 */
LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)3939 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
3940 {
3941 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
3942 }
3943
3944 /**
3945 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
3946 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
3947 * @param TIMx Timer instance
3948 * @retval State of bit (1 or 0).
3949 */
LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef * TIMx)3950 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
3951 {
3952 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
3953 }
3954
3955 /**
3956 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
3957 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
3958 * @param TIMx Timer instance
3959 * @retval None
3960 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)3961 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
3962 {
3963 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
3964 }
3965
3966 /**
3967 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
3968 * (Capture/Compare 1 interrupt is pending).
3969 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
3970 * @param TIMx Timer instance
3971 * @retval State of bit (1 or 0).
3972 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)3973 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
3974 {
3975 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
3976 }
3977
3978 /**
3979 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
3980 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
3981 * @param TIMx Timer instance
3982 * @retval None
3983 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)3984 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
3985 {
3986 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
3987 }
3988
3989 /**
3990 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
3991 * (Capture/Compare 2 over-capture interrupt is pending).
3992 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
3993 * @param TIMx Timer instance
3994 * @retval State of bit (1 or 0).
3995 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)3996 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
3997 {
3998 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
3999 }
4000
4001 /**
4002 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
4003 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
4004 * @param TIMx Timer instance
4005 * @retval None
4006 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)4007 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
4008 {
4009 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
4010 }
4011
4012 /**
4013 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
4014 * (Capture/Compare 3 over-capture interrupt is pending).
4015 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
4016 * @param TIMx Timer instance
4017 * @retval State of bit (1 or 0).
4018 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)4019 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
4020 {
4021 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
4022 }
4023
4024 /**
4025 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
4026 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
4027 * @param TIMx Timer instance
4028 * @retval None
4029 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)4030 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
4031 {
4032 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
4033 }
4034
4035 /**
4036 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
4037 * (Capture/Compare 4 over-capture interrupt is pending).
4038 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
4039 * @param TIMx Timer instance
4040 * @retval State of bit (1 or 0).
4041 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)4042 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
4043 {
4044 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
4045 }
4046
4047 /**
4048 * @brief Clear the system break interrupt flag (SBIF).
4049 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
4050 * @param TIMx Timer instance
4051 * @retval None
4052 */
LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)4053 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
4054 {
4055 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
4056 }
4057
4058 /**
4059 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
4060 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
4061 * @param TIMx Timer instance
4062 * @retval State of bit (1 or 0).
4063 */
LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef * TIMx)4064 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
4065 {
4066 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
4067 }
4068
4069 /**
4070 * @}
4071 */
4072
4073 /** @defgroup TIM_LL_EF_IT_Management IT-Management
4074 * @{
4075 */
4076 /**
4077 * @brief Enable update interrupt (UIE).
4078 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
4079 * @param TIMx Timer instance
4080 * @retval None
4081 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)4082 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
4083 {
4084 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
4085 }
4086
4087 /**
4088 * @brief Disable update interrupt (UIE).
4089 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
4090 * @param TIMx Timer instance
4091 * @retval None
4092 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)4093 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
4094 {
4095 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
4096 }
4097
4098 /**
4099 * @brief Indicates whether the update interrupt (UIE) is enabled.
4100 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
4101 * @param TIMx Timer instance
4102 * @retval State of bit (1 or 0).
4103 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)4104 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
4105 {
4106 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
4107 }
4108
4109 /**
4110 * @brief Enable capture/compare 1 interrupt (CC1IE).
4111 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
4112 * @param TIMx Timer instance
4113 * @retval None
4114 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)4115 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
4116 {
4117 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4118 }
4119
4120 /**
4121 * @brief Disable capture/compare 1 interrupt (CC1IE).
4122 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
4123 * @param TIMx Timer instance
4124 * @retval None
4125 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)4126 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
4127 {
4128 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4129 }
4130
4131 /**
4132 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
4133 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
4134 * @param TIMx Timer instance
4135 * @retval State of bit (1 or 0).
4136 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)4137 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
4138 {
4139 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
4140 }
4141
4142 /**
4143 * @brief Enable capture/compare 2 interrupt (CC2IE).
4144 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
4145 * @param TIMx Timer instance
4146 * @retval None
4147 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)4148 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
4149 {
4150 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4151 }
4152
4153 /**
4154 * @brief Disable capture/compare 2 interrupt (CC2IE).
4155 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
4156 * @param TIMx Timer instance
4157 * @retval None
4158 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)4159 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
4160 {
4161 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4162 }
4163
4164 /**
4165 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
4166 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
4167 * @param TIMx Timer instance
4168 * @retval State of bit (1 or 0).
4169 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)4170 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
4171 {
4172 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
4173 }
4174
4175 /**
4176 * @brief Enable capture/compare 3 interrupt (CC3IE).
4177 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
4178 * @param TIMx Timer instance
4179 * @retval None
4180 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)4181 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
4182 {
4183 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4184 }
4185
4186 /**
4187 * @brief Disable capture/compare 3 interrupt (CC3IE).
4188 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
4189 * @param TIMx Timer instance
4190 * @retval None
4191 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)4192 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
4193 {
4194 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4195 }
4196
4197 /**
4198 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
4199 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
4200 * @param TIMx Timer instance
4201 * @retval State of bit (1 or 0).
4202 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)4203 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
4204 {
4205 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
4206 }
4207
4208 /**
4209 * @brief Enable capture/compare 4 interrupt (CC4IE).
4210 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
4211 * @param TIMx Timer instance
4212 * @retval None
4213 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)4214 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
4215 {
4216 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4217 }
4218
4219 /**
4220 * @brief Disable capture/compare 4 interrupt (CC4IE).
4221 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
4222 * @param TIMx Timer instance
4223 * @retval None
4224 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)4225 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
4226 {
4227 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4228 }
4229
4230 /**
4231 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
4232 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
4233 * @param TIMx Timer instance
4234 * @retval State of bit (1 or 0).
4235 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)4236 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
4237 {
4238 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
4239 }
4240
4241 /**
4242 * @brief Enable commutation interrupt (COMIE).
4243 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
4244 * @param TIMx Timer instance
4245 * @retval None
4246 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)4247 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
4248 {
4249 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
4250 }
4251
4252 /**
4253 * @brief Disable commutation interrupt (COMIE).
4254 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
4255 * @param TIMx Timer instance
4256 * @retval None
4257 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)4258 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
4259 {
4260 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
4261 }
4262
4263 /**
4264 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
4265 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
4266 * @param TIMx Timer instance
4267 * @retval State of bit (1 or 0).
4268 */
LL_TIM_IsEnabledIT_COM(const TIM_TypeDef * TIMx)4269 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
4270 {
4271 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
4272 }
4273
4274 /**
4275 * @brief Enable trigger interrupt (TIE).
4276 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
4277 * @param TIMx Timer instance
4278 * @retval None
4279 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)4280 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
4281 {
4282 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
4283 }
4284
4285 /**
4286 * @brief Disable trigger interrupt (TIE).
4287 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
4288 * @param TIMx Timer instance
4289 * @retval None
4290 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)4291 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
4292 {
4293 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
4294 }
4295
4296 /**
4297 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
4298 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
4299 * @param TIMx Timer instance
4300 * @retval State of bit (1 or 0).
4301 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)4302 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
4303 {
4304 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
4305 }
4306
4307 /**
4308 * @brief Enable break interrupt (BIE).
4309 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
4310 * @param TIMx Timer instance
4311 * @retval None
4312 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)4313 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
4314 {
4315 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
4316 }
4317
4318 /**
4319 * @brief Disable break interrupt (BIE).
4320 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
4321 * @param TIMx Timer instance
4322 * @retval None
4323 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)4324 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
4325 {
4326 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
4327 }
4328
4329 /**
4330 * @brief Indicates whether the break interrupt (BIE) is enabled.
4331 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
4332 * @param TIMx Timer instance
4333 * @retval State of bit (1 or 0).
4334 */
LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef * TIMx)4335 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
4336 {
4337 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
4338 }
4339
4340 /**
4341 * @}
4342 */
4343
4344 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
4345 * @{
4346 */
4347 /**
4348 * @brief Enable update DMA request (UDE).
4349 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
4350 * @param TIMx Timer instance
4351 * @retval None
4352 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)4353 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4354 {
4355 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
4356 }
4357
4358 /**
4359 * @brief Disable update DMA request (UDE).
4360 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
4361 * @param TIMx Timer instance
4362 * @retval None
4363 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)4364 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4365 {
4366 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
4367 }
4368
4369 /**
4370 * @brief Indicates whether the update DMA request (UDE) is enabled.
4371 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
4372 * @param TIMx Timer instance
4373 * @retval State of bit (1 or 0).
4374 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)4375 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
4376 {
4377 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
4378 }
4379
4380 /**
4381 * @brief Enable capture/compare 1 DMA request (CC1DE).
4382 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
4383 * @param TIMx Timer instance
4384 * @retval None
4385 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)4386 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
4387 {
4388 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4389 }
4390
4391 /**
4392 * @brief Disable capture/compare 1 DMA request (CC1DE).
4393 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
4394 * @param TIMx Timer instance
4395 * @retval None
4396 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)4397 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
4398 {
4399 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4400 }
4401
4402 /**
4403 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
4404 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
4405 * @param TIMx Timer instance
4406 * @retval State of bit (1 or 0).
4407 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)4408 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
4409 {
4410 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
4411 }
4412
4413 /**
4414 * @brief Enable capture/compare 2 DMA request (CC2DE).
4415 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
4416 * @param TIMx Timer instance
4417 * @retval None
4418 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)4419 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
4420 {
4421 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4422 }
4423
4424 /**
4425 * @brief Disable capture/compare 2 DMA request (CC2DE).
4426 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
4427 * @param TIMx Timer instance
4428 * @retval None
4429 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)4430 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
4431 {
4432 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4433 }
4434
4435 /**
4436 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
4437 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
4438 * @param TIMx Timer instance
4439 * @retval State of bit (1 or 0).
4440 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)4441 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
4442 {
4443 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
4444 }
4445
4446 /**
4447 * @brief Enable capture/compare 3 DMA request (CC3DE).
4448 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
4449 * @param TIMx Timer instance
4450 * @retval None
4451 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)4452 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
4453 {
4454 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4455 }
4456
4457 /**
4458 * @brief Disable capture/compare 3 DMA request (CC3DE).
4459 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
4460 * @param TIMx Timer instance
4461 * @retval None
4462 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)4463 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
4464 {
4465 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4466 }
4467
4468 /**
4469 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
4470 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
4471 * @param TIMx Timer instance
4472 * @retval State of bit (1 or 0).
4473 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)4474 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
4475 {
4476 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
4477 }
4478
4479 /**
4480 * @brief Enable capture/compare 4 DMA request (CC4DE).
4481 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
4482 * @param TIMx Timer instance
4483 * @retval None
4484 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)4485 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
4486 {
4487 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4488 }
4489
4490 /**
4491 * @brief Disable capture/compare 4 DMA request (CC4DE).
4492 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
4493 * @param TIMx Timer instance
4494 * @retval None
4495 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)4496 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
4497 {
4498 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4499 }
4500
4501 /**
4502 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
4503 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
4504 * @param TIMx Timer instance
4505 * @retval State of bit (1 or 0).
4506 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)4507 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
4508 {
4509 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
4510 }
4511
4512 /**
4513 * @brief Enable commutation DMA request (COMDE).
4514 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
4515 * @param TIMx Timer instance
4516 * @retval None
4517 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)4518 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
4519 {
4520 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
4521 }
4522
4523 /**
4524 * @brief Disable commutation DMA request (COMDE).
4525 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
4526 * @param TIMx Timer instance
4527 * @retval None
4528 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)4529 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
4530 {
4531 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
4532 }
4533
4534 /**
4535 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
4536 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
4537 * @param TIMx Timer instance
4538 * @retval State of bit (1 or 0).
4539 */
LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef * TIMx)4540 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
4541 {
4542 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
4543 }
4544
4545 /**
4546 * @brief Enable trigger interrupt (TDE).
4547 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
4548 * @param TIMx Timer instance
4549 * @retval None
4550 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)4551 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
4552 {
4553 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
4554 }
4555
4556 /**
4557 * @brief Disable trigger interrupt (TDE).
4558 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
4559 * @param TIMx Timer instance
4560 * @retval None
4561 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)4562 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
4563 {
4564 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
4565 }
4566
4567 /**
4568 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
4569 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
4570 * @param TIMx Timer instance
4571 * @retval State of bit (1 or 0).
4572 */
LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef * TIMx)4573 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
4574 {
4575 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
4576 }
4577
4578 /**
4579 * @}
4580 */
4581
4582 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
4583 * @{
4584 */
4585 /**
4586 * @brief Generate an update event.
4587 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
4588 * @param TIMx Timer instance
4589 * @retval None
4590 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)4591 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
4592 {
4593 SET_BIT(TIMx->EGR, TIM_EGR_UG);
4594 }
4595
4596 /**
4597 * @brief Generate Capture/Compare 1 event.
4598 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
4599 * @param TIMx Timer instance
4600 * @retval None
4601 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)4602 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
4603 {
4604 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
4605 }
4606
4607 /**
4608 * @brief Generate Capture/Compare 2 event.
4609 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
4610 * @param TIMx Timer instance
4611 * @retval None
4612 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)4613 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
4614 {
4615 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
4616 }
4617
4618 /**
4619 * @brief Generate Capture/Compare 3 event.
4620 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
4621 * @param TIMx Timer instance
4622 * @retval None
4623 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)4624 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
4625 {
4626 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
4627 }
4628
4629 /**
4630 * @brief Generate Capture/Compare 4 event.
4631 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
4632 * @param TIMx Timer instance
4633 * @retval None
4634 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)4635 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
4636 {
4637 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
4638 }
4639
4640 /**
4641 * @brief Generate commutation event.
4642 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
4643 * @param TIMx Timer instance
4644 * @retval None
4645 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)4646 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
4647 {
4648 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
4649 }
4650
4651 /**
4652 * @brief Generate trigger event.
4653 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
4654 * @param TIMx Timer instance
4655 * @retval None
4656 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)4657 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
4658 {
4659 SET_BIT(TIMx->EGR, TIM_EGR_TG);
4660 }
4661
4662 /**
4663 * @brief Generate break event.
4664 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
4665 * @param TIMx Timer instance
4666 * @retval None
4667 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)4668 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
4669 {
4670 SET_BIT(TIMx->EGR, TIM_EGR_BG);
4671 }
4672
4673 /**
4674 * @brief Generate break 2 event.
4675 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
4676 * @param TIMx Timer instance
4677 * @retval None
4678 */
LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)4679 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
4680 {
4681 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
4682 }
4683
4684 /**
4685 * @}
4686 */
4687
4688 #if defined(USE_FULL_LL_DRIVER)
4689 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
4690 * @{
4691 */
4692
4693 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
4694 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
4695 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
4696 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4697 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4698 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
4699 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
4700 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4701 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4702 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4703 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4704 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4705 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4706 /**
4707 * @}
4708 */
4709 #endif /* USE_FULL_LL_DRIVER */
4710
4711 /**
4712 * @}
4713 */
4714
4715 /**
4716 * @}
4717 */
4718
4719 #endif /* TIM1 || TIM8 || TIM2 || TIM3 || TIM4 || TIM5 ||TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM6 || TIM7 */
4720
4721 /**
4722 * @}
4723 */
4724
4725 #ifdef __cplusplus
4726 }
4727 #endif
4728
4729 #endif /* __STM32F7xx_LL_TIM_H */
4730
