1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL SYSTEM driver contains a set of generic APIs that can be
23 used by user:
24 (+) Some of the FLASH features need to be handled in the SYSTEM file.
25 (+) Access to DBGCMU registers
26 (+) Access to SYSCFG registers
27
28 @endverbatim
29 ******************************************************************************
30 */
31
32 /* Define to prevent recursive inclusion -------------------------------------*/
33 #ifndef __STM32F7xx_LL_SYSTEM_H
34 #define __STM32F7xx_LL_SYSTEM_H
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /* Includes ------------------------------------------------------------------*/
41 #include "stm32f7xx.h"
42
43 /** @addtogroup STM32F7xx_LL_Driver
44 * @{
45 */
46
47 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
48
49 /** @defgroup SYSTEM_LL SYSTEM
50 * @{
51 */
52
53 /* Private types -------------------------------------------------------------*/
54 /* Private variables ---------------------------------------------------------*/
55
56 /* Private constants ---------------------------------------------------------*/
57 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
58 * @{
59 */
60
61 /**
62 * @}
63 */
64
65 /* Private macros ------------------------------------------------------------*/
66
67 /* Exported types ------------------------------------------------------------*/
68 /* Exported constants --------------------------------------------------------*/
69 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
70 * @{
71 */
72
73 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
74 * @{
75 */
76 #define LL_SYSCFG_REMAP_BOOT0 0x00000000U /*!< Boot information after Reset */
77 #define LL_SYSCFG_REMAP_BOOT1 SYSCFG_MEMRMP_MEM_BOOT /*!< Boot information after Reset */
78 /**
79 * @}
80 */
81
82
83 #if defined(SYSCFG_MEMRMP_SWP_FB)
84 /** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
85 * @{
86 */
87 #define LL_SYSCFG_BANKMODE_BANK1 0x00000000U /*!< Flash Bank 1 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000 (TCM)
88 and Flash Bank 2 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000 (TCM)*/
89
90 #define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_SWP_FB /*!< Flash Bank 2 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000(TCM)
91 and Flash Bank 1 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000(TCM) */
92 /**
93 * @}
94 */
95 #endif /* SYSCFG_MEMRMP_SWP_FB */
96
97 #if defined(SYSCFG_PMC_MII_RMII_SEL)
98 /** @defgroup SYSTEM_LL_EC_PMC SYSCFG PMC
99 * @{
100 */
101 #define LL_SYSCFG_PMC_ETHMII 0x00000000U /*!< ETH Media MII interface */
102 #define LL_SYSCFG_PMC_ETHRMII (uint32_t)SYSCFG_PMC_MII_RMII_SEL /*!< ETH Media RMII interface */
103
104 /**
105 * @}
106 */
107 #endif /* SYSCFG_PMC_MII_RMII_SEL */
108
109 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
110 * @{
111 */
112 #if defined(SYSCFG_PMC_I2C1_FMP)
113 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_PMC_I2C1_FMP /*!< Enable Fast Mode Plus for I2C1 */
114 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_PMC_I2C2_FMP /*!< Enable Fast Mode Plus for I2C2 */
115 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_PMC_I2C3_FMP /*!< Enable Fast Mode Plus for I2C3 */
116 #endif /* SYSCFG_PMC_I2C1_FMP */
117 #if defined(SYSCFG_PMC_I2C4_FMP)
118 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_PMC_I2C4_FMP /*!< Enable Fast Mode Plus for I2C4 */
119 #endif /* SYSCFG_PMC_I2C4_FMP */
120 #if defined(SYSCFG_PMC_I2C_PB6_FMP)
121 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_PMC_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
122 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_PMC_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
123 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_PMC_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
124 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_PMC_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
125 #endif /* SYSCFG_PMC_I2C_PB6_FMP */
126 /**
127 * @}
128 */
129
130 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
131 * @{
132 */
133 #define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */
134 #define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */
135 #define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */
136 #define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */
137 #define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */
138 #if defined(GPIOF)
139 #define LL_SYSCFG_EXTI_PORTF 5U /*!< EXTI PORT F */
140 #endif /* GPIOF */
141 #if defined(GPIOG)
142 #define LL_SYSCFG_EXTI_PORTG 6U /*!< EXTI PORT G */
143 #endif /* GPIOG */
144 #define LL_SYSCFG_EXTI_PORTH 7U /*!< EXTI PORT H */
145 #if defined(GPIOI)
146 #define LL_SYSCFG_EXTI_PORTI 8U /*!< EXTI PORT I */
147 #endif /* GPIOI */
148 #if defined(GPIOJ)
149 #define LL_SYSCFG_EXTI_PORTJ 9U /*!< EXTI PORT J */
150 #endif /* GPIOJ */
151 #if defined(GPIOK)
152 #define LL_SYSCFG_EXTI_PORTK 10U /*!< EXTI PORT k */
153 #endif /* GPIOK */
154 /**
155 * @}
156 */
157
158 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
159 * @{
160 */
161 #define LL_SYSCFG_EXTI_LINE0 (0x000FU << 16U | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */
162 #define LL_SYSCFG_EXTI_LINE1 (0x00F0U << 16U | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */
163 #define LL_SYSCFG_EXTI_LINE2 (0x0F00U << 16U | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */
164 #define LL_SYSCFG_EXTI_LINE3 (0xF000U << 16U | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */
165 #define LL_SYSCFG_EXTI_LINE4 (0x000FU << 16U | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */
166 #define LL_SYSCFG_EXTI_LINE5 (0x00F0U << 16U | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */
167 #define LL_SYSCFG_EXTI_LINE6 (0x0F00U << 16U | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */
168 #define LL_SYSCFG_EXTI_LINE7 (0xF000U << 16U | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */
169 #define LL_SYSCFG_EXTI_LINE8 (0x000FU << 16U | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */
170 #define LL_SYSCFG_EXTI_LINE9 (0x00F0U << 16U | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */
171 #define LL_SYSCFG_EXTI_LINE10 (0x0F00U << 16U | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */
172 #define LL_SYSCFG_EXTI_LINE11 (0xF000U << 16U | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */
173 #define LL_SYSCFG_EXTI_LINE12 (0x000FU << 16U | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */
174 #define LL_SYSCFG_EXTI_LINE13 (0x00F0U << 16U | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */
175 #define LL_SYSCFG_EXTI_LINE14 (0x0F00U << 16U | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */
176 #define LL_SYSCFG_EXTI_LINE15 (0xF000U << 16U | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */
177 /**
178 * @}
179 */
180
181 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
182 * @{
183 */
184 #if defined(SYSCFG_CBR_CLL)
185 #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CBR_CLL /*!< Enables and locks the Lockup output (raised during core
186 lockup state) of Cortex-M7 with Break Input of TIMER1, TIMER8 */
187 #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CBR_PVDL /*!< Enables and locks the PVD connection with TIMER1, TIMER8 Break input.
188 It also locks (write protect) the PVD_EN and PVDSEL[2:0] bits
189 of the power controller */
190 #endif /* SYSCFG_CBR_CLL */
191 /**
192 * @}
193 */
194 /** @defgroup SYSTEM_LL_EC_CMP_PD SYSCFG CMP PD
195 * @{
196 */
197 #define LL_SYSCFG_DISABLE_CMP_PD 0x00000000U /*!< I/O compensation cell power-down mode */
198 #define LL_SYSCFG_ENABLE_CMP_PD SYSCFG_CMPCR_CMP_PD /*!< I/O compensation cell enabled */
199 /**
200 * @}
201 */
202
203 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
204 * @{
205 */
206 #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
207 #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
208 #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
209 #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
210 #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
211 /**
212 * @}
213 */
214
215 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
216 * @{
217 */
218 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
219 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
220 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */
221 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */
222 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
223 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
224 #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */
225 #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */
226 #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
227 #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1_FZ_DBG_LPTIM1_STOP /*!< LPTIIM1 counter stopped when core is halted */
228 #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC counter stopped when core is halted */
229 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
230 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
231 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
232 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
233 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
234 #if defined(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)
235 #define LL_DBGMCU_APB1_GRP1_I2C4_STOP DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT /*!< I2C4 SMBUS timeout mode stopped when core is halted */
236 #endif /* DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT */
237 #define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */
238 #if defined(DBGMCU_APB1_FZ_DBG_CAN2_STOP)
239 #define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */
240 #endif /* DBGMCU_APB1_FZ_DBG_CAN2_STOP */
241 #if defined(DBGMCU_APB1_FZ_DBG_CAN3_STOP)
242 #define LL_DBGMCU_APB1_GRP1_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP /*!< CAN3 debug stopped when Core is halted */
243 #endif /*DBGMCU_APB1_FZ_DBG_CAN3_STOP*/
244 /**
245 * @}
246 */
247
248 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
249 * @{
250 */
251 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
252 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */
253 #define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */
254 #define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */
255 #define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */
256 /**
257 * @}
258 */
259
260 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
261 * @{
262 */
263 #define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
264 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
265 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
266 #define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
267 #define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */
268 #define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */
269 #define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */
270 #define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */
271 #define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH eight wait states */
272 #define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */
273 #define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */
274 #define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */
275 #define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */
276 #define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */
277 #define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */
278 #define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */
279 /**
280 * @}
281 */
282
283 /**
284 * @}
285 */
286
287 /* Exported macro ------------------------------------------------------------*/
288
289 /* Exported functions --------------------------------------------------------*/
290 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
291 * @{
292 */
293
294 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
295 * @{
296 */
297
298 /**
299 * @brief Enables the FMC Memory Mapping Swapping
300 * @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_EnableFMCMemorySwapping
301 * @note SDRAM is accessible at 0x60000000 and NOR/RAM
302 * is accessible at 0xC0000000
303 * @retval None
304 */
LL_SYSCFG_EnableFMCMemorySwapping(void)305 __STATIC_INLINE void LL_SYSCFG_EnableFMCMemorySwapping(void)
306 {
307 SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC_0);
308 }
309
310 /**
311 * @brief Disables the FMC Memory Mapping Swapping
312 * @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_DisableFMCMemorySwapping
313 * @note SDRAM is accessible at 0xC0000000 (default mapping)
314 * and NOR/RAM is accessible at 0x60000000 (default mapping)
315 * @retval None
316 */
LL_SYSCFG_DisableFMCMemorySwapping(void)317 __STATIC_INLINE void LL_SYSCFG_DisableFMCMemorySwapping(void)
318 {
319 CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC);
320 }
321
322 /**
323 * @brief Enables the Compensation Cell
324 * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_EnableCompensationCell
325 * @note The I/O compensation cell can be used only when the device supply
326 * voltage ranges from 2.4 to 3.6 V
327 * @retval None
328 */
LL_SYSCFG_EnableCompensationCell(void)329 __STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
330 {
331 SET_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
332 }
333
334 /**
335 * @brief Disables the Compensation Cell
336 * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_DisableCompensationCell
337 * @note The I/O compensation cell can be used only when the device supply
338 * voltage ranges from 2.4 to 3.6 V
339 * @retval None
340 */
LL_SYSCFG_DisableCompensationCell(void)341 __STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
342 {
343 CLEAR_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
344 }
345
346 /**
347 * @brief Get Compensation Cell ready Flag
348 * @rmtoll SYSCFG_CMPCR READY LL_SYSCFG_IsActiveFlag_CMPCR
349 * @retval State of bit (1 or 0).
350 */
LL_SYSCFG_IsActiveFlag_CMPCR(void)351 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
352 {
353 return (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY));
354 }
355
356
357 /**
358 * @brief Get the memory boot mapping as configured by user
359 * @rmtoll SYSCFG_MEMRMP MEM_BOOT LL_SYSCFG_GetRemapMemoryBoot
360 * @retval Returned value can be one of the following values:
361 * @arg @ref LL_SYSCFG_REMAP_BOOT0
362 * @arg @ref LL_SYSCFG_REMAP_BOOT1
363 *
364 * (*) value not defined in all devices
365 */
LL_SYSCFG_GetRemapMemoryBoot(void)366 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemoryBoot(void)
367 {
368 return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_BOOT));
369 }
370
371 #if defined(SYSCFG_PMC_MII_RMII_SEL)
372 /**
373 * @brief Select Ethernet PHY interface
374 * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_SetPHYInterface
375 * @param Interface This parameter can be one of the following values:
376 * @arg @ref LL_SYSCFG_PMC_ETHMII
377 * @arg @ref LL_SYSCFG_PMC_ETHRMII
378 * @retval None
379 */
LL_SYSCFG_SetPHYInterface(uint32_t Interface)380 __STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
381 {
382 MODIFY_REG(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL, Interface);
383 }
384
385 /**
386 * @brief Get Ethernet PHY interface
387 * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_GetPHYInterface
388 * @retval Returned value can be one of the following values:
389 * @arg @ref LL_SYSCFG_PMC_ETHMII
390 * @arg @ref LL_SYSCFG_PMC_ETHRMII
391 * @retval None
392 */
LL_SYSCFG_GetPHYInterface(void)393 __STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
394 {
395 return (uint32_t)(READ_BIT(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL));
396 }
397 #endif /* SYSCFG_PMC_MII_RMII_SEL */
398
399
400 #if defined(SYSCFG_MEMRMP_SWP_FB)
401 /**
402 * @brief Select Flash bank mode (Bank flashed at 0x08000000)
403 * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_SetFlashBankMode
404 * @param Bank This parameter can be one of the following values:
405 * @arg @ref LL_SYSCFG_BANKMODE_BANK1
406 * @arg @ref LL_SYSCFG_BANKMODE_BANK2
407 * @retval None
408 */
LL_SYSCFG_SetFlashBankMode(uint32_t Bank)409 __STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
410 {
411 MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB, Bank);
412 }
413
414 /**
415 * @brief Get Flash bank mode (Bank flashed at 0x08000000)
416 * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_GetFlashBankMode
417 * @retval Returned value can be one of the following values:
418 * @arg @ref LL_SYSCFG_BANKMODE_BANK1
419 * @arg @ref LL_SYSCFG_BANKMODE_BANK2
420 */
LL_SYSCFG_GetFlashBankMode(void)421 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
422 {
423 return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB));
424 }
425
426 #endif /* SYSCFG_MEMRMP_SWP_FB */
427
428 #if defined(SYSCFG_PMC_I2C1_FMP)
429 /**
430 * @brief Enable the I2C fast mode plus driving capability.
431 * @rmtoll SYSCFG_PMC I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n
432 * SYSCFG_PMC I2Cx_FMP LL_SYSCFG_EnableFastModePlus
433 * @param ConfigFastModePlus This parameter can be a combination of the following values:
434 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
435 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
436 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
437 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
438 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
439 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
440 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
441 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4(*)
442 *
443 * (*) value not defined in all devices
444 * @retval None
445 */
LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)446 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
447 {
448 SET_BIT(SYSCFG->PMC, ConfigFastModePlus);
449 }
450
451 /**
452 * @brief Disable the I2C fast mode plus driving capability.
453 * @rmtoll SYSCFG_PMC I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n
454 * SYSCFG_PMC I2Cx_FMP LL_SYSCFG_DisableFastModePlus
455 * @param ConfigFastModePlus This parameter can be a combination of the following values:
456 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
457 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
458 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
459 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
460 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
461 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
462 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
463 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4
464 * (*) value not defined in all devices
465 * @retval None
466 */
LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)467 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
468 {
469 CLEAR_BIT(SYSCFG->PMC, ConfigFastModePlus);
470 }
471 #endif /* SYSCFG_PMC_I2C1_FMP */
472
473
474 /**
475 * @brief Configure source input for the EXTI external interrupt.
476 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
477 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
478 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
479 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
480 * @param Port This parameter can be one of the following values:
481 * @arg @ref LL_SYSCFG_EXTI_PORTA
482 * @arg @ref LL_SYSCFG_EXTI_PORTB
483 * @arg @ref LL_SYSCFG_EXTI_PORTC
484 * @arg @ref LL_SYSCFG_EXTI_PORTD
485 * @arg @ref LL_SYSCFG_EXTI_PORTE
486 * @arg @ref LL_SYSCFG_EXTI_PORTF
487 * @arg @ref LL_SYSCFG_EXTI_PORTG
488 * @arg @ref LL_SYSCFG_EXTI_PORTH
489 * @arg @ref LL_SYSCFG_EXTI_PORTI
490 * @arg @ref LL_SYSCFG_EXTI_PORTJ
491 * @arg @ref LL_SYSCFG_EXTI_PORTK
492 *
493 * (*) value not defined in all devices
494 * @param Line This parameter can be one of the following values:
495 * @arg @ref LL_SYSCFG_EXTI_LINE0
496 * @arg @ref LL_SYSCFG_EXTI_LINE1
497 * @arg @ref LL_SYSCFG_EXTI_LINE2
498 * @arg @ref LL_SYSCFG_EXTI_LINE3
499 * @arg @ref LL_SYSCFG_EXTI_LINE4
500 * @arg @ref LL_SYSCFG_EXTI_LINE5
501 * @arg @ref LL_SYSCFG_EXTI_LINE6
502 * @arg @ref LL_SYSCFG_EXTI_LINE7
503 * @arg @ref LL_SYSCFG_EXTI_LINE8
504 * @arg @ref LL_SYSCFG_EXTI_LINE9
505 * @arg @ref LL_SYSCFG_EXTI_LINE10
506 * @arg @ref LL_SYSCFG_EXTI_LINE11
507 * @arg @ref LL_SYSCFG_EXTI_LINE12
508 * @arg @ref LL_SYSCFG_EXTI_LINE13
509 * @arg @ref LL_SYSCFG_EXTI_LINE14
510 * @arg @ref LL_SYSCFG_EXTI_LINE15
511 * @retval None
512 */
LL_SYSCFG_SetEXTISource(uint32_t Port,uint32_t Line)513 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
514 {
515 MODIFY_REG(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U), Port << POSITION_VAL((Line >> 16U)));
516 }
517
518 /**
519 * @brief Get the configured defined for specific EXTI Line
520 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
521 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
522 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
523 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
524 * @param Line This parameter can be one of the following values:
525 * @arg @ref LL_SYSCFG_EXTI_LINE0
526 * @arg @ref LL_SYSCFG_EXTI_LINE1
527 * @arg @ref LL_SYSCFG_EXTI_LINE2
528 * @arg @ref LL_SYSCFG_EXTI_LINE3
529 * @arg @ref LL_SYSCFG_EXTI_LINE4
530 * @arg @ref LL_SYSCFG_EXTI_LINE5
531 * @arg @ref LL_SYSCFG_EXTI_LINE6
532 * @arg @ref LL_SYSCFG_EXTI_LINE7
533 * @arg @ref LL_SYSCFG_EXTI_LINE8
534 * @arg @ref LL_SYSCFG_EXTI_LINE9
535 * @arg @ref LL_SYSCFG_EXTI_LINE10
536 * @arg @ref LL_SYSCFG_EXTI_LINE11
537 * @arg @ref LL_SYSCFG_EXTI_LINE12
538 * @arg @ref LL_SYSCFG_EXTI_LINE13
539 * @arg @ref LL_SYSCFG_EXTI_LINE14
540 * @arg @ref LL_SYSCFG_EXTI_LINE15
541 * @retval Returned value can be one of the following values:
542 * @arg @ref LL_SYSCFG_EXTI_PORTA
543 * @arg @ref LL_SYSCFG_EXTI_PORTB
544 * @arg @ref LL_SYSCFG_EXTI_PORTC
545 * @arg @ref LL_SYSCFG_EXTI_PORTD
546 * @arg @ref LL_SYSCFG_EXTI_PORTE
547 * @arg @ref LL_SYSCFG_EXTI_PORTF
548 * @arg @ref LL_SYSCFG_EXTI_PORTG
549 * @arg @ref LL_SYSCFG_EXTI_PORTH
550 * @arg @ref LL_SYSCFG_EXTI_PORTI
551 * @arg @ref LL_SYSCFG_EXTI_PORTJ
552 * @arg @ref LL_SYSCFG_EXTI_PORTK
553 * (*) value not defined in all devices
554 */
LL_SYSCFG_GetEXTISource(uint32_t Line)555 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
556 {
557 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U)) >> POSITION_VAL(Line >> 16U));
558 }
559
560 #if defined(SYSCFG_CBR_CLL)
561 /**
562 * @brief Set connections to TIM1/8/15/16/17 Break inputs
563 * SYSCFG_CBR CLL LL_SYSCFG_SetTIMBreakInputs\n
564 * SYSCFG_CBR PVDL LL_SYSCFG_SetTIMBreakInputs
565 * @param Break This parameter can be a combination of the following values:
566 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
567 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
568 * @retval None
569 */
LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)570 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
571 {
572 MODIFY_REG(SYSCFG->CBR, SYSCFG_CBR_CLL | SYSCFG_CBR_PVDL, Break);
573 }
574
575 /**
576 * @brief Get connections to TIM1/8/15/16/17 Break inputs
577 * SYSCFG_CBR CLL LL_SYSCFG_GetTIMBreakInputs\n
578 * SYSCFG_CBR PVDL LL_SYSCFG_GetTIMBreakInputs
579 * @retval Returned value can be can be a combination of the following values:
580 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
581 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
582 */
LL_SYSCFG_GetTIMBreakInputs(void)583 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
584 {
585 return (uint32_t)(READ_BIT(SYSCFG->CBR, SYSCFG_CBR_CLL | SYSCFG_CBR_PVDL));
586 }
587 #endif /* SYSCFG_CBR_CLL */
588
589 /**
590 * @}
591 */
592
593 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
594 * @{
595 */
596
597 /**
598 * @brief Return the device identifier
599 * @note For STM32F75xxx and STM32F74xxx devices, the device ID is 0x449
600 * @note For STM32F77xxx and STM32F76xxx devices, the device ID is 0x451
601 * @note For STM32F72xxx and STM32F73xxx devices, the device ID is 0x452
602 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
603 * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
604 */
LL_DBGMCU_GetDeviceID(void)605 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
606 {
607 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
608 }
609
610 /**
611 * @brief Return the device revision identifier
612 * @note This field indicates the revision of the device.
613 For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001
614 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
615 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
616 */
LL_DBGMCU_GetRevisionID(void)617 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
618 {
619 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
620 }
621
622 /**
623 * @brief Enable the Debug Module during SLEEP mode
624 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
625 * @retval None
626 */
LL_DBGMCU_EnableDBGSleepMode(void)627 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
628 {
629 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
630 }
631
632 /**
633 * @brief Disable the Debug Module during SLEEP mode
634 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
635 * @retval None
636 */
LL_DBGMCU_DisableDBGSleepMode(void)637 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
638 {
639 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
640 }
641
642 /**
643 * @brief Enable the Debug Module during STOP mode
644 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
645 * @retval None
646 */
LL_DBGMCU_EnableDBGStopMode(void)647 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
648 {
649 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
650 }
651
652 /**
653 * @brief Disable the Debug Module during STOP mode
654 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
655 * @retval None
656 */
LL_DBGMCU_DisableDBGStopMode(void)657 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
658 {
659 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
660 }
661
662 /**
663 * @brief Enable the Debug Module during STANDBY mode
664 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
665 * @retval None
666 */
LL_DBGMCU_EnableDBGStandbyMode(void)667 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
668 {
669 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
670 }
671
672 /**
673 * @brief Disable the Debug Module during STANDBY mode
674 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
675 * @retval None
676 */
LL_DBGMCU_DisableDBGStandbyMode(void)677 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
678 {
679 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
680 }
681
682 /**
683 * @brief Set Trace pin assignment control
684 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
685 * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
686 * @param PinAssignment This parameter can be one of the following values:
687 * @arg @ref LL_DBGMCU_TRACE_NONE
688 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
689 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
690 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
691 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
692 * @retval None
693 */
LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)694 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
695 {
696 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
697 }
698
699 /**
700 * @brief Get Trace pin assignment control
701 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
702 * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
703 * @retval Returned value can be one of the following values:
704 * @arg @ref LL_DBGMCU_TRACE_NONE
705 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
706 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
707 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
708 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
709 */
LL_DBGMCU_GetTracePinAssignment(void)710 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
711 {
712 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
713 }
714
715 /**
716 * @brief Freeze APB1 peripherals (group1 peripherals)
717 * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
718 * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
719 * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
720 * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
721 * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
722 * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
723 * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
724 * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
725 * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
726 * DBGMCU_APB1_FZ DBG_LPTIM1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
727 * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
728 * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
729 * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
730 * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
731 * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
732 * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
733 * DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
734 * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
735 * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
736 * DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
737 * @param Periphs This parameter can be a combination of the following values:
738 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
739 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
740 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
741 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
742 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
743 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
744 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
745 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
746 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
747 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
748 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
749 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
750 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
751 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
752 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
753 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
754 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
755 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP
756 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
757 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
758 *
759 * (*) value not defined in all devices.
760 * @retval None
761 */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)762 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
763 {
764 SET_BIT(DBGMCU->APB1FZ, Periphs);
765 }
766
767 /**
768 * @brief Unfreeze APB1 peripherals (group1 peripherals)
769 * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
770 * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
771 * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
772 * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
773 * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
774 * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
775 * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
776 * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
777 * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
778 * DBGMCU_APB1_FZ DBG_LPTIM1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
779 * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
780 * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
781 * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
782 * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
783 * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
784 * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
785 * DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
786 * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
787 * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
788 * DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
789 * @param Periphs This parameter can be a combination of the following values:
790 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
791 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
792 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
793 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
794 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
795 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
796 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
797 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
798 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
799 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
800 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
801 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
802 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
803 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
804 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
805 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
806 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
807 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP
808 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
809 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
810 * (*) value not defined in all devices.
811 * @retval None
812 */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)813 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
814 {
815 CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
816 }
817
818 /**
819 * @brief Freeze APB2 peripherals
820 * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
821 * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
822 * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
823 * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
824 * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
825 * @param Periphs This parameter can be a combination of the following values:
826 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
827 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
828 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP
829 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP
830 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP
831 *
832 * (*) value not defined in all devices.
833 * @retval None
834 */
LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)835 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
836 {
837 SET_BIT(DBGMCU->APB2FZ, Periphs);
838 }
839
840 /**
841 * @brief Unfreeze APB2 peripherals
842 * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
843 * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
844 * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
845 * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
846 * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
847 * @param Periphs This parameter can be a combination of the following values:
848 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
849 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
850 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP
851 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP
852 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP
853 *
854 * (*) value not defined in all devices.
855 * @retval None
856 */
LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)857 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
858 {
859 CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
860 }
861 /**
862 * @}
863 */
864
865 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
866 * @{
867 */
868
869 /**
870 * @brief Set FLASH Latency
871 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
872 * @param Latency This parameter can be one of the following values:
873 * @arg @ref LL_FLASH_LATENCY_0
874 * @arg @ref LL_FLASH_LATENCY_1
875 * @arg @ref LL_FLASH_LATENCY_2
876 * @arg @ref LL_FLASH_LATENCY_3
877 * @arg @ref LL_FLASH_LATENCY_4
878 * @arg @ref LL_FLASH_LATENCY_5
879 * @arg @ref LL_FLASH_LATENCY_6
880 * @arg @ref LL_FLASH_LATENCY_7
881 * @arg @ref LL_FLASH_LATENCY_8
882 * @arg @ref LL_FLASH_LATENCY_9
883 * @arg @ref LL_FLASH_LATENCY_10
884 * @arg @ref LL_FLASH_LATENCY_11
885 * @arg @ref LL_FLASH_LATENCY_12
886 * @arg @ref LL_FLASH_LATENCY_13
887 * @arg @ref LL_FLASH_LATENCY_14
888 * @arg @ref LL_FLASH_LATENCY_15
889 * @retval None
890 */
LL_FLASH_SetLatency(uint32_t Latency)891 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
892 {
893 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
894 }
895
896 /**
897 * @brief Get FLASH Latency
898 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
899 * @retval Returned value can be one of the following values:
900 * @arg @ref LL_FLASH_LATENCY_0
901 * @arg @ref LL_FLASH_LATENCY_1
902 * @arg @ref LL_FLASH_LATENCY_2
903 * @arg @ref LL_FLASH_LATENCY_3
904 * @arg @ref LL_FLASH_LATENCY_4
905 * @arg @ref LL_FLASH_LATENCY_5
906 * @arg @ref LL_FLASH_LATENCY_6
907 * @arg @ref LL_FLASH_LATENCY_7
908 * @arg @ref LL_FLASH_LATENCY_8
909 * @arg @ref LL_FLASH_LATENCY_9
910 * @arg @ref LL_FLASH_LATENCY_10
911 * @arg @ref LL_FLASH_LATENCY_11
912 * @arg @ref LL_FLASH_LATENCY_12
913 * @arg @ref LL_FLASH_LATENCY_13
914 * @arg @ref LL_FLASH_LATENCY_14
915 * @arg @ref LL_FLASH_LATENCY_15
916 */
LL_FLASH_GetLatency(void)917 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
918 {
919 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
920 }
921
922 /**
923 * @brief Enable Prefetch
924 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
925 * @retval None
926 */
LL_FLASH_EnablePrefetch(void)927 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
928 {
929 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
930 }
931
932 /**
933 * @brief Disable Prefetch
934 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
935 * @retval None
936 */
LL_FLASH_DisablePrefetch(void)937 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
938 {
939 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
940 }
941
942 /**
943 * @brief Check if Prefetch buffer is enabled
944 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
945 * @retval State of bit (1 or 0).
946 */
LL_FLASH_IsPrefetchEnabled(void)947 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
948 {
949 return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
950 }
951
952
953
954 /**
955 * @brief Enable ART Accelerator
956 * @rmtoll FLASH_ACR ARTEN LL_FLASH_EnableART
957 * @retval None
958 */
LL_FLASH_EnableART(void)959 __STATIC_INLINE void LL_FLASH_EnableART(void)
960 {
961 SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN);
962 }
963
964 /**
965 * @brief Disable ART Accelerator
966 * @rmtoll FLASH_ACR ARTEN LL_FLASH_DisableART
967 * @retval None
968 */
LL_FLASH_DisableART(void)969 __STATIC_INLINE void LL_FLASH_DisableART(void)
970 {
971 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTEN);
972 }
973
974 /**
975 * @brief Enable ART Reset
976 * @rmtoll FLASH_ACR ARTRST LL_FLASH_EnableARTReset
977 * @retval None
978 */
LL_FLASH_EnableARTReset(void)979 __STATIC_INLINE void LL_FLASH_EnableARTReset(void)
980 {
981 SET_BIT(FLASH->ACR, FLASH_ACR_ARTRST);
982 }
983
984 /**
985 * @brief Disable ART Reset
986 * @rmtoll FLASH_ACR ARTRST LL_FLASH_DisableARTReset
987 * @retval None
988 */
LL_FLASH_DisableARTReset(void)989 __STATIC_INLINE void LL_FLASH_DisableARTReset(void)
990 {
991 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTRST);
992 }
993
994 /**
995 * @}
996 */
997
998 /**
999 * @}
1000 */
1001
1002 /**
1003 * @}
1004 */
1005
1006 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
1007
1008 /**
1009 * @}
1010 */
1011
1012 #ifdef __cplusplus
1013 }
1014 #endif
1015
1016 #endif /* __STM32F7xx_LL_SYSTEM_H */
1017
1018
