1 /**
2   ******************************************************************************
3   * @file    stm32f7xx_ll_pwr.h
4   * @author  MCD Application Team
5   * @brief   Header file of PWR LL module.
6   ******************************************************************************
7   * @attention
8   *
9   * Copyright (c) 2017 STMicroelectronics.
10   * All rights reserved.
11   *
12   * This software is licensed under terms that can be found in the LICENSE file
13   * in the root directory of this software component.
14   * If no LICENSE file comes with this software, it is provided AS-IS.
15   *
16   ******************************************************************************
17   */
18 
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32F7xx_LL_PWR_H
21 #define __STM32F7xx_LL_PWR_H
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f7xx.h"
29 
30 /** @addtogroup STM32F7xx_LL_Driver
31   * @{
32   */
33 
34 #if defined(PWR)
35 
36 /** @defgroup PWR_LL PWR
37   * @{
38   */
39 
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /* Exported types ------------------------------------------------------------*/
45 /* Exported constants --------------------------------------------------------*/
46 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
47   * @{
48   */
49 
50 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
51   * @brief    Flags defines which can be used with LL_PWR_WriteReg function
52   * @{
53   */
54 #define LL_PWR_CR1_CSBF                    PWR_CR1_CSBF            /*!< Clear standby flag */
55 
56 #define LL_PWR_CR2_CWUF6                   PWR_CR2_CWUF6           /*!< Clear WKUP pin 6 */
57 #define LL_PWR_CR2_CWUF5                   PWR_CR2_CWUF5           /*!< Clear WKUP pin 5 */
58 #define LL_PWR_CR2_CWUF4                   PWR_CR2_CWUF4           /*!< Clear WKUP pin 4 */
59 #define LL_PWR_CR2_CWUF3                   PWR_CR2_CWUF3           /*!< Clear WKUP pin 3 */
60 #define LL_PWR_CR2_CWUF2                   PWR_CR2_CWUF2           /*!< Clear WKUP pin 2 */
61 #define LL_PWR_CR2_CWUF1                   PWR_CR2_CWUF1           /*!< Clear WKUP pin 1 */
62 /**
63   * @}
64   */
65 
66 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
67   * @brief    Flags defines which can be used with LL_PWR_ReadReg function
68   * @{
69   */
70 #define LL_PWR_CSR1_WUIF                   PWR_CSR1_WUIF           /*!< Wakeup flag */
71 #define LL_PWR_CSR1_SBF                    PWR_CSR1_SBF            /*!< Standby flag */
72 #define LL_PWR_CSR1_PVDO                   PWR_CSR1_PVDO           /*!< Power voltage detector output flag */
73 #define LL_PWR_CSR1_BRR                    PWR_CSR1_BRR            /*!< Backup Regulator ready flag */
74 #define LL_PWR_CSR1_VOSRDY                 PWR_CSR1_VOSRDY         /*!< Voltage scaling select flag */
75 #define LL_PWR_CSR1_ODRDY                  PWR_CSR1_ODRDY          /*!< Over-drive mode ready */
76 #define LL_PWR_CSR1_ODSWRDY                PWR_CSR1_ODSWRDY        /*!< Over-drive mode switching ready */
77 #define LL_PWR_CSR1_UDRDY                  PWR_CSR1_UDRDY          /*!< Under-drive ready flag */
78 
79 #define LL_PWR_CSR2_EWUP1                  PWR_CSR2_EWUP1          /*!< Enable WKUP pin 1 */
80 #define LL_PWR_CSR2_EWUP2                  PWR_CSR2_EWUP2          /*!< Enable WKUP pin 2 */
81 #define LL_PWR_CSR2_EWUP3                  PWR_CSR2_EWUP3          /*!< Enable WKUP pin 3 */
82 #define LL_PWR_CSR2_EWUP4                  PWR_CSR2_EWUP4          /*!< Enable WKUP pin 4 */
83 #define LL_PWR_CSR2_EWUP5                  PWR_CSR2_EWUP5          /*!< Enable WKUP pin 5 */
84 #define LL_PWR_CSR2_EWUP6                  PWR_CSR2_EWUP6          /*!< Enable WKUP pin 6 */
85 /**
86   * @}
87   */
88 
89 /** @defgroup PWR_LL_EC_MODE_PWR Mode Power
90   * @{
91   */
92 #define LL_PWR_MODE_STOP_MAINREGU                     0x00000000U                                    /*!< Enter Stop mode (with main Regulator ON) when the CPU enters deepsleep */
93 #define LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE          (PWR_CR1_MRUDS | PWR_CR1_FPDS)                 /*!< Enter Stop mode (with main Regulator in under-drive mode) when the CPU enters deepsleep */
94 #define LL_PWR_MODE_STOP_LPREGU                       PWR_CR1_LPDS                                   /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
95 #define LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE            (PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_FPDS)  /*!< Enter Stop mode (with low power Regulator in under-drive mode) when the CPU enters deepsleep */
96 #define LL_PWR_MODE_STANDBY                           PWR_CR1_PDDS                                   /*!< Enter Standby mode when the CPU enters deepsleep */
97 /**
98   * @}
99   */
100 
101 /** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage
102   * @{
103   */
104 #define LL_PWR_REGU_VOLTAGE_SCALE3         PWR_CR1_VOS_0
105 #define LL_PWR_REGU_VOLTAGE_SCALE2         PWR_CR1_VOS_1
106 #define LL_PWR_REGU_VOLTAGE_SCALE1         (PWR_CR1_VOS_0 | PWR_CR1_VOS_1)
107 /**
108   * @}
109   */
110 
111 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE  Regulator Mode In Deep Sleep Mode
112   * @{
113   */
114 #define LL_PWR_REGU_DSMODE_MAIN        0x00000000U                    /*!< Voltage Regulator in main mode during deepsleep mode */
115 #define LL_PWR_REGU_DSMODE_LOW_POWER   PWR_CR1_LPDS                   /*!< Voltage Regulator in low-power mode during deepsleep mode */
116 /**
117   * @}
118   */
119 
120 /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
121   * @{
122   */
123 #define LL_PWR_PVDLEVEL_0                  PWR_CR1_PLS_LEV0      /*!< Voltage threshold detected by PVD 2.0 V */
124 #define LL_PWR_PVDLEVEL_1                  PWR_CR1_PLS_LEV1      /*!< Voltage threshold detected by PVD 2.1 V */
125 #define LL_PWR_PVDLEVEL_2                  PWR_CR1_PLS_LEV2      /*!< Voltage threshold detected by PVD 2.3 V */
126 #define LL_PWR_PVDLEVEL_3                  PWR_CR1_PLS_LEV3      /*!< Voltage threshold detected by PVD 2.5 V */
127 #define LL_PWR_PVDLEVEL_4                  PWR_CR1_PLS_LEV4      /*!< Voltage threshold detected by PVD 2.6 V */
128 #define LL_PWR_PVDLEVEL_5                  PWR_CR1_PLS_LEV5      /*!< Voltage threshold detected by PVD 2.7 V */
129 #define LL_PWR_PVDLEVEL_6                  PWR_CR1_PLS_LEV6      /*!< Voltage threshold detected by PVD 2.8 V */
130 #define LL_PWR_PVDLEVEL_7                  PWR_CR1_PLS_LEV7      /*!< Voltage threshold detected by PVD 2.9 V */
131 /**
132   * @}
133   */
134 
135 /** @defgroup PWR_LL_EC_WAKEUP_PIN  Wakeup Pins
136   * @{
137   */
138 #define LL_PWR_WAKEUP_PIN1                 PWR_CSR2_EWUP1        /*!< WKUP pin 1 : PA0  */
139 #define LL_PWR_WAKEUP_PIN2                 PWR_CSR2_EWUP2        /*!< WKUP pin 2 : PA2  */
140 #define LL_PWR_WAKEUP_PIN3                 PWR_CSR2_EWUP3        /*!< WKUP pin 3 : PC1  */
141 #define LL_PWR_WAKEUP_PIN4                 PWR_CSR2_EWUP4        /*!< WKUP pin 4 : PC13 */
142 #define LL_PWR_WAKEUP_PIN5                 PWR_CSR2_EWUP5        /*!< WKUP pin 5 : PI8  */
143 #define LL_PWR_WAKEUP_PIN6                 PWR_CSR2_EWUP6        /*!< WKUP pin 6 : PI11 */
144 /**
145   * @}
146   */
147 
148 /**
149   * @}
150   */
151 /* Exported macro ------------------------------------------------------------*/
152 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
153   * @{
154   */
155 
156 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
157   * @{
158   */
159 
160 /**
161   * @brief  Write a value in PWR register
162   * @param  __REG__ Register to be written
163   * @param  __VALUE__ Value to be written in the register
164   * @retval None
165   */
166 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
167 
168 /**
169   * @brief  Read a value in PWR register
170   * @param  __REG__ Register to be read
171   * @retval Register value
172   */
173 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
174 /**
175   * @}
176   */
177 
178 /**
179   * @}
180   */
181 /* Exported functions --------------------------------------------------------*/
182 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
183   * @{
184   */
185 
186 /** @defgroup PWR_LL_EF_Configuration Configuration
187   * @{
188   */
189 
190 /**
191   * @brief  Enable Under Drive Mode
192   * @rmtoll CR1    UDEN       LL_PWR_EnableUnderDriveMode
193   * @note  This mode is enabled only with STOP low power mode.
194   *        In this mode, the 1.2V domain is preserved in reduced leakage mode. This
195   *        mode is only available when the main Regulator or the low power Regulator
196   *        is in low voltage mode.
197   * @note  If the Under-drive mode was enabled, it is automatically disabled after
198   *        exiting Stop mode.
199   *        When the voltage Regulator operates in Under-drive mode, an additional
200   *        startup delay is induced when waking up from Stop mode.
201   * @retval None
202   */
LL_PWR_EnableUnderDriveMode(void)203 __STATIC_INLINE void LL_PWR_EnableUnderDriveMode(void)
204 {
205   SET_BIT(PWR->CR1, PWR_CR1_UDEN);
206 }
207 
208 /**
209   * @brief  Disable Under Drive Mode
210   * @rmtoll CR1    UDEN       LL_PWR_DisableUnderDriveMode
211   * @retval None
212   */
LL_PWR_DisableUnderDriveMode(void)213 __STATIC_INLINE void LL_PWR_DisableUnderDriveMode(void)
214 {
215   CLEAR_BIT(PWR->CR1, PWR_CR1_UDEN);
216 }
217 
218 /**
219   * @brief  Check if Under Drive Mode is enabled
220   * @rmtoll CR1    UDEN       LL_PWR_IsEnabledUnderDriveMode
221   * @retval State of bit (1 or 0).
222   */
LL_PWR_IsEnabledUnderDriveMode(void)223 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUnderDriveMode(void)
224 {
225   return (READ_BIT(PWR->CR1, PWR_CR1_UDEN) == (PWR_CR1_UDEN));
226 }
227 
228 /**
229   * @brief  Enable Over drive switching
230   * @rmtoll CR1    ODSWEN       LL_PWR_EnableOverDriveSwitching
231   * @retval None
232   */
LL_PWR_EnableOverDriveSwitching(void)233 __STATIC_INLINE void LL_PWR_EnableOverDriveSwitching(void)
234 {
235   SET_BIT(PWR->CR1, PWR_CR1_ODSWEN);
236 }
237 
238 /**
239   * @brief  Disable Over drive switching
240   * @rmtoll CR1    ODSWEN       LL_PWR_DisableOverDriveSwitching
241   * @retval None
242   */
LL_PWR_DisableOverDriveSwitching(void)243 __STATIC_INLINE void LL_PWR_DisableOverDriveSwitching(void)
244 {
245   CLEAR_BIT(PWR->CR1, PWR_CR1_ODSWEN);
246 }
247 
248 /**
249   * @brief  Check if Over drive switching is enabled
250   * @rmtoll CR1    ODSWEN       LL_PWR_IsEnabledOverDriveSwitching
251   * @retval State of bit (1 or 0).
252   */
LL_PWR_IsEnabledOverDriveSwitching(void)253 __STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveSwitching(void)
254 {
255   return (READ_BIT(PWR->CR1, PWR_CR1_ODSWEN) == (PWR_CR1_ODSWEN));
256 }
257 
258 /**
259   * @brief  Enable Over drive Mode
260   * @rmtoll CR1    ODEN       LL_PWR_EnableOverDriveMode
261   * @retval None
262   */
LL_PWR_EnableOverDriveMode(void)263 __STATIC_INLINE void LL_PWR_EnableOverDriveMode(void)
264 {
265   SET_BIT(PWR->CR1, PWR_CR1_ODEN);
266 }
267 
268 /**
269   * @brief  Disable Over drive Mode
270   * @rmtoll CR1    ODEN       LL_PWR_DisableOverDriveMode
271   * @retval None
272   */
LL_PWR_DisableOverDriveMode(void)273 __STATIC_INLINE void LL_PWR_DisableOverDriveMode(void)
274 {
275   CLEAR_BIT(PWR->CR1, PWR_CR1_ODEN);
276 }
277 
278 /**
279   * @brief  Check if Over drive switching is enabled
280   * @rmtoll CR1    ODEN       LL_PWR_IsEnabledOverDriveMode
281   * @retval State of bit (1 or 0).
282   */
LL_PWR_IsEnabledOverDriveMode(void)283 __STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveMode(void)
284 {
285   return (READ_BIT(PWR->CR1, PWR_CR1_ODEN) == (PWR_CR1_ODEN));
286 }
287 
288 /**
289   * @brief  Set the main internal Regulator output voltage
290   * @rmtoll CR1    VOS       LL_PWR_SetRegulVoltageScaling
291   * @param  VoltageScaling This parameter can be one of the following values:
292   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
293   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
294   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
295   * @retval None
296   */
LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)297 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
298 {
299   MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
300 }
301 
302 /**
303   * @brief  Get the main internal Regulator output voltage
304   * @rmtoll CR1    VOS       LL_PWR_GetRegulVoltageScaling
305   * @retval Returned value can be one of the following values:
306   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
307   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
308   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
309   */
LL_PWR_GetRegulVoltageScaling(void)310 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
311 {
312   return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS));
313 }
314 
315 /**
316   * @brief  Enable Main Regulator in deepsleep under-drive Mode
317   * @rmtoll CR1    MRUDS       LL_PWR_EnableMainRegulatorDeepSleepUDMode
318   * @retval None
319   */
LL_PWR_EnableMainRegulatorDeepSleepUDMode(void)320 __STATIC_INLINE void LL_PWR_EnableMainRegulatorDeepSleepUDMode(void)
321 {
322   SET_BIT(PWR->CR1, PWR_CR1_MRUDS);
323 }
324 
325 /**
326   * @brief  Disable Main Regulator in deepsleep under-drive Mode
327   * @rmtoll CR1    MRUDS       LL_PWR_DisableMainRegulatorDeepSleepUDMode
328   * @retval None
329   */
LL_PWR_DisableMainRegulatorDeepSleepUDMode(void)330 __STATIC_INLINE void LL_PWR_DisableMainRegulatorDeepSleepUDMode(void)
331 {
332   CLEAR_BIT(PWR->CR1, PWR_CR1_MRUDS);
333 }
334 
335 /**
336   * @brief  Check if Main Regulator in deepsleep under-drive Mode is enabled
337   * @rmtoll CR1    MRUDS       LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode
338   * @retval State of bit (1 or 0).
339   */
LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode(void)340 __STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode(void)
341 {
342   return (READ_BIT(PWR->CR1, PWR_CR1_MRUDS) == (PWR_CR1_MRUDS));
343 }
344 
345 /**
346   * @brief  Enable Low Power Regulator in deepsleep under-drive Mode
347   * @rmtoll CR1    LPUDS       LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode
348   * @retval None
349   */
LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode(void)350 __STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode(void)
351 {
352   SET_BIT(PWR->CR1, PWR_CR1_LPUDS);
353 }
354 
355 /**
356   * @brief  Disable Low Power Regulator in deepsleep under-drive Mode
357   * @rmtoll CR1    LPUDS       LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode
358   * @retval None
359   */
LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode(void)360 __STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode(void)
361 {
362   CLEAR_BIT(PWR->CR1, PWR_CR1_LPUDS);
363 }
364 
365 /**
366   * @brief  Check if Low Power Regulator in deepsleep under-drive Mode is enabled
367   * @rmtoll CR1    LPUDS       LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode
368   * @retval State of bit (1 or 0).
369   */
LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode(void)370 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode(void)
371 {
372   return (READ_BIT(PWR->CR1, PWR_CR1_LPUDS) == (PWR_CR1_LPUDS));
373 }
374 
375 /**
376   * @brief  Enable the Flash Power Down in Stop Mode
377   * @rmtoll CR1    FPDS       LL_PWR_EnableFlashPowerDown
378   * @retval None
379   */
LL_PWR_EnableFlashPowerDown(void)380 __STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
381 {
382   SET_BIT(PWR->CR1, PWR_CR1_FPDS);
383 }
384 
385 /**
386   * @brief  Disable the Flash Power Down in Stop Mode
387   * @rmtoll CR1    FPDS       LL_PWR_DisableFlashPowerDown
388   * @retval None
389   */
LL_PWR_DisableFlashPowerDown(void)390 __STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
391 {
392   CLEAR_BIT(PWR->CR1, PWR_CR1_FPDS);
393 }
394 
395 /**
396   * @brief  Check if the Flash Power Down in Stop Mode is enabled
397   * @rmtoll CR1    FPDS       LL_PWR_IsEnabledFlashPowerDown
398   * @retval State of bit (1 or 0).
399   */
LL_PWR_IsEnabledFlashPowerDown(void)400 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
401 {
402   return (READ_BIT(PWR->CR1, PWR_CR1_FPDS) == (PWR_CR1_FPDS));
403 }
404 
405 /**
406   * @brief  Enable access to the backup domain
407   * @rmtoll CR1    DBP       LL_PWR_EnableBkUpAccess
408   * @retval None
409   */
LL_PWR_EnableBkUpAccess(void)410 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
411 {
412   SET_BIT(PWR->CR1, PWR_CR1_DBP);
413 }
414 
415 /**
416   * @brief  Disable access to the backup domain
417   * @rmtoll CR1    DBP       LL_PWR_DisableBkUpAccess
418   * @retval None
419   */
LL_PWR_DisableBkUpAccess(void)420 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
421 {
422   CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
423 }
424 
425 /**
426   * @brief  Check if the backup domain is enabled
427   * @rmtoll CR1    DBP       LL_PWR_IsEnabledBkUpAccess
428   * @retval State of bit (1 or 0).
429   */
LL_PWR_IsEnabledBkUpAccess(void)430 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
431 {
432   return (READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP));
433 }
434 
435 /**
436   * @brief  Enable Backup Regulator
437   * @rmtoll CSR1    BRE       LL_PWR_EnableBkUpRegulator
438   * @note When set, the Backup Regulator (used to maintain backup SRAM content in Standby and
439   *       VBAT modes) is enabled. If BRE is reset, the backup Regulator is switched off. The backup
440   *       SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set,
441   *       the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that
442   *       the data written into the RAM will be maintained in the Standby and VBAT modes.
443   * @retval None
444   */
LL_PWR_EnableBkUpRegulator(void)445 __STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
446 {
447   SET_BIT(PWR->CSR1, PWR_CSR1_BRE);
448 }
449 
450 /**
451   * @brief  Disable Backup Regulator
452   * @rmtoll CSR1    BRE       LL_PWR_DisableBkUpRegulator
453   * @retval None
454   */
LL_PWR_DisableBkUpRegulator(void)455 __STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
456 {
457   CLEAR_BIT(PWR->CSR1, PWR_CSR1_BRE);
458 }
459 
460 /**
461   * @brief  Check if the backup Regulator is enabled
462   * @rmtoll CSR1    BRE      LL_PWR_IsEnabledBkUpRegulator
463   * @retval State of bit (1 or 0).
464   */
LL_PWR_IsEnabledBkUpRegulator(void)465 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
466 {
467   return (READ_BIT(PWR->CSR1, PWR_CSR1_BRE) == (PWR_CSR1_BRE));
468 }
469 
470 /**
471   * @brief  Set voltage Regulator mode during deep sleep mode
472   * @rmtoll CR1    LPDS         LL_PWR_SetRegulModeDS
473   * @param  RegulMode This parameter can be one of the following values:
474   *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
475   *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
476   * @retval None
477   */
LL_PWR_SetRegulModeDS(uint32_t RegulMode)478 __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
479 {
480   MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, RegulMode);
481 }
482 
483 /**
484   * @brief  Get voltage Regulator mode during deep sleep mode
485   * @rmtoll CR1    LPDS         LL_PWR_GetRegulModeDS
486   * @retval Returned value can be one of the following values:
487   *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
488   *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
489   */
LL_PWR_GetRegulModeDS(void)490 __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
491 {
492   return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPDS));
493 }
494 
495 /**
496   * @brief  Set Power Down mode when CPU enters deepsleep
497   * @rmtoll CR1    PDDS         LL_PWR_SetPowerMode\n
498   *         CR1    LPDS         LL_PWR_SetPowerMode\n
499   *         CR1    FPDS         LL_PWR_SetPowerMode\n
500   *         CR1    LPUDS        LL_PWR_SetPowerMode\n
501   *         CR1    MRUDS        LL_PWR_SetPowerMode
502   * @param  PDMode This parameter can be one of the following values:
503   *         @arg @ref LL_PWR_MODE_STOP_MAINREGU
504   *         @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE
505   *         @arg @ref LL_PWR_MODE_STOP_LPREGU
506   *         @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE
507   *         @arg @ref LL_PWR_MODE_STANDBY
508   * @retval None
509   */
LL_PWR_SetPowerMode(uint32_t PDMode)510 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
511 {
512   MODIFY_REG(PWR->CR1, (PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_FPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS), PDMode);
513 }
514 
515 /**
516   * @brief  Get Power Down mode when CPU enters deepsleep
517   * @rmtoll CR1    PDDS         LL_PWR_GetPowerMode\n
518   *         CR1    LPDS         LL_PWR_GetPowerMode\n
519   *         CR1    FPDS         LL_PWR_GetPowerMode\n
520   *         CR1    LPUDS        LL_PWR_GetPowerMode\n
521   *         CR1    MRUDS        LL_PWR_GetPowerMode
522   * @retval Returned value can be one of the following values:
523   *         @arg @ref LL_PWR_MODE_STOP_MAINREGU
524   *         @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE
525   *         @arg @ref LL_PWR_MODE_STOP_LPREGU
526   *         @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE
527   *         @arg @ref LL_PWR_MODE_STANDBY
528   */
LL_PWR_GetPowerMode(void)529 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
530 {
531   return (uint32_t)(READ_BIT(PWR->CR1, (PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_FPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS)));
532 }
533 
534 /**
535   * @brief  Configure the voltage threshold detected by the Power Voltage Detector
536   * @rmtoll CR1    PLS       LL_PWR_SetPVDLevel
537   * @param  PVDLevel This parameter can be one of the following values:
538   *         @arg @ref LL_PWR_PVDLEVEL_0
539   *         @arg @ref LL_PWR_PVDLEVEL_1
540   *         @arg @ref LL_PWR_PVDLEVEL_2
541   *         @arg @ref LL_PWR_PVDLEVEL_3
542   *         @arg @ref LL_PWR_PVDLEVEL_4
543   *         @arg @ref LL_PWR_PVDLEVEL_5
544   *         @arg @ref LL_PWR_PVDLEVEL_6
545   *         @arg @ref LL_PWR_PVDLEVEL_7
546   * @retval None
547   */
LL_PWR_SetPVDLevel(uint32_t PVDLevel)548 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
549 {
550   MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel);
551 }
552 
553 /**
554   * @brief  Get the voltage threshold detection
555   * @rmtoll CR1    PLS       LL_PWR_GetPVDLevel
556   * @retval Returned value can be one of the following values:
557   *         @arg @ref LL_PWR_PVDLEVEL_0
558   *         @arg @ref LL_PWR_PVDLEVEL_1
559   *         @arg @ref LL_PWR_PVDLEVEL_2
560   *         @arg @ref LL_PWR_PVDLEVEL_3
561   *         @arg @ref LL_PWR_PVDLEVEL_4
562   *         @arg @ref LL_PWR_PVDLEVEL_5
563   *         @arg @ref LL_PWR_PVDLEVEL_6
564   *         @arg @ref LL_PWR_PVDLEVEL_7
565   */
LL_PWR_GetPVDLevel(void)566 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
567 {
568   return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_PLS));
569 }
570 
571 /**
572   * @brief  Enable Power Voltage Detector
573   * @rmtoll CR1    PVDE       LL_PWR_EnablePVD
574   * @retval None
575   */
LL_PWR_EnablePVD(void)576 __STATIC_INLINE void LL_PWR_EnablePVD(void)
577 {
578   SET_BIT(PWR->CR1, PWR_CR1_PVDE);
579 }
580 
581 /**
582   * @brief  Disable Power Voltage Detector
583   * @rmtoll CR1    PVDE       LL_PWR_DisablePVD
584   * @retval None
585   */
LL_PWR_DisablePVD(void)586 __STATIC_INLINE void LL_PWR_DisablePVD(void)
587 {
588   CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE);
589 }
590 
591 /**
592   * @brief  Check if Power Voltage Detector is enabled
593   * @rmtoll CR1    PVDE       LL_PWR_IsEnabledPVD
594   * @retval State of bit (1 or 0).
595   */
LL_PWR_IsEnabledPVD(void)596 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
597 {
598   return (READ_BIT(PWR->CR1, PWR_CR1_PVDE) == (PWR_CR1_PVDE));
599 }
600 
601 /**
602   * @brief  Enable the WakeUp PINx functionality
603   * @rmtoll CSR2   EWUP1       LL_PWR_EnableWakeUpPin\n
604   *         CSR2   EWUP2       LL_PWR_EnableWakeUpPin\n
605   *         CSR2   EWUP3       LL_PWR_EnableWakeUpPin\n
606   *         CSR2   EWUP4       LL_PWR_EnableWakeUpPin\n
607   *         CSR2   EWUP5       LL_PWR_EnableWakeUpPin\n
608   *         CSR2   EWUP6       LL_PWR_EnableWakeUpPin
609   * @param  WakeUpPin This parameter can be one of the following values:
610   *         @arg @ref LL_PWR_WAKEUP_PIN1
611   *         @arg @ref LL_PWR_WAKEUP_PIN2
612   *         @arg @ref LL_PWR_WAKEUP_PIN3
613   *         @arg @ref LL_PWR_WAKEUP_PIN4
614   *         @arg @ref LL_PWR_WAKEUP_PIN5
615   *         @arg @ref LL_PWR_WAKEUP_PIN6
616   * @retval None
617   */
LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)618 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
619 {
620   SET_BIT(PWR->CSR2, WakeUpPin);
621 }
622 
623 /**
624   * @brief  Disable the WakeUp PINx functionality
625   * @rmtoll CSR2   EWUP1       LL_PWR_DisableWakeUpPin\n
626   *         CSR2   EWUP2       LL_PWR_DisableWakeUpPin\n
627   *         CSR2   EWUP3       LL_PWR_DisableWakeUpPin\n
628   *         CSR2   EWUP4       LL_PWR_DisableWakeUpPin\n
629   *         CSR2   EWUP5       LL_PWR_DisableWakeUpPin\n
630   *         CSR2   EWUP6       LL_PWR_DisableWakeUpPin
631   * @param  WakeUpPin This parameter can be one of the following values:
632   *         @arg @ref LL_PWR_WAKEUP_PIN1
633   *         @arg @ref LL_PWR_WAKEUP_PIN2
634   *         @arg @ref LL_PWR_WAKEUP_PIN3
635   *         @arg @ref LL_PWR_WAKEUP_PIN4
636   *         @arg @ref LL_PWR_WAKEUP_PIN5
637   *         @arg @ref LL_PWR_WAKEUP_PIN6
638   * @retval None
639   */
LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)640 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
641 {
642   CLEAR_BIT(PWR->CSR2, WakeUpPin);
643 }
644 
645 /**
646   * @brief  Check if the WakeUp PINx functionality is enabled
647   * @rmtoll CSR2   EWUP1       LL_PWR_IsEnabledWakeUpPin\n
648   *         CSR2   EWUP2       LL_PWR_IsEnabledWakeUpPin\n
649   *         CSR2   EWUP3       LL_PWR_IsEnabledWakeUpPin\n
650   *         CSR2   EWUP4       LL_PWR_IsEnabledWakeUpPin\n
651   *         CSR2   EWUP5       LL_PWR_IsEnabledWakeUpPin\n
652   *         CSR2   EWUP6       LL_PWR_IsEnabledWakeUpPin
653   * @param  WakeUpPin This parameter can be one of the following values:
654   *         @arg @ref LL_PWR_WAKEUP_PIN1
655   *         @arg @ref LL_PWR_WAKEUP_PIN2
656   *         @arg @ref LL_PWR_WAKEUP_PIN3
657   *         @arg @ref LL_PWR_WAKEUP_PIN4
658   *         @arg @ref LL_PWR_WAKEUP_PIN5
659   *         @arg @ref LL_PWR_WAKEUP_PIN6
660   * @retval State of bit (1 or 0).
661   */
LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)662 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
663 {
664   return (READ_BIT(PWR->CSR2, WakeUpPin) == (WakeUpPin));
665 }
666 
667 /**
668   * @brief  Set the Wake-Up pin polarity low for the event detection
669   * @rmtoll CR2   WUPP1       LL_PWR_SetWakeUpPinPolarityLow\n
670   *         CR2   WUPP2       LL_PWR_SetWakeUpPinPolarityLow\n
671   *         CR2   WUPP3       LL_PWR_SetWakeUpPinPolarityLow\n
672   *         CR2   WUPP4       LL_PWR_SetWakeUpPinPolarityLow\n
673   *         CR2   WUPP5       LL_PWR_SetWakeUpPinPolarityLow\n
674   *         CR2   WUPP6       LL_PWR_SetWakeUpPinPolarityLow
675   * @param  WakeUpPin This parameter can be one of the following values:
676   *         @arg @ref LL_PWR_WAKEUP_PIN1
677   *         @arg @ref LL_PWR_WAKEUP_PIN2
678   *         @arg @ref LL_PWR_WAKEUP_PIN3
679   *         @arg @ref LL_PWR_WAKEUP_PIN4
680   *         @arg @ref LL_PWR_WAKEUP_PIN5
681   *         @arg @ref LL_PWR_WAKEUP_PIN6
682   * @retval None
683   */
LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)684 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
685 {
686   SET_BIT(PWR->CR2, WakeUpPin);
687 }
688 
689 /**
690   * @brief  Set the Wake-Up pin polarity high for the event detection
691   * @rmtoll CR2   WUPP1       LL_PWR_SetWakeUpPinPolarityHigh\n
692   *         CR2   WUPP2       LL_PWR_SetWakeUpPinPolarityHigh\n
693   *         CR2   WUPP3       LL_PWR_SetWakeUpPinPolarityHigh\n
694   *         CR2   WUPP4       LL_PWR_SetWakeUpPinPolarityHigh\n
695   *         CR2   WUPP5       LL_PWR_SetWakeUpPinPolarityHigh\n
696   *         CR2   WUPP6       LL_PWR_SetWakeUpPinPolarityHigh
697   * @param  WakeUpPin This parameter can be one of the following values:
698   *         @arg @ref LL_PWR_WAKEUP_PIN1
699   *         @arg @ref LL_PWR_WAKEUP_PIN2
700   *         @arg @ref LL_PWR_WAKEUP_PIN3
701   *         @arg @ref LL_PWR_WAKEUP_PIN4
702   *         @arg @ref LL_PWR_WAKEUP_PIN5
703   *         @arg @ref LL_PWR_WAKEUP_PIN6
704   * @retval None
705   */
LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)706 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
707 {
708   CLEAR_BIT(PWR->CR2, WakeUpPin);
709 }
710 
711 /**
712   * @brief  Get the Wake-Up pin polarity for the event detection
713   * @rmtoll CR2   WUPP1       LL_PWR_IsWakeUpPinPolarityLow\n
714   *         CR2   WUPP2       LL_PWR_IsWakeUpPinPolarityLow\n
715   *         CR2   WUPP3       LL_PWR_IsWakeUpPinPolarityLow\n
716   *         CR2   WUPP4       LL_PWR_IsWakeUpPinPolarityLow\n
717   *         CR2   WUPP5       LL_PWR_IsWakeUpPinPolarityLow\n
718   *         CR2   WUPP6       LL_PWR_IsWakeUpPinPolarityLow
719   * @param  WakeUpPin This parameter can be one of the following values:
720   *         @arg @ref LL_PWR_WAKEUP_PIN1
721   *         @arg @ref LL_PWR_WAKEUP_PIN2
722   *         @arg @ref LL_PWR_WAKEUP_PIN3
723   *         @arg @ref LL_PWR_WAKEUP_PIN4
724   *         @arg @ref LL_PWR_WAKEUP_PIN5
725   *         @arg @ref LL_PWR_WAKEUP_PIN6
726   * @retval State of bit (1 or 0).
727   */
LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)728 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
729 {
730   return (READ_BIT(PWR->CR2, WakeUpPin) == (WakeUpPin));
731 }
732 
733 /**
734   * @brief  Enable Internal WakeUp
735   * @rmtoll CSR1    EIWUP       LL_PWR_EnableInternalWakeUp
736   * @note This API must be used when RTC events (Alarm A or Alarm B, RTC Tamper, RTC TimeStamp
737   *  or RTC Wakeup time) are used to wake up the system from Standby mode.
738   * @retval None
739   */
LL_PWR_EnableInternalWakeUp(void)740 __STATIC_INLINE void LL_PWR_EnableInternalWakeUp(void)
741 {
742   SET_BIT(PWR->CSR1, PWR_CSR1_EIWUP);
743 }
744 
745 /**
746   * @brief  Disable Internal WakeUp
747   * @rmtoll CSR1    EIWUP       LL_PWR_DisableInternalWakeUp
748   * @retval None
749   */
LL_PWR_DisableInternalWakeUp(void)750 __STATIC_INLINE void LL_PWR_DisableInternalWakeUp(void)
751 {
752   CLEAR_BIT(PWR->CSR1, PWR_CSR1_EIWUP);
753 }
754 
755 /**
756   * @brief  Check if the Internal WakeUp functionality is enabled
757   * @rmtoll CSR1   EIWUP       LL_PWR_IsEnabledInternalWakeUp
758   * @retval State of bit (1 or 0).
759   */
LL_PWR_IsEnabledInternalWakeUp(void)760 __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternalWakeUp(void)
761 {
762   return (READ_BIT(PWR->CSR1, PWR_CSR1_EIWUP) == (PWR_CSR1_EIWUP));
763 }
764 
765 /**
766   * @}
767   */
768 
769 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
770   * @{
771   */
772 
773 /**
774   * @brief  Get Wake-up Flag 6
775   * @rmtoll CSR2          WUPF6          LL_PWR_IsActiveFlag_WU6
776   * @retval State of bit (1 or 0).
777   */
LL_PWR_IsActiveFlag_WU6(void)778 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
779 {
780   return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF6) == (PWR_CSR2_WUPF6));
781 }
782 
783 /**
784   * @brief  Get Wake-up Flag 5
785   * @rmtoll CSR2          WUPF5          LL_PWR_IsActiveFlag_WU5
786   * @retval State of bit (1 or 0).
787   */
LL_PWR_IsActiveFlag_WU5(void)788 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
789 {
790   return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF5) == (PWR_CSR2_WUPF5));
791 }
792 
793 /**
794   * @brief  Get Wake-up Flag 4
795   * @rmtoll CSR2          WUPF4          LL_PWR_IsActiveFlag_WU4
796   * @retval State of bit (1 or 0).
797   */
LL_PWR_IsActiveFlag_WU4(void)798 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
799 {
800   return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF4) == (PWR_CSR2_WUPF4));
801 }
802 
803 /**
804   * @brief  Get Wake-up Flag 3
805   * @rmtoll CSR2          WUPF3          LL_PWR_IsActiveFlag_WU3
806   * @retval State of bit (1 or 0).
807   */
LL_PWR_IsActiveFlag_WU3(void)808 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
809 {
810   return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF3) == (PWR_CSR2_WUPF3));
811 }
812 
813 /**
814   * @brief  Get Wake-up Flag 2
815   * @rmtoll CSR2          WUPF2          LL_PWR_IsActiveFlag_WU2
816   * @retval State of bit (1 or 0).
817   */
LL_PWR_IsActiveFlag_WU2(void)818 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
819 {
820   return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF2) == (PWR_CSR2_WUPF2));
821 }
822 
823 /**
824   * @brief  Get Wake-up Flag 1
825   * @rmtoll CSR2          WUPF1          LL_PWR_IsActiveFlag_WU1
826   * @retval State of bit (1 or 0).
827   */
LL_PWR_IsActiveFlag_WU1(void)828 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
829 {
830   return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF1) == (PWR_CSR2_WUPF1));
831 }
832 
833 /**
834   * @brief  Get Standby Flag
835   * @rmtoll CSR1   SBF       LL_PWR_IsActiveFlag_SB
836   * @retval State of bit (1 or 0).
837   */
LL_PWR_IsActiveFlag_SB(void)838 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
839 {
840   return (READ_BIT(PWR->CSR1, PWR_CSR1_SBF) == (PWR_CSR1_SBF));
841 }
842 
843 /**
844   * @brief  Indicate whether VDD voltage is below the selected PVD threshold
845   * @rmtoll CSR1   PVDO       LL_PWR_IsActiveFlag_PVDO
846   * @retval State of bit (1 or 0).
847   */
LL_PWR_IsActiveFlag_PVDO(void)848 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
849 {
850   return (READ_BIT(PWR->CSR1, PWR_CSR1_PVDO) == (PWR_CSR1_PVDO));
851 }
852 
853 /**
854   * @brief  Get Backup Regulator ready Flag
855   * @rmtoll CSR1   BRR       LL_PWR_IsActiveFlag_BRR
856   * @retval State of bit (1 or 0).
857   */
LL_PWR_IsActiveFlag_BRR(void)858 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
859 {
860   return (READ_BIT(PWR->CSR1, PWR_CSR1_BRR) == (PWR_CSR1_BRR));
861 }
862 
863 /**
864   * @brief  Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
865   * @rmtoll CSR1   VOSRDY       LL_PWR_IsActiveFlag_VOS
866   * @retval State of bit (1 or 0).
867   */
LL_PWR_IsActiveFlag_VOS(void)868 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
869 {
870   return (READ_BIT(PWR->CSR1, PWR_CSR1_VOSRDY) == (PWR_CSR1_VOSRDY));
871 }
872 
873 /**
874   * @brief  Indicate whether the Over-Drive mode is ready or not
875   * @rmtoll CSR1   ODRDY       LL_PWR_IsActiveFlag_OD
876   * @retval State of bit (1 or 0).
877   */
LL_PWR_IsActiveFlag_OD(void)878 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_OD(void)
879 {
880   return (READ_BIT(PWR->CSR1, PWR_CSR1_ODRDY) == (PWR_CSR1_ODRDY));
881 }
882 
883 /**
884   * @brief  Indicate whether the Over-Drive mode switching is ready or not
885   * @rmtoll CSR1   ODSWRDY       LL_PWR_IsActiveFlag_ODSW
886   * @retval State of bit (1 or 0).
887   */
LL_PWR_IsActiveFlag_ODSW(void)888 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ODSW(void)
889 {
890   return (READ_BIT(PWR->CSR1, PWR_CSR1_ODSWRDY) == (PWR_CSR1_ODSWRDY));
891 }
892 
893 /**
894   * @brief  Indicate whether the Under-Drive mode is ready or not
895   * @rmtoll CSR1   UDRDY       LL_PWR_IsActiveFlag_UD
896   * @retval State of bit (1 or 0).
897   */
LL_PWR_IsActiveFlag_UD(void)898 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_UD(void)
899 {
900   return (READ_BIT(PWR->CSR1, PWR_CSR1_UDRDY) == (PWR_CSR1_UDRDY));
901 }
902 
903 /**
904   * @brief  Clear Standby Flag
905   * @rmtoll CR1   CSBF       LL_PWR_ClearFlag_SB
906   * @retval None
907   */
LL_PWR_ClearFlag_SB(void)908 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
909 {
910   SET_BIT(PWR->CR1, PWR_CR1_CSBF);
911 }
912 
913 /**
914   * @brief  Clear Wake-up Flag 6
915   * @rmtoll CR2          CWUF6         LL_PWR_ClearFlag_WU6
916   * @retval None
917   */
LL_PWR_ClearFlag_WU6(void)918 __STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
919 {
920   WRITE_REG(PWR->CR2, PWR_CR2_CWUPF6);
921 }
922 
923 /**
924   * @brief  Clear Wake-up Flag 5
925   * @rmtoll CR2          CWUF5         LL_PWR_ClearFlag_WU5
926   * @retval None
927   */
LL_PWR_ClearFlag_WU5(void)928 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
929 {
930   WRITE_REG(PWR->CR2, PWR_CR2_CWUPF5);
931 }
932 
933 /**
934   * @brief  Clear Wake-up Flag 4
935   * @rmtoll CR2          CWUF4         LL_PWR_ClearFlag_WU4
936   * @retval None
937   */
LL_PWR_ClearFlag_WU4(void)938 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
939 {
940   WRITE_REG(PWR->CR2, PWR_CR2_CWUPF4);
941 }
942 
943 /**
944   * @brief  Clear Wake-up Flag 3
945   * @rmtoll CR2          CWUF3         LL_PWR_ClearFlag_WU3
946   * @retval None
947   */
LL_PWR_ClearFlag_WU3(void)948 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
949 {
950   WRITE_REG(PWR->CR2, PWR_CR2_CWUPF3);
951 }
952 
953 /**
954   * @brief  Clear Wake-up Flag 2
955   * @rmtoll CR2          CWUF2         LL_PWR_ClearFlag_WU2
956   * @retval None
957   */
LL_PWR_ClearFlag_WU2(void)958 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
959 {
960   WRITE_REG(PWR->CR2, PWR_CR2_CWUPF2);
961 }
962 
963 /**
964   * @brief  Clear Wake-up Flag 1
965   * @rmtoll CR2          CWUF1         LL_PWR_ClearFlag_WU1
966   * @retval None
967   */
LL_PWR_ClearFlag_WU1(void)968 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
969 {
970   WRITE_REG(PWR->CR2, PWR_CR2_CWUPF1);
971 }
972 
973 /**
974   * @brief  Clear Under-Drive ready Flag
975   * @rmtoll CSR1          UDRDY         LL_PWR_ClearFlag_UD
976   * @retval None
977   */
LL_PWR_ClearFlag_UD(void)978 __STATIC_INLINE void LL_PWR_ClearFlag_UD(void)
979 {
980   WRITE_REG(PWR->CSR1, PWR_CSR1_UDRDY);
981 }
982 
983 #if defined(USE_FULL_LL_DRIVER)
984 /** @defgroup PWR_LL_EF_Init De-initialization function
985   * @{
986   */
987 ErrorStatus LL_PWR_DeInit(void);
988 /**
989   * @}
990   */
991 #endif /* USE_FULL_LL_DRIVER */
992 
993 /**
994   * @}
995   */
996 
997 /**
998   * @}
999   */
1000 
1001 /**
1002   * @}
1003   */
1004 
1005 #endif /* defined(PWR) */
1006 
1007 /**
1008   * @}
1009   */
1010 
1011 #ifdef __cplusplus
1012 }
1013 #endif
1014 
1015 #endif /* __STM32F7xx_LL_PWR_H */
1016 
1017