1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_i2c.h
4 * @author MCD Application Team
5 * @brief Header file of I2C LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32F7xx_LL_I2C_H
21 #define STM32F7xx_LL_I2C_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f7xx.h"
29
30 /** @addtogroup STM32F7xx_LL_Driver
31 * @{
32 */
33
34 #if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4)
35
36 /** @defgroup I2C_LL I2C
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup I2C_LL_Private_Constants I2C Private Constants
45 * @{
46 */
47 /**
48 * @}
49 */
50
51 /* Private macros ------------------------------------------------------------*/
52 #if defined(USE_FULL_LL_DRIVER)
53 /** @defgroup I2C_LL_Private_Macros I2C Private Macros
54 * @{
55 */
56 /**
57 * @}
58 */
59 #endif /*USE_FULL_LL_DRIVER*/
60
61 /* Exported types ------------------------------------------------------------*/
62 #if defined(USE_FULL_LL_DRIVER)
63 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
64 * @{
65 */
66 typedef struct
67 {
68 uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
69 This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE.
70
71 This feature can be modified afterwards using unitary function
72 @ref LL_I2C_SetMode(). */
73
74 uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
75 This parameter must be set by referring to the STM32CubeMX Tool and
76 the helper macro @ref __LL_I2C_CONVERT_TIMINGS().
77
78 This feature can be modified afterwards using unitary function
79 @ref LL_I2C_SetTiming(). */
80
81 uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
82 This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION.
83
84 This feature can be modified afterwards using unitary functions
85 @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
86
87 uint32_t DigitalFilter; /*!< Configures the digital noise filter.
88 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
89
90 This feature can be modified afterwards using unitary function
91 @ref LL_I2C_SetDigitalFilter(). */
92
93 uint32_t OwnAddress1; /*!< Specifies the device own address 1.
94 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
95
96 This feature can be modified afterwards using unitary function
97 @ref LL_I2C_SetOwnAddress1(). */
98
99 uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive
100 match code or next received byte.
101 This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE.
102
103 This feature can be modified afterwards using unitary function
104 @ref LL_I2C_AcknowledgeNextData(). */
105
106 uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
107 This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1.
108
109 This feature can be modified afterwards using unitary function
110 @ref LL_I2C_SetOwnAddress1(). */
111 } LL_I2C_InitTypeDef;
112 /**
113 * @}
114 */
115 #endif /*USE_FULL_LL_DRIVER*/
116
117 /* Exported constants --------------------------------------------------------*/
118 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
119 * @{
120 */
121
122 /** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
123 * @brief Flags defines which can be used with LL_I2C_WriteReg function
124 * @{
125 */
126 #define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */
127 #define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */
128 #define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */
129 #define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */
130 #define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */
131 #define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */
132 #define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */
133 #define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */
134 #define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */
135 /**
136 * @}
137 */
138
139 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
140 * @brief Flags defines which can be used with LL_I2C_ReadReg function
141 * @{
142 */
143 #define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */
144 #define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */
145 #define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */
146 #define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */
147 #define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */
148 #define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */
149 #define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */
150 #define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */
151 #define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */
152 #define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */
153 #define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */
154 #define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
155 #define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
156 #define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */
157 #define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */
158 /**
159 * @}
160 */
161
162 /** @defgroup I2C_LL_EC_IT IT Defines
163 * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
164 * @{
165 */
166 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */
167 #define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */
168 #define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */
169 #define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */
170 #define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */
171 #define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */
172 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */
173 /**
174 * @}
175 */
176
177 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
178 * @{
179 */
180 #define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
181 #define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */
182 #define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode
183 (Default address not acknowledge) */
184 #define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */
185 /**
186 * @}
187 */
188
189 /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
190 * @{
191 */
192 #define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */
193 #define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */
194 /**
195 * @}
196 */
197
198 /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
199 * @{
200 */
201 #define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */
202 #define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/
203 /**
204 * @}
205 */
206
207 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
208 * @{
209 */
210 #define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */
211 #define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/
212 /**
213 * @}
214 */
215
216 /** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
217 * @{
218 */
219 #define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */
220 #define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */
221 #define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */
222 #define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */
223 #define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */
224 #define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */
225 #define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */
226 #define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done.
227 All Address2 are acknowledged. */
228 /**
229 * @}
230 */
231
232 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
233 * @{
234 */
235 #define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */
236 #define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/
237 /**
238 * @}
239 */
240
241 /** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
242 * @{
243 */
244 #define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */
245 #define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/
246 /**
247 * @}
248 */
249
250 /** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
251 * @{
252 */
253 #define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */
254 #define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */
255 /**
256 * @}
257 */
258
259 /** @defgroup I2C_LL_EC_MODE Transfer End Mode
260 * @{
261 */
262 #define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */
263 #define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode
264 with no HW PEC comparison. */
265 #define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode
266 with no HW PEC comparison. */
267 #define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode
268 with HW PEC comparison. */
269 #define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode
270 with HW PEC comparison. */
271 #define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode
272 with HW PEC comparison. */
273 #define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
274 /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
275 #define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)
276 /*!< Enable SMBUS Software end mode with HW PEC comparison. */
277 /**
278 * @}
279 */
280
281 /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
282 * @{
283 */
284 #define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U
285 /*!< Don't Generate Stop and Start condition. */
286 #define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
287 /*!< Generate Stop condition (Size should be set to 0). */
288 #define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
289 /*!< Generate Start for read request. */
290 #define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
291 /*!< Generate Start for write request. */
292 #define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
293 /*!< Generate Restart for read request, slave 7Bit address. */
294 #define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
295 /*!< Generate Restart for write request, slave 7Bit address. */
296 #define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | \
297 I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
298 /*!< Generate Restart for read request, slave 10Bit address. */
299 #define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
300 /*!< Generate Restart for write request, slave 10Bit address.*/
301 /**
302 * @}
303 */
304
305 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
306 * @{
307 */
308 #define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master,
309 slave enters receiver mode. */
310 #define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master,
311 slave enters transmitter mode.*/
312 /**
313 * @}
314 */
315
316 /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
317 * @{
318 */
319 #define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for
320 transmission */
321 #define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for
322 reception */
323 /**
324 * @}
325 */
326
327 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
328 * @{
329 */
330 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect
331 SCL low level timeout. */
332 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect
333 both SCL and SDA high level timeout.*/
334 /**
335 * @}
336 */
337
338 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
339 * @{
340 */
341 #define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */
342 #define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock)
343 enable bit */
344 #define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \
345 I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB
346 (extended clock) enable bits */
347 /**
348 * @}
349 */
350
351 /**
352 * @}
353 */
354
355 /* Exported macro ------------------------------------------------------------*/
356 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
357 * @{
358 */
359
360 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
361 * @{
362 */
363
364 /**
365 * @brief Write a value in I2C register
366 * @param __INSTANCE__ I2C Instance
367 * @param __REG__ Register to be written
368 * @param __VALUE__ Value to be written in the register
369 * @retval None
370 */
371 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
372
373 /**
374 * @brief Read a value in I2C register
375 * @param __INSTANCE__ I2C Instance
376 * @param __REG__ Register to be read
377 * @retval Register value
378 */
379 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
380 /**
381 * @}
382 */
383
384 /** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
385 * @{
386 */
387 /**
388 * @brief Configure the SDA setup, hold time and the SCL high, low period.
389 * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
390 * @param __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
391 (tscldel = (SCLDEL+1)xtpresc)
392 * @param __HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
393 (tsdadel = SDADELxtpresc)
394 * @param __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
395 (tsclh = (SCLH+1)xtpresc)
396 * @param __SCLL_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
397 (tscll = (SCLL+1)xtpresc)
398 * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
399 */
400 #define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \
401 ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
402 (((uint32_t)(__SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
403 (((uint32_t)(__HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
404 (((uint32_t)(__SCLH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
405 (((uint32_t)(__SCLL_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
406 /**
407 * @}
408 */
409
410 /**
411 * @}
412 */
413
414 /* Exported functions --------------------------------------------------------*/
415 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
416 * @{
417 */
418
419 /** @defgroup I2C_LL_EF_Configuration Configuration
420 * @{
421 */
422
423 /**
424 * @brief Enable I2C peripheral (PE = 1).
425 * @rmtoll CR1 PE LL_I2C_Enable
426 * @param I2Cx I2C Instance.
427 * @retval None
428 */
LL_I2C_Enable(I2C_TypeDef * I2Cx)429 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
430 {
431 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
432 }
433
434 /**
435 * @brief Disable I2C peripheral (PE = 0).
436 * @note When PE = 0, the I2C SCL and SDA lines are released.
437 * Internal state machines and status bits are put back to their reset value.
438 * When cleared, PE must be kept low for at least 3 APB clock cycles.
439 * @rmtoll CR1 PE LL_I2C_Disable
440 * @param I2Cx I2C Instance.
441 * @retval None
442 */
LL_I2C_Disable(I2C_TypeDef * I2Cx)443 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
444 {
445 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
446 }
447
448 /**
449 * @brief Check if the I2C peripheral is enabled or disabled.
450 * @rmtoll CR1 PE LL_I2C_IsEnabled
451 * @param I2Cx I2C Instance.
452 * @retval State of bit (1 or 0).
453 */
LL_I2C_IsEnabled(I2C_TypeDef * I2Cx)454 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
455 {
456 return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
457 }
458
459 /**
460 * @brief Configure Noise Filters (Analog and Digital).
461 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
462 * The filters can only be programmed when the I2C is disabled (PE = 0).
463 * @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n
464 * CR1 DNF LL_I2C_ConfigFilters
465 * @param I2Cx I2C Instance.
466 * @param AnalogFilter This parameter can be one of the following values:
467 * @arg @ref LL_I2C_ANALOGFILTER_ENABLE
468 * @arg @ref LL_I2C_ANALOGFILTER_DISABLE
469 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
470 and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
471 * This parameter is used to configure the digital noise filter on SDA and SCL input.
472 * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
473 * @retval None
474 */
LL_I2C_ConfigFilters(I2C_TypeDef * I2Cx,uint32_t AnalogFilter,uint32_t DigitalFilter)475 __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
476 {
477 MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
478 }
479
480 /**
481 * @brief Configure Digital Noise Filter.
482 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
483 * This filter can only be programmed when the I2C is disabled (PE = 0).
484 * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter
485 * @param I2Cx I2C Instance.
486 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
487 and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
488 * This parameter is used to configure the digital noise filter on SDA and SCL input.
489 * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
490 * @retval None
491 */
LL_I2C_SetDigitalFilter(I2C_TypeDef * I2Cx,uint32_t DigitalFilter)492 __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
493 {
494 MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
495 }
496
497 /**
498 * @brief Get the current Digital Noise Filter configuration.
499 * @rmtoll CR1 DNF LL_I2C_GetDigitalFilter
500 * @param I2Cx I2C Instance.
501 * @retval Value between Min_Data=0x0 and Max_Data=0xF
502 */
LL_I2C_GetDigitalFilter(I2C_TypeDef * I2Cx)503 __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
504 {
505 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
506 }
507
508 /**
509 * @brief Enable Analog Noise Filter.
510 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
511 * @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter
512 * @param I2Cx I2C Instance.
513 * @retval None
514 */
LL_I2C_EnableAnalogFilter(I2C_TypeDef * I2Cx)515 __STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
516 {
517 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
518 }
519
520 /**
521 * @brief Disable Analog Noise Filter.
522 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
523 * @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter
524 * @param I2Cx I2C Instance.
525 * @retval None
526 */
LL_I2C_DisableAnalogFilter(I2C_TypeDef * I2Cx)527 __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
528 {
529 SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
530 }
531
532 /**
533 * @brief Check if Analog Noise Filter is enabled or disabled.
534 * @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
535 * @param I2Cx I2C Instance.
536 * @retval State of bit (1 or 0).
537 */
LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef * I2Cx)538 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
539 {
540 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
541 }
542
543 /**
544 * @brief Enable DMA transmission requests.
545 * @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
546 * @param I2Cx I2C Instance.
547 * @retval None
548 */
LL_I2C_EnableDMAReq_TX(I2C_TypeDef * I2Cx)549 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
550 {
551 SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
552 }
553
554 /**
555 * @brief Disable DMA transmission requests.
556 * @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
557 * @param I2Cx I2C Instance.
558 * @retval None
559 */
LL_I2C_DisableDMAReq_TX(I2C_TypeDef * I2Cx)560 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
561 {
562 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
563 }
564
565 /**
566 * @brief Check if DMA transmission requests are enabled or disabled.
567 * @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
568 * @param I2Cx I2C Instance.
569 * @retval State of bit (1 or 0).
570 */
LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef * I2Cx)571 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
572 {
573 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
574 }
575
576 /**
577 * @brief Enable DMA reception requests.
578 * @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
579 * @param I2Cx I2C Instance.
580 * @retval None
581 */
LL_I2C_EnableDMAReq_RX(I2C_TypeDef * I2Cx)582 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
583 {
584 SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
585 }
586
587 /**
588 * @brief Disable DMA reception requests.
589 * @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
590 * @param I2Cx I2C Instance.
591 * @retval None
592 */
LL_I2C_DisableDMAReq_RX(I2C_TypeDef * I2Cx)593 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
594 {
595 CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
596 }
597
598 /**
599 * @brief Check if DMA reception requests are enabled or disabled.
600 * @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
601 * @param I2Cx I2C Instance.
602 * @retval State of bit (1 or 0).
603 */
LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef * I2Cx)604 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
605 {
606 return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
607 }
608
609 /**
610 * @brief Get the data register address used for DMA transfer
611 * @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n
612 * RXDR RXDATA LL_I2C_DMA_GetRegAddr
613 * @param I2Cx I2C Instance
614 * @param Direction This parameter can be one of the following values:
615 * @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
616 * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
617 * @retval Address of data register
618 */
LL_I2C_DMA_GetRegAddr(I2C_TypeDef * I2Cx,uint32_t Direction)619 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
620 {
621 uint32_t data_reg_addr;
622
623 if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
624 {
625 /* return address of TXDR register */
626 data_reg_addr = (uint32_t) &(I2Cx->TXDR);
627 }
628 else
629 {
630 /* return address of RXDR register */
631 data_reg_addr = (uint32_t) &(I2Cx->RXDR);
632 }
633
634 return data_reg_addr;
635 }
636
637 /**
638 * @brief Enable Clock stretching.
639 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
640 * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
641 * @param I2Cx I2C Instance.
642 * @retval None
643 */
LL_I2C_EnableClockStretching(I2C_TypeDef * I2Cx)644 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
645 {
646 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
647 }
648
649 /**
650 * @brief Disable Clock stretching.
651 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
652 * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
653 * @param I2Cx I2C Instance.
654 * @retval None
655 */
LL_I2C_DisableClockStretching(I2C_TypeDef * I2Cx)656 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
657 {
658 SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
659 }
660
661 /**
662 * @brief Check if Clock stretching is enabled or disabled.
663 * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
664 * @param I2Cx I2C Instance.
665 * @retval State of bit (1 or 0).
666 */
LL_I2C_IsEnabledClockStretching(I2C_TypeDef * I2Cx)667 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
668 {
669 return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
670 }
671
672 /**
673 * @brief Enable hardware byte control in slave mode.
674 * @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl
675 * @param I2Cx I2C Instance.
676 * @retval None
677 */
LL_I2C_EnableSlaveByteControl(I2C_TypeDef * I2Cx)678 __STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
679 {
680 SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
681 }
682
683 /**
684 * @brief Disable hardware byte control in slave mode.
685 * @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl
686 * @param I2Cx I2C Instance.
687 * @retval None
688 */
LL_I2C_DisableSlaveByteControl(I2C_TypeDef * I2Cx)689 __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
690 {
691 CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
692 }
693
694 /**
695 * @brief Check if hardware byte control in slave mode is enabled or disabled.
696 * @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl
697 * @param I2Cx I2C Instance.
698 * @retval State of bit (1 or 0).
699 */
LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef * I2Cx)700 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
701 {
702 return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
703 }
704
705 /**
706 * @brief Enable General Call.
707 * @note When enabled the Address 0x00 is ACKed.
708 * @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall
709 * @param I2Cx I2C Instance.
710 * @retval None
711 */
LL_I2C_EnableGeneralCall(I2C_TypeDef * I2Cx)712 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
713 {
714 SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
715 }
716
717 /**
718 * @brief Disable General Call.
719 * @note When disabled the Address 0x00 is NACKed.
720 * @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall
721 * @param I2Cx I2C Instance.
722 * @retval None
723 */
LL_I2C_DisableGeneralCall(I2C_TypeDef * I2Cx)724 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
725 {
726 CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
727 }
728
729 /**
730 * @brief Check if General Call is enabled or disabled.
731 * @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall
732 * @param I2Cx I2C Instance.
733 * @retval State of bit (1 or 0).
734 */
LL_I2C_IsEnabledGeneralCall(I2C_TypeDef * I2Cx)735 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
736 {
737 return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
738 }
739
740 /**
741 * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
742 * @note Changing this bit is not allowed, when the START bit is set.
743 * @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode
744 * @param I2Cx I2C Instance.
745 * @param AddressingMode This parameter can be one of the following values:
746 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
747 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
748 * @retval None
749 */
LL_I2C_SetMasterAddressingMode(I2C_TypeDef * I2Cx,uint32_t AddressingMode)750 __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
751 {
752 MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
753 }
754
755 /**
756 * @brief Get the Master addressing mode.
757 * @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode
758 * @param I2Cx I2C Instance.
759 * @retval Returned value can be one of the following values:
760 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
761 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
762 */
LL_I2C_GetMasterAddressingMode(I2C_TypeDef * I2Cx)763 __STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
764 {
765 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
766 }
767
768 /**
769 * @brief Set the Own Address1.
770 * @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n
771 * OAR1 OA1MODE LL_I2C_SetOwnAddress1
772 * @param I2Cx I2C Instance.
773 * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
774 * @param OwnAddrSize This parameter can be one of the following values:
775 * @arg @ref LL_I2C_OWNADDRESS1_7BIT
776 * @arg @ref LL_I2C_OWNADDRESS1_10BIT
777 * @retval None
778 */
LL_I2C_SetOwnAddress1(I2C_TypeDef * I2Cx,uint32_t OwnAddress1,uint32_t OwnAddrSize)779 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
780 {
781 MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
782 }
783
784 /**
785 * @brief Enable acknowledge on Own Address1 match address.
786 * @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1
787 * @param I2Cx I2C Instance.
788 * @retval None
789 */
LL_I2C_EnableOwnAddress1(I2C_TypeDef * I2Cx)790 __STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
791 {
792 SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
793 }
794
795 /**
796 * @brief Disable acknowledge on Own Address1 match address.
797 * @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1
798 * @param I2Cx I2C Instance.
799 * @retval None
800 */
LL_I2C_DisableOwnAddress1(I2C_TypeDef * I2Cx)801 __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
802 {
803 CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
804 }
805
806 /**
807 * @brief Check if Own Address1 acknowledge is enabled or disabled.
808 * @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
809 * @param I2Cx I2C Instance.
810 * @retval State of bit (1 or 0).
811 */
LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef * I2Cx)812 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
813 {
814 return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
815 }
816
817 /**
818 * @brief Set the 7bits Own Address2.
819 * @note This action has no effect if own address2 is enabled.
820 * @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n
821 * OAR2 OA2MSK LL_I2C_SetOwnAddress2
822 * @param I2Cx I2C Instance.
823 * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
824 * @param OwnAddrMask This parameter can be one of the following values:
825 * @arg @ref LL_I2C_OWNADDRESS2_NOMASK
826 * @arg @ref LL_I2C_OWNADDRESS2_MASK01
827 * @arg @ref LL_I2C_OWNADDRESS2_MASK02
828 * @arg @ref LL_I2C_OWNADDRESS2_MASK03
829 * @arg @ref LL_I2C_OWNADDRESS2_MASK04
830 * @arg @ref LL_I2C_OWNADDRESS2_MASK05
831 * @arg @ref LL_I2C_OWNADDRESS2_MASK06
832 * @arg @ref LL_I2C_OWNADDRESS2_MASK07
833 * @retval None
834 */
LL_I2C_SetOwnAddress2(I2C_TypeDef * I2Cx,uint32_t OwnAddress2,uint32_t OwnAddrMask)835 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
836 {
837 MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
838 }
839
840 /**
841 * @brief Enable acknowledge on Own Address2 match address.
842 * @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2
843 * @param I2Cx I2C Instance.
844 * @retval None
845 */
LL_I2C_EnableOwnAddress2(I2C_TypeDef * I2Cx)846 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
847 {
848 SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
849 }
850
851 /**
852 * @brief Disable acknowledge on Own Address2 match address.
853 * @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2
854 * @param I2Cx I2C Instance.
855 * @retval None
856 */
LL_I2C_DisableOwnAddress2(I2C_TypeDef * I2Cx)857 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
858 {
859 CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
860 }
861
862 /**
863 * @brief Check if Own Address1 acknowledge is enabled or disabled.
864 * @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
865 * @param I2Cx I2C Instance.
866 * @retval State of bit (1 or 0).
867 */
LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef * I2Cx)868 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
869 {
870 return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
871 }
872
873 /**
874 * @brief Configure the SDA setup, hold time and the SCL high, low period.
875 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
876 * @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming
877 * @param I2Cx I2C Instance.
878 * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
879 * @note This parameter is computed with the STM32CubeMX Tool.
880 * @retval None
881 */
LL_I2C_SetTiming(I2C_TypeDef * I2Cx,uint32_t Timing)882 __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
883 {
884 WRITE_REG(I2Cx->TIMINGR, Timing);
885 }
886
887 /**
888 * @brief Get the Timing Prescaler setting.
889 * @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler
890 * @param I2Cx I2C Instance.
891 * @retval Value between Min_Data=0x0 and Max_Data=0xF
892 */
LL_I2C_GetTimingPrescaler(I2C_TypeDef * I2Cx)893 __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
894 {
895 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
896 }
897
898 /**
899 * @brief Get the SCL low period setting.
900 * @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod
901 * @param I2Cx I2C Instance.
902 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
903 */
LL_I2C_GetClockLowPeriod(I2C_TypeDef * I2Cx)904 __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
905 {
906 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
907 }
908
909 /**
910 * @brief Get the SCL high period setting.
911 * @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod
912 * @param I2Cx I2C Instance.
913 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
914 */
LL_I2C_GetClockHighPeriod(I2C_TypeDef * I2Cx)915 __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
916 {
917 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
918 }
919
920 /**
921 * @brief Get the SDA hold time.
922 * @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime
923 * @param I2Cx I2C Instance.
924 * @retval Value between Min_Data=0x0 and Max_Data=0xF
925 */
LL_I2C_GetDataHoldTime(I2C_TypeDef * I2Cx)926 __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
927 {
928 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
929 }
930
931 /**
932 * @brief Get the SDA setup time.
933 * @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime
934 * @param I2Cx I2C Instance.
935 * @retval Value between Min_Data=0x0 and Max_Data=0xF
936 */
LL_I2C_GetDataSetupTime(I2C_TypeDef * I2Cx)937 __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
938 {
939 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
940 }
941
942 /**
943 * @brief Configure peripheral mode.
944 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
945 * SMBus feature is supported by the I2Cx Instance.
946 * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n
947 * CR1 SMBDEN LL_I2C_SetMode
948 * @param I2Cx I2C Instance.
949 * @param PeripheralMode This parameter can be one of the following values:
950 * @arg @ref LL_I2C_MODE_I2C
951 * @arg @ref LL_I2C_MODE_SMBUS_HOST
952 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
953 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
954 * @retval None
955 */
LL_I2C_SetMode(I2C_TypeDef * I2Cx,uint32_t PeripheralMode)956 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
957 {
958 MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
959 }
960
961 /**
962 * @brief Get peripheral mode.
963 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
964 * SMBus feature is supported by the I2Cx Instance.
965 * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n
966 * CR1 SMBDEN LL_I2C_GetMode
967 * @param I2Cx I2C Instance.
968 * @retval Returned value can be one of the following values:
969 * @arg @ref LL_I2C_MODE_I2C
970 * @arg @ref LL_I2C_MODE_SMBUS_HOST
971 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
972 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
973 */
LL_I2C_GetMode(I2C_TypeDef * I2Cx)974 __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
975 {
976 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
977 }
978
979 /**
980 * @brief Enable SMBus alert (Host or Device mode)
981 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
982 * SMBus feature is supported by the I2Cx Instance.
983 * @note SMBus Device mode:
984 * - SMBus Alert pin is drived low and
985 * Alert Response Address Header acknowledge is enabled.
986 * SMBus Host mode:
987 * - SMBus Alert pin management is supported.
988 * @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert
989 * @param I2Cx I2C Instance.
990 * @retval None
991 */
LL_I2C_EnableSMBusAlert(I2C_TypeDef * I2Cx)992 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
993 {
994 SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
995 }
996
997 /**
998 * @brief Disable SMBus alert (Host or Device mode)
999 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1000 * SMBus feature is supported by the I2Cx Instance.
1001 * @note SMBus Device mode:
1002 * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
1003 * Alert Response Address Header acknowledge is disabled.
1004 * SMBus Host mode:
1005 * - SMBus Alert pin management is not supported.
1006 * @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert
1007 * @param I2Cx I2C Instance.
1008 * @retval None
1009 */
LL_I2C_DisableSMBusAlert(I2C_TypeDef * I2Cx)1010 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
1011 {
1012 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
1013 }
1014
1015 /**
1016 * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
1017 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1018 * SMBus feature is supported by the I2Cx Instance.
1019 * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
1020 * @param I2Cx I2C Instance.
1021 * @retval State of bit (1 or 0).
1022 */
LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef * I2Cx)1023 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
1024 {
1025 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
1026 }
1027
1028 /**
1029 * @brief Enable SMBus Packet Error Calculation (PEC).
1030 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1031 * SMBus feature is supported by the I2Cx Instance.
1032 * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC
1033 * @param I2Cx I2C Instance.
1034 * @retval None
1035 */
LL_I2C_EnableSMBusPEC(I2C_TypeDef * I2Cx)1036 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
1037 {
1038 SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
1039 }
1040
1041 /**
1042 * @brief Disable SMBus Packet Error Calculation (PEC).
1043 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1044 * SMBus feature is supported by the I2Cx Instance.
1045 * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC
1046 * @param I2Cx I2C Instance.
1047 * @retval None
1048 */
LL_I2C_DisableSMBusPEC(I2C_TypeDef * I2Cx)1049 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
1050 {
1051 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
1052 }
1053
1054 /**
1055 * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
1056 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1057 * SMBus feature is supported by the I2Cx Instance.
1058 * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC
1059 * @param I2Cx I2C Instance.
1060 * @retval State of bit (1 or 0).
1061 */
LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef * I2Cx)1062 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
1063 {
1064 return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
1065 }
1066
1067 /**
1068 * @brief Configure the SMBus Clock Timeout.
1069 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1070 * SMBus feature is supported by the I2Cx Instance.
1071 * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
1072 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n
1073 * TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n
1074 * TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout
1075 * @param I2Cx I2C Instance.
1076 * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1077 * @param TimeoutAMode This parameter can be one of the following values:
1078 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1079 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1080 * @param TimeoutB
1081 * @retval None
1082 */
LL_I2C_ConfigSMBusTimeout(I2C_TypeDef * I2Cx,uint32_t TimeoutA,uint32_t TimeoutAMode,uint32_t TimeoutB)1083 __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
1084 uint32_t TimeoutB)
1085 {
1086 MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
1087 TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
1088 }
1089
1090 /**
1091 * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
1092 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1093 * SMBus feature is supported by the I2Cx Instance.
1094 * @note These bits can only be programmed when TimeoutA is disabled.
1095 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
1096 * @param I2Cx I2C Instance.
1097 * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1098 * @retval None
1099 */
LL_I2C_SetSMBusTimeoutA(I2C_TypeDef * I2Cx,uint32_t TimeoutA)1100 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
1101 {
1102 WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
1103 }
1104
1105 /**
1106 * @brief Get the SMBus Clock TimeoutA setting.
1107 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1108 * SMBus feature is supported by the I2Cx Instance.
1109 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
1110 * @param I2Cx I2C Instance.
1111 * @retval Value between Min_Data=0 and Max_Data=0xFFF
1112 */
LL_I2C_GetSMBusTimeoutA(I2C_TypeDef * I2Cx)1113 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
1114 {
1115 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
1116 }
1117
1118 /**
1119 * @brief Set the SMBus Clock TimeoutA mode.
1120 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1121 * SMBus feature is supported by the I2Cx Instance.
1122 * @note This bit can only be programmed when TimeoutA is disabled.
1123 * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
1124 * @param I2Cx I2C Instance.
1125 * @param TimeoutAMode This parameter can be one of the following values:
1126 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1127 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1128 * @retval None
1129 */
LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef * I2Cx,uint32_t TimeoutAMode)1130 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
1131 {
1132 WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
1133 }
1134
1135 /**
1136 * @brief Get the SMBus Clock TimeoutA mode.
1137 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1138 * SMBus feature is supported by the I2Cx Instance.
1139 * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
1140 * @param I2Cx I2C Instance.
1141 * @retval Returned value can be one of the following values:
1142 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1143 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1144 */
LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef * I2Cx)1145 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
1146 {
1147 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
1148 }
1149
1150 /**
1151 * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
1152 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1153 * SMBus feature is supported by the I2Cx Instance.
1154 * @note These bits can only be programmed when TimeoutB is disabled.
1155 * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
1156 * @param I2Cx I2C Instance.
1157 * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1158 * @retval None
1159 */
LL_I2C_SetSMBusTimeoutB(I2C_TypeDef * I2Cx,uint32_t TimeoutB)1160 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
1161 {
1162 WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
1163 }
1164
1165 /**
1166 * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting.
1167 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1168 * SMBus feature is supported by the I2Cx Instance.
1169 * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
1170 * @param I2Cx I2C Instance.
1171 * @retval Value between Min_Data=0 and Max_Data=0xFFF
1172 */
LL_I2C_GetSMBusTimeoutB(I2C_TypeDef * I2Cx)1173 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
1174 {
1175 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
1176 }
1177
1178 /**
1179 * @brief Enable the SMBus Clock Timeout.
1180 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1181 * SMBus feature is supported by the I2Cx Instance.
1182 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n
1183 * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
1184 * @param I2Cx I2C Instance.
1185 * @param ClockTimeout This parameter can be one of the following values:
1186 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1187 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1188 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1189 * @retval None
1190 */
LL_I2C_EnableSMBusTimeout(I2C_TypeDef * I2Cx,uint32_t ClockTimeout)1191 __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1192 {
1193 SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
1194 }
1195
1196 /**
1197 * @brief Disable the SMBus Clock Timeout.
1198 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1199 * SMBus feature is supported by the I2Cx Instance.
1200 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n
1201 * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
1202 * @param I2Cx I2C Instance.
1203 * @param ClockTimeout This parameter can be one of the following values:
1204 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1205 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1206 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1207 * @retval None
1208 */
LL_I2C_DisableSMBusTimeout(I2C_TypeDef * I2Cx,uint32_t ClockTimeout)1209 __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1210 {
1211 CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
1212 }
1213
1214 /**
1215 * @brief Check if the SMBus Clock Timeout is enabled or disabled.
1216 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1217 * SMBus feature is supported by the I2Cx Instance.
1218 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n
1219 * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
1220 * @param I2Cx I2C Instance.
1221 * @param ClockTimeout This parameter can be one of the following values:
1222 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1223 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1224 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1225 * @retval State of bit (1 or 0).
1226 */
LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef * I2Cx,uint32_t ClockTimeout)1227 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1228 {
1229 return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
1230 (ClockTimeout)) ? 1UL : 0UL);
1231 }
1232
1233 /**
1234 * @}
1235 */
1236
1237 /** @defgroup I2C_LL_EF_IT_Management IT_Management
1238 * @{
1239 */
1240
1241 /**
1242 * @brief Enable TXIS interrupt.
1243 * @rmtoll CR1 TXIE LL_I2C_EnableIT_TX
1244 * @param I2Cx I2C Instance.
1245 * @retval None
1246 */
LL_I2C_EnableIT_TX(I2C_TypeDef * I2Cx)1247 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
1248 {
1249 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
1250 }
1251
1252 /**
1253 * @brief Disable TXIS interrupt.
1254 * @rmtoll CR1 TXIE LL_I2C_DisableIT_TX
1255 * @param I2Cx I2C Instance.
1256 * @retval None
1257 */
LL_I2C_DisableIT_TX(I2C_TypeDef * I2Cx)1258 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
1259 {
1260 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
1261 }
1262
1263 /**
1264 * @brief Check if the TXIS Interrupt is enabled or disabled.
1265 * @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX
1266 * @param I2Cx I2C Instance.
1267 * @retval State of bit (1 or 0).
1268 */
LL_I2C_IsEnabledIT_TX(I2C_TypeDef * I2Cx)1269 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
1270 {
1271 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
1272 }
1273
1274 /**
1275 * @brief Enable RXNE interrupt.
1276 * @rmtoll CR1 RXIE LL_I2C_EnableIT_RX
1277 * @param I2Cx I2C Instance.
1278 * @retval None
1279 */
LL_I2C_EnableIT_RX(I2C_TypeDef * I2Cx)1280 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
1281 {
1282 SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
1283 }
1284
1285 /**
1286 * @brief Disable RXNE interrupt.
1287 * @rmtoll CR1 RXIE LL_I2C_DisableIT_RX
1288 * @param I2Cx I2C Instance.
1289 * @retval None
1290 */
LL_I2C_DisableIT_RX(I2C_TypeDef * I2Cx)1291 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
1292 {
1293 CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
1294 }
1295
1296 /**
1297 * @brief Check if the RXNE Interrupt is enabled or disabled.
1298 * @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX
1299 * @param I2Cx I2C Instance.
1300 * @retval State of bit (1 or 0).
1301 */
LL_I2C_IsEnabledIT_RX(I2C_TypeDef * I2Cx)1302 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
1303 {
1304 return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
1305 }
1306
1307 /**
1308 * @brief Enable Address match interrupt (slave mode only).
1309 * @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR
1310 * @param I2Cx I2C Instance.
1311 * @retval None
1312 */
LL_I2C_EnableIT_ADDR(I2C_TypeDef * I2Cx)1313 __STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
1314 {
1315 SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
1316 }
1317
1318 /**
1319 * @brief Disable Address match interrupt (slave mode only).
1320 * @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR
1321 * @param I2Cx I2C Instance.
1322 * @retval None
1323 */
LL_I2C_DisableIT_ADDR(I2C_TypeDef * I2Cx)1324 __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
1325 {
1326 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
1327 }
1328
1329 /**
1330 * @brief Check if Address match interrupt is enabled or disabled.
1331 * @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
1332 * @param I2Cx I2C Instance.
1333 * @retval State of bit (1 or 0).
1334 */
LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef * I2Cx)1335 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
1336 {
1337 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
1338 }
1339
1340 /**
1341 * @brief Enable Not acknowledge received interrupt.
1342 * @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK
1343 * @param I2Cx I2C Instance.
1344 * @retval None
1345 */
LL_I2C_EnableIT_NACK(I2C_TypeDef * I2Cx)1346 __STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
1347 {
1348 SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
1349 }
1350
1351 /**
1352 * @brief Disable Not acknowledge received interrupt.
1353 * @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK
1354 * @param I2Cx I2C Instance.
1355 * @retval None
1356 */
LL_I2C_DisableIT_NACK(I2C_TypeDef * I2Cx)1357 __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
1358 {
1359 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
1360 }
1361
1362 /**
1363 * @brief Check if Not acknowledge received interrupt is enabled or disabled.
1364 * @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK
1365 * @param I2Cx I2C Instance.
1366 * @retval State of bit (1 or 0).
1367 */
LL_I2C_IsEnabledIT_NACK(I2C_TypeDef * I2Cx)1368 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
1369 {
1370 return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
1371 }
1372
1373 /**
1374 * @brief Enable STOP detection interrupt.
1375 * @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP
1376 * @param I2Cx I2C Instance.
1377 * @retval None
1378 */
LL_I2C_EnableIT_STOP(I2C_TypeDef * I2Cx)1379 __STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
1380 {
1381 SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
1382 }
1383
1384 /**
1385 * @brief Disable STOP detection interrupt.
1386 * @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP
1387 * @param I2Cx I2C Instance.
1388 * @retval None
1389 */
LL_I2C_DisableIT_STOP(I2C_TypeDef * I2Cx)1390 __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
1391 {
1392 CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
1393 }
1394
1395 /**
1396 * @brief Check if STOP detection interrupt is enabled or disabled.
1397 * @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP
1398 * @param I2Cx I2C Instance.
1399 * @retval State of bit (1 or 0).
1400 */
LL_I2C_IsEnabledIT_STOP(I2C_TypeDef * I2Cx)1401 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
1402 {
1403 return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
1404 }
1405
1406 /**
1407 * @brief Enable Transfer Complete interrupt.
1408 * @note Any of these events will generate interrupt :
1409 * Transfer Complete (TC)
1410 * Transfer Complete Reload (TCR)
1411 * @rmtoll CR1 TCIE LL_I2C_EnableIT_TC
1412 * @param I2Cx I2C Instance.
1413 * @retval None
1414 */
LL_I2C_EnableIT_TC(I2C_TypeDef * I2Cx)1415 __STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
1416 {
1417 SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
1418 }
1419
1420 /**
1421 * @brief Disable Transfer Complete interrupt.
1422 * @note Any of these events will generate interrupt :
1423 * Transfer Complete (TC)
1424 * Transfer Complete Reload (TCR)
1425 * @rmtoll CR1 TCIE LL_I2C_DisableIT_TC
1426 * @param I2Cx I2C Instance.
1427 * @retval None
1428 */
LL_I2C_DisableIT_TC(I2C_TypeDef * I2Cx)1429 __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
1430 {
1431 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
1432 }
1433
1434 /**
1435 * @brief Check if Transfer Complete interrupt is enabled or disabled.
1436 * @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC
1437 * @param I2Cx I2C Instance.
1438 * @retval State of bit (1 or 0).
1439 */
LL_I2C_IsEnabledIT_TC(I2C_TypeDef * I2Cx)1440 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
1441 {
1442 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
1443 }
1444
1445 /**
1446 * @brief Enable Error interrupts.
1447 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1448 * SMBus feature is supported by the I2Cx Instance.
1449 * @note Any of these errors will generate interrupt :
1450 * Arbitration Loss (ARLO)
1451 * Bus Error detection (BERR)
1452 * Overrun/Underrun (OVR)
1453 * SMBus Timeout detection (TIMEOUT)
1454 * SMBus PEC error detection (PECERR)
1455 * SMBus Alert pin event detection (ALERT)
1456 * @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR
1457 * @param I2Cx I2C Instance.
1458 * @retval None
1459 */
LL_I2C_EnableIT_ERR(I2C_TypeDef * I2Cx)1460 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
1461 {
1462 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
1463 }
1464
1465 /**
1466 * @brief Disable Error interrupts.
1467 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1468 * SMBus feature is supported by the I2Cx Instance.
1469 * @note Any of these errors will generate interrupt :
1470 * Arbitration Loss (ARLO)
1471 * Bus Error detection (BERR)
1472 * Overrun/Underrun (OVR)
1473 * SMBus Timeout detection (TIMEOUT)
1474 * SMBus PEC error detection (PECERR)
1475 * SMBus Alert pin event detection (ALERT)
1476 * @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR
1477 * @param I2Cx I2C Instance.
1478 * @retval None
1479 */
LL_I2C_DisableIT_ERR(I2C_TypeDef * I2Cx)1480 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
1481 {
1482 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
1483 }
1484
1485 /**
1486 * @brief Check if Error interrupts are enabled or disabled.
1487 * @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR
1488 * @param I2Cx I2C Instance.
1489 * @retval State of bit (1 or 0).
1490 */
LL_I2C_IsEnabledIT_ERR(I2C_TypeDef * I2Cx)1491 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
1492 {
1493 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
1494 }
1495
1496 /**
1497 * @}
1498 */
1499
1500 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
1501 * @{
1502 */
1503
1504 /**
1505 * @brief Indicate the status of Transmit data register empty flag.
1506 * @note RESET: When next data is written in Transmit data register.
1507 * SET: When Transmit data register is empty.
1508 * @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE
1509 * @param I2Cx I2C Instance.
1510 * @retval State of bit (1 or 0).
1511 */
LL_I2C_IsActiveFlag_TXE(I2C_TypeDef * I2Cx)1512 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
1513 {
1514 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
1515 }
1516
1517 /**
1518 * @brief Indicate the status of Transmit interrupt flag.
1519 * @note RESET: When next data is written in Transmit data register.
1520 * SET: When Transmit data register is empty.
1521 * @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS
1522 * @param I2Cx I2C Instance.
1523 * @retval State of bit (1 or 0).
1524 */
LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef * I2Cx)1525 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
1526 {
1527 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
1528 }
1529
1530 /**
1531 * @brief Indicate the status of Receive data register not empty flag.
1532 * @note RESET: When Receive data register is read.
1533 * SET: When the received data is copied in Receive data register.
1534 * @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE
1535 * @param I2Cx I2C Instance.
1536 * @retval State of bit (1 or 0).
1537 */
LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef * I2Cx)1538 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
1539 {
1540 return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
1541 }
1542
1543 /**
1544 * @brief Indicate the status of Address matched flag (slave mode).
1545 * @note RESET: Clear default value.
1546 * SET: When the received slave address matched with one of the enabled slave address.
1547 * @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR
1548 * @param I2Cx I2C Instance.
1549 * @retval State of bit (1 or 0).
1550 */
LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef * I2Cx)1551 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
1552 {
1553 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
1554 }
1555
1556 /**
1557 * @brief Indicate the status of Not Acknowledge received flag.
1558 * @note RESET: Clear default value.
1559 * SET: When a NACK is received after a byte transmission.
1560 * @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK
1561 * @param I2Cx I2C Instance.
1562 * @retval State of bit (1 or 0).
1563 */
LL_I2C_IsActiveFlag_NACK(I2C_TypeDef * I2Cx)1564 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
1565 {
1566 return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
1567 }
1568
1569 /**
1570 * @brief Indicate the status of Stop detection flag.
1571 * @note RESET: Clear default value.
1572 * SET: When a Stop condition is detected.
1573 * @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP
1574 * @param I2Cx I2C Instance.
1575 * @retval State of bit (1 or 0).
1576 */
LL_I2C_IsActiveFlag_STOP(I2C_TypeDef * I2Cx)1577 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
1578 {
1579 return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
1580 }
1581
1582 /**
1583 * @brief Indicate the status of Transfer complete flag (master mode).
1584 * @note RESET: Clear default value.
1585 * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
1586 * @rmtoll ISR TC LL_I2C_IsActiveFlag_TC
1587 * @param I2Cx I2C Instance.
1588 * @retval State of bit (1 or 0).
1589 */
LL_I2C_IsActiveFlag_TC(I2C_TypeDef * I2Cx)1590 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
1591 {
1592 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
1593 }
1594
1595 /**
1596 * @brief Indicate the status of Transfer complete flag (master mode).
1597 * @note RESET: Clear default value.
1598 * SET: When RELOAD=1 and NBYTES date have been transferred.
1599 * @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR
1600 * @param I2Cx I2C Instance.
1601 * @retval State of bit (1 or 0).
1602 */
LL_I2C_IsActiveFlag_TCR(I2C_TypeDef * I2Cx)1603 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
1604 {
1605 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
1606 }
1607
1608 /**
1609 * @brief Indicate the status of Bus error flag.
1610 * @note RESET: Clear default value.
1611 * SET: When a misplaced Start or Stop condition is detected.
1612 * @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR
1613 * @param I2Cx I2C Instance.
1614 * @retval State of bit (1 or 0).
1615 */
LL_I2C_IsActiveFlag_BERR(I2C_TypeDef * I2Cx)1616 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
1617 {
1618 return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
1619 }
1620
1621 /**
1622 * @brief Indicate the status of Arbitration lost flag.
1623 * @note RESET: Clear default value.
1624 * SET: When arbitration lost.
1625 * @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO
1626 * @param I2Cx I2C Instance.
1627 * @retval State of bit (1 or 0).
1628 */
LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef * I2Cx)1629 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
1630 {
1631 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
1632 }
1633
1634 /**
1635 * @brief Indicate the status of Overrun/Underrun flag (slave mode).
1636 * @note RESET: Clear default value.
1637 * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
1638 * @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR
1639 * @param I2Cx I2C Instance.
1640 * @retval State of bit (1 or 0).
1641 */
LL_I2C_IsActiveFlag_OVR(I2C_TypeDef * I2Cx)1642 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
1643 {
1644 return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
1645 }
1646
1647 /**
1648 * @brief Indicate the status of SMBus PEC error flag in reception.
1649 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1650 * SMBus feature is supported by the I2Cx Instance.
1651 * @note RESET: Clear default value.
1652 * SET: When the received PEC does not match with the PEC register content.
1653 * @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
1654 * @param I2Cx I2C Instance.
1655 * @retval State of bit (1 or 0).
1656 */
LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef * I2Cx)1657 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
1658 {
1659 return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
1660 }
1661
1662 /**
1663 * @brief Indicate the status of SMBus Timeout detection flag.
1664 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1665 * SMBus feature is supported by the I2Cx Instance.
1666 * @note RESET: Clear default value.
1667 * SET: When a timeout or extended clock timeout occurs.
1668 * @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
1669 * @param I2Cx I2C Instance.
1670 * @retval State of bit (1 or 0).
1671 */
LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef * I2Cx)1672 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
1673 {
1674 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
1675 }
1676
1677 /**
1678 * @brief Indicate the status of SMBus alert flag.
1679 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1680 * SMBus feature is supported by the I2Cx Instance.
1681 * @note RESET: Clear default value.
1682 * SET: When SMBus host configuration, SMBus alert enabled and
1683 * a falling edge event occurs on SMBA pin.
1684 * @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
1685 * @param I2Cx I2C Instance.
1686 * @retval State of bit (1 or 0).
1687 */
LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef * I2Cx)1688 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
1689 {
1690 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
1691 }
1692
1693 /**
1694 * @brief Indicate the status of Bus Busy flag.
1695 * @note RESET: Clear default value.
1696 * SET: When a Start condition is detected.
1697 * @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY
1698 * @param I2Cx I2C Instance.
1699 * @retval State of bit (1 or 0).
1700 */
LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef * I2Cx)1701 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
1702 {
1703 return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
1704 }
1705
1706 /**
1707 * @brief Clear Address Matched flag.
1708 * @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR
1709 * @param I2Cx I2C Instance.
1710 * @retval None
1711 */
LL_I2C_ClearFlag_ADDR(I2C_TypeDef * I2Cx)1712 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
1713 {
1714 SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
1715 }
1716
1717 /**
1718 * @brief Clear Not Acknowledge flag.
1719 * @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK
1720 * @param I2Cx I2C Instance.
1721 * @retval None
1722 */
LL_I2C_ClearFlag_NACK(I2C_TypeDef * I2Cx)1723 __STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
1724 {
1725 SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
1726 }
1727
1728 /**
1729 * @brief Clear Stop detection flag.
1730 * @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP
1731 * @param I2Cx I2C Instance.
1732 * @retval None
1733 */
LL_I2C_ClearFlag_STOP(I2C_TypeDef * I2Cx)1734 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
1735 {
1736 SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
1737 }
1738
1739 /**
1740 * @brief Clear Transmit data register empty flag (TXE).
1741 * @note This bit can be clear by software in order to flush the transmit data register (TXDR).
1742 * @rmtoll ISR TXE LL_I2C_ClearFlag_TXE
1743 * @param I2Cx I2C Instance.
1744 * @retval None
1745 */
LL_I2C_ClearFlag_TXE(I2C_TypeDef * I2Cx)1746 __STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
1747 {
1748 WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
1749 }
1750
1751 /**
1752 * @brief Clear Bus error flag.
1753 * @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR
1754 * @param I2Cx I2C Instance.
1755 * @retval None
1756 */
LL_I2C_ClearFlag_BERR(I2C_TypeDef * I2Cx)1757 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
1758 {
1759 SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
1760 }
1761
1762 /**
1763 * @brief Clear Arbitration lost flag.
1764 * @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO
1765 * @param I2Cx I2C Instance.
1766 * @retval None
1767 */
LL_I2C_ClearFlag_ARLO(I2C_TypeDef * I2Cx)1768 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
1769 {
1770 SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
1771 }
1772
1773 /**
1774 * @brief Clear Overrun/Underrun flag.
1775 * @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR
1776 * @param I2Cx I2C Instance.
1777 * @retval None
1778 */
LL_I2C_ClearFlag_OVR(I2C_TypeDef * I2Cx)1779 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
1780 {
1781 SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
1782 }
1783
1784 /**
1785 * @brief Clear SMBus PEC error flag.
1786 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1787 * SMBus feature is supported by the I2Cx Instance.
1788 * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
1789 * @param I2Cx I2C Instance.
1790 * @retval None
1791 */
LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef * I2Cx)1792 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
1793 {
1794 SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
1795 }
1796
1797 /**
1798 * @brief Clear SMBus Timeout detection flag.
1799 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1800 * SMBus feature is supported by the I2Cx Instance.
1801 * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
1802 * @param I2Cx I2C Instance.
1803 * @retval None
1804 */
LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef * I2Cx)1805 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
1806 {
1807 SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
1808 }
1809
1810 /**
1811 * @brief Clear SMBus Alert flag.
1812 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1813 * SMBus feature is supported by the I2Cx Instance.
1814 * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
1815 * @param I2Cx I2C Instance.
1816 * @retval None
1817 */
LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef * I2Cx)1818 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
1819 {
1820 SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
1821 }
1822
1823 /**
1824 * @}
1825 */
1826
1827 /** @defgroup I2C_LL_EF_Data_Management Data_Management
1828 * @{
1829 */
1830
1831 /**
1832 * @brief Enable automatic STOP condition generation (master mode).
1833 * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
1834 * This bit has no effect in slave mode or when RELOAD bit is set.
1835 * @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode
1836 * @param I2Cx I2C Instance.
1837 * @retval None
1838 */
LL_I2C_EnableAutoEndMode(I2C_TypeDef * I2Cx)1839 __STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
1840 {
1841 SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
1842 }
1843
1844 /**
1845 * @brief Disable automatic STOP condition generation (master mode).
1846 * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
1847 * @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode
1848 * @param I2Cx I2C Instance.
1849 * @retval None
1850 */
LL_I2C_DisableAutoEndMode(I2C_TypeDef * I2Cx)1851 __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
1852 {
1853 CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
1854 }
1855
1856 /**
1857 * @brief Check if automatic STOP condition is enabled or disabled.
1858 * @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
1859 * @param I2Cx I2C Instance.
1860 * @retval State of bit (1 or 0).
1861 */
LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef * I2Cx)1862 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
1863 {
1864 return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
1865 }
1866
1867 /**
1868 * @brief Enable reload mode (master mode).
1869 * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
1870 * @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode
1871 * @param I2Cx I2C Instance.
1872 * @retval None
1873 */
LL_I2C_EnableReloadMode(I2C_TypeDef * I2Cx)1874 __STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
1875 {
1876 SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
1877 }
1878
1879 /**
1880 * @brief Disable reload mode (master mode).
1881 * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
1882 * @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode
1883 * @param I2Cx I2C Instance.
1884 * @retval None
1885 */
LL_I2C_DisableReloadMode(I2C_TypeDef * I2Cx)1886 __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
1887 {
1888 CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
1889 }
1890
1891 /**
1892 * @brief Check if reload mode is enabled or disabled.
1893 * @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode
1894 * @param I2Cx I2C Instance.
1895 * @retval State of bit (1 or 0).
1896 */
LL_I2C_IsEnabledReloadMode(I2C_TypeDef * I2Cx)1897 __STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
1898 {
1899 return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
1900 }
1901
1902 /**
1903 * @brief Configure the number of bytes for transfer.
1904 * @note Changing these bits when START bit is set is not allowed.
1905 * @rmtoll CR2 NBYTES LL_I2C_SetTransferSize
1906 * @param I2Cx I2C Instance.
1907 * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
1908 * @retval None
1909 */
LL_I2C_SetTransferSize(I2C_TypeDef * I2Cx,uint32_t TransferSize)1910 __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
1911 {
1912 MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
1913 }
1914
1915 /**
1916 * @brief Get the number of bytes configured for transfer.
1917 * @rmtoll CR2 NBYTES LL_I2C_GetTransferSize
1918 * @param I2Cx I2C Instance.
1919 * @retval Value between Min_Data=0x0 and Max_Data=0xFF
1920 */
LL_I2C_GetTransferSize(I2C_TypeDef * I2Cx)1921 __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
1922 {
1923 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
1924 }
1925
1926 /**
1927 * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code
1928 or next received byte.
1929 * @note Usage in Slave mode only.
1930 * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData
1931 * @param I2Cx I2C Instance.
1932 * @param TypeAcknowledge This parameter can be one of the following values:
1933 * @arg @ref LL_I2C_ACK
1934 * @arg @ref LL_I2C_NACK
1935 * @retval None
1936 */
LL_I2C_AcknowledgeNextData(I2C_TypeDef * I2Cx,uint32_t TypeAcknowledge)1937 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
1938 {
1939 MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
1940 }
1941
1942 /**
1943 * @brief Generate a START or RESTART condition
1944 * @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
1945 * This action has no effect when RELOAD is set.
1946 * @rmtoll CR2 START LL_I2C_GenerateStartCondition
1947 * @param I2Cx I2C Instance.
1948 * @retval None
1949 */
LL_I2C_GenerateStartCondition(I2C_TypeDef * I2Cx)1950 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
1951 {
1952 SET_BIT(I2Cx->CR2, I2C_CR2_START);
1953 }
1954
1955 /**
1956 * @brief Generate a STOP condition after the current byte transfer (master mode).
1957 * @rmtoll CR2 STOP LL_I2C_GenerateStopCondition
1958 * @param I2Cx I2C Instance.
1959 * @retval None
1960 */
LL_I2C_GenerateStopCondition(I2C_TypeDef * I2Cx)1961 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
1962 {
1963 SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
1964 }
1965
1966 /**
1967 * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
1968 * @note The master sends the complete 10bit slave address read sequence :
1969 * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address
1970 in Read direction.
1971 * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead
1972 * @param I2Cx I2C Instance.
1973 * @retval None
1974 */
LL_I2C_EnableAuto10BitRead(I2C_TypeDef * I2Cx)1975 __STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
1976 {
1977 CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
1978 }
1979
1980 /**
1981 * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode).
1982 * @note The master only sends the first 7 bits of 10bit address in Read direction.
1983 * @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead
1984 * @param I2Cx I2C Instance.
1985 * @retval None
1986 */
LL_I2C_DisableAuto10BitRead(I2C_TypeDef * I2Cx)1987 __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
1988 {
1989 SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
1990 }
1991
1992 /**
1993 * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
1994 * @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
1995 * @param I2Cx I2C Instance.
1996 * @retval State of bit (1 or 0).
1997 */
LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef * I2Cx)1998 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
1999 {
2000 return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
2001 }
2002
2003 /**
2004 * @brief Configure the transfer direction (master mode).
2005 * @note Changing these bits when START bit is set is not allowed.
2006 * @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest
2007 * @param I2Cx I2C Instance.
2008 * @param TransferRequest This parameter can be one of the following values:
2009 * @arg @ref LL_I2C_REQUEST_WRITE
2010 * @arg @ref LL_I2C_REQUEST_READ
2011 * @retval None
2012 */
LL_I2C_SetTransferRequest(I2C_TypeDef * I2Cx,uint32_t TransferRequest)2013 __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
2014 {
2015 MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
2016 }
2017
2018 /**
2019 * @brief Get the transfer direction requested (master mode).
2020 * @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest
2021 * @param I2Cx I2C Instance.
2022 * @retval Returned value can be one of the following values:
2023 * @arg @ref LL_I2C_REQUEST_WRITE
2024 * @arg @ref LL_I2C_REQUEST_READ
2025 */
LL_I2C_GetTransferRequest(I2C_TypeDef * I2Cx)2026 __STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
2027 {
2028 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
2029 }
2030
2031 /**
2032 * @brief Configure the slave address for transfer (master mode).
2033 * @note Changing these bits when START bit is set is not allowed.
2034 * @rmtoll CR2 SADD LL_I2C_SetSlaveAddr
2035 * @param I2Cx I2C Instance.
2036 * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
2037 * @retval None
2038 */
LL_I2C_SetSlaveAddr(I2C_TypeDef * I2Cx,uint32_t SlaveAddr)2039 __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
2040 {
2041 MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
2042 }
2043
2044 /**
2045 * @brief Get the slave address programmed for transfer.
2046 * @rmtoll CR2 SADD LL_I2C_GetSlaveAddr
2047 * @param I2Cx I2C Instance.
2048 * @retval Value between Min_Data=0x0 and Max_Data=0x3F
2049 */
LL_I2C_GetSlaveAddr(I2C_TypeDef * I2Cx)2050 __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
2051 {
2052 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
2053 }
2054
2055 /**
2056 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
2057 * @rmtoll CR2 SADD LL_I2C_HandleTransfer\n
2058 * CR2 ADD10 LL_I2C_HandleTransfer\n
2059 * CR2 RD_WRN LL_I2C_HandleTransfer\n
2060 * CR2 START LL_I2C_HandleTransfer\n
2061 * CR2 STOP LL_I2C_HandleTransfer\n
2062 * CR2 RELOAD LL_I2C_HandleTransfer\n
2063 * CR2 NBYTES LL_I2C_HandleTransfer\n
2064 * CR2 AUTOEND LL_I2C_HandleTransfer\n
2065 * CR2 HEAD10R LL_I2C_HandleTransfer
2066 * @param I2Cx I2C Instance.
2067 * @param SlaveAddr Specifies the slave address to be programmed.
2068 * @param SlaveAddrSize This parameter can be one of the following values:
2069 * @arg @ref LL_I2C_ADDRSLAVE_7BIT
2070 * @arg @ref LL_I2C_ADDRSLAVE_10BIT
2071 * @param TransferSize Specifies the number of bytes to be programmed.
2072 * This parameter must be a value between Min_Data=0 and Max_Data=255.
2073 * @param EndMode This parameter can be one of the following values:
2074 * @arg @ref LL_I2C_MODE_RELOAD
2075 * @arg @ref LL_I2C_MODE_AUTOEND
2076 * @arg @ref LL_I2C_MODE_SOFTEND
2077 * @arg @ref LL_I2C_MODE_SMBUS_RELOAD
2078 * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
2079 * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
2080 * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
2081 * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
2082 * @param Request This parameter can be one of the following values:
2083 * @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
2084 * @arg @ref LL_I2C_GENERATE_STOP
2085 * @arg @ref LL_I2C_GENERATE_START_READ
2086 * @arg @ref LL_I2C_GENERATE_START_WRITE
2087 * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
2088 * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
2089 * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
2090 * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
2091 * @retval None
2092 */
LL_I2C_HandleTransfer(I2C_TypeDef * I2Cx,uint32_t SlaveAddr,uint32_t SlaveAddrSize,uint32_t TransferSize,uint32_t EndMode,uint32_t Request)2093 __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
2094 uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
2095 {
2096 MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
2097 (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
2098 I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
2099 I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
2100 SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
2101 }
2102
2103 /**
2104 * @brief Indicate the value of transfer direction (slave mode).
2105 * @note RESET: Write transfer, Slave enters in receiver mode.
2106 * SET: Read transfer, Slave enters in transmitter mode.
2107 * @rmtoll ISR DIR LL_I2C_GetTransferDirection
2108 * @param I2Cx I2C Instance.
2109 * @retval Returned value can be one of the following values:
2110 * @arg @ref LL_I2C_DIRECTION_WRITE
2111 * @arg @ref LL_I2C_DIRECTION_READ
2112 */
LL_I2C_GetTransferDirection(I2C_TypeDef * I2Cx)2113 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
2114 {
2115 return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
2116 }
2117
2118 /**
2119 * @brief Return the slave matched address.
2120 * @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode
2121 * @param I2Cx I2C Instance.
2122 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
2123 */
LL_I2C_GetAddressMatchCode(I2C_TypeDef * I2Cx)2124 __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
2125 {
2126 return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
2127 }
2128
2129 /**
2130 * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
2131 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2132 * SMBus feature is supported by the I2Cx Instance.
2133 * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition
2134 or an Address Matched is received.
2135 * This bit has no effect when RELOAD bit is set.
2136 * This bit has no effect in device mode when SBC bit is not set.
2137 * @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
2138 * @param I2Cx I2C Instance.
2139 * @retval None
2140 */
LL_I2C_EnableSMBusPECCompare(I2C_TypeDef * I2Cx)2141 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
2142 {
2143 SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
2144 }
2145
2146 /**
2147 * @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
2148 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2149 * SMBus feature is supported by the I2Cx Instance.
2150 * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
2151 * @param I2Cx I2C Instance.
2152 * @retval State of bit (1 or 0).
2153 */
LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef * I2Cx)2154 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
2155 {
2156 return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
2157 }
2158
2159 /**
2160 * @brief Get the SMBus Packet Error byte calculated.
2161 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2162 * SMBus feature is supported by the I2Cx Instance.
2163 * @rmtoll PECR PEC LL_I2C_GetSMBusPEC
2164 * @param I2Cx I2C Instance.
2165 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
2166 */
LL_I2C_GetSMBusPEC(I2C_TypeDef * I2Cx)2167 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
2168 {
2169 return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
2170 }
2171
2172 /**
2173 * @brief Read Receive Data register.
2174 * @rmtoll RXDR RXDATA LL_I2C_ReceiveData8
2175 * @param I2Cx I2C Instance.
2176 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
2177 */
LL_I2C_ReceiveData8(I2C_TypeDef * I2Cx)2178 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
2179 {
2180 return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
2181 }
2182
2183 /**
2184 * @brief Write in Transmit Data Register .
2185 * @rmtoll TXDR TXDATA LL_I2C_TransmitData8
2186 * @param I2Cx I2C Instance.
2187 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
2188 * @retval None
2189 */
LL_I2C_TransmitData8(I2C_TypeDef * I2Cx,uint8_t Data)2190 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
2191 {
2192 WRITE_REG(I2Cx->TXDR, Data);
2193 }
2194
2195 /**
2196 * @}
2197 */
2198
2199 #if defined(USE_FULL_LL_DRIVER)
2200 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
2201 * @{
2202 */
2203
2204 ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
2205 ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx);
2206 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
2207
2208
2209 /**
2210 * @}
2211 */
2212 #endif /* USE_FULL_LL_DRIVER */
2213
2214 /**
2215 * @}
2216 */
2217
2218 /**
2219 * @}
2220 */
2221
2222 #endif /* I2C1 || I2C2 || I2C3 || I2C4 */
2223
2224 /**
2225 * @}
2226 */
2227
2228 #ifdef __cplusplus
2229 }
2230 #endif
2231
2232 #endif /* STM32F7xx_LL_I2C_H */
2233
