1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_dma2d.h
4 * @author MCD Application Team
5 * @brief Header file of DMA2D LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32F7xx_LL_DMA2D_H
21 #define STM32F7xx_LL_DMA2D_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f7xx.h"
29
30 /** @addtogroup STM32F7xx_LL_Driver
31 * @{
32 */
33
34 #if defined (DMA2D)
35
36 /** @defgroup DMA2D_LL DMA2D
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 #if defined(USE_FULL_LL_DRIVER)
45 /** @defgroup DMA2D_LL_Private_Macros DMA2D Private Macros
46 * @{
47 */
48
49 /**
50 * @}
51 */
52 #endif /*USE_FULL_LL_DRIVER*/
53
54 /* Exported types ------------------------------------------------------------*/
55 #if defined(USE_FULL_LL_DRIVER)
56 /** @defgroup DMA2D_LL_ES_Init_Struct DMA2D Exported Init structures
57 * @{
58 */
59
60 /**
61 * @brief LL DMA2D Init Structure Definition
62 */
63 typedef struct
64 {
65 uint32_t Mode; /*!< Specifies the DMA2D transfer mode.
66 - This parameter can be one value of @ref DMA2D_LL_EC_MODE.
67
68 This parameter can be modified afterwards,
69 using unitary function @ref LL_DMA2D_SetMode(). */
70
71 uint32_t ColorMode; /*!< Specifies the color format of the output image.
72 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
73
74 This parameter can be modified afterwards using,
75 unitary function @ref LL_DMA2D_SetOutputColorMode(). */
76
77 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
78 - This parameter must be a number between:
79 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
80 - This parameter must be a number between:
81 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
82 - This parameter must be a number between:
83 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
84 - This parameter must be a number between:
85 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
86 - This parameter must be a number between:
87 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
88
89 This parameter can be modified afterwards,
90 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
91 function @ref LL_DMA2D_ConfigOutputColor(). */
92
93 uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
94 - This parameter must be a number between:
95 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
96 - This parameter must be a number between:
97 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
98 - This parameter must be a number between:
99 Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
100 - This parameter must be a number between:
101 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
102 - This parameter must be a number between:
103 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
104
105 This parameter can be modified afterwards
106 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
107 function @ref LL_DMA2D_ConfigOutputColor(). */
108
109 uint32_t OutputRed; /*!< Specifies the Red value of the output image.
110 - This parameter must be a number between:
111 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
112 - This parameter must be a number between:
113 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
114 - This parameter must be a number between:
115 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
116 - This parameter must be a number between:
117 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
118 - This parameter must be a number between:
119 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
120
121 This parameter can be modified afterwards
122 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
123 function @ref LL_DMA2D_ConfigOutputColor(). */
124
125 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
126 - This parameter must be a number between:
127 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
128 - This parameter must be a number between:
129 Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
130 - This parameter must be a number between:
131 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
132 - This parameter is not considered if RGB888 or RGB565 color mode is selected.
133
134 This parameter can be modified afterwards using,
135 unitary function @ref LL_DMA2D_SetOutputColor() or configuration
136 function @ref LL_DMA2D_ConfigOutputColor(). */
137
138 uint32_t OutputMemoryAddress; /*!< Specifies the memory address.
139 - This parameter must be a number between:
140 Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
141
142 This parameter can be modified afterwards,
143 using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
144
145
146
147 uint32_t LineOffset; /*!< Specifies the output line offset value.
148 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
149
150 This parameter can be modified afterwards,
151 using unitary function @ref LL_DMA2D_SetLineOffset(). */
152
153 uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred.
154 - This parameter must be a number between:
155 Min_Data = 0x0000 and Max_Data = 0xFFFF.
156
157 This parameter can be modified afterwards,
158 using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
159
160 uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transferred.
161 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
162
163 This parameter can be modified afterwards using,
164 unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
165
166 #if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
167 uint32_t AlphaInversionMode; /*!< Specifies the output alpha inversion mode.
168 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
169
170 This parameter can be modified afterwards using,
171 unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */
172
173 uint32_t RBSwapMode; /*!< Specifies the output Red Blue swap mode.
174 - This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP.
175
176 This parameter can be modified afterwards using,
177 unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */
178 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
179
180 } LL_DMA2D_InitTypeDef;
181
182 /**
183 * @brief LL DMA2D Layer Configuration Structure Definition
184 */
185 typedef struct
186 {
187 uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address.
188 - This parameter must be a number between:
189 Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
190
191 This parameter can be modified afterwards using unitary functions
192 - @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer,
193 - @ref LL_DMA2D_BGND_SetMemAddr() for background layer. */
194
195 uint32_t LineOffset; /*!< Specifies the foreground or background line offset value.
196 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
197
198 This parameter can be modified afterwards using unitary functions
199 - @ref LL_DMA2D_FGND_SetLineOffset() for foreground layer,
200 - @ref LL_DMA2D_BGND_SetLineOffset() for background layer. */
201
202 uint32_t ColorMode; /*!< Specifies the foreground or background color mode.
203 - This parameter can be one value of @ref DMA2D_LL_EC_INPUT_COLOR_MODE.
204
205 This parameter can be modified afterwards using unitary functions
206 - @ref LL_DMA2D_FGND_SetColorMode() for foreground layer,
207 - @ref LL_DMA2D_BGND_SetColorMode() for background layer. */
208
209 uint32_t CLUTColorMode; /*!< Specifies the foreground or background CLUT color mode.
210 - This parameter can be one value of @ref DMA2D_LL_EC_CLUT_COLOR_MODE.
211
212 This parameter can be modified afterwards using unitary functions
213 - @ref LL_DMA2D_FGND_SetCLUTColorMode() for foreground layer,
214 - @ref LL_DMA2D_BGND_SetCLUTColorMode() for background layer. */
215
216 uint32_t CLUTSize; /*!< Specifies the foreground or background CLUT size.
217 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
218
219 This parameter can be modified afterwards using unitary functions
220 - @ref LL_DMA2D_FGND_SetCLUTSize() for foreground layer,
221 - @ref LL_DMA2D_BGND_SetCLUTSize() for background layer. */
222
223 uint32_t AlphaMode; /*!< Specifies the foreground or background alpha mode.
224 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_MODE.
225
226 This parameter can be modified afterwards using unitary functions
227 - @ref LL_DMA2D_FGND_SetAlphaMode() for foreground layer,
228 - @ref LL_DMA2D_BGND_SetAlphaMode() for background layer. */
229
230 uint32_t Alpha; /*!< Specifies the foreground or background Alpha value.
231 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
232
233 This parameter can be modified afterwards using unitary functions
234 - @ref LL_DMA2D_FGND_SetAlpha() for foreground layer,
235 - @ref LL_DMA2D_BGND_SetAlpha() for background layer. */
236
237 uint32_t Blue; /*!< Specifies the foreground or background Blue color value.
238 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
239
240 This parameter can be modified afterwards using unitary functions
241 - @ref LL_DMA2D_FGND_SetBlueColor() for foreground layer,
242 - @ref LL_DMA2D_BGND_SetBlueColor() for background layer. */
243
244 uint32_t Green; /*!< Specifies the foreground or background Green color value.
245 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
246
247 This parameter can be modified afterwards using unitary functions
248 - @ref LL_DMA2D_FGND_SetGreenColor() for foreground layer,
249 - @ref LL_DMA2D_BGND_SetGreenColor() for background layer. */
250
251 uint32_t Red; /*!< Specifies the foreground or background Red color value.
252 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
253
254 This parameter can be modified afterwards using unitary functions
255 - @ref LL_DMA2D_FGND_SetRedColor() for foreground layer,
256 - @ref LL_DMA2D_BGND_SetRedColor() for background layer. */
257
258 uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address.
259 - This parameter must be a number between:
260 Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
261
262 This parameter can be modified afterwards using unitary functions
263 - @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer,
264 - @ref LL_DMA2D_BGND_SetCLUTMemAddr() for background layer. */
265
266 #if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
267 uint32_t AlphaInversionMode; /*!< Specifies the foreground or background alpha inversion mode.
268 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
269
270 This parameter can be modified afterwards using unitary functions
271 - @ref LL_DMA2D_FGND_SetAlphaInvMode() for foreground layer,
272 - @ref LL_DMA2D_BGND_SetAlphaInvMode() for background layer. */
273
274 uint32_t RBSwapMode; /*!< Specifies the foreground or background Red Blue swap mode.
275 This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP .
276
277 This parameter can be modified afterwards using unitary functions
278 - @ref LL_DMA2D_FGND_SetRBSwapMode() for foreground layer,
279 - @ref LL_DMA2D_BGND_SetRBSwapMode() for background layer. */
280 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
281
282
283 } LL_DMA2D_LayerCfgTypeDef;
284
285 /**
286 * @brief LL DMA2D Output Color Structure Definition
287 */
288 typedef struct
289 {
290 uint32_t ColorMode; /*!< Specifies the color format of the output image.
291 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
292
293 This parameter can be modified afterwards using
294 unitary function @ref LL_DMA2D_SetOutputColorMode(). */
295
296 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
297 - This parameter must be a number between:
298 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
299 - This parameter must be a number between:
300 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
301 - This parameter must be a number between:
302 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
303 - This parameter must be a number between:
304 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
305 - This parameter must be a number between:
306 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
307
308 This parameter can be modified afterwards using,
309 unitary function @ref LL_DMA2D_SetOutputColor() or configuration
310 function @ref LL_DMA2D_ConfigOutputColor(). */
311
312 uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
313 - This parameter must be a number between:
314 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
315 - This parameter must be a number between
316 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
317 - This parameter must be a number between:
318 Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
319 - This parameter must be a number between:
320 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
321 - This parameter must be a number between:
322 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
323
324 This parameter can be modified afterwards,
325 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
326 function @ref LL_DMA2D_ConfigOutputColor(). */
327
328 uint32_t OutputRed; /*!< Specifies the Red value of the output image.
329 - This parameter must be a number between:
330 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
331 - This parameter must be a number between:
332 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
333 - This parameter must be a number between:
334 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
335 - This parameter must be a number between:
336 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
337 - This parameter must be a number between:
338 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
339
340 This parameter can be modified afterwards,
341 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
342 function @ref LL_DMA2D_ConfigOutputColor(). */
343
344 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
345 - This parameter must be a number between:
346 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
347 - This parameter must be a number between:
348 Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
349 - This parameter must be a number between:
350 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
351 - This parameter is not considered if RGB888 or RGB565 color mode is selected.
352
353 This parameter can be modified afterwards,
354 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
355 function @ref LL_DMA2D_ConfigOutputColor(). */
356
357 } LL_DMA2D_ColorTypeDef;
358
359 /**
360 * @}
361 */
362 #endif /* USE_FULL_LL_DRIVER */
363
364 /* Exported constants --------------------------------------------------------*/
365 /** @defgroup DMA2D_LL_Exported_Constants DMA2D Exported Constants
366 * @{
367 */
368
369 /** @defgroup DMA2D_LL_EC_GET_FLAG Get Flags Defines
370 * @brief Flags defines which can be used with LL_DMA2D_ReadReg function
371 * @{
372 */
373 #define LL_DMA2D_FLAG_CEIF DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
374 #define LL_DMA2D_FLAG_CTCIF DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */
375 #define LL_DMA2D_FLAG_CAEIF DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */
376 #define LL_DMA2D_FLAG_TWIF DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
377 #define LL_DMA2D_FLAG_TCIF DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
378 #define LL_DMA2D_FLAG_TEIF DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
379 /**
380 * @}
381 */
382
383 /** @defgroup DMA2D_LL_EC_IT IT Defines
384 * @brief IT defines which can be used with LL_DMA2D_ReadReg and LL_DMA2D_WriteReg functions
385 * @{
386 */
387 #define LL_DMA2D_IT_CEIE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
388 #define LL_DMA2D_IT_CTCIE DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */
389 #define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
390 #define LL_DMA2D_IT_TWIE DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
391 #define LL_DMA2D_IT_TCIE DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
392 #define LL_DMA2D_IT_TEIE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
393 /**
394 * @}
395 */
396
397 /** @defgroup DMA2D_LL_EC_MODE Mode
398 * @{
399 */
400 #define LL_DMA2D_MODE_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */
401 #define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
402 #define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
403 #define LL_DMA2D_MODE_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */
404 /**
405 * @}
406 */
407
408 /** @defgroup DMA2D_LL_EC_OUTPUT_COLOR_MODE Output Color Mode
409 * @{
410 */
411 #define LL_DMA2D_OUTPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
412 #define LL_DMA2D_OUTPUT_MODE_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 */
413 #define LL_DMA2D_OUTPUT_MODE_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 */
414 #define LL_DMA2D_OUTPUT_MODE_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 */
415 #define LL_DMA2D_OUTPUT_MODE_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 */
416 /**
417 * @}
418 */
419
420 /** @defgroup DMA2D_LL_EC_INPUT_COLOR_MODE Input Color Mode
421 * @{
422 */
423 #define LL_DMA2D_INPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
424 #define LL_DMA2D_INPUT_MODE_RGB888 DMA2D_FGPFCCR_CM_0 /*!< RGB888 */
425 #define LL_DMA2D_INPUT_MODE_RGB565 DMA2D_FGPFCCR_CM_1 /*!< RGB565 */
426 #define LL_DMA2D_INPUT_MODE_ARGB1555 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1) /*!< ARGB1555 */
427 #define LL_DMA2D_INPUT_MODE_ARGB4444 DMA2D_FGPFCCR_CM_2 /*!< ARGB4444 */
428 #define LL_DMA2D_INPUT_MODE_L8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2) /*!< L8 */
429 #define LL_DMA2D_INPUT_MODE_AL44 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL44 */
430 #define LL_DMA2D_INPUT_MODE_AL88 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL88 */
431 #define LL_DMA2D_INPUT_MODE_L4 DMA2D_FGPFCCR_CM_3 /*!< L4 */
432 #define LL_DMA2D_INPUT_MODE_A8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3) /*!< A8 */
433 #define LL_DMA2D_INPUT_MODE_A4 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< A4 */
434 /**
435 * @}
436 */
437
438 /** @defgroup DMA2D_LL_EC_ALPHA_MODE Alpha Mode
439 * @{
440 */
441 #define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /*!< No modification of the alpha channel value */
442 #define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by
443 programmed alpha value */
444 #define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by
445 programmed alpha value with,
446 original alpha channel value */
447 /**
448 * @}
449 */
450
451
452 #if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
453 /** @defgroup DMA2D_LL_EC_RED_BLUE_SWAP Red Blue Swap
454 * @{
455 */
456 #define LL_DMA2D_RB_MODE_REGULAR 0x00000000U /*!< RGB or ARGB */
457 #define LL_DMA2D_RB_MODE_SWAP DMA2D_FGPFCCR_RBS /*!< BGR or ABGR */
458 /**
459 * @}
460 */
461
462 /** @defgroup DMA2D_LL_EC_ALPHA_INVERSION Alpha Inversion
463 * @{
464 */
465 #define LL_DMA2D_ALPHA_REGULAR 0x00000000U /*!< Regular alpha */
466 #define LL_DMA2D_ALPHA_INVERTED DMA2D_FGPFCCR_AI /*!< Inverted alpha */
467 /**
468 * @}
469 */
470
471 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
472
473
474 /** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode
475 * @{
476 */
477 #define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
478 #define LL_DMA2D_CLUT_COLOR_MODE_RGB888 DMA2D_FGPFCCR_CCM /*!< RGB888 */
479 /**
480 * @}
481 */
482
483
484 /**
485 * @}
486 */
487
488 /* Exported macro ------------------------------------------------------------*/
489 /** @defgroup DMA2D_LL_Exported_Macros DMA2D Exported Macros
490 * @{
491 */
492
493 /** @defgroup DMA2D_LL_EM_WRITE_READ Common Write and read registers Macros
494 * @{
495 */
496
497 /**
498 * @brief Write a value in DMA2D register.
499 * @param __INSTANCE__ DMA2D Instance
500 * @param __REG__ Register to be written
501 * @param __VALUE__ Value to be written in the register
502 * @retval None
503 */
504 #define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
505
506 /**
507 * @brief Read a value in DMA2D register.
508 * @param __INSTANCE__ DMA2D Instance
509 * @param __REG__ Register to be read
510 * @retval Register value
511 */
512 #define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
513 /**
514 * @}
515 */
516
517 /**
518 * @}
519 */
520
521 /* Exported functions --------------------------------------------------------*/
522 /** @defgroup DMA2D_LL_Exported_Functions DMA2D Exported Functions
523 * @{
524 */
525
526 /** @defgroup DMA2D_LL_EF_Configuration Configuration Functions
527 * @{
528 */
529
530 /**
531 * @brief Start a DMA2D transfer.
532 * @rmtoll CR START LL_DMA2D_Start
533 * @param DMA2Dx DMA2D Instance
534 * @retval None
535 */
LL_DMA2D_Start(DMA2D_TypeDef * DMA2Dx)536 __STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx)
537 {
538 SET_BIT(DMA2Dx->CR, DMA2D_CR_START);
539 }
540
541 /**
542 * @brief Indicate if a DMA2D transfer is ongoing.
543 * @rmtoll CR START LL_DMA2D_IsTransferOngoing
544 * @param DMA2Dx DMA2D Instance
545 * @retval State of bit (1 or 0).
546 */
LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef * DMA2Dx)547 __STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx)
548 {
549 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL);
550 }
551
552 /**
553 * @brief Suspend DMA2D transfer.
554 * @note This API can be used to suspend automatic foreground or background CLUT loading.
555 * @rmtoll CR SUSP LL_DMA2D_Suspend
556 * @param DMA2Dx DMA2D Instance
557 * @retval None
558 */
LL_DMA2D_Suspend(DMA2D_TypeDef * DMA2Dx)559 __STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx)
560 {
561 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);
562 }
563
564 /**
565 * @brief Resume DMA2D transfer.
566 * @note This API can be used to resume automatic foreground or background CLUT loading.
567 * @rmtoll CR SUSP LL_DMA2D_Resume
568 * @param DMA2Dx DMA2D Instance
569 * @retval None
570 */
LL_DMA2D_Resume(DMA2D_TypeDef * DMA2Dx)571 __STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx)
572 {
573 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START);
574 }
575
576 /**
577 * @brief Indicate if DMA2D transfer is suspended.
578 * @note This API can be used to indicate whether or not automatic foreground or
579 * background CLUT loading is suspended.
580 * @rmtoll CR SUSP LL_DMA2D_IsSuspended
581 * @param DMA2Dx DMA2D Instance
582 * @retval State of bit (1 or 0).
583 */
LL_DMA2D_IsSuspended(DMA2D_TypeDef * DMA2Dx)584 __STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx)
585 {
586 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL);
587 }
588
589 /**
590 * @brief Abort DMA2D transfer.
591 * @note This API can be used to abort automatic foreground or background CLUT loading.
592 * @rmtoll CR ABORT LL_DMA2D_Abort
593 * @param DMA2Dx DMA2D Instance
594 * @retval None
595 */
LL_DMA2D_Abort(DMA2D_TypeDef * DMA2Dx)596 __STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx)
597 {
598 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);
599 }
600
601 /**
602 * @brief Indicate if DMA2D transfer is aborted.
603 * @note This API can be used to indicate whether or not automatic foreground or
604 * background CLUT loading is aborted.
605 * @rmtoll CR ABORT LL_DMA2D_IsAborted
606 * @param DMA2Dx DMA2D Instance
607 * @retval State of bit (1 or 0).
608 */
LL_DMA2D_IsAborted(DMA2D_TypeDef * DMA2Dx)609 __STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx)
610 {
611 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL);
612 }
613
614 /**
615 * @brief Set DMA2D mode.
616 * @rmtoll CR MODE LL_DMA2D_SetMode
617 * @param DMA2Dx DMA2D Instance
618 * @param Mode This parameter can be one of the following values:
619 * @arg @ref LL_DMA2D_MODE_M2M
620 * @arg @ref LL_DMA2D_MODE_M2M_PFC
621 * @arg @ref LL_DMA2D_MODE_M2M_BLEND
622 * @arg @ref LL_DMA2D_MODE_R2M
623 * @retval None
624 */
LL_DMA2D_SetMode(DMA2D_TypeDef * DMA2Dx,uint32_t Mode)625 __STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode)
626 {
627 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode);
628 }
629
630 /**
631 * @brief Return DMA2D mode
632 * @rmtoll CR MODE LL_DMA2D_GetMode
633 * @param DMA2Dx DMA2D Instance
634 * @retval Returned value can be one of the following values:
635 * @arg @ref LL_DMA2D_MODE_M2M
636 * @arg @ref LL_DMA2D_MODE_M2M_PFC
637 * @arg @ref LL_DMA2D_MODE_M2M_BLEND
638 * @arg @ref LL_DMA2D_MODE_R2M
639 */
LL_DMA2D_GetMode(DMA2D_TypeDef * DMA2Dx)640 __STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx)
641 {
642 return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE));
643 }
644
645 /**
646 * @brief Set DMA2D output color mode.
647 * @rmtoll OPFCCR CM LL_DMA2D_SetOutputColorMode
648 * @param DMA2Dx DMA2D Instance
649 * @param ColorMode This parameter can be one of the following values:
650 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
651 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
652 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
653 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
654 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
655 * @retval None
656 */
LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t ColorMode)657 __STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
658 {
659 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode);
660 }
661
662 /**
663 * @brief Return DMA2D output color mode.
664 * @rmtoll OPFCCR CM LL_DMA2D_GetOutputColorMode
665 * @param DMA2Dx DMA2D Instance
666 * @retval Returned value can be one of the following values:
667 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
668 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
669 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
670 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
671 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
672 */
LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef * DMA2Dx)673 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx)
674 {
675 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM));
676 }
677
678 #if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
679 /**
680 * @brief Set DMA2D output Red Blue swap mode.
681 * @rmtoll OPFCCR RBS LL_DMA2D_SetOutputRBSwapMode
682 * @param DMA2Dx DMA2D Instance
683 * @param RBSwapMode This parameter can be one of the following values:
684 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
685 * @arg @ref LL_DMA2D_RB_MODE_SWAP
686 * @retval None
687 */
LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef * DMA2Dx,uint32_t RBSwapMode)688 __STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
689 {
690 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS, RBSwapMode);
691 }
692
693 /**
694 * @brief Return DMA2D output Red Blue swap mode.
695 * @rmtoll OPFCCR RBS LL_DMA2D_GetOutputRBSwapMode
696 * @param DMA2Dx DMA2D Instance
697 * @retval Returned value can be one of the following values:
698 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
699 * @arg @ref LL_DMA2D_RB_MODE_SWAP
700 */
LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef * DMA2Dx)701 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx)
702 {
703 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS));
704 }
705
706 /**
707 * @brief Set DMA2D output alpha inversion mode.
708 * @rmtoll OPFCCR AI LL_DMA2D_SetOutputAlphaInvMode
709 * @param DMA2Dx DMA2D Instance
710 * @param AlphaInversionMode This parameter can be one of the following values:
711 * @arg @ref LL_DMA2D_ALPHA_REGULAR
712 * @arg @ref LL_DMA2D_ALPHA_INVERTED
713 * @retval None
714 */
LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef * DMA2Dx,uint32_t AlphaInversionMode)715 __STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
716 {
717 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI, AlphaInversionMode);
718 }
719
720 /**
721 * @brief Return DMA2D output alpha inversion mode.
722 * @rmtoll OPFCCR AI LL_DMA2D_GetOutputAlphaInvMode
723 * @param DMA2Dx DMA2D Instance
724 * @retval Returned value can be one of the following values:
725 * @arg @ref LL_DMA2D_ALPHA_REGULAR
726 * @arg @ref LL_DMA2D_ALPHA_INVERTED
727 */
LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef * DMA2Dx)728 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
729 {
730 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI));
731 }
732
733 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
734
735
736
737 /**
738 * @brief Set DMA2D line offset, expressed on 14 bits ([13:0] bits).
739 * @rmtoll OOR LO LL_DMA2D_SetLineOffset
740 * @param DMA2Dx DMA2D Instance
741 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FFF
742 * @retval None
743 */
LL_DMA2D_SetLineOffset(DMA2D_TypeDef * DMA2Dx,uint32_t LineOffset)744 __STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
745 {
746 MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset);
747 }
748
749 /**
750 * @brief Return DMA2D line offset, expressed on 14 bits ([13:0] bits).
751 * @rmtoll OOR LO LL_DMA2D_GetLineOffset
752 * @param DMA2Dx DMA2D Instance
753 * @retval Line offset value between Min_Data=0 and Max_Data=0x3FFF
754 */
LL_DMA2D_GetLineOffset(DMA2D_TypeDef * DMA2Dx)755 __STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
756 {
757 return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO));
758 }
759
760 /**
761 * @brief Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits).
762 * @rmtoll NLR PL LL_DMA2D_SetNbrOfPixelsPerLines
763 * @param DMA2Dx DMA2D Instance
764 * @param NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF
765 * @retval None
766 */
LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef * DMA2Dx,uint32_t NbrOfPixelsPerLines)767 __STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines)
768 {
769 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos));
770 }
771
772 /**
773 * @brief Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits)
774 * @rmtoll NLR PL LL_DMA2D_GetNbrOfPixelsPerLines
775 * @param DMA2Dx DMA2D Instance
776 * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF
777 */
LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef * DMA2Dx)778 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx)
779 {
780 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos);
781 }
782
783 /**
784 * @brief Set DMA2D number of lines, expressed on 16 bits ([15:0] bits).
785 * @rmtoll NLR NL LL_DMA2D_SetNbrOfLines
786 * @param DMA2Dx DMA2D Instance
787 * @param NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF
788 * @retval None
789 */
LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef * DMA2Dx,uint32_t NbrOfLines)790 __STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines)
791 {
792 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_NL, NbrOfLines);
793 }
794
795 /**
796 * @brief Return DMA2D number of lines, expressed on 16 bits ([15:0] bits).
797 * @rmtoll NLR NL LL_DMA2D_GetNbrOfLines
798 * @param DMA2Dx DMA2D Instance
799 * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF
800 */
LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef * DMA2Dx)801 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx)
802 {
803 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL));
804 }
805
806 /**
807 * @brief Set DMA2D output memory address, expressed on 32 bits ([31:0] bits).
808 * @rmtoll OMAR MA LL_DMA2D_SetOutputMemAddr
809 * @param DMA2Dx DMA2D Instance
810 * @param OutputMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
811 * @retval None
812 */
LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t OutputMemoryAddress)813 __STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress)
814 {
815 LL_DMA2D_WriteReg(DMA2Dx, OMAR, OutputMemoryAddress);
816 }
817
818 /**
819 * @brief Get DMA2D output memory address, expressed on 32 bits ([31:0] bits).
820 * @rmtoll OMAR MA LL_DMA2D_GetOutputMemAddr
821 * @param DMA2Dx DMA2D Instance
822 * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
823 */
LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef * DMA2Dx)824 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx)
825 {
826 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR));
827 }
828
829 /**
830 * @brief Set DMA2D output color, expressed on 32 bits ([31:0] bits).
831 * @note Output color format depends on output color mode, ARGB8888, RGB888,
832 * RGB565, ARGB1555 or ARGB4444.
833 * @note LL_DMA2D_ConfigOutputColor() API may be used instead if colors values formatting
834 * with respect to color mode is not done by the user code.
835 * @rmtoll OCOLR BLUE LL_DMA2D_SetOutputColor\n
836 * OCOLR GREEN LL_DMA2D_SetOutputColor\n
837 * OCOLR RED LL_DMA2D_SetOutputColor\n
838 * OCOLR ALPHA LL_DMA2D_SetOutputColor
839 * @param DMA2Dx DMA2D Instance
840 * @param OutputColor Value between Min_Data=0 and Max_Data=0xFFFFFFFF
841 * @retval None
842 */
LL_DMA2D_SetOutputColor(DMA2D_TypeDef * DMA2Dx,uint32_t OutputColor)843 __STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor)
844 {
845 MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \
846 OutputColor);
847 }
848
849 /**
850 * @brief Get DMA2D output color, expressed on 32 bits ([31:0] bits).
851 * @note Alpha channel and red, green, blue color values must be retrieved from the returned
852 * value based on the output color mode (ARGB8888, RGB888, RGB565, ARGB1555 or ARGB4444)
853 * as set by @ref LL_DMA2D_SetOutputColorMode.
854 * @rmtoll OCOLR BLUE LL_DMA2D_GetOutputColor\n
855 * OCOLR GREEN LL_DMA2D_GetOutputColor\n
856 * OCOLR RED LL_DMA2D_GetOutputColor\n
857 * OCOLR ALPHA LL_DMA2D_GetOutputColor
858 * @param DMA2Dx DMA2D Instance
859 * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF
860 */
LL_DMA2D_GetOutputColor(DMA2D_TypeDef * DMA2Dx)861 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx)
862 {
863 return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \
864 (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1)));
865 }
866
867 /**
868 * @brief Set DMA2D line watermark, expressed on 16 bits ([15:0] bits).
869 * @rmtoll LWR LW LL_DMA2D_SetLineWatermark
870 * @param DMA2Dx DMA2D Instance
871 * @param LineWatermark Value between Min_Data=0 and Max_Data=0xFFFF
872 * @retval None
873 */
LL_DMA2D_SetLineWatermark(DMA2D_TypeDef * DMA2Dx,uint32_t LineWatermark)874 __STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark)
875 {
876 MODIFY_REG(DMA2Dx->LWR, DMA2D_LWR_LW, LineWatermark);
877 }
878
879 /**
880 * @brief Return DMA2D line watermark, expressed on 16 bits ([15:0] bits).
881 * @rmtoll LWR LW LL_DMA2D_GetLineWatermark
882 * @param DMA2Dx DMA2D Instance
883 * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF
884 */
LL_DMA2D_GetLineWatermark(DMA2D_TypeDef * DMA2Dx)885 __STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx)
886 {
887 return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW));
888 }
889
890 /**
891 * @brief Set DMA2D dead time, expressed on 8 bits ([7:0] bits).
892 * @rmtoll AMTCR DT LL_DMA2D_SetDeadTime
893 * @param DMA2Dx DMA2D Instance
894 * @param DeadTime Value between Min_Data=0 and Max_Data=0xFF
895 * @retval None
896 */
LL_DMA2D_SetDeadTime(DMA2D_TypeDef * DMA2Dx,uint32_t DeadTime)897 __STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime)
898 {
899 MODIFY_REG(DMA2Dx->AMTCR, DMA2D_AMTCR_DT, (DeadTime << DMA2D_AMTCR_DT_Pos));
900 }
901
902 /**
903 * @brief Return DMA2D dead time, expressed on 8 bits ([7:0] bits).
904 * @rmtoll AMTCR DT LL_DMA2D_GetDeadTime
905 * @param DMA2Dx DMA2D Instance
906 * @retval Dead time value between Min_Data=0 and Max_Data=0xFF
907 */
LL_DMA2D_GetDeadTime(DMA2D_TypeDef * DMA2Dx)908 __STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx)
909 {
910 return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos);
911 }
912
913 /**
914 * @brief Enable DMA2D dead time functionality.
915 * @rmtoll AMTCR EN LL_DMA2D_EnableDeadTime
916 * @param DMA2Dx DMA2D Instance
917 * @retval None
918 */
LL_DMA2D_EnableDeadTime(DMA2D_TypeDef * DMA2Dx)919 __STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx)
920 {
921 SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
922 }
923
924 /**
925 * @brief Disable DMA2D dead time functionality.
926 * @rmtoll AMTCR EN LL_DMA2D_DisableDeadTime
927 * @param DMA2Dx DMA2D Instance
928 * @retval None
929 */
LL_DMA2D_DisableDeadTime(DMA2D_TypeDef * DMA2Dx)930 __STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx)
931 {
932 CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
933 }
934
935 /**
936 * @brief Indicate if DMA2D dead time functionality is enabled.
937 * @rmtoll AMTCR EN LL_DMA2D_IsEnabledDeadTime
938 * @param DMA2Dx DMA2D Instance
939 * @retval State of bit (1 or 0).
940 */
LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef * DMA2Dx)941 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx)
942 {
943 return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL);
944 }
945
946 /** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions
947 * @{
948 */
949
950 /**
951 * @brief Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
952 * @rmtoll FGMAR MA LL_DMA2D_FGND_SetMemAddr
953 * @param DMA2Dx DMA2D Instance
954 * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
955 * @retval None
956 */
LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t MemoryAddress)957 __STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
958 {
959 LL_DMA2D_WriteReg(DMA2Dx, FGMAR, MemoryAddress);
960 }
961
962 /**
963 * @brief Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
964 * @rmtoll FGMAR MA LL_DMA2D_FGND_GetMemAddr
965 * @param DMA2Dx DMA2D Instance
966 * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
967 */
LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef * DMA2Dx)968 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
969 {
970 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR));
971 }
972
973 /**
974 * @brief Enable DMA2D foreground CLUT loading.
975 * @rmtoll FGPFCCR START LL_DMA2D_FGND_EnableCLUTLoad
976 * @param DMA2Dx DMA2D Instance
977 * @retval None
978 */
LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef * DMA2Dx)979 __STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
980 {
981 SET_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START);
982 }
983
984 /**
985 * @brief Indicate if DMA2D foreground CLUT loading is enabled.
986 * @rmtoll FGPFCCR START LL_DMA2D_FGND_IsEnabledCLUTLoad
987 * @param DMA2Dx DMA2D Instance
988 * @retval State of bit (1 or 0).
989 */
LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef * DMA2Dx)990 __STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
991 {
992 return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL);
993 }
994
995 /**
996 * @brief Set DMA2D foreground color mode.
997 * @rmtoll FGPFCCR CM LL_DMA2D_FGND_SetColorMode
998 * @param DMA2Dx DMA2D Instance
999 * @param ColorMode This parameter can be one of the following values:
1000 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1001 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1002 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1003 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1004 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1005 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1006 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1007 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1008 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1009 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1010 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1011 * @retval None
1012 */
LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t ColorMode)1013 __STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
1014 {
1015 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM, ColorMode);
1016 }
1017
1018 /**
1019 * @brief Return DMA2D foreground color mode.
1020 * @rmtoll FGPFCCR CM LL_DMA2D_FGND_GetColorMode
1021 * @param DMA2Dx DMA2D Instance
1022 * @retval Returned value can be one of the following values:
1023 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1024 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1025 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1026 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1027 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1028 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1029 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1030 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1031 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1032 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1033 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1034 */
LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef * DMA2Dx)1035 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
1036 {
1037 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM));
1038 }
1039
1040 /**
1041 * @brief Set DMA2D foreground alpha mode.
1042 * @rmtoll FGPFCCR AM LL_DMA2D_FGND_SetAlphaMode
1043 * @param DMA2Dx DMA2D Instance
1044 * @param AphaMode This parameter can be one of the following values:
1045 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1046 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1047 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1048 * @retval None
1049 */
LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef * DMA2Dx,uint32_t AphaMode)1050 __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
1051 {
1052 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM, AphaMode);
1053 }
1054
1055 /**
1056 * @brief Return DMA2D foreground alpha mode.
1057 * @rmtoll FGPFCCR AM LL_DMA2D_FGND_GetAlphaMode
1058 * @param DMA2Dx DMA2D Instance
1059 * @retval Returned value can be one of the following values:
1060 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1061 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1062 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1063 */
LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef * DMA2Dx)1064 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
1065 {
1066 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM));
1067 }
1068
1069 /**
1070 * @brief Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
1071 * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_SetAlpha
1072 * @param DMA2Dx DMA2D Instance
1073 * @param Alpha Value between Min_Data=0 and Max_Data=0xFF
1074 * @retval None
1075 */
LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef * DMA2Dx,uint32_t Alpha)1076 __STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
1077 {
1078 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA, (Alpha << DMA2D_FGPFCCR_ALPHA_Pos));
1079 }
1080
1081 /**
1082 * @brief Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
1083 * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_GetAlpha
1084 * @param DMA2Dx DMA2D Instance
1085 * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
1086 */
LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef * DMA2Dx)1087 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
1088 {
1089 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos);
1090 }
1091
1092 #if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
1093 /**
1094 * @brief Set DMA2D foreground Red Blue swap mode.
1095 * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_SetRBSwapMode
1096 * @param DMA2Dx DMA2D Instance
1097 * @param RBSwapMode This parameter can be one of the following values:
1098 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1099 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1100 * @retval None
1101 */
LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef * DMA2Dx,uint32_t RBSwapMode)1102 __STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
1103 {
1104 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS, RBSwapMode);
1105 }
1106
1107 /**
1108 * @brief Return DMA2D foreground Red Blue swap mode.
1109 * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_GetRBSwapMode
1110 * @param DMA2Dx DMA2D Instance
1111 * @retval Returned value can be one of the following values:
1112 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1113 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1114 */
LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef * DMA2Dx)1115 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)
1116 {
1117 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS));
1118 }
1119
1120 /**
1121 * @brief Set DMA2D foreground alpha inversion mode.
1122 * @rmtoll FGPFCCR AI LL_DMA2D_FGND_SetAlphaInvMode
1123 * @param DMA2Dx DMA2D Instance
1124 * @param AlphaInversionMode This parameter can be one of the following values:
1125 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1126 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1127 * @retval None
1128 */
LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef * DMA2Dx,uint32_t AlphaInversionMode)1129 __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
1130 {
1131 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI, AlphaInversionMode);
1132 }
1133
1134 /**
1135 * @brief Return DMA2D foreground alpha inversion mode.
1136 * @rmtoll FGPFCCR AI LL_DMA2D_FGND_GetAlphaInvMode
1137 * @param DMA2Dx DMA2D Instance
1138 * @retval Returned value can be one of the following values:
1139 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1140 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1141 */
LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef * DMA2Dx)1142 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
1143 {
1144 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI));
1145 }
1146
1147 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
1148
1149 /**
1150 * @brief Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
1151 * @rmtoll FGOR LO LL_DMA2D_FGND_SetLineOffset
1152 * @param DMA2Dx DMA2D Instance
1153 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
1154 * @retval None
1155 */
LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef * DMA2Dx,uint32_t LineOffset)1156 __STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
1157 {
1158 MODIFY_REG(DMA2Dx->FGOR, DMA2D_FGOR_LO, LineOffset);
1159 }
1160
1161 /**
1162 * @brief Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
1163 * @rmtoll FGOR LO LL_DMA2D_FGND_GetLineOffset
1164 * @param DMA2Dx DMA2D Instance
1165 * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF
1166 */
LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef * DMA2Dx)1167 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
1168 {
1169 return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO));
1170 }
1171
1172 /**
1173 * @brief Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits).
1174 * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetColor
1175 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetColor
1176 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetColor
1177 * @param DMA2Dx DMA2D Instance
1178 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1179 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1180 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1181 * @retval None
1182 */
LL_DMA2D_FGND_SetColor(DMA2D_TypeDef * DMA2Dx,uint32_t Red,uint32_t Green,uint32_t Blue)1183 __STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
1184 {
1185 MODIFY_REG(DMA2Dx->FGCOLR, (DMA2D_FGCOLR_RED | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_BLUE), \
1186 ((Red << DMA2D_FGCOLR_RED_Pos) | (Green << DMA2D_FGCOLR_GREEN_Pos) | Blue));
1187 }
1188
1189 /**
1190 * @brief Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
1191 * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetRedColor
1192 * @param DMA2Dx DMA2D Instance
1193 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1194 * @retval None
1195 */
LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef * DMA2Dx,uint32_t Red)1196 __STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
1197 {
1198 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED, (Red << DMA2D_FGCOLR_RED_Pos));
1199 }
1200
1201 /**
1202 * @brief Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
1203 * @rmtoll FGCOLR RED LL_DMA2D_FGND_GetRedColor
1204 * @param DMA2Dx DMA2D Instance
1205 * @retval Red color value between Min_Data=0 and Max_Data=0xFF
1206 */
LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef * DMA2Dx)1207 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
1208 {
1209 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos);
1210 }
1211
1212 /**
1213 * @brief Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
1214 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetGreenColor
1215 * @param DMA2Dx DMA2D Instance
1216 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1217 * @retval None
1218 */
LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef * DMA2Dx,uint32_t Green)1219 __STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
1220 {
1221 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN, (Green << DMA2D_FGCOLR_GREEN_Pos));
1222 }
1223
1224 /**
1225 * @brief Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
1226 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_GetGreenColor
1227 * @param DMA2Dx DMA2D Instance
1228 * @retval Green color value between Min_Data=0 and Max_Data=0xFF
1229 */
LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef * DMA2Dx)1230 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
1231 {
1232 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos);
1233 }
1234
1235 /**
1236 * @brief Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
1237 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetBlueColor
1238 * @param DMA2Dx DMA2D Instance
1239 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1240 * @retval None
1241 */
LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef * DMA2Dx,uint32_t Blue)1242 __STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
1243 {
1244 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE, Blue);
1245 }
1246
1247 /**
1248 * @brief Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
1249 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_GetBlueColor
1250 * @param DMA2Dx DMA2D Instance
1251 * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
1252 */
LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef * DMA2Dx)1253 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
1254 {
1255 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE));
1256 }
1257
1258 /**
1259 * @brief Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
1260 * @rmtoll FGCMAR MA LL_DMA2D_FGND_SetCLUTMemAddr
1261 * @param DMA2Dx DMA2D Instance
1262 * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1263 * @retval None
1264 */
LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTMemoryAddress)1265 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
1266 {
1267 LL_DMA2D_WriteReg(DMA2Dx, FGCMAR, CLUTMemoryAddress);
1268 }
1269
1270 /**
1271 * @brief Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
1272 * @rmtoll FGCMAR MA LL_DMA2D_FGND_GetCLUTMemAddr
1273 * @param DMA2Dx DMA2D Instance
1274 * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1275 */
LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef * DMA2Dx)1276 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
1277 {
1278 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR));
1279 }
1280
1281 /**
1282 * @brief Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
1283 * @rmtoll FGPFCCR CS LL_DMA2D_FGND_SetCLUTSize
1284 * @param DMA2Dx DMA2D Instance
1285 * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
1286 * @retval None
1287 */
LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTSize)1288 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
1289 {
1290 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS, (CLUTSize << DMA2D_FGPFCCR_CS_Pos));
1291 }
1292
1293 /**
1294 * @brief Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
1295 * @rmtoll FGPFCCR CS LL_DMA2D_FGND_GetCLUTSize
1296 * @param DMA2Dx DMA2D Instance
1297 * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF
1298 */
LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef * DMA2Dx)1299 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
1300 {
1301 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos);
1302 }
1303
1304 /**
1305 * @brief Set DMA2D foreground CLUT color mode.
1306 * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_SetCLUTColorMode
1307 * @param DMA2Dx DMA2D Instance
1308 * @param CLUTColorMode This parameter can be one of the following values:
1309 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1310 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1311 * @retval None
1312 */
LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTColorMode)1313 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
1314 {
1315 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM, CLUTColorMode);
1316 }
1317
1318 /**
1319 * @brief Return DMA2D foreground CLUT color mode.
1320 * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_GetCLUTColorMode
1321 * @param DMA2Dx DMA2D Instance
1322 * @retval Returned value can be one of the following values:
1323 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1324 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1325 */
LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef * DMA2Dx)1326 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
1327 {
1328 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM));
1329 }
1330
1331 /**
1332 * @}
1333 */
1334
1335 /** @defgroup DMA2D_LL_EF_BGND_Configuration Background Configuration Functions
1336 * @{
1337 */
1338
1339 /**
1340 * @brief Set DMA2D background memory address, expressed on 32 bits ([31:0] bits).
1341 * @rmtoll BGMAR MA LL_DMA2D_BGND_SetMemAddr
1342 * @param DMA2Dx DMA2D Instance
1343 * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1344 * @retval None
1345 */
LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t MemoryAddress)1346 __STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
1347 {
1348 LL_DMA2D_WriteReg(DMA2Dx, BGMAR, MemoryAddress);
1349 }
1350
1351 /**
1352 * @brief Get DMA2D background memory address, expressed on 32 bits ([31:0] bits).
1353 * @rmtoll BGMAR MA LL_DMA2D_BGND_GetMemAddr
1354 * @param DMA2Dx DMA2D Instance
1355 * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1356 */
LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef * DMA2Dx)1357 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
1358 {
1359 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR));
1360 }
1361
1362 /**
1363 * @brief Enable DMA2D background CLUT loading.
1364 * @rmtoll BGPFCCR START LL_DMA2D_BGND_EnableCLUTLoad
1365 * @param DMA2Dx DMA2D Instance
1366 * @retval None
1367 */
LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef * DMA2Dx)1368 __STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1369 {
1370 SET_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START);
1371 }
1372
1373 /**
1374 * @brief Indicate if DMA2D background CLUT loading is enabled.
1375 * @rmtoll BGPFCCR START LL_DMA2D_BGND_IsEnabledCLUTLoad
1376 * @param DMA2Dx DMA2D Instance
1377 * @retval State of bit (1 or 0).
1378 */
LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef * DMA2Dx)1379 __STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1380 {
1381 return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL);
1382 }
1383
1384 /**
1385 * @brief Set DMA2D background color mode.
1386 * @rmtoll BGPFCCR CM LL_DMA2D_BGND_SetColorMode
1387 * @param DMA2Dx DMA2D Instance
1388 * @param ColorMode This parameter can be one of the following values:
1389 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1390 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1391 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1392 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1393 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1394 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1395 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1396 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1397 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1398 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1399 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1400 * @retval None
1401 */
LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t ColorMode)1402 __STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
1403 {
1404 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM, ColorMode);
1405 }
1406
1407 /**
1408 * @brief Return DMA2D background color mode.
1409 * @rmtoll BGPFCCR CM LL_DMA2D_BGND_GetColorMode
1410 * @param DMA2Dx DMA2D Instance
1411 * @retval Returned value can be one of the following values:
1412 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1413 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1414 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1415 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1416 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1417 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1418 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1419 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1420 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1421 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1422 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1423 */
LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef * DMA2Dx)1424 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
1425 {
1426 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM));
1427 }
1428
1429 /**
1430 * @brief Set DMA2D background alpha mode.
1431 * @rmtoll BGPFCCR AM LL_DMA2D_BGND_SetAlphaMode
1432 * @param DMA2Dx DMA2D Instance
1433 * @param AphaMode This parameter can be one of the following values:
1434 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1435 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1436 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1437 * @retval None
1438 */
LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef * DMA2Dx,uint32_t AphaMode)1439 __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
1440 {
1441 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM, AphaMode);
1442 }
1443
1444 /**
1445 * @brief Return DMA2D background alpha mode.
1446 * @rmtoll BGPFCCR AM LL_DMA2D_BGND_GetAlphaMode
1447 * @param DMA2Dx DMA2D Instance
1448 * @retval Returned value can be one of the following values:
1449 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1450 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1451 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1452 */
LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef * DMA2Dx)1453 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
1454 {
1455 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM));
1456 }
1457
1458 /**
1459 * @brief Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
1460 * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_SetAlpha
1461 * @param DMA2Dx DMA2D Instance
1462 * @param Alpha Value between Min_Data=0 and Max_Data=0xFF
1463 * @retval None
1464 */
LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef * DMA2Dx,uint32_t Alpha)1465 __STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
1466 {
1467 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA, (Alpha << DMA2D_BGPFCCR_ALPHA_Pos));
1468 }
1469
1470 /**
1471 * @brief Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
1472 * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_GetAlpha
1473 * @param DMA2Dx DMA2D Instance
1474 * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
1475 */
LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef * DMA2Dx)1476 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
1477 {
1478 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos);
1479 }
1480
1481 #if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
1482 /**
1483 * @brief Set DMA2D background Red Blue swap mode.
1484 * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_SetRBSwapMode
1485 * @param DMA2Dx DMA2D Instance
1486 * @param RBSwapMode This parameter can be one of the following values:
1487 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1488 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1489 * @retval None
1490 */
LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef * DMA2Dx,uint32_t RBSwapMode)1491 __STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
1492 {
1493 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS, RBSwapMode);
1494 }
1495
1496 /**
1497 * @brief Return DMA2D background Red Blue swap mode.
1498 * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_GetRBSwapMode
1499 * @param DMA2Dx DMA2D Instance
1500 * @retval Returned value can be one of the following values:
1501 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1502 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1503 */
LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef * DMA2Dx)1504 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)
1505 {
1506 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS));
1507 }
1508
1509 /**
1510 * @brief Set DMA2D background alpha inversion mode.
1511 * @rmtoll BGPFCCR AI LL_DMA2D_BGND_SetAlphaInvMode
1512 * @param DMA2Dx DMA2D Instance
1513 * @param AlphaInversionMode This parameter can be one of the following values:
1514 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1515 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1516 * @retval None
1517 */
LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef * DMA2Dx,uint32_t AlphaInversionMode)1518 __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
1519 {
1520 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI, AlphaInversionMode);
1521 }
1522
1523 /**
1524 * @brief Return DMA2D background alpha inversion mode.
1525 * @rmtoll BGPFCCR AI LL_DMA2D_BGND_GetAlphaInvMode
1526 * @param DMA2Dx DMA2D Instance
1527 * @retval Returned value can be one of the following values:
1528 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1529 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1530 */
LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef * DMA2Dx)1531 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
1532 {
1533 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI));
1534 }
1535
1536 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
1537
1538 /**
1539 * @brief Set DMA2D background line offset, expressed on 14 bits ([13:0] bits).
1540 * @rmtoll BGOR LO LL_DMA2D_BGND_SetLineOffset
1541 * @param DMA2Dx DMA2D Instance
1542 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
1543 * @retval None
1544 */
LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef * DMA2Dx,uint32_t LineOffset)1545 __STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
1546 {
1547 MODIFY_REG(DMA2Dx->BGOR, DMA2D_BGOR_LO, LineOffset);
1548 }
1549
1550 /**
1551 * @brief Return DMA2D background line offset, expressed on 14 bits ([13:0] bits).
1552 * @rmtoll BGOR LO LL_DMA2D_BGND_GetLineOffset
1553 * @param DMA2Dx DMA2D Instance
1554 * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF
1555 */
LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef * DMA2Dx)1556 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
1557 {
1558 return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO));
1559 }
1560
1561 /**
1562 * @brief Set DMA2D background color values, expressed on 24 bits ([23:0] bits).
1563 * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetColor
1564 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetColor
1565 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetColor
1566 * @param DMA2Dx DMA2D Instance
1567 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1568 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1569 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1570 * @retval None
1571 */
LL_DMA2D_BGND_SetColor(DMA2D_TypeDef * DMA2Dx,uint32_t Red,uint32_t Green,uint32_t Blue)1572 __STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
1573 {
1574 MODIFY_REG(DMA2Dx->BGCOLR, (DMA2D_BGCOLR_RED | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_BLUE), \
1575 ((Red << DMA2D_BGCOLR_RED_Pos) | (Green << DMA2D_BGCOLR_GREEN_Pos) | Blue));
1576 }
1577
1578 /**
1579 * @brief Set DMA2D background red color value, expressed on 8 bits ([7:0] bits).
1580 * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetRedColor
1581 * @param DMA2Dx DMA2D Instance
1582 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1583 * @retval None
1584 */
LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef * DMA2Dx,uint32_t Red)1585 __STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
1586 {
1587 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED, (Red << DMA2D_BGCOLR_RED_Pos));
1588 }
1589
1590 /**
1591 * @brief Return DMA2D background red color value, expressed on 8 bits ([7:0] bits).
1592 * @rmtoll BGCOLR RED LL_DMA2D_BGND_GetRedColor
1593 * @param DMA2Dx DMA2D Instance
1594 * @retval Red color value between Min_Data=0 and Max_Data=0xFF
1595 */
LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef * DMA2Dx)1596 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
1597 {
1598 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos);
1599 }
1600
1601 /**
1602 * @brief Set DMA2D background green color value, expressed on 8 bits ([7:0] bits).
1603 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetGreenColor
1604 * @param DMA2Dx DMA2D Instance
1605 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1606 * @retval None
1607 */
LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef * DMA2Dx,uint32_t Green)1608 __STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
1609 {
1610 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN, (Green << DMA2D_BGCOLR_GREEN_Pos));
1611 }
1612
1613 /**
1614 * @brief Return DMA2D background green color value, expressed on 8 bits ([7:0] bits).
1615 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_GetGreenColor
1616 * @param DMA2Dx DMA2D Instance
1617 * @retval Green color value between Min_Data=0 and Max_Data=0xFF
1618 */
LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef * DMA2Dx)1619 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
1620 {
1621 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos);
1622 }
1623
1624 /**
1625 * @brief Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
1626 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetBlueColor
1627 * @param DMA2Dx DMA2D Instance
1628 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1629 * @retval None
1630 */
LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef * DMA2Dx,uint32_t Blue)1631 __STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
1632 {
1633 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE, Blue);
1634 }
1635
1636 /**
1637 * @brief Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
1638 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_GetBlueColor
1639 * @param DMA2Dx DMA2D Instance
1640 * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
1641 */
LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef * DMA2Dx)1642 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
1643 {
1644 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE));
1645 }
1646
1647 /**
1648 * @brief Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
1649 * @rmtoll BGCMAR MA LL_DMA2D_BGND_SetCLUTMemAddr
1650 * @param DMA2Dx DMA2D Instance
1651 * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1652 * @retval None
1653 */
LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTMemoryAddress)1654 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
1655 {
1656 LL_DMA2D_WriteReg(DMA2Dx, BGCMAR, CLUTMemoryAddress);
1657 }
1658
1659 /**
1660 * @brief Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
1661 * @rmtoll BGCMAR MA LL_DMA2D_BGND_GetCLUTMemAddr
1662 * @param DMA2Dx DMA2D Instance
1663 * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1664 */
LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef * DMA2Dx)1665 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
1666 {
1667 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR));
1668 }
1669
1670 /**
1671 * @brief Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
1672 * @rmtoll BGPFCCR CS LL_DMA2D_BGND_SetCLUTSize
1673 * @param DMA2Dx DMA2D Instance
1674 * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
1675 * @retval None
1676 */
LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTSize)1677 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
1678 {
1679 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS, (CLUTSize << DMA2D_BGPFCCR_CS_Pos));
1680 }
1681
1682 /**
1683 * @brief Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
1684 * @rmtoll BGPFCCR CS LL_DMA2D_BGND_GetCLUTSize
1685 * @param DMA2Dx DMA2D Instance
1686 * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF
1687 */
LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef * DMA2Dx)1688 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
1689 {
1690 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos);
1691 }
1692
1693 /**
1694 * @brief Set DMA2D background CLUT color mode.
1695 * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_SetCLUTColorMode
1696 * @param DMA2Dx DMA2D Instance
1697 * @param CLUTColorMode This parameter can be one of the following values:
1698 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1699 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1700 * @retval None
1701 */
LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTColorMode)1702 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
1703 {
1704 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM, CLUTColorMode);
1705 }
1706
1707 /**
1708 * @brief Return DMA2D background CLUT color mode.
1709 * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_GetCLUTColorMode
1710 * @param DMA2Dx DMA2D Instance
1711 * @retval Returned value can be one of the following values:
1712 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1713 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1714 */
LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef * DMA2Dx)1715 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
1716 {
1717 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM));
1718 }
1719
1720 /**
1721 * @}
1722 */
1723
1724 /**
1725 * @}
1726 */
1727
1728
1729 /** @defgroup DMA2D_LL_EF_FLAG_MANAGEMENT Flag Management
1730 * @{
1731 */
1732
1733 /**
1734 * @brief Check if the DMA2D Configuration Error Interrupt Flag is set or not
1735 * @rmtoll ISR CEIF LL_DMA2D_IsActiveFlag_CE
1736 * @param DMA2Dx DMA2D Instance
1737 * @retval State of bit (1 or 0).
1738 */
LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef * DMA2Dx)1739 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx)
1740 {
1741 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL);
1742 }
1743
1744 /**
1745 * @brief Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not
1746 * @rmtoll ISR CTCIF LL_DMA2D_IsActiveFlag_CTC
1747 * @param DMA2Dx DMA2D Instance
1748 * @retval State of bit (1 or 0).
1749 */
LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef * DMA2Dx)1750 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx)
1751 {
1752 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL);
1753 }
1754
1755 /**
1756 * @brief Check if the DMA2D CLUT Access Error Interrupt Flag is set or not
1757 * @rmtoll ISR CAEIF LL_DMA2D_IsActiveFlag_CAE
1758 * @param DMA2Dx DMA2D Instance
1759 * @retval State of bit (1 or 0).
1760 */
LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef * DMA2Dx)1761 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx)
1762 {
1763 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL);
1764 }
1765
1766 /**
1767 * @brief Check if the DMA2D Transfer Watermark Interrupt Flag is set or not
1768 * @rmtoll ISR TWIF LL_DMA2D_IsActiveFlag_TW
1769 * @param DMA2Dx DMA2D Instance
1770 * @retval State of bit (1 or 0).
1771 */
LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef * DMA2Dx)1772 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx)
1773 {
1774 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL);
1775 }
1776
1777 /**
1778 * @brief Check if the DMA2D Transfer Complete Interrupt Flag is set or not
1779 * @rmtoll ISR TCIF LL_DMA2D_IsActiveFlag_TC
1780 * @param DMA2Dx DMA2D Instance
1781 * @retval State of bit (1 or 0).
1782 */
LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef * DMA2Dx)1783 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx)
1784 {
1785 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL);
1786 }
1787
1788 /**
1789 * @brief Check if the DMA2D Transfer Error Interrupt Flag is set or not
1790 * @rmtoll ISR TEIF LL_DMA2D_IsActiveFlag_TE
1791 * @param DMA2Dx DMA2D Instance
1792 * @retval State of bit (1 or 0).
1793 */
LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef * DMA2Dx)1794 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx)
1795 {
1796 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL);
1797 }
1798
1799 /**
1800 * @brief Clear DMA2D Configuration Error Interrupt Flag
1801 * @rmtoll IFCR CCEIF LL_DMA2D_ClearFlag_CE
1802 * @param DMA2Dx DMA2D Instance
1803 * @retval None
1804 */
LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef * DMA2Dx)1805 __STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx)
1806 {
1807 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF);
1808 }
1809
1810 /**
1811 * @brief Clear DMA2D CLUT Transfer Complete Interrupt Flag
1812 * @rmtoll IFCR CCTCIF LL_DMA2D_ClearFlag_CTC
1813 * @param DMA2Dx DMA2D Instance
1814 * @retval None
1815 */
LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef * DMA2Dx)1816 __STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx)
1817 {
1818 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF);
1819 }
1820
1821 /**
1822 * @brief Clear DMA2D CLUT Access Error Interrupt Flag
1823 * @rmtoll IFCR CAECIF LL_DMA2D_ClearFlag_CAE
1824 * @param DMA2Dx DMA2D Instance
1825 * @retval None
1826 */
LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef * DMA2Dx)1827 __STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx)
1828 {
1829 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF);
1830 }
1831
1832 /**
1833 * @brief Clear DMA2D Transfer Watermark Interrupt Flag
1834 * @rmtoll IFCR CTWIF LL_DMA2D_ClearFlag_TW
1835 * @param DMA2Dx DMA2D Instance
1836 * @retval None
1837 */
LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef * DMA2Dx)1838 __STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx)
1839 {
1840 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF);
1841 }
1842
1843 /**
1844 * @brief Clear DMA2D Transfer Complete Interrupt Flag
1845 * @rmtoll IFCR CTCIF LL_DMA2D_ClearFlag_TC
1846 * @param DMA2Dx DMA2D Instance
1847 * @retval None
1848 */
LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef * DMA2Dx)1849 __STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx)
1850 {
1851 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF);
1852 }
1853
1854 /**
1855 * @brief Clear DMA2D Transfer Error Interrupt Flag
1856 * @rmtoll IFCR CTEIF LL_DMA2D_ClearFlag_TE
1857 * @param DMA2Dx DMA2D Instance
1858 * @retval None
1859 */
LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef * DMA2Dx)1860 __STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx)
1861 {
1862 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF);
1863 }
1864
1865 /**
1866 * @}
1867 */
1868
1869 /** @defgroup DMA2D_LL_EF_IT_MANAGEMENT Interruption Management
1870 * @{
1871 */
1872
1873 /**
1874 * @brief Enable Configuration Error Interrupt
1875 * @rmtoll CR CEIE LL_DMA2D_EnableIT_CE
1876 * @param DMA2Dx DMA2D Instance
1877 * @retval None
1878 */
LL_DMA2D_EnableIT_CE(DMA2D_TypeDef * DMA2Dx)1879 __STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx)
1880 {
1881 SET_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
1882 }
1883
1884 /**
1885 * @brief Enable CLUT Transfer Complete Interrupt
1886 * @rmtoll CR CTCIE LL_DMA2D_EnableIT_CTC
1887 * @param DMA2Dx DMA2D Instance
1888 * @retval None
1889 */
LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef * DMA2Dx)1890 __STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx)
1891 {
1892 SET_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
1893 }
1894
1895 /**
1896 * @brief Enable CLUT Access Error Interrupt
1897 * @rmtoll CR CAEIE LL_DMA2D_EnableIT_CAE
1898 * @param DMA2Dx DMA2D Instance
1899 * @retval None
1900 */
LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef * DMA2Dx)1901 __STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx)
1902 {
1903 SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
1904 }
1905
1906 /**
1907 * @brief Enable Transfer Watermark Interrupt
1908 * @rmtoll CR TWIE LL_DMA2D_EnableIT_TW
1909 * @param DMA2Dx DMA2D Instance
1910 * @retval None
1911 */
LL_DMA2D_EnableIT_TW(DMA2D_TypeDef * DMA2Dx)1912 __STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx)
1913 {
1914 SET_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
1915 }
1916
1917 /**
1918 * @brief Enable Transfer Complete Interrupt
1919 * @rmtoll CR TCIE LL_DMA2D_EnableIT_TC
1920 * @param DMA2Dx DMA2D Instance
1921 * @retval None
1922 */
LL_DMA2D_EnableIT_TC(DMA2D_TypeDef * DMA2Dx)1923 __STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx)
1924 {
1925 SET_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
1926 }
1927
1928 /**
1929 * @brief Enable Transfer Error Interrupt
1930 * @rmtoll CR TEIE LL_DMA2D_EnableIT_TE
1931 * @param DMA2Dx DMA2D Instance
1932 * @retval None
1933 */
LL_DMA2D_EnableIT_TE(DMA2D_TypeDef * DMA2Dx)1934 __STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx)
1935 {
1936 SET_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
1937 }
1938
1939 /**
1940 * @brief Disable Configuration Error Interrupt
1941 * @rmtoll CR CEIE LL_DMA2D_DisableIT_CE
1942 * @param DMA2Dx DMA2D Instance
1943 * @retval None
1944 */
LL_DMA2D_DisableIT_CE(DMA2D_TypeDef * DMA2Dx)1945 __STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx)
1946 {
1947 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
1948 }
1949
1950 /**
1951 * @brief Disable CLUT Transfer Complete Interrupt
1952 * @rmtoll CR CTCIE LL_DMA2D_DisableIT_CTC
1953 * @param DMA2Dx DMA2D Instance
1954 * @retval None
1955 */
LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef * DMA2Dx)1956 __STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx)
1957 {
1958 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
1959 }
1960
1961 /**
1962 * @brief Disable CLUT Access Error Interrupt
1963 * @rmtoll CR CAEIE LL_DMA2D_DisableIT_CAE
1964 * @param DMA2Dx DMA2D Instance
1965 * @retval None
1966 */
LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef * DMA2Dx)1967 __STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx)
1968 {
1969 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
1970 }
1971
1972 /**
1973 * @brief Disable Transfer Watermark Interrupt
1974 * @rmtoll CR TWIE LL_DMA2D_DisableIT_TW
1975 * @param DMA2Dx DMA2D Instance
1976 * @retval None
1977 */
LL_DMA2D_DisableIT_TW(DMA2D_TypeDef * DMA2Dx)1978 __STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx)
1979 {
1980 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
1981 }
1982
1983 /**
1984 * @brief Disable Transfer Complete Interrupt
1985 * @rmtoll CR TCIE LL_DMA2D_DisableIT_TC
1986 * @param DMA2Dx DMA2D Instance
1987 * @retval None
1988 */
LL_DMA2D_DisableIT_TC(DMA2D_TypeDef * DMA2Dx)1989 __STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx)
1990 {
1991 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
1992 }
1993
1994 /**
1995 * @brief Disable Transfer Error Interrupt
1996 * @rmtoll CR TEIE LL_DMA2D_DisableIT_TE
1997 * @param DMA2Dx DMA2D Instance
1998 * @retval None
1999 */
LL_DMA2D_DisableIT_TE(DMA2D_TypeDef * DMA2Dx)2000 __STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx)
2001 {
2002 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
2003 }
2004
2005 /**
2006 * @brief Check if the DMA2D Configuration Error interrupt source is enabled or disabled.
2007 * @rmtoll CR CEIE LL_DMA2D_IsEnabledIT_CE
2008 * @param DMA2Dx DMA2D Instance
2009 * @retval State of bit (1 or 0).
2010 */
LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef * DMA2Dx)2011 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx)
2012 {
2013 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL);
2014 }
2015
2016 /**
2017 * @brief Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled.
2018 * @rmtoll CR CTCIE LL_DMA2D_IsEnabledIT_CTC
2019 * @param DMA2Dx DMA2D Instance
2020 * @retval State of bit (1 or 0).
2021 */
LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef * DMA2Dx)2022 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx)
2023 {
2024 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL);
2025 }
2026
2027 /**
2028 * @brief Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled.
2029 * @rmtoll CR CAEIE LL_DMA2D_IsEnabledIT_CAE
2030 * @param DMA2Dx DMA2D Instance
2031 * @retval State of bit (1 or 0).
2032 */
LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef * DMA2Dx)2033 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx)
2034 {
2035 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL);
2036 }
2037
2038 /**
2039 * @brief Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled.
2040 * @rmtoll CR TWIE LL_DMA2D_IsEnabledIT_TW
2041 * @param DMA2Dx DMA2D Instance
2042 * @retval State of bit (1 or 0).
2043 */
LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef * DMA2Dx)2044 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx)
2045 {
2046 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL);
2047 }
2048
2049 /**
2050 * @brief Check if the DMA2D Transfer Complete interrupt source is enabled or disabled.
2051 * @rmtoll CR TCIE LL_DMA2D_IsEnabledIT_TC
2052 * @param DMA2Dx DMA2D Instance
2053 * @retval State of bit (1 or 0).
2054 */
LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef * DMA2Dx)2055 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx)
2056 {
2057 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL);
2058 }
2059
2060 /**
2061 * @brief Check if the DMA2D Transfer Error interrupt source is enabled or disabled.
2062 * @rmtoll CR TEIE LL_DMA2D_IsEnabledIT_TE
2063 * @param DMA2Dx DMA2D Instance
2064 * @retval State of bit (1 or 0).
2065 */
LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef * DMA2Dx)2066 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx)
2067 {
2068 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL);
2069 }
2070
2071
2072
2073 /**
2074 * @}
2075 */
2076
2077 #if defined(USE_FULL_LL_DRIVER)
2078 /** @defgroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions
2079 * @{
2080 */
2081
2082 ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx);
2083 ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
2084 void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
2085 void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx);
2086 void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg);
2087 void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct);
2088 uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2089 uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2090 uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2091 uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2092 void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines);
2093
2094 /**
2095 * @}
2096 */
2097 #endif /* USE_FULL_LL_DRIVER */
2098
2099 /**
2100 * @}
2101 */
2102
2103 /**
2104 * @}
2105 */
2106
2107 #endif /* defined (DMA2D) */
2108
2109 /**
2110 * @}
2111 */
2112
2113 #ifdef __cplusplus
2114 }
2115 #endif
2116
2117 #endif /* STM32F7xx_LL_DMA2D_H */
2118
