1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32F7xx_LL_DMA_H
21 #define __STM32F7xx_LL_DMA_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f7xx.h"
29
30 /** @addtogroup STM32F7xx_LL_Driver
31 * @{
32 */
33
34 #if defined (DMA1) || defined (DMA2)
35
36 /** @defgroup DMA_LL DMA
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
43 * @{
44 */
45 /* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
46 static const uint8_t STREAM_OFFSET_TAB[] =
47 {
48 (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
49 (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
50 (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
51 (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
52 (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
53 (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
54 (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
55 (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
56 };
57
58 /**
59 * @}
60 */
61
62 /* Private constants ---------------------------------------------------------*/
63 /** @defgroup DMA_LL_Private_Constants DMA Private Constants
64 * @{
65 */
66 #if defined(DMA_SxCR_CHSEL_3)
67 #define DMA_CHANNEL_SELECTION_8_15
68 #endif /* DMA_SxCR_CHSEL_3 */
69 /**
70 * @}
71 */
72
73
74 /* Private macros ------------------------------------------------------------*/
75 /* Exported types ------------------------------------------------------------*/
76 #if defined(USE_FULL_LL_DRIVER)
77 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
78 * @{
79 */
80 typedef struct
81 {
82 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
83 or as Source base address in case of memory to memory transfer direction.
84
85 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
86
87 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
88 or as Destination base address in case of memory to memory transfer direction.
89
90 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
91
92 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
93 from memory to memory or from peripheral to memory.
94 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
95
96 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
97
98 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
99 This parameter can be a value of @ref DMA_LL_EC_MODE
100 @note The circular buffer mode cannot be used if the memory to memory
101 data transfer direction is configured on the selected Stream
102
103 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
104
105 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
106 is incremented or not.
107 This parameter can be a value of @ref DMA_LL_EC_PERIPH
108
109 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
110
111 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
112 is incremented or not.
113 This parameter can be a value of @ref DMA_LL_EC_MEMORY
114
115 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
116
117 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
118 in case of memory to memory transfer direction.
119 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
120
121 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
122
123 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
124 in case of memory to memory transfer direction.
125 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
126
127 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
128
129 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
130 The data unit is equal to the source buffer configuration set in PeripheralSize
131 or MemorySize parameters depending in the transfer direction.
132 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
133
134 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
135
136 uint32_t Channel; /*!< Specifies the peripheral channel.
137 This parameter can be a value of @ref DMA_LL_EC_CHANNEL
138
139 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */
140
141 uint32_t Priority; /*!< Specifies the channel priority level.
142 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
143
144 This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
145
146 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
147 This parameter can be a value of @ref DMA_LL_FIFOMODE
148 @note The Direct mode (FIFO mode disabled) cannot be used if the
149 memory-to-memory data transfer is configured on the selected stream
150
151 This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
152
153 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
154 This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
155
156 This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
157
158 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
159 It specifies the amount of data to be transferred in a single non interruptible
160 transaction.
161 This parameter can be a value of @ref DMA_LL_EC_MBURST
162 @note The burst mode is possible only if the address Increment mode is enabled.
163
164 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
165
166 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
167 It specifies the amount of data to be transferred in a single non interruptible
168 transaction.
169 This parameter can be a value of @ref DMA_LL_EC_PBURST
170 @note The burst mode is possible only if the address Increment mode is enabled.
171
172 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
173
174 } LL_DMA_InitTypeDef;
175 /**
176 * @}
177 */
178 #endif /*USE_FULL_LL_DRIVER*/
179 /* Exported constants --------------------------------------------------------*/
180 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
181 * @{
182 */
183
184 /** @defgroup DMA_LL_EC_STREAM STREAM
185 * @{
186 */
187 #define LL_DMA_STREAM_0 0x00000000U
188 #define LL_DMA_STREAM_1 0x00000001U
189 #define LL_DMA_STREAM_2 0x00000002U
190 #define LL_DMA_STREAM_3 0x00000003U
191 #define LL_DMA_STREAM_4 0x00000004U
192 #define LL_DMA_STREAM_5 0x00000005U
193 #define LL_DMA_STREAM_6 0x00000006U
194 #define LL_DMA_STREAM_7 0x00000007U
195 #define LL_DMA_STREAM_ALL 0xFFFF0000U
196 /**
197 * @}
198 */
199
200 /** @defgroup DMA_LL_EC_DIRECTION DIRECTION
201 * @{
202 */
203 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
204 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */
205 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */
206 /**
207 * @}
208 */
209
210 /** @defgroup DMA_LL_EC_MODE MODE
211 * @{
212 */
213 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
214 #define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode */
215 #define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */
216 /**
217 * @}
218 */
219
220 /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
221 * @{
222 */
223 #define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */
224 #define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mode */
225 /**
226 * @}
227 */
228
229 /** @defgroup DMA_LL_EC_PERIPH PERIPH
230 * @{
231 */
232 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
233 #define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode Enable */
234 /**
235 * @}
236 */
237
238 /** @defgroup DMA_LL_EC_MEMORY MEMORY
239 * @{
240 */
241 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
242 #define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enable */
243 /**
244 * @}
245 */
246
247 /** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
248 * @{
249 */
250 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
251 #define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
252 #define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment : Word */
253 /**
254 * @}
255 */
256
257 /** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
258 * @{
259 */
260 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
261 #define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
262 #define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Word */
263 /**
264 * @}
265 */
266
267 /** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
268 * @{
269 */
270 #define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */
271 #define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */
272 /**
273 * @}
274 */
275
276 /** @defgroup DMA_LL_EC_PRIORITY PRIORITY
277 * @{
278 */
279 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
280 #define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium */
281 #define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High */
282 #define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High */
283 /**
284 * @}
285 */
286
287 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
288 * @{
289 */
290 #define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */
291 #define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */
292 #define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */
293 #define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */
294 #define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */
295 #define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */
296 #define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */
297 #define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */
298 #if defined(DMA_CHANNEL_SELECTION_8_15)
299 #define LL_DMA_CHANNEL_8 DMA_SxCR_CHSEL_3 /* Select Channel8 of DMA Instance */
300 #define LL_DMA_CHANNEL_9 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_0) /* Select Channel9 of DMA Instance */
301 #define LL_DMA_CHANNEL_10 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1) /* Select Channel10 of DMA Instance */
302 #define LL_DMA_CHANNEL_11 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel11 of DMA Instance */
303 #define LL_DMA_CHANNEL_12 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2) /* Select Channel12 of DMA Instance */
304 #define LL_DMA_CHANNEL_13 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel13 of DMA Instance */
305 #define LL_DMA_CHANNEL_14 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel14 of DMA Instance */
306 #define LL_DMA_CHANNEL_15 DMA_SxCR_CHSEL /* Select Channel15 of DMA Instance */
307 #endif /* DMA_CHANNEL_SELECTION_8_15 */
308 /**
309 * @}
310 */
311
312 /** @defgroup DMA_LL_EC_MBURST MBURST
313 * @{
314 */
315 #define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst single transfer configuration */
316 #define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */
317 #define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */
318 #define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */
319 /**
320 * @}
321 */
322
323 /** @defgroup DMA_LL_EC_PBURST PBURST
324 * @{
325 */
326 #define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral burst single transfer configuration */
327 #define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */
328 #define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */
329 #define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */
330 /**
331 * @}
332 */
333
334 /** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
335 * @{
336 */
337 #define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable (direct mode is enabled) */
338 #define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */
339 /**
340 * @}
341 */
342
343 /** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
344 * @{
345 */
346 #define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_level < 1/4 */
347 #define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_level < 1/2 */
348 #define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_level < 3/4 */
349 #define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */
350 #define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empty */
351 #define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full */
352 /**
353 * @}
354 */
355
356 /** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
357 * @{
358 */
359 #define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO threshold 1 quart full configuration */
360 #define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */
361 #define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */
362 #define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */
363 /**
364 * @}
365 */
366
367 /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
368 * @{
369 */
370 #define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */
371 #define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */
372 /**
373 * @}
374 */
375
376 /**
377 * @}
378 */
379
380 /* Exported macro ------------------------------------------------------------*/
381 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
382 * @{
383 */
384
385 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
386 * @{
387 */
388 /**
389 * @brief Write a value in DMA register
390 * @param __INSTANCE__ DMA Instance
391 * @param __REG__ Register to be written
392 * @param __VALUE__ Value to be written in the register
393 * @retval None
394 */
395 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
396
397 /**
398 * @brief Read a value in DMA register
399 * @param __INSTANCE__ DMA Instance
400 * @param __REG__ Register to be read
401 * @retval Register value
402 */
403 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
404 /**
405 * @}
406 */
407
408 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
409 * @{
410 */
411 /**
412 * @brief Convert DMAx_Streamy into DMAx
413 * @param __STREAM_INSTANCE__ DMAx_Streamy
414 * @retval DMAx
415 */
416 #define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \
417 (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1)
418
419 /**
420 * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y
421 * @param __STREAM_INSTANCE__ DMAx_Streamy
422 * @retval LL_DMA_CHANNEL_y
423 */
424 #define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \
425 (((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
426 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
427 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
428 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
429 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
430 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
431 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
432 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
433 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
434 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
435 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
436 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
437 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
438 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
439 LL_DMA_STREAM_7)
440
441 /**
442 * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
443 * @param __DMA_INSTANCE__ DMAx
444 * @param __STREAM__ LL_DMA_STREAM_y
445 * @retval DMAx_Streamy
446 */
447 #define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \
448 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
449 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
450 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
451 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
452 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
453 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
454 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
455 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
456 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
457 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
458 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
459 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
460 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
461 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
462 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
463 DMA2_Stream7)
464
465 /**
466 * @}
467 */
468
469 /**
470 * @}
471 */
472
473
474 /* Exported functions --------------------------------------------------------*/
475 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
476 * @{
477 */
478
479 /** @defgroup DMA_LL_EF_Configuration Configuration
480 * @{
481 */
482 /**
483 * @brief Enable DMA stream.
484 * @rmtoll CR EN LL_DMA_EnableStream
485 * @param DMAx DMAx Instance
486 * @param Stream This parameter can be one of the following values:
487 * @arg @ref LL_DMA_STREAM_0
488 * @arg @ref LL_DMA_STREAM_1
489 * @arg @ref LL_DMA_STREAM_2
490 * @arg @ref LL_DMA_STREAM_3
491 * @arg @ref LL_DMA_STREAM_4
492 * @arg @ref LL_DMA_STREAM_5
493 * @arg @ref LL_DMA_STREAM_6
494 * @arg @ref LL_DMA_STREAM_7
495 * @retval None
496 */
LL_DMA_EnableStream(DMA_TypeDef * DMAx,uint32_t Stream)497 __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
498 {
499 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
500 }
501
502 /**
503 * @brief Disable DMA stream.
504 * @rmtoll CR EN LL_DMA_DisableStream
505 * @param DMAx DMAx Instance
506 * @param Stream This parameter can be one of the following values:
507 * @arg @ref LL_DMA_STREAM_0
508 * @arg @ref LL_DMA_STREAM_1
509 * @arg @ref LL_DMA_STREAM_2
510 * @arg @ref LL_DMA_STREAM_3
511 * @arg @ref LL_DMA_STREAM_4
512 * @arg @ref LL_DMA_STREAM_5
513 * @arg @ref LL_DMA_STREAM_6
514 * @arg @ref LL_DMA_STREAM_7
515 * @retval None
516 */
LL_DMA_DisableStream(DMA_TypeDef * DMAx,uint32_t Stream)517 __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
518 {
519 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
520 }
521
522 /**
523 * @brief Check if DMA stream is enabled or disabled.
524 * @rmtoll CR EN LL_DMA_IsEnabledStream
525 * @param DMAx DMAx Instance
526 * @param Stream This parameter can be one of the following values:
527 * @arg @ref LL_DMA_STREAM_0
528 * @arg @ref LL_DMA_STREAM_1
529 * @arg @ref LL_DMA_STREAM_2
530 * @arg @ref LL_DMA_STREAM_3
531 * @arg @ref LL_DMA_STREAM_4
532 * @arg @ref LL_DMA_STREAM_5
533 * @arg @ref LL_DMA_STREAM_6
534 * @arg @ref LL_DMA_STREAM_7
535 * @retval State of bit (1 or 0).
536 */
LL_DMA_IsEnabledStream(DMA_TypeDef * DMAx,uint32_t Stream)537 __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
538 {
539 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN));
540 }
541
542 /**
543 * @brief Configure all parameters linked to DMA transfer.
544 * @rmtoll CR DIR LL_DMA_ConfigTransfer\n
545 * CR CIRC LL_DMA_ConfigTransfer\n
546 * CR PINC LL_DMA_ConfigTransfer\n
547 * CR MINC LL_DMA_ConfigTransfer\n
548 * CR PSIZE LL_DMA_ConfigTransfer\n
549 * CR MSIZE LL_DMA_ConfigTransfer\n
550 * CR PL LL_DMA_ConfigTransfer\n
551 * CR PFCTRL LL_DMA_ConfigTransfer
552 * @param DMAx DMAx Instance
553 * @param Stream This parameter can be one of the following values:
554 * @arg @ref LL_DMA_STREAM_0
555 * @arg @ref LL_DMA_STREAM_1
556 * @arg @ref LL_DMA_STREAM_2
557 * @arg @ref LL_DMA_STREAM_3
558 * @arg @ref LL_DMA_STREAM_4
559 * @arg @ref LL_DMA_STREAM_5
560 * @arg @ref LL_DMA_STREAM_6
561 * @arg @ref LL_DMA_STREAM_7
562 * @param Configuration This parameter must be a combination of all the following values:
563 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
564 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL
565 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
566 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
567 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
568 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
569 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
570 *@retval None
571 */
LL_DMA_ConfigTransfer(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Configuration)572 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
573 {
574 MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR,
575 DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL,
576 Configuration);
577 }
578
579 /**
580 * @brief Set Data transfer direction (read from peripheral or from memory).
581 * @rmtoll CR DIR LL_DMA_SetDataTransferDirection
582 * @param DMAx DMAx Instance
583 * @param Stream This parameter can be one of the following values:
584 * @arg @ref LL_DMA_STREAM_0
585 * @arg @ref LL_DMA_STREAM_1
586 * @arg @ref LL_DMA_STREAM_2
587 * @arg @ref LL_DMA_STREAM_3
588 * @arg @ref LL_DMA_STREAM_4
589 * @arg @ref LL_DMA_STREAM_5
590 * @arg @ref LL_DMA_STREAM_6
591 * @arg @ref LL_DMA_STREAM_7
592 * @param Direction This parameter can be one of the following values:
593 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
594 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
595 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
596 * @retval None
597 */
LL_DMA_SetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Direction)598 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction)
599 {
600 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction);
601 }
602
603 /**
604 * @brief Get Data transfer direction (read from peripheral or from memory).
605 * @rmtoll CR DIR LL_DMA_GetDataTransferDirection
606 * @param DMAx DMAx Instance
607 * @param Stream This parameter can be one of the following values:
608 * @arg @ref LL_DMA_STREAM_0
609 * @arg @ref LL_DMA_STREAM_1
610 * @arg @ref LL_DMA_STREAM_2
611 * @arg @ref LL_DMA_STREAM_3
612 * @arg @ref LL_DMA_STREAM_4
613 * @arg @ref LL_DMA_STREAM_5
614 * @arg @ref LL_DMA_STREAM_6
615 * @arg @ref LL_DMA_STREAM_7
616 * @retval Returned value can be one of the following values:
617 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
618 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
619 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
620 */
LL_DMA_GetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Stream)621 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
622 {
623 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR));
624 }
625
626 /**
627 * @brief Set DMA mode normal, circular or peripheral flow control.
628 * @rmtoll CR CIRC LL_DMA_SetMode\n
629 * CR PFCTRL LL_DMA_SetMode
630 * @param DMAx DMAx Instance
631 * @param Stream This parameter can be one of the following values:
632 * @arg @ref LL_DMA_STREAM_0
633 * @arg @ref LL_DMA_STREAM_1
634 * @arg @ref LL_DMA_STREAM_2
635 * @arg @ref LL_DMA_STREAM_3
636 * @arg @ref LL_DMA_STREAM_4
637 * @arg @ref LL_DMA_STREAM_5
638 * @arg @ref LL_DMA_STREAM_6
639 * @arg @ref LL_DMA_STREAM_7
640 * @param Mode This parameter can be one of the following values:
641 * @arg @ref LL_DMA_MODE_NORMAL
642 * @arg @ref LL_DMA_MODE_CIRCULAR
643 * @arg @ref LL_DMA_MODE_PFCTRL
644 * @retval None
645 */
LL_DMA_SetMode(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Mode)646 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
647 {
648 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode);
649 }
650
651 /**
652 * @brief Get DMA mode normal, circular or peripheral flow control.
653 * @rmtoll CR CIRC LL_DMA_GetMode\n
654 * CR PFCTRL LL_DMA_GetMode
655 * @param DMAx DMAx Instance
656 * @param Stream This parameter can be one of the following values:
657 * @arg @ref LL_DMA_STREAM_0
658 * @arg @ref LL_DMA_STREAM_1
659 * @arg @ref LL_DMA_STREAM_2
660 * @arg @ref LL_DMA_STREAM_3
661 * @arg @ref LL_DMA_STREAM_4
662 * @arg @ref LL_DMA_STREAM_5
663 * @arg @ref LL_DMA_STREAM_6
664 * @arg @ref LL_DMA_STREAM_7
665 * @retval Returned value can be one of the following values:
666 * @arg @ref LL_DMA_MODE_NORMAL
667 * @arg @ref LL_DMA_MODE_CIRCULAR
668 * @arg @ref LL_DMA_MODE_PFCTRL
669 */
LL_DMA_GetMode(DMA_TypeDef * DMAx,uint32_t Stream)670 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
671 {
672 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL));
673 }
674
675 /**
676 * @brief Set Peripheral increment mode.
677 * @rmtoll CR PINC LL_DMA_SetPeriphIncMode
678 * @param DMAx DMAx Instance
679 * @param Stream This parameter can be one of the following values:
680 * @arg @ref LL_DMA_STREAM_0
681 * @arg @ref LL_DMA_STREAM_1
682 * @arg @ref LL_DMA_STREAM_2
683 * @arg @ref LL_DMA_STREAM_3
684 * @arg @ref LL_DMA_STREAM_4
685 * @arg @ref LL_DMA_STREAM_5
686 * @arg @ref LL_DMA_STREAM_6
687 * @arg @ref LL_DMA_STREAM_7
688 * @param IncrementMode This parameter can be one of the following values:
689 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
690 * @arg @ref LL_DMA_PERIPH_INCREMENT
691 * @retval None
692 */
LL_DMA_SetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t IncrementMode)693 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
694 {
695 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode);
696 }
697
698 /**
699 * @brief Get Peripheral increment mode.
700 * @rmtoll CR PINC LL_DMA_GetPeriphIncMode
701 * @param DMAx DMAx Instance
702 * @param Stream This parameter can be one of the following values:
703 * @arg @ref LL_DMA_STREAM_0
704 * @arg @ref LL_DMA_STREAM_1
705 * @arg @ref LL_DMA_STREAM_2
706 * @arg @ref LL_DMA_STREAM_3
707 * @arg @ref LL_DMA_STREAM_4
708 * @arg @ref LL_DMA_STREAM_5
709 * @arg @ref LL_DMA_STREAM_6
710 * @arg @ref LL_DMA_STREAM_7
711 * @retval Returned value can be one of the following values:
712 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
713 * @arg @ref LL_DMA_PERIPH_INCREMENT
714 */
LL_DMA_GetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Stream)715 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
716 {
717 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC));
718 }
719
720 /**
721 * @brief Set Memory increment mode.
722 * @rmtoll CR MINC LL_DMA_SetMemoryIncMode
723 * @param DMAx DMAx Instance
724 * @param Stream This parameter can be one of the following values:
725 * @arg @ref LL_DMA_STREAM_0
726 * @arg @ref LL_DMA_STREAM_1
727 * @arg @ref LL_DMA_STREAM_2
728 * @arg @ref LL_DMA_STREAM_3
729 * @arg @ref LL_DMA_STREAM_4
730 * @arg @ref LL_DMA_STREAM_5
731 * @arg @ref LL_DMA_STREAM_6
732 * @arg @ref LL_DMA_STREAM_7
733 * @param IncrementMode This parameter can be one of the following values:
734 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
735 * @arg @ref LL_DMA_MEMORY_INCREMENT
736 * @retval None
737 */
LL_DMA_SetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t IncrementMode)738 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
739 {
740 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode);
741 }
742
743 /**
744 * @brief Get Memory increment mode.
745 * @rmtoll CR MINC LL_DMA_GetMemoryIncMode
746 * @param DMAx DMAx Instance
747 * @param Stream This parameter can be one of the following values:
748 * @arg @ref LL_DMA_STREAM_0
749 * @arg @ref LL_DMA_STREAM_1
750 * @arg @ref LL_DMA_STREAM_2
751 * @arg @ref LL_DMA_STREAM_3
752 * @arg @ref LL_DMA_STREAM_4
753 * @arg @ref LL_DMA_STREAM_5
754 * @arg @ref LL_DMA_STREAM_6
755 * @arg @ref LL_DMA_STREAM_7
756 * @retval Returned value can be one of the following values:
757 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
758 * @arg @ref LL_DMA_MEMORY_INCREMENT
759 */
LL_DMA_GetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Stream)760 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
761 {
762 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC));
763 }
764
765 /**
766 * @brief Set Peripheral size.
767 * @rmtoll CR PSIZE LL_DMA_SetPeriphSize
768 * @param DMAx DMAx Instance
769 * @param Stream This parameter can be one of the following values:
770 * @arg @ref LL_DMA_STREAM_0
771 * @arg @ref LL_DMA_STREAM_1
772 * @arg @ref LL_DMA_STREAM_2
773 * @arg @ref LL_DMA_STREAM_3
774 * @arg @ref LL_DMA_STREAM_4
775 * @arg @ref LL_DMA_STREAM_5
776 * @arg @ref LL_DMA_STREAM_6
777 * @arg @ref LL_DMA_STREAM_7
778 * @param Size This parameter can be one of the following values:
779 * @arg @ref LL_DMA_PDATAALIGN_BYTE
780 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
781 * @arg @ref LL_DMA_PDATAALIGN_WORD
782 * @retval None
783 */
LL_DMA_SetPeriphSize(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Size)784 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
785 {
786 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size);
787 }
788
789 /**
790 * @brief Get Peripheral size.
791 * @rmtoll CR PSIZE LL_DMA_GetPeriphSize
792 * @param DMAx DMAx Instance
793 * @param Stream This parameter can be one of the following values:
794 * @arg @ref LL_DMA_STREAM_0
795 * @arg @ref LL_DMA_STREAM_1
796 * @arg @ref LL_DMA_STREAM_2
797 * @arg @ref LL_DMA_STREAM_3
798 * @arg @ref LL_DMA_STREAM_4
799 * @arg @ref LL_DMA_STREAM_5
800 * @arg @ref LL_DMA_STREAM_6
801 * @arg @ref LL_DMA_STREAM_7
802 * @retval Returned value can be one of the following values:
803 * @arg @ref LL_DMA_PDATAALIGN_BYTE
804 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
805 * @arg @ref LL_DMA_PDATAALIGN_WORD
806 */
LL_DMA_GetPeriphSize(DMA_TypeDef * DMAx,uint32_t Stream)807 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
808 {
809 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE));
810 }
811
812 /**
813 * @brief Set Memory size.
814 * @rmtoll CR MSIZE LL_DMA_SetMemorySize
815 * @param DMAx DMAx Instance
816 * @param Stream This parameter can be one of the following values:
817 * @arg @ref LL_DMA_STREAM_0
818 * @arg @ref LL_DMA_STREAM_1
819 * @arg @ref LL_DMA_STREAM_2
820 * @arg @ref LL_DMA_STREAM_3
821 * @arg @ref LL_DMA_STREAM_4
822 * @arg @ref LL_DMA_STREAM_5
823 * @arg @ref LL_DMA_STREAM_6
824 * @arg @ref LL_DMA_STREAM_7
825 * @param Size This parameter can be one of the following values:
826 * @arg @ref LL_DMA_MDATAALIGN_BYTE
827 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
828 * @arg @ref LL_DMA_MDATAALIGN_WORD
829 * @retval None
830 */
LL_DMA_SetMemorySize(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Size)831 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
832 {
833 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size);
834 }
835
836 /**
837 * @brief Get Memory size.
838 * @rmtoll CR MSIZE LL_DMA_GetMemorySize
839 * @param DMAx DMAx Instance
840 * @param Stream This parameter can be one of the following values:
841 * @arg @ref LL_DMA_STREAM_0
842 * @arg @ref LL_DMA_STREAM_1
843 * @arg @ref LL_DMA_STREAM_2
844 * @arg @ref LL_DMA_STREAM_3
845 * @arg @ref LL_DMA_STREAM_4
846 * @arg @ref LL_DMA_STREAM_5
847 * @arg @ref LL_DMA_STREAM_6
848 * @arg @ref LL_DMA_STREAM_7
849 * @retval Returned value can be one of the following values:
850 * @arg @ref LL_DMA_MDATAALIGN_BYTE
851 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
852 * @arg @ref LL_DMA_MDATAALIGN_WORD
853 */
LL_DMA_GetMemorySize(DMA_TypeDef * DMAx,uint32_t Stream)854 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
855 {
856 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE));
857 }
858
859 /**
860 * @brief Set Peripheral increment offset size.
861 * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize
862 * @param DMAx DMAx Instance
863 * @param Stream This parameter can be one of the following values:
864 * @arg @ref LL_DMA_STREAM_0
865 * @arg @ref LL_DMA_STREAM_1
866 * @arg @ref LL_DMA_STREAM_2
867 * @arg @ref LL_DMA_STREAM_3
868 * @arg @ref LL_DMA_STREAM_4
869 * @arg @ref LL_DMA_STREAM_5
870 * @arg @ref LL_DMA_STREAM_6
871 * @arg @ref LL_DMA_STREAM_7
872 * @param OffsetSize This parameter can be one of the following values:
873 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
874 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
875 * @retval None
876 */
LL_DMA_SetIncOffsetSize(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t OffsetSize)877 __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
878 {
879 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize);
880 }
881
882 /**
883 * @brief Get Peripheral increment offset size.
884 * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize
885 * @param DMAx DMAx Instance
886 * @param Stream This parameter can be one of the following values:
887 * @arg @ref LL_DMA_STREAM_0
888 * @arg @ref LL_DMA_STREAM_1
889 * @arg @ref LL_DMA_STREAM_2
890 * @arg @ref LL_DMA_STREAM_3
891 * @arg @ref LL_DMA_STREAM_4
892 * @arg @ref LL_DMA_STREAM_5
893 * @arg @ref LL_DMA_STREAM_6
894 * @arg @ref LL_DMA_STREAM_7
895 * @retval Returned value can be one of the following values:
896 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
897 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
898 */
LL_DMA_GetIncOffsetSize(DMA_TypeDef * DMAx,uint32_t Stream)899 __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
900 {
901 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS));
902 }
903
904 /**
905 * @brief Set Stream priority level.
906 * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel
907 * @param DMAx DMAx Instance
908 * @param Stream This parameter can be one of the following values:
909 * @arg @ref LL_DMA_STREAM_0
910 * @arg @ref LL_DMA_STREAM_1
911 * @arg @ref LL_DMA_STREAM_2
912 * @arg @ref LL_DMA_STREAM_3
913 * @arg @ref LL_DMA_STREAM_4
914 * @arg @ref LL_DMA_STREAM_5
915 * @arg @ref LL_DMA_STREAM_6
916 * @arg @ref LL_DMA_STREAM_7
917 * @param Priority This parameter can be one of the following values:
918 * @arg @ref LL_DMA_PRIORITY_LOW
919 * @arg @ref LL_DMA_PRIORITY_MEDIUM
920 * @arg @ref LL_DMA_PRIORITY_HIGH
921 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
922 * @retval None
923 */
LL_DMA_SetStreamPriorityLevel(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Priority)924 __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority)
925 {
926 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority);
927 }
928
929 /**
930 * @brief Get Stream priority level.
931 * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel
932 * @param DMAx DMAx Instance
933 * @param Stream This parameter can be one of the following values:
934 * @arg @ref LL_DMA_STREAM_0
935 * @arg @ref LL_DMA_STREAM_1
936 * @arg @ref LL_DMA_STREAM_2
937 * @arg @ref LL_DMA_STREAM_3
938 * @arg @ref LL_DMA_STREAM_4
939 * @arg @ref LL_DMA_STREAM_5
940 * @arg @ref LL_DMA_STREAM_6
941 * @arg @ref LL_DMA_STREAM_7
942 * @retval Returned value can be one of the following values:
943 * @arg @ref LL_DMA_PRIORITY_LOW
944 * @arg @ref LL_DMA_PRIORITY_MEDIUM
945 * @arg @ref LL_DMA_PRIORITY_HIGH
946 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
947 */
LL_DMA_GetStreamPriorityLevel(DMA_TypeDef * DMAx,uint32_t Stream)948 __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
949 {
950 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL));
951 }
952
953 /**
954 * @brief Set Number of data to transfer.
955 * @rmtoll NDTR NDT LL_DMA_SetDataLength
956 * @note This action has no effect if
957 * stream is enabled.
958 * @param DMAx DMAx Instance
959 * @param Stream This parameter can be one of the following values:
960 * @arg @ref LL_DMA_STREAM_0
961 * @arg @ref LL_DMA_STREAM_1
962 * @arg @ref LL_DMA_STREAM_2
963 * @arg @ref LL_DMA_STREAM_3
964 * @arg @ref LL_DMA_STREAM_4
965 * @arg @ref LL_DMA_STREAM_5
966 * @arg @ref LL_DMA_STREAM_6
967 * @arg @ref LL_DMA_STREAM_7
968 * @param NbData Between 0 to 0xFFFFFFFF
969 * @retval None
970 */
LL_DMA_SetDataLength(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t NbData)971 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData)
972 {
973 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData);
974 }
975
976 /**
977 * @brief Get Number of data to transfer.
978 * @rmtoll NDTR NDT LL_DMA_GetDataLength
979 * @note Once the stream is enabled, the return value indicate the
980 * remaining bytes to be transmitted.
981 * @param DMAx DMAx Instance
982 * @param Stream This parameter can be one of the following values:
983 * @arg @ref LL_DMA_STREAM_0
984 * @arg @ref LL_DMA_STREAM_1
985 * @arg @ref LL_DMA_STREAM_2
986 * @arg @ref LL_DMA_STREAM_3
987 * @arg @ref LL_DMA_STREAM_4
988 * @arg @ref LL_DMA_STREAM_5
989 * @arg @ref LL_DMA_STREAM_6
990 * @arg @ref LL_DMA_STREAM_7
991 * @retval Between 0 to 0xFFFFFFFF
992 */
LL_DMA_GetDataLength(DMA_TypeDef * DMAx,uint32_t Stream)993 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream)
994 {
995 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT));
996 }
997
998 /**
999 * @brief Select Channel number associated to the Stream.
1000 * @rmtoll CR CHSEL LL_DMA_SetChannelSelection
1001 * @param DMAx DMAx Instance
1002 * @param Stream This parameter can be one of the following values:
1003 * @arg @ref LL_DMA_STREAM_0
1004 * @arg @ref LL_DMA_STREAM_1
1005 * @arg @ref LL_DMA_STREAM_2
1006 * @arg @ref LL_DMA_STREAM_3
1007 * @arg @ref LL_DMA_STREAM_4
1008 * @arg @ref LL_DMA_STREAM_5
1009 * @arg @ref LL_DMA_STREAM_6
1010 * @arg @ref LL_DMA_STREAM_7
1011 * @param Channel This parameter can be one of the following values:
1012 * @arg @ref LL_DMA_CHANNEL_0
1013 * @arg @ref LL_DMA_CHANNEL_1
1014 * @arg @ref LL_DMA_CHANNEL_2
1015 * @arg @ref LL_DMA_CHANNEL_3
1016 * @arg @ref LL_DMA_CHANNEL_4
1017 * @arg @ref LL_DMA_CHANNEL_5
1018 * @arg @ref LL_DMA_CHANNEL_6
1019 * @arg @ref LL_DMA_CHANNEL_7
1020 * @arg @ref LL_DMA_CHANNEL_8 (*)
1021 * @arg @ref LL_DMA_CHANNEL_9 (*)
1022 * @arg @ref LL_DMA_CHANNEL_10 (*)
1023 * @arg @ref LL_DMA_CHANNEL_11 (*)
1024 * @arg @ref LL_DMA_CHANNEL_12 (*)
1025 * @arg @ref LL_DMA_CHANNEL_13 (*)
1026 * @arg @ref LL_DMA_CHANNEL_14 (*)
1027 * @arg @ref LL_DMA_CHANNEL_15 (*)
1028 *
1029 * (*) value not defined in all devices.
1030 * @retval None
1031 */
LL_DMA_SetChannelSelection(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Channel)1032 __STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel)
1033 {
1034 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel);
1035 }
1036
1037 /**
1038 * @brief Get the Channel number associated to the Stream.
1039 * @rmtoll CR CHSEL LL_DMA_GetChannelSelection
1040 * @param DMAx DMAx Instance
1041 * @param Stream This parameter can be one of the following values:
1042 * @arg @ref LL_DMA_STREAM_0
1043 * @arg @ref LL_DMA_STREAM_1
1044 * @arg @ref LL_DMA_STREAM_2
1045 * @arg @ref LL_DMA_STREAM_3
1046 * @arg @ref LL_DMA_STREAM_4
1047 * @arg @ref LL_DMA_STREAM_5
1048 * @arg @ref LL_DMA_STREAM_6
1049 * @arg @ref LL_DMA_STREAM_7
1050 * @retval Returned value can be one of the following values:
1051 * @arg @ref LL_DMA_CHANNEL_0
1052 * @arg @ref LL_DMA_CHANNEL_1
1053 * @arg @ref LL_DMA_CHANNEL_2
1054 * @arg @ref LL_DMA_CHANNEL_3
1055 * @arg @ref LL_DMA_CHANNEL_4
1056 * @arg @ref LL_DMA_CHANNEL_5
1057 * @arg @ref LL_DMA_CHANNEL_6
1058 * @arg @ref LL_DMA_CHANNEL_7
1059 * @arg @ref LL_DMA_CHANNEL_8 (*)
1060 * @arg @ref LL_DMA_CHANNEL_9 (*)
1061 * @arg @ref LL_DMA_CHANNEL_10 (*)
1062 * @arg @ref LL_DMA_CHANNEL_11 (*)
1063 * @arg @ref LL_DMA_CHANNEL_12 (*)
1064 * @arg @ref LL_DMA_CHANNEL_13 (*)
1065 * @arg @ref LL_DMA_CHANNEL_14 (*)
1066 * @arg @ref LL_DMA_CHANNEL_15 (*)
1067 *
1068 * (*) value not defined in all devices.
1069 */
LL_DMA_GetChannelSelection(DMA_TypeDef * DMAx,uint32_t Stream)1070 __STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream)
1071 {
1072 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL));
1073 }
1074
1075 /**
1076 * @brief Set Memory burst transfer configuration.
1077 * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer
1078 * @param DMAx DMAx Instance
1079 * @param Stream This parameter can be one of the following values:
1080 * @arg @ref LL_DMA_STREAM_0
1081 * @arg @ref LL_DMA_STREAM_1
1082 * @arg @ref LL_DMA_STREAM_2
1083 * @arg @ref LL_DMA_STREAM_3
1084 * @arg @ref LL_DMA_STREAM_4
1085 * @arg @ref LL_DMA_STREAM_5
1086 * @arg @ref LL_DMA_STREAM_6
1087 * @arg @ref LL_DMA_STREAM_7
1088 * @param Mburst This parameter can be one of the following values:
1089 * @arg @ref LL_DMA_MBURST_SINGLE
1090 * @arg @ref LL_DMA_MBURST_INC4
1091 * @arg @ref LL_DMA_MBURST_INC8
1092 * @arg @ref LL_DMA_MBURST_INC16
1093 * @retval None
1094 */
LL_DMA_SetMemoryBurstxfer(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Mburst)1095 __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
1096 {
1097 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst);
1098 }
1099
1100 /**
1101 * @brief Get Memory burst transfer configuration.
1102 * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer
1103 * @param DMAx DMAx Instance
1104 * @param Stream This parameter can be one of the following values:
1105 * @arg @ref LL_DMA_STREAM_0
1106 * @arg @ref LL_DMA_STREAM_1
1107 * @arg @ref LL_DMA_STREAM_2
1108 * @arg @ref LL_DMA_STREAM_3
1109 * @arg @ref LL_DMA_STREAM_4
1110 * @arg @ref LL_DMA_STREAM_5
1111 * @arg @ref LL_DMA_STREAM_6
1112 * @arg @ref LL_DMA_STREAM_7
1113 * @retval Returned value can be one of the following values:
1114 * @arg @ref LL_DMA_MBURST_SINGLE
1115 * @arg @ref LL_DMA_MBURST_INC4
1116 * @arg @ref LL_DMA_MBURST_INC8
1117 * @arg @ref LL_DMA_MBURST_INC16
1118 */
LL_DMA_GetMemoryBurstxfer(DMA_TypeDef * DMAx,uint32_t Stream)1119 __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
1120 {
1121 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST));
1122 }
1123
1124 /**
1125 * @brief Set Peripheral burst transfer configuration.
1126 * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer
1127 * @param DMAx DMAx Instance
1128 * @param Stream This parameter can be one of the following values:
1129 * @arg @ref LL_DMA_STREAM_0
1130 * @arg @ref LL_DMA_STREAM_1
1131 * @arg @ref LL_DMA_STREAM_2
1132 * @arg @ref LL_DMA_STREAM_3
1133 * @arg @ref LL_DMA_STREAM_4
1134 * @arg @ref LL_DMA_STREAM_5
1135 * @arg @ref LL_DMA_STREAM_6
1136 * @arg @ref LL_DMA_STREAM_7
1137 * @param Pburst This parameter can be one of the following values:
1138 * @arg @ref LL_DMA_PBURST_SINGLE
1139 * @arg @ref LL_DMA_PBURST_INC4
1140 * @arg @ref LL_DMA_PBURST_INC8
1141 * @arg @ref LL_DMA_PBURST_INC16
1142 * @retval None
1143 */
LL_DMA_SetPeriphBurstxfer(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Pburst)1144 __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
1145 {
1146 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst);
1147 }
1148
1149 /**
1150 * @brief Get Peripheral burst transfer configuration.
1151 * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer
1152 * @param DMAx DMAx Instance
1153 * @param Stream This parameter can be one of the following values:
1154 * @arg @ref LL_DMA_STREAM_0
1155 * @arg @ref LL_DMA_STREAM_1
1156 * @arg @ref LL_DMA_STREAM_2
1157 * @arg @ref LL_DMA_STREAM_3
1158 * @arg @ref LL_DMA_STREAM_4
1159 * @arg @ref LL_DMA_STREAM_5
1160 * @arg @ref LL_DMA_STREAM_6
1161 * @arg @ref LL_DMA_STREAM_7
1162 * @retval Returned value can be one of the following values:
1163 * @arg @ref LL_DMA_PBURST_SINGLE
1164 * @arg @ref LL_DMA_PBURST_INC4
1165 * @arg @ref LL_DMA_PBURST_INC8
1166 * @arg @ref LL_DMA_PBURST_INC16
1167 */
LL_DMA_GetPeriphBurstxfer(DMA_TypeDef * DMAx,uint32_t Stream)1168 __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
1169 {
1170 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST));
1171 }
1172
1173 /**
1174 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1175 * @rmtoll CR CT LL_DMA_SetCurrentTargetMem
1176 * @param DMAx DMAx Instance
1177 * @param Stream This parameter can be one of the following values:
1178 * @arg @ref LL_DMA_STREAM_0
1179 * @arg @ref LL_DMA_STREAM_1
1180 * @arg @ref LL_DMA_STREAM_2
1181 * @arg @ref LL_DMA_STREAM_3
1182 * @arg @ref LL_DMA_STREAM_4
1183 * @arg @ref LL_DMA_STREAM_5
1184 * @arg @ref LL_DMA_STREAM_6
1185 * @arg @ref LL_DMA_STREAM_7
1186 * @param CurrentMemory This parameter can be one of the following values:
1187 * @arg @ref LL_DMA_CURRENTTARGETMEM0
1188 * @arg @ref LL_DMA_CURRENTTARGETMEM1
1189 * @retval None
1190 */
LL_DMA_SetCurrentTargetMem(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t CurrentMemory)1191 __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
1192 {
1193 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory);
1194 }
1195
1196 /**
1197 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1198 * @rmtoll CR CT LL_DMA_GetCurrentTargetMem
1199 * @param DMAx DMAx Instance
1200 * @param Stream This parameter can be one of the following values:
1201 * @arg @ref LL_DMA_STREAM_0
1202 * @arg @ref LL_DMA_STREAM_1
1203 * @arg @ref LL_DMA_STREAM_2
1204 * @arg @ref LL_DMA_STREAM_3
1205 * @arg @ref LL_DMA_STREAM_4
1206 * @arg @ref LL_DMA_STREAM_5
1207 * @arg @ref LL_DMA_STREAM_6
1208 * @arg @ref LL_DMA_STREAM_7
1209 * @retval Returned value can be one of the following values:
1210 * @arg @ref LL_DMA_CURRENTTARGETMEM0
1211 * @arg @ref LL_DMA_CURRENTTARGETMEM1
1212 */
LL_DMA_GetCurrentTargetMem(DMA_TypeDef * DMAx,uint32_t Stream)1213 __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
1214 {
1215 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT));
1216 }
1217
1218 /**
1219 * @brief Enable the double buffer mode.
1220 * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode
1221 * @param DMAx DMAx Instance
1222 * @param Stream This parameter can be one of the following values:
1223 * @arg @ref LL_DMA_STREAM_0
1224 * @arg @ref LL_DMA_STREAM_1
1225 * @arg @ref LL_DMA_STREAM_2
1226 * @arg @ref LL_DMA_STREAM_3
1227 * @arg @ref LL_DMA_STREAM_4
1228 * @arg @ref LL_DMA_STREAM_5
1229 * @arg @ref LL_DMA_STREAM_6
1230 * @arg @ref LL_DMA_STREAM_7
1231 * @retval None
1232 */
LL_DMA_EnableDoubleBufferMode(DMA_TypeDef * DMAx,uint32_t Stream)1233 __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
1234 {
1235 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
1236 }
1237
1238 /**
1239 * @brief Disable the double buffer mode.
1240 * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode
1241 * @param DMAx DMAx Instance
1242 * @param Stream This parameter can be one of the following values:
1243 * @arg @ref LL_DMA_STREAM_0
1244 * @arg @ref LL_DMA_STREAM_1
1245 * @arg @ref LL_DMA_STREAM_2
1246 * @arg @ref LL_DMA_STREAM_3
1247 * @arg @ref LL_DMA_STREAM_4
1248 * @arg @ref LL_DMA_STREAM_5
1249 * @arg @ref LL_DMA_STREAM_6
1250 * @arg @ref LL_DMA_STREAM_7
1251 * @retval None
1252 */
LL_DMA_DisableDoubleBufferMode(DMA_TypeDef * DMAx,uint32_t Stream)1253 __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
1254 {
1255 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
1256 }
1257
1258 /**
1259 * @brief Get FIFO status.
1260 * @rmtoll FCR FS LL_DMA_GetFIFOStatus
1261 * @param DMAx DMAx Instance
1262 * @param Stream This parameter can be one of the following values:
1263 * @arg @ref LL_DMA_STREAM_0
1264 * @arg @ref LL_DMA_STREAM_1
1265 * @arg @ref LL_DMA_STREAM_2
1266 * @arg @ref LL_DMA_STREAM_3
1267 * @arg @ref LL_DMA_STREAM_4
1268 * @arg @ref LL_DMA_STREAM_5
1269 * @arg @ref LL_DMA_STREAM_6
1270 * @arg @ref LL_DMA_STREAM_7
1271 * @retval Returned value can be one of the following values:
1272 * @arg @ref LL_DMA_FIFOSTATUS_0_25
1273 * @arg @ref LL_DMA_FIFOSTATUS_25_50
1274 * @arg @ref LL_DMA_FIFOSTATUS_50_75
1275 * @arg @ref LL_DMA_FIFOSTATUS_75_100
1276 * @arg @ref LL_DMA_FIFOSTATUS_EMPTY
1277 * @arg @ref LL_DMA_FIFOSTATUS_FULL
1278 */
LL_DMA_GetFIFOStatus(DMA_TypeDef * DMAx,uint32_t Stream)1279 __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
1280 {
1281 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS));
1282 }
1283
1284 /**
1285 * @brief Disable Fifo mode.
1286 * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode
1287 * @param DMAx DMAx Instance
1288 * @param Stream This parameter can be one of the following values:
1289 * @arg @ref LL_DMA_STREAM_0
1290 * @arg @ref LL_DMA_STREAM_1
1291 * @arg @ref LL_DMA_STREAM_2
1292 * @arg @ref LL_DMA_STREAM_3
1293 * @arg @ref LL_DMA_STREAM_4
1294 * @arg @ref LL_DMA_STREAM_5
1295 * @arg @ref LL_DMA_STREAM_6
1296 * @arg @ref LL_DMA_STREAM_7
1297 * @retval None
1298 */
LL_DMA_DisableFifoMode(DMA_TypeDef * DMAx,uint32_t Stream)1299 __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
1300 {
1301 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
1302 }
1303
1304 /**
1305 * @brief Enable Fifo mode.
1306 * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode
1307 * @param DMAx DMAx Instance
1308 * @param Stream This parameter can be one of the following values:
1309 * @arg @ref LL_DMA_STREAM_0
1310 * @arg @ref LL_DMA_STREAM_1
1311 * @arg @ref LL_DMA_STREAM_2
1312 * @arg @ref LL_DMA_STREAM_3
1313 * @arg @ref LL_DMA_STREAM_4
1314 * @arg @ref LL_DMA_STREAM_5
1315 * @arg @ref LL_DMA_STREAM_6
1316 * @arg @ref LL_DMA_STREAM_7
1317 * @retval None
1318 */
LL_DMA_EnableFifoMode(DMA_TypeDef * DMAx,uint32_t Stream)1319 __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
1320 {
1321 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
1322 }
1323
1324 /**
1325 * @brief Select FIFO threshold.
1326 * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold
1327 * @param DMAx DMAx Instance
1328 * @param Stream This parameter can be one of the following values:
1329 * @arg @ref LL_DMA_STREAM_0
1330 * @arg @ref LL_DMA_STREAM_1
1331 * @arg @ref LL_DMA_STREAM_2
1332 * @arg @ref LL_DMA_STREAM_3
1333 * @arg @ref LL_DMA_STREAM_4
1334 * @arg @ref LL_DMA_STREAM_5
1335 * @arg @ref LL_DMA_STREAM_6
1336 * @arg @ref LL_DMA_STREAM_7
1337 * @param Threshold This parameter can be one of the following values:
1338 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1339 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1340 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1341 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1342 * @retval None
1343 */
LL_DMA_SetFIFOThreshold(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Threshold)1344 __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
1345 {
1346 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold);
1347 }
1348
1349 /**
1350 * @brief Get FIFO threshold.
1351 * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold
1352 * @param DMAx DMAx Instance
1353 * @param Stream This parameter can be one of the following values:
1354 * @arg @ref LL_DMA_STREAM_0
1355 * @arg @ref LL_DMA_STREAM_1
1356 * @arg @ref LL_DMA_STREAM_2
1357 * @arg @ref LL_DMA_STREAM_3
1358 * @arg @ref LL_DMA_STREAM_4
1359 * @arg @ref LL_DMA_STREAM_5
1360 * @arg @ref LL_DMA_STREAM_6
1361 * @arg @ref LL_DMA_STREAM_7
1362 * @retval Returned value can be one of the following values:
1363 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1364 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1365 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1366 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1367 */
LL_DMA_GetFIFOThreshold(DMA_TypeDef * DMAx,uint32_t Stream)1368 __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
1369 {
1370 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH));
1371 }
1372
1373 /**
1374 * @brief Configure the FIFO .
1375 * @rmtoll FCR FTH LL_DMA_ConfigFifo\n
1376 * FCR DMDIS LL_DMA_ConfigFifo
1377 * @param DMAx DMAx Instance
1378 * @param Stream This parameter can be one of the following values:
1379 * @arg @ref LL_DMA_STREAM_0
1380 * @arg @ref LL_DMA_STREAM_1
1381 * @arg @ref LL_DMA_STREAM_2
1382 * @arg @ref LL_DMA_STREAM_3
1383 * @arg @ref LL_DMA_STREAM_4
1384 * @arg @ref LL_DMA_STREAM_5
1385 * @arg @ref LL_DMA_STREAM_6
1386 * @arg @ref LL_DMA_STREAM_7
1387 * @param FifoMode This parameter can be one of the following values:
1388 * @arg @ref LL_DMA_FIFOMODE_ENABLE
1389 * @arg @ref LL_DMA_FIFOMODE_DISABLE
1390 * @param FifoThreshold This parameter can be one of the following values:
1391 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1392 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1393 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1394 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1395 * @retval None
1396 */
LL_DMA_ConfigFifo(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t FifoMode,uint32_t FifoThreshold)1397 __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
1398 {
1399 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH|DMA_SxFCR_DMDIS, FifoMode|FifoThreshold);
1400 }
1401
1402 /**
1403 * @brief Configure the Source and Destination addresses.
1404 * @note This API must not be called when the DMA stream is enabled.
1405 * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n
1406 * PAR PA LL_DMA_ConfigAddresses
1407 * @param DMAx DMAx Instance
1408 * @param Stream This parameter can be one of the following values:
1409 * @arg @ref LL_DMA_STREAM_0
1410 * @arg @ref LL_DMA_STREAM_1
1411 * @arg @ref LL_DMA_STREAM_2
1412 * @arg @ref LL_DMA_STREAM_3
1413 * @arg @ref LL_DMA_STREAM_4
1414 * @arg @ref LL_DMA_STREAM_5
1415 * @arg @ref LL_DMA_STREAM_6
1416 * @arg @ref LL_DMA_STREAM_7
1417 * @param SrcAddress Between 0 to 0xFFFFFFFF
1418 * @param DstAddress Between 0 to 0xFFFFFFFF
1419 * @param Direction This parameter can be one of the following values:
1420 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
1421 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
1422 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
1423 * @retval None
1424 */
LL_DMA_ConfigAddresses(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t SrcAddress,uint32_t DstAddress,uint32_t Direction)1425 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
1426 {
1427 /* Direction Memory to Periph */
1428 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
1429 {
1430 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress);
1431 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress);
1432 }
1433 /* Direction Periph to Memory and Memory to Memory */
1434 else
1435 {
1436 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress);
1437 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress);
1438 }
1439 }
1440
1441 /**
1442 * @brief Set the Memory address.
1443 * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress
1444 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1445 * @note This API must not be called when the DMA channel is enabled.
1446 * @param DMAx DMAx Instance
1447 * @param Stream This parameter can be one of the following values:
1448 * @arg @ref LL_DMA_STREAM_0
1449 * @arg @ref LL_DMA_STREAM_1
1450 * @arg @ref LL_DMA_STREAM_2
1451 * @arg @ref LL_DMA_STREAM_3
1452 * @arg @ref LL_DMA_STREAM_4
1453 * @arg @ref LL_DMA_STREAM_5
1454 * @arg @ref LL_DMA_STREAM_6
1455 * @arg @ref LL_DMA_STREAM_7
1456 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1457 * @retval None
1458 */
LL_DMA_SetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t MemoryAddress)1459 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
1460 {
1461 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
1462 }
1463
1464 /**
1465 * @brief Set the Peripheral address.
1466 * @rmtoll PAR PA LL_DMA_SetPeriphAddress
1467 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1468 * @note This API must not be called when the DMA channel is enabled.
1469 * @param DMAx DMAx Instance
1470 * @param Stream This parameter can be one of the following values:
1471 * @arg @ref LL_DMA_STREAM_0
1472 * @arg @ref LL_DMA_STREAM_1
1473 * @arg @ref LL_DMA_STREAM_2
1474 * @arg @ref LL_DMA_STREAM_3
1475 * @arg @ref LL_DMA_STREAM_4
1476 * @arg @ref LL_DMA_STREAM_5
1477 * @arg @ref LL_DMA_STREAM_6
1478 * @arg @ref LL_DMA_STREAM_7
1479 * @param PeriphAddress Between 0 to 0xFFFFFFFF
1480 * @retval None
1481 */
LL_DMA_SetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t PeriphAddress)1482 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress)
1483 {
1484 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress);
1485 }
1486
1487 /**
1488 * @brief Get the Memory address.
1489 * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress
1490 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1491 * @param DMAx DMAx Instance
1492 * @param Stream This parameter can be one of the following values:
1493 * @arg @ref LL_DMA_STREAM_0
1494 * @arg @ref LL_DMA_STREAM_1
1495 * @arg @ref LL_DMA_STREAM_2
1496 * @arg @ref LL_DMA_STREAM_3
1497 * @arg @ref LL_DMA_STREAM_4
1498 * @arg @ref LL_DMA_STREAM_5
1499 * @arg @ref LL_DMA_STREAM_6
1500 * @arg @ref LL_DMA_STREAM_7
1501 * @retval Between 0 to 0xFFFFFFFF
1502 */
LL_DMA_GetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Stream)1503 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1504 {
1505 return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
1506 }
1507
1508 /**
1509 * @brief Get the Peripheral address.
1510 * @rmtoll PAR PA LL_DMA_GetPeriphAddress
1511 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1512 * @param DMAx DMAx Instance
1513 * @param Stream This parameter can be one of the following values:
1514 * @arg @ref LL_DMA_STREAM_0
1515 * @arg @ref LL_DMA_STREAM_1
1516 * @arg @ref LL_DMA_STREAM_2
1517 * @arg @ref LL_DMA_STREAM_3
1518 * @arg @ref LL_DMA_STREAM_4
1519 * @arg @ref LL_DMA_STREAM_5
1520 * @arg @ref LL_DMA_STREAM_6
1521 * @arg @ref LL_DMA_STREAM_7
1522 * @retval Between 0 to 0xFFFFFFFF
1523 */
LL_DMA_GetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Stream)1524 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1525 {
1526 return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
1527 }
1528
1529 /**
1530 * @brief Set the Memory to Memory Source address.
1531 * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress
1532 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1533 * @note This API must not be called when the DMA channel is enabled.
1534 * @param DMAx DMAx Instance
1535 * @param Stream This parameter can be one of the following values:
1536 * @arg @ref LL_DMA_STREAM_0
1537 * @arg @ref LL_DMA_STREAM_1
1538 * @arg @ref LL_DMA_STREAM_2
1539 * @arg @ref LL_DMA_STREAM_3
1540 * @arg @ref LL_DMA_STREAM_4
1541 * @arg @ref LL_DMA_STREAM_5
1542 * @arg @ref LL_DMA_STREAM_6
1543 * @arg @ref LL_DMA_STREAM_7
1544 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1545 * @retval None
1546 */
LL_DMA_SetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t MemoryAddress)1547 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
1548 {
1549 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress);
1550 }
1551
1552 /**
1553 * @brief Set the Memory to Memory Destination address.
1554 * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress
1555 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1556 * @note This API must not be called when the DMA channel is enabled.
1557 * @param DMAx DMAx Instance
1558 * @param Stream This parameter can be one of the following values:
1559 * @arg @ref LL_DMA_STREAM_0
1560 * @arg @ref LL_DMA_STREAM_1
1561 * @arg @ref LL_DMA_STREAM_2
1562 * @arg @ref LL_DMA_STREAM_3
1563 * @arg @ref LL_DMA_STREAM_4
1564 * @arg @ref LL_DMA_STREAM_5
1565 * @arg @ref LL_DMA_STREAM_6
1566 * @arg @ref LL_DMA_STREAM_7
1567 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1568 * @retval None
1569 */
LL_DMA_SetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t MemoryAddress)1570 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
1571 {
1572 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
1573 }
1574
1575 /**
1576 * @brief Get the Memory to Memory Source address.
1577 * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress
1578 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1579 * @param DMAx DMAx Instance
1580 * @param Stream This parameter can be one of the following values:
1581 * @arg @ref LL_DMA_STREAM_0
1582 * @arg @ref LL_DMA_STREAM_1
1583 * @arg @ref LL_DMA_STREAM_2
1584 * @arg @ref LL_DMA_STREAM_3
1585 * @arg @ref LL_DMA_STREAM_4
1586 * @arg @ref LL_DMA_STREAM_5
1587 * @arg @ref LL_DMA_STREAM_6
1588 * @arg @ref LL_DMA_STREAM_7
1589 * @retval Between 0 to 0xFFFFFFFF
1590 */
LL_DMA_GetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Stream)1591 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1592 {
1593 return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
1594 }
1595
1596 /**
1597 * @brief Get the Memory to Memory Destination address.
1598 * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress
1599 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1600 * @param DMAx DMAx Instance
1601 * @param Stream This parameter can be one of the following values:
1602 * @arg @ref LL_DMA_STREAM_0
1603 * @arg @ref LL_DMA_STREAM_1
1604 * @arg @ref LL_DMA_STREAM_2
1605 * @arg @ref LL_DMA_STREAM_3
1606 * @arg @ref LL_DMA_STREAM_4
1607 * @arg @ref LL_DMA_STREAM_5
1608 * @arg @ref LL_DMA_STREAM_6
1609 * @arg @ref LL_DMA_STREAM_7
1610 * @retval Between 0 to 0xFFFFFFFF
1611 */
LL_DMA_GetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Stream)1612 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1613 {
1614 return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
1615 }
1616
1617 /**
1618 * @brief Set Memory 1 address (used in case of Double buffer mode).
1619 * @rmtoll M1AR M1A LL_DMA_SetMemory1Address
1620 * @param DMAx DMAx Instance
1621 * @param Stream This parameter can be one of the following values:
1622 * @arg @ref LL_DMA_STREAM_0
1623 * @arg @ref LL_DMA_STREAM_1
1624 * @arg @ref LL_DMA_STREAM_2
1625 * @arg @ref LL_DMA_STREAM_3
1626 * @arg @ref LL_DMA_STREAM_4
1627 * @arg @ref LL_DMA_STREAM_5
1628 * @arg @ref LL_DMA_STREAM_6
1629 * @arg @ref LL_DMA_STREAM_7
1630 * @param Address Between 0 to 0xFFFFFFFF
1631 * @retval None
1632 */
LL_DMA_SetMemory1Address(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Address)1633 __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
1634 {
1635 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, DMA_SxM1AR_M1A, Address);
1636 }
1637
1638 /**
1639 * @brief Get Memory 1 address (used in case of Double buffer mode).
1640 * @rmtoll M1AR M1A LL_DMA_GetMemory1Address
1641 * @param DMAx DMAx Instance
1642 * @param Stream This parameter can be one of the following values:
1643 * @arg @ref LL_DMA_STREAM_0
1644 * @arg @ref LL_DMA_STREAM_1
1645 * @arg @ref LL_DMA_STREAM_2
1646 * @arg @ref LL_DMA_STREAM_3
1647 * @arg @ref LL_DMA_STREAM_4
1648 * @arg @ref LL_DMA_STREAM_5
1649 * @arg @ref LL_DMA_STREAM_6
1650 * @arg @ref LL_DMA_STREAM_7
1651 * @retval Between 0 to 0xFFFFFFFF
1652 */
LL_DMA_GetMemory1Address(DMA_TypeDef * DMAx,uint32_t Stream)1653 __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
1654 {
1655 return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR);
1656 }
1657
1658 /**
1659 * @}
1660 */
1661
1662 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1663 * @{
1664 */
1665
1666 /**
1667 * @brief Get Stream 0 half transfer flag.
1668 * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0
1669 * @param DMAx DMAx Instance
1670 * @retval State of bit (1 or 0).
1671 */
LL_DMA_IsActiveFlag_HT0(DMA_TypeDef * DMAx)1672 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
1673 {
1674 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0));
1675 }
1676
1677 /**
1678 * @brief Get Stream 1 half transfer flag.
1679 * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1
1680 * @param DMAx DMAx Instance
1681 * @retval State of bit (1 or 0).
1682 */
LL_DMA_IsActiveFlag_HT1(DMA_TypeDef * DMAx)1683 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
1684 {
1685 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1));
1686 }
1687
1688 /**
1689 * @brief Get Stream 2 half transfer flag.
1690 * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2
1691 * @param DMAx DMAx Instance
1692 * @retval State of bit (1 or 0).
1693 */
LL_DMA_IsActiveFlag_HT2(DMA_TypeDef * DMAx)1694 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
1695 {
1696 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2));
1697 }
1698
1699 /**
1700 * @brief Get Stream 3 half transfer flag.
1701 * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3
1702 * @param DMAx DMAx Instance
1703 * @retval State of bit (1 or 0).
1704 */
LL_DMA_IsActiveFlag_HT3(DMA_TypeDef * DMAx)1705 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
1706 {
1707 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3));
1708 }
1709
1710 /**
1711 * @brief Get Stream 4 half transfer flag.
1712 * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4
1713 * @param DMAx DMAx Instance
1714 * @retval State of bit (1 or 0).
1715 */
LL_DMA_IsActiveFlag_HT4(DMA_TypeDef * DMAx)1716 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
1717 {
1718 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4));
1719 }
1720
1721 /**
1722 * @brief Get Stream 5 half transfer flag.
1723 * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5
1724 * @param DMAx DMAx Instance
1725 * @retval State of bit (1 or 0).
1726 */
LL_DMA_IsActiveFlag_HT5(DMA_TypeDef * DMAx)1727 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
1728 {
1729 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5));
1730 }
1731
1732 /**
1733 * @brief Get Stream 6 half transfer flag.
1734 * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6
1735 * @param DMAx DMAx Instance
1736 * @retval State of bit (1 or 0).
1737 */
LL_DMA_IsActiveFlag_HT6(DMA_TypeDef * DMAx)1738 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
1739 {
1740 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6));
1741 }
1742
1743 /**
1744 * @brief Get Stream 7 half transfer flag.
1745 * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7
1746 * @param DMAx DMAx Instance
1747 * @retval State of bit (1 or 0).
1748 */
LL_DMA_IsActiveFlag_HT7(DMA_TypeDef * DMAx)1749 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
1750 {
1751 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7));
1752 }
1753
1754 /**
1755 * @brief Get Stream 0 transfer complete flag.
1756 * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0
1757 * @param DMAx DMAx Instance
1758 * @retval State of bit (1 or 0).
1759 */
LL_DMA_IsActiveFlag_TC0(DMA_TypeDef * DMAx)1760 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
1761 {
1762 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0));
1763 }
1764
1765 /**
1766 * @brief Get Stream 1 transfer complete flag.
1767 * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1
1768 * @param DMAx DMAx Instance
1769 * @retval State of bit (1 or 0).
1770 */
LL_DMA_IsActiveFlag_TC1(DMA_TypeDef * DMAx)1771 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
1772 {
1773 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1));
1774 }
1775
1776 /**
1777 * @brief Get Stream 2 transfer complete flag.
1778 * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2
1779 * @param DMAx DMAx Instance
1780 * @retval State of bit (1 or 0).
1781 */
LL_DMA_IsActiveFlag_TC2(DMA_TypeDef * DMAx)1782 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
1783 {
1784 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2));
1785 }
1786
1787 /**
1788 * @brief Get Stream 3 transfer complete flag.
1789 * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3
1790 * @param DMAx DMAx Instance
1791 * @retval State of bit (1 or 0).
1792 */
LL_DMA_IsActiveFlag_TC3(DMA_TypeDef * DMAx)1793 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
1794 {
1795 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3));
1796 }
1797
1798 /**
1799 * @brief Get Stream 4 transfer complete flag.
1800 * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4
1801 * @param DMAx DMAx Instance
1802 * @retval State of bit (1 or 0).
1803 */
LL_DMA_IsActiveFlag_TC4(DMA_TypeDef * DMAx)1804 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
1805 {
1806 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4));
1807 }
1808
1809 /**
1810 * @brief Get Stream 5 transfer complete flag.
1811 * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5
1812 * @param DMAx DMAx Instance
1813 * @retval State of bit (1 or 0).
1814 */
LL_DMA_IsActiveFlag_TC5(DMA_TypeDef * DMAx)1815 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
1816 {
1817 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5));
1818 }
1819
1820 /**
1821 * @brief Get Stream 6 transfer complete flag.
1822 * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6
1823 * @param DMAx DMAx Instance
1824 * @retval State of bit (1 or 0).
1825 */
LL_DMA_IsActiveFlag_TC6(DMA_TypeDef * DMAx)1826 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
1827 {
1828 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6));
1829 }
1830
1831 /**
1832 * @brief Get Stream 7 transfer complete flag.
1833 * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7
1834 * @param DMAx DMAx Instance
1835 * @retval State of bit (1 or 0).
1836 */
LL_DMA_IsActiveFlag_TC7(DMA_TypeDef * DMAx)1837 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
1838 {
1839 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7));
1840 }
1841
1842 /**
1843 * @brief Get Stream 0 transfer error flag.
1844 * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0
1845 * @param DMAx DMAx Instance
1846 * @retval State of bit (1 or 0).
1847 */
LL_DMA_IsActiveFlag_TE0(DMA_TypeDef * DMAx)1848 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
1849 {
1850 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0));
1851 }
1852
1853 /**
1854 * @brief Get Stream 1 transfer error flag.
1855 * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1
1856 * @param DMAx DMAx Instance
1857 * @retval State of bit (1 or 0).
1858 */
LL_DMA_IsActiveFlag_TE1(DMA_TypeDef * DMAx)1859 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
1860 {
1861 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1));
1862 }
1863
1864 /**
1865 * @brief Get Stream 2 transfer error flag.
1866 * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2
1867 * @param DMAx DMAx Instance
1868 * @retval State of bit (1 or 0).
1869 */
LL_DMA_IsActiveFlag_TE2(DMA_TypeDef * DMAx)1870 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
1871 {
1872 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2));
1873 }
1874
1875 /**
1876 * @brief Get Stream 3 transfer error flag.
1877 * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3
1878 * @param DMAx DMAx Instance
1879 * @retval State of bit (1 or 0).
1880 */
LL_DMA_IsActiveFlag_TE3(DMA_TypeDef * DMAx)1881 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
1882 {
1883 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3));
1884 }
1885
1886 /**
1887 * @brief Get Stream 4 transfer error flag.
1888 * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4
1889 * @param DMAx DMAx Instance
1890 * @retval State of bit (1 or 0).
1891 */
LL_DMA_IsActiveFlag_TE4(DMA_TypeDef * DMAx)1892 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
1893 {
1894 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4));
1895 }
1896
1897 /**
1898 * @brief Get Stream 5 transfer error flag.
1899 * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5
1900 * @param DMAx DMAx Instance
1901 * @retval State of bit (1 or 0).
1902 */
LL_DMA_IsActiveFlag_TE5(DMA_TypeDef * DMAx)1903 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
1904 {
1905 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5));
1906 }
1907
1908 /**
1909 * @brief Get Stream 6 transfer error flag.
1910 * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6
1911 * @param DMAx DMAx Instance
1912 * @retval State of bit (1 or 0).
1913 */
LL_DMA_IsActiveFlag_TE6(DMA_TypeDef * DMAx)1914 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
1915 {
1916 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6));
1917 }
1918
1919 /**
1920 * @brief Get Stream 7 transfer error flag.
1921 * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7
1922 * @param DMAx DMAx Instance
1923 * @retval State of bit (1 or 0).
1924 */
LL_DMA_IsActiveFlag_TE7(DMA_TypeDef * DMAx)1925 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
1926 {
1927 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7));
1928 }
1929
1930 /**
1931 * @brief Get Stream 0 direct mode error flag.
1932 * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0
1933 * @param DMAx DMAx Instance
1934 * @retval State of bit (1 or 0).
1935 */
LL_DMA_IsActiveFlag_DME0(DMA_TypeDef * DMAx)1936 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
1937 {
1938 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0));
1939 }
1940
1941 /**
1942 * @brief Get Stream 1 direct mode error flag.
1943 * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1
1944 * @param DMAx DMAx Instance
1945 * @retval State of bit (1 or 0).
1946 */
LL_DMA_IsActiveFlag_DME1(DMA_TypeDef * DMAx)1947 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
1948 {
1949 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1));
1950 }
1951
1952 /**
1953 * @brief Get Stream 2 direct mode error flag.
1954 * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2
1955 * @param DMAx DMAx Instance
1956 * @retval State of bit (1 or 0).
1957 */
LL_DMA_IsActiveFlag_DME2(DMA_TypeDef * DMAx)1958 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
1959 {
1960 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2));
1961 }
1962
1963 /**
1964 * @brief Get Stream 3 direct mode error flag.
1965 * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3
1966 * @param DMAx DMAx Instance
1967 * @retval State of bit (1 or 0).
1968 */
LL_DMA_IsActiveFlag_DME3(DMA_TypeDef * DMAx)1969 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
1970 {
1971 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3));
1972 }
1973
1974 /**
1975 * @brief Get Stream 4 direct mode error flag.
1976 * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4
1977 * @param DMAx DMAx Instance
1978 * @retval State of bit (1 or 0).
1979 */
LL_DMA_IsActiveFlag_DME4(DMA_TypeDef * DMAx)1980 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
1981 {
1982 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4));
1983 }
1984
1985 /**
1986 * @brief Get Stream 5 direct mode error flag.
1987 * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5
1988 * @param DMAx DMAx Instance
1989 * @retval State of bit (1 or 0).
1990 */
LL_DMA_IsActiveFlag_DME5(DMA_TypeDef * DMAx)1991 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
1992 {
1993 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5));
1994 }
1995
1996 /**
1997 * @brief Get Stream 6 direct mode error flag.
1998 * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6
1999 * @param DMAx DMAx Instance
2000 * @retval State of bit (1 or 0).
2001 */
LL_DMA_IsActiveFlag_DME6(DMA_TypeDef * DMAx)2002 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
2003 {
2004 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6));
2005 }
2006
2007 /**
2008 * @brief Get Stream 7 direct mode error flag.
2009 * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7
2010 * @param DMAx DMAx Instance
2011 * @retval State of bit (1 or 0).
2012 */
LL_DMA_IsActiveFlag_DME7(DMA_TypeDef * DMAx)2013 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
2014 {
2015 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7));
2016 }
2017
2018 /**
2019 * @brief Get Stream 0 FIFO error flag.
2020 * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0
2021 * @param DMAx DMAx Instance
2022 * @retval State of bit (1 or 0).
2023 */
LL_DMA_IsActiveFlag_FE0(DMA_TypeDef * DMAx)2024 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
2025 {
2026 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0));
2027 }
2028
2029 /**
2030 * @brief Get Stream 1 FIFO error flag.
2031 * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1
2032 * @param DMAx DMAx Instance
2033 * @retval State of bit (1 or 0).
2034 */
LL_DMA_IsActiveFlag_FE1(DMA_TypeDef * DMAx)2035 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
2036 {
2037 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1));
2038 }
2039
2040 /**
2041 * @brief Get Stream 2 FIFO error flag.
2042 * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2
2043 * @param DMAx DMAx Instance
2044 * @retval State of bit (1 or 0).
2045 */
LL_DMA_IsActiveFlag_FE2(DMA_TypeDef * DMAx)2046 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
2047 {
2048 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2));
2049 }
2050
2051 /**
2052 * @brief Get Stream 3 FIFO error flag.
2053 * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3
2054 * @param DMAx DMAx Instance
2055 * @retval State of bit (1 or 0).
2056 */
LL_DMA_IsActiveFlag_FE3(DMA_TypeDef * DMAx)2057 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
2058 {
2059 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3));
2060 }
2061
2062 /**
2063 * @brief Get Stream 4 FIFO error flag.
2064 * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4
2065 * @param DMAx DMAx Instance
2066 * @retval State of bit (1 or 0).
2067 */
LL_DMA_IsActiveFlag_FE4(DMA_TypeDef * DMAx)2068 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
2069 {
2070 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4));
2071 }
2072
2073 /**
2074 * @brief Get Stream 5 FIFO error flag.
2075 * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5
2076 * @param DMAx DMAx Instance
2077 * @retval State of bit (1 or 0).
2078 */
LL_DMA_IsActiveFlag_FE5(DMA_TypeDef * DMAx)2079 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
2080 {
2081 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5));
2082 }
2083
2084 /**
2085 * @brief Get Stream 6 FIFO error flag.
2086 * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6
2087 * @param DMAx DMAx Instance
2088 * @retval State of bit (1 or 0).
2089 */
LL_DMA_IsActiveFlag_FE6(DMA_TypeDef * DMAx)2090 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
2091 {
2092 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6));
2093 }
2094
2095 /**
2096 * @brief Get Stream 7 FIFO error flag.
2097 * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7
2098 * @param DMAx DMAx Instance
2099 * @retval State of bit (1 or 0).
2100 */
LL_DMA_IsActiveFlag_FE7(DMA_TypeDef * DMAx)2101 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
2102 {
2103 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7));
2104 }
2105
2106 /**
2107 * @brief Clear Stream 0 half transfer flag.
2108 * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0
2109 * @param DMAx DMAx Instance
2110 * @retval None
2111 */
LL_DMA_ClearFlag_HT0(DMA_TypeDef * DMAx)2112 __STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
2113 {
2114 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0);
2115 }
2116
2117 /**
2118 * @brief Clear Stream 1 half transfer flag.
2119 * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1
2120 * @param DMAx DMAx Instance
2121 * @retval None
2122 */
LL_DMA_ClearFlag_HT1(DMA_TypeDef * DMAx)2123 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
2124 {
2125 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1);
2126 }
2127
2128 /**
2129 * @brief Clear Stream 2 half transfer flag.
2130 * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2
2131 * @param DMAx DMAx Instance
2132 * @retval None
2133 */
LL_DMA_ClearFlag_HT2(DMA_TypeDef * DMAx)2134 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
2135 {
2136 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2);
2137 }
2138
2139 /**
2140 * @brief Clear Stream 3 half transfer flag.
2141 * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3
2142 * @param DMAx DMAx Instance
2143 * @retval None
2144 */
LL_DMA_ClearFlag_HT3(DMA_TypeDef * DMAx)2145 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
2146 {
2147 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3);
2148 }
2149
2150 /**
2151 * @brief Clear Stream 4 half transfer flag.
2152 * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4
2153 * @param DMAx DMAx Instance
2154 * @retval None
2155 */
LL_DMA_ClearFlag_HT4(DMA_TypeDef * DMAx)2156 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
2157 {
2158 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4);
2159 }
2160
2161 /**
2162 * @brief Clear Stream 5 half transfer flag.
2163 * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5
2164 * @param DMAx DMAx Instance
2165 * @retval None
2166 */
LL_DMA_ClearFlag_HT5(DMA_TypeDef * DMAx)2167 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
2168 {
2169 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5);
2170 }
2171
2172 /**
2173 * @brief Clear Stream 6 half transfer flag.
2174 * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6
2175 * @param DMAx DMAx Instance
2176 * @retval None
2177 */
LL_DMA_ClearFlag_HT6(DMA_TypeDef * DMAx)2178 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
2179 {
2180 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6);
2181 }
2182
2183 /**
2184 * @brief Clear Stream 7 half transfer flag.
2185 * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7
2186 * @param DMAx DMAx Instance
2187 * @retval None
2188 */
LL_DMA_ClearFlag_HT7(DMA_TypeDef * DMAx)2189 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
2190 {
2191 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7);
2192 }
2193
2194 /**
2195 * @brief Clear Stream 0 transfer complete flag.
2196 * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0
2197 * @param DMAx DMAx Instance
2198 * @retval None
2199 */
LL_DMA_ClearFlag_TC0(DMA_TypeDef * DMAx)2200 __STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
2201 {
2202 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0);
2203 }
2204
2205 /**
2206 * @brief Clear Stream 1 transfer complete flag.
2207 * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1
2208 * @param DMAx DMAx Instance
2209 * @retval None
2210 */
LL_DMA_ClearFlag_TC1(DMA_TypeDef * DMAx)2211 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
2212 {
2213 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1);
2214 }
2215
2216 /**
2217 * @brief Clear Stream 2 transfer complete flag.
2218 * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2
2219 * @param DMAx DMAx Instance
2220 * @retval None
2221 */
LL_DMA_ClearFlag_TC2(DMA_TypeDef * DMAx)2222 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
2223 {
2224 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2);
2225 }
2226
2227 /**
2228 * @brief Clear Stream 3 transfer complete flag.
2229 * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3
2230 * @param DMAx DMAx Instance
2231 * @retval None
2232 */
LL_DMA_ClearFlag_TC3(DMA_TypeDef * DMAx)2233 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
2234 {
2235 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3);
2236 }
2237
2238 /**
2239 * @brief Clear Stream 4 transfer complete flag.
2240 * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4
2241 * @param DMAx DMAx Instance
2242 * @retval None
2243 */
LL_DMA_ClearFlag_TC4(DMA_TypeDef * DMAx)2244 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
2245 {
2246 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4);
2247 }
2248
2249 /**
2250 * @brief Clear Stream 5 transfer complete flag.
2251 * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5
2252 * @param DMAx DMAx Instance
2253 * @retval None
2254 */
LL_DMA_ClearFlag_TC5(DMA_TypeDef * DMAx)2255 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
2256 {
2257 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5);
2258 }
2259
2260 /**
2261 * @brief Clear Stream 6 transfer complete flag.
2262 * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6
2263 * @param DMAx DMAx Instance
2264 * @retval None
2265 */
LL_DMA_ClearFlag_TC6(DMA_TypeDef * DMAx)2266 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
2267 {
2268 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6);
2269 }
2270
2271 /**
2272 * @brief Clear Stream 7 transfer complete flag.
2273 * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7
2274 * @param DMAx DMAx Instance
2275 * @retval None
2276 */
LL_DMA_ClearFlag_TC7(DMA_TypeDef * DMAx)2277 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
2278 {
2279 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7);
2280 }
2281
2282 /**
2283 * @brief Clear Stream 0 transfer error flag.
2284 * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0
2285 * @param DMAx DMAx Instance
2286 * @retval None
2287 */
LL_DMA_ClearFlag_TE0(DMA_TypeDef * DMAx)2288 __STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
2289 {
2290 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0);
2291 }
2292
2293 /**
2294 * @brief Clear Stream 1 transfer error flag.
2295 * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1
2296 * @param DMAx DMAx Instance
2297 * @retval None
2298 */
LL_DMA_ClearFlag_TE1(DMA_TypeDef * DMAx)2299 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
2300 {
2301 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1);
2302 }
2303
2304 /**
2305 * @brief Clear Stream 2 transfer error flag.
2306 * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2
2307 * @param DMAx DMAx Instance
2308 * @retval None
2309 */
LL_DMA_ClearFlag_TE2(DMA_TypeDef * DMAx)2310 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
2311 {
2312 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2);
2313 }
2314
2315 /**
2316 * @brief Clear Stream 3 transfer error flag.
2317 * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3
2318 * @param DMAx DMAx Instance
2319 * @retval None
2320 */
LL_DMA_ClearFlag_TE3(DMA_TypeDef * DMAx)2321 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
2322 {
2323 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3);
2324 }
2325
2326 /**
2327 * @brief Clear Stream 4 transfer error flag.
2328 * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4
2329 * @param DMAx DMAx Instance
2330 * @retval None
2331 */
LL_DMA_ClearFlag_TE4(DMA_TypeDef * DMAx)2332 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
2333 {
2334 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4);
2335 }
2336
2337 /**
2338 * @brief Clear Stream 5 transfer error flag.
2339 * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5
2340 * @param DMAx DMAx Instance
2341 * @retval None
2342 */
LL_DMA_ClearFlag_TE5(DMA_TypeDef * DMAx)2343 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
2344 {
2345 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5);
2346 }
2347
2348 /**
2349 * @brief Clear Stream 6 transfer error flag.
2350 * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6
2351 * @param DMAx DMAx Instance
2352 * @retval None
2353 */
LL_DMA_ClearFlag_TE6(DMA_TypeDef * DMAx)2354 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
2355 {
2356 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6);
2357 }
2358
2359 /**
2360 * @brief Clear Stream 7 transfer error flag.
2361 * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7
2362 * @param DMAx DMAx Instance
2363 * @retval None
2364 */
LL_DMA_ClearFlag_TE7(DMA_TypeDef * DMAx)2365 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
2366 {
2367 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7);
2368 }
2369
2370 /**
2371 * @brief Clear Stream 0 direct mode error flag.
2372 * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0
2373 * @param DMAx DMAx Instance
2374 * @retval None
2375 */
LL_DMA_ClearFlag_DME0(DMA_TypeDef * DMAx)2376 __STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
2377 {
2378 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0);
2379 }
2380
2381 /**
2382 * @brief Clear Stream 1 direct mode error flag.
2383 * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1
2384 * @param DMAx DMAx Instance
2385 * @retval None
2386 */
LL_DMA_ClearFlag_DME1(DMA_TypeDef * DMAx)2387 __STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
2388 {
2389 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1);
2390 }
2391
2392 /**
2393 * @brief Clear Stream 2 direct mode error flag.
2394 * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2
2395 * @param DMAx DMAx Instance
2396 * @retval None
2397 */
LL_DMA_ClearFlag_DME2(DMA_TypeDef * DMAx)2398 __STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
2399 {
2400 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2);
2401 }
2402
2403 /**
2404 * @brief Clear Stream 3 direct mode error flag.
2405 * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3
2406 * @param DMAx DMAx Instance
2407 * @retval None
2408 */
LL_DMA_ClearFlag_DME3(DMA_TypeDef * DMAx)2409 __STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
2410 {
2411 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3);
2412 }
2413
2414 /**
2415 * @brief Clear Stream 4 direct mode error flag.
2416 * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4
2417 * @param DMAx DMAx Instance
2418 * @retval None
2419 */
LL_DMA_ClearFlag_DME4(DMA_TypeDef * DMAx)2420 __STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
2421 {
2422 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4);
2423 }
2424
2425 /**
2426 * @brief Clear Stream 5 direct mode error flag.
2427 * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5
2428 * @param DMAx DMAx Instance
2429 * @retval None
2430 */
LL_DMA_ClearFlag_DME5(DMA_TypeDef * DMAx)2431 __STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
2432 {
2433 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5);
2434 }
2435
2436 /**
2437 * @brief Clear Stream 6 direct mode error flag.
2438 * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6
2439 * @param DMAx DMAx Instance
2440 * @retval None
2441 */
LL_DMA_ClearFlag_DME6(DMA_TypeDef * DMAx)2442 __STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
2443 {
2444 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6);
2445 }
2446
2447 /**
2448 * @brief Clear Stream 7 direct mode error flag.
2449 * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7
2450 * @param DMAx DMAx Instance
2451 * @retval None
2452 */
LL_DMA_ClearFlag_DME7(DMA_TypeDef * DMAx)2453 __STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
2454 {
2455 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7);
2456 }
2457
2458 /**
2459 * @brief Clear Stream 0 FIFO error flag.
2460 * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0
2461 * @param DMAx DMAx Instance
2462 * @retval None
2463 */
LL_DMA_ClearFlag_FE0(DMA_TypeDef * DMAx)2464 __STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
2465 {
2466 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0);
2467 }
2468
2469 /**
2470 * @brief Clear Stream 1 FIFO error flag.
2471 * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1
2472 * @param DMAx DMAx Instance
2473 * @retval None
2474 */
LL_DMA_ClearFlag_FE1(DMA_TypeDef * DMAx)2475 __STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
2476 {
2477 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1);
2478 }
2479
2480 /**
2481 * @brief Clear Stream 2 FIFO error flag.
2482 * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2
2483 * @param DMAx DMAx Instance
2484 * @retval None
2485 */
LL_DMA_ClearFlag_FE2(DMA_TypeDef * DMAx)2486 __STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
2487 {
2488 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2);
2489 }
2490
2491 /**
2492 * @brief Clear Stream 3 FIFO error flag.
2493 * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3
2494 * @param DMAx DMAx Instance
2495 * @retval None
2496 */
LL_DMA_ClearFlag_FE3(DMA_TypeDef * DMAx)2497 __STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
2498 {
2499 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3);
2500 }
2501
2502 /**
2503 * @brief Clear Stream 4 FIFO error flag.
2504 * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4
2505 * @param DMAx DMAx Instance
2506 * @retval None
2507 */
LL_DMA_ClearFlag_FE4(DMA_TypeDef * DMAx)2508 __STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
2509 {
2510 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4);
2511 }
2512
2513 /**
2514 * @brief Clear Stream 5 FIFO error flag.
2515 * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5
2516 * @param DMAx DMAx Instance
2517 * @retval None
2518 */
LL_DMA_ClearFlag_FE5(DMA_TypeDef * DMAx)2519 __STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
2520 {
2521 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5);
2522 }
2523
2524 /**
2525 * @brief Clear Stream 6 FIFO error flag.
2526 * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6
2527 * @param DMAx DMAx Instance
2528 * @retval None
2529 */
LL_DMA_ClearFlag_FE6(DMA_TypeDef * DMAx)2530 __STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
2531 {
2532 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6);
2533 }
2534
2535 /**
2536 * @brief Clear Stream 7 FIFO error flag.
2537 * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7
2538 * @param DMAx DMAx Instance
2539 * @retval None
2540 */
LL_DMA_ClearFlag_FE7(DMA_TypeDef * DMAx)2541 __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
2542 {
2543 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7);
2544 }
2545
2546 /**
2547 * @}
2548 */
2549
2550 /** @defgroup DMA_LL_EF_IT_Management IT_Management
2551 * @{
2552 */
2553
2554 /**
2555 * @brief Enable Half transfer interrupt.
2556 * @rmtoll CR HTIE LL_DMA_EnableIT_HT
2557 * @param DMAx DMAx Instance
2558 * @param Stream This parameter can be one of the following values:
2559 * @arg @ref LL_DMA_STREAM_0
2560 * @arg @ref LL_DMA_STREAM_1
2561 * @arg @ref LL_DMA_STREAM_2
2562 * @arg @ref LL_DMA_STREAM_3
2563 * @arg @ref LL_DMA_STREAM_4
2564 * @arg @ref LL_DMA_STREAM_5
2565 * @arg @ref LL_DMA_STREAM_6
2566 * @arg @ref LL_DMA_STREAM_7
2567 * @retval None
2568 */
LL_DMA_EnableIT_HT(DMA_TypeDef * DMAx,uint32_t Stream)2569 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
2570 {
2571 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
2572 }
2573
2574 /**
2575 * @brief Enable Transfer error interrupt.
2576 * @rmtoll CR TEIE LL_DMA_EnableIT_TE
2577 * @param DMAx DMAx Instance
2578 * @param Stream This parameter can be one of the following values:
2579 * @arg @ref LL_DMA_STREAM_0
2580 * @arg @ref LL_DMA_STREAM_1
2581 * @arg @ref LL_DMA_STREAM_2
2582 * @arg @ref LL_DMA_STREAM_3
2583 * @arg @ref LL_DMA_STREAM_4
2584 * @arg @ref LL_DMA_STREAM_5
2585 * @arg @ref LL_DMA_STREAM_6
2586 * @arg @ref LL_DMA_STREAM_7
2587 * @retval None
2588 */
LL_DMA_EnableIT_TE(DMA_TypeDef * DMAx,uint32_t Stream)2589 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
2590 {
2591 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
2592 }
2593
2594 /**
2595 * @brief Enable Transfer complete interrupt.
2596 * @rmtoll CR TCIE LL_DMA_EnableIT_TC
2597 * @param DMAx DMAx Instance
2598 * @param Stream This parameter can be one of the following values:
2599 * @arg @ref LL_DMA_STREAM_0
2600 * @arg @ref LL_DMA_STREAM_1
2601 * @arg @ref LL_DMA_STREAM_2
2602 * @arg @ref LL_DMA_STREAM_3
2603 * @arg @ref LL_DMA_STREAM_4
2604 * @arg @ref LL_DMA_STREAM_5
2605 * @arg @ref LL_DMA_STREAM_6
2606 * @arg @ref LL_DMA_STREAM_7
2607 * @retval None
2608 */
LL_DMA_EnableIT_TC(DMA_TypeDef * DMAx,uint32_t Stream)2609 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
2610 {
2611 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
2612 }
2613
2614 /**
2615 * @brief Enable Direct mode error interrupt.
2616 * @rmtoll CR DMEIE LL_DMA_EnableIT_DME
2617 * @param DMAx DMAx Instance
2618 * @param Stream This parameter can be one of the following values:
2619 * @arg @ref LL_DMA_STREAM_0
2620 * @arg @ref LL_DMA_STREAM_1
2621 * @arg @ref LL_DMA_STREAM_2
2622 * @arg @ref LL_DMA_STREAM_3
2623 * @arg @ref LL_DMA_STREAM_4
2624 * @arg @ref LL_DMA_STREAM_5
2625 * @arg @ref LL_DMA_STREAM_6
2626 * @arg @ref LL_DMA_STREAM_7
2627 * @retval None
2628 */
LL_DMA_EnableIT_DME(DMA_TypeDef * DMAx,uint32_t Stream)2629 __STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
2630 {
2631 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
2632 }
2633
2634 /**
2635 * @brief Enable FIFO error interrupt.
2636 * @rmtoll FCR FEIE LL_DMA_EnableIT_FE
2637 * @param DMAx DMAx Instance
2638 * @param Stream This parameter can be one of the following values:
2639 * @arg @ref LL_DMA_STREAM_0
2640 * @arg @ref LL_DMA_STREAM_1
2641 * @arg @ref LL_DMA_STREAM_2
2642 * @arg @ref LL_DMA_STREAM_3
2643 * @arg @ref LL_DMA_STREAM_4
2644 * @arg @ref LL_DMA_STREAM_5
2645 * @arg @ref LL_DMA_STREAM_6
2646 * @arg @ref LL_DMA_STREAM_7
2647 * @retval None
2648 */
LL_DMA_EnableIT_FE(DMA_TypeDef * DMAx,uint32_t Stream)2649 __STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
2650 {
2651 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
2652 }
2653
2654 /**
2655 * @brief Disable Half transfer interrupt.
2656 * @rmtoll CR HTIE LL_DMA_DisableIT_HT
2657 * @param DMAx DMAx Instance
2658 * @param Stream This parameter can be one of the following values:
2659 * @arg @ref LL_DMA_STREAM_0
2660 * @arg @ref LL_DMA_STREAM_1
2661 * @arg @ref LL_DMA_STREAM_2
2662 * @arg @ref LL_DMA_STREAM_3
2663 * @arg @ref LL_DMA_STREAM_4
2664 * @arg @ref LL_DMA_STREAM_5
2665 * @arg @ref LL_DMA_STREAM_6
2666 * @arg @ref LL_DMA_STREAM_7
2667 * @retval None
2668 */
LL_DMA_DisableIT_HT(DMA_TypeDef * DMAx,uint32_t Stream)2669 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
2670 {
2671 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
2672 }
2673
2674 /**
2675 * @brief Disable Transfer error interrupt.
2676 * @rmtoll CR TEIE LL_DMA_DisableIT_TE
2677 * @param DMAx DMAx Instance
2678 * @param Stream This parameter can be one of the following values:
2679 * @arg @ref LL_DMA_STREAM_0
2680 * @arg @ref LL_DMA_STREAM_1
2681 * @arg @ref LL_DMA_STREAM_2
2682 * @arg @ref LL_DMA_STREAM_3
2683 * @arg @ref LL_DMA_STREAM_4
2684 * @arg @ref LL_DMA_STREAM_5
2685 * @arg @ref LL_DMA_STREAM_6
2686 * @arg @ref LL_DMA_STREAM_7
2687 * @retval None
2688 */
LL_DMA_DisableIT_TE(DMA_TypeDef * DMAx,uint32_t Stream)2689 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
2690 {
2691 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
2692 }
2693
2694 /**
2695 * @brief Disable Transfer complete interrupt.
2696 * @rmtoll CR TCIE LL_DMA_DisableIT_TC
2697 * @param DMAx DMAx Instance
2698 * @param Stream This parameter can be one of the following values:
2699 * @arg @ref LL_DMA_STREAM_0
2700 * @arg @ref LL_DMA_STREAM_1
2701 * @arg @ref LL_DMA_STREAM_2
2702 * @arg @ref LL_DMA_STREAM_3
2703 * @arg @ref LL_DMA_STREAM_4
2704 * @arg @ref LL_DMA_STREAM_5
2705 * @arg @ref LL_DMA_STREAM_6
2706 * @arg @ref LL_DMA_STREAM_7
2707 * @retval None
2708 */
LL_DMA_DisableIT_TC(DMA_TypeDef * DMAx,uint32_t Stream)2709 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
2710 {
2711 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
2712 }
2713
2714 /**
2715 * @brief Disable Direct mode error interrupt.
2716 * @rmtoll CR DMEIE LL_DMA_DisableIT_DME
2717 * @param DMAx DMAx Instance
2718 * @param Stream This parameter can be one of the following values:
2719 * @arg @ref LL_DMA_STREAM_0
2720 * @arg @ref LL_DMA_STREAM_1
2721 * @arg @ref LL_DMA_STREAM_2
2722 * @arg @ref LL_DMA_STREAM_3
2723 * @arg @ref LL_DMA_STREAM_4
2724 * @arg @ref LL_DMA_STREAM_5
2725 * @arg @ref LL_DMA_STREAM_6
2726 * @arg @ref LL_DMA_STREAM_7
2727 * @retval None
2728 */
LL_DMA_DisableIT_DME(DMA_TypeDef * DMAx,uint32_t Stream)2729 __STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
2730 {
2731 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
2732 }
2733
2734 /**
2735 * @brief Disable FIFO error interrupt.
2736 * @rmtoll FCR FEIE LL_DMA_DisableIT_FE
2737 * @param DMAx DMAx Instance
2738 * @param Stream This parameter can be one of the following values:
2739 * @arg @ref LL_DMA_STREAM_0
2740 * @arg @ref LL_DMA_STREAM_1
2741 * @arg @ref LL_DMA_STREAM_2
2742 * @arg @ref LL_DMA_STREAM_3
2743 * @arg @ref LL_DMA_STREAM_4
2744 * @arg @ref LL_DMA_STREAM_5
2745 * @arg @ref LL_DMA_STREAM_6
2746 * @arg @ref LL_DMA_STREAM_7
2747 * @retval None
2748 */
LL_DMA_DisableIT_FE(DMA_TypeDef * DMAx,uint32_t Stream)2749 __STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
2750 {
2751 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
2752 }
2753
2754 /**
2755 * @brief Check if Half transfer interrup is enabled.
2756 * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT
2757 * @param DMAx DMAx Instance
2758 * @param Stream This parameter can be one of the following values:
2759 * @arg @ref LL_DMA_STREAM_0
2760 * @arg @ref LL_DMA_STREAM_1
2761 * @arg @ref LL_DMA_STREAM_2
2762 * @arg @ref LL_DMA_STREAM_3
2763 * @arg @ref LL_DMA_STREAM_4
2764 * @arg @ref LL_DMA_STREAM_5
2765 * @arg @ref LL_DMA_STREAM_6
2766 * @arg @ref LL_DMA_STREAM_7
2767 * @retval State of bit (1 or 0).
2768 */
LL_DMA_IsEnabledIT_HT(DMA_TypeDef * DMAx,uint32_t Stream)2769 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
2770 {
2771 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE);
2772 }
2773
2774 /**
2775 * @brief Check if Transfer error nterrup is enabled.
2776 * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE
2777 * @param DMAx DMAx Instance
2778 * @param Stream This parameter can be one of the following values:
2779 * @arg @ref LL_DMA_STREAM_0
2780 * @arg @ref LL_DMA_STREAM_1
2781 * @arg @ref LL_DMA_STREAM_2
2782 * @arg @ref LL_DMA_STREAM_3
2783 * @arg @ref LL_DMA_STREAM_4
2784 * @arg @ref LL_DMA_STREAM_5
2785 * @arg @ref LL_DMA_STREAM_6
2786 * @arg @ref LL_DMA_STREAM_7
2787 * @retval State of bit (1 or 0).
2788 */
LL_DMA_IsEnabledIT_TE(DMA_TypeDef * DMAx,uint32_t Stream)2789 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
2790 {
2791 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE);
2792 }
2793
2794 /**
2795 * @brief Check if Transfer complete interrup is enabled.
2796 * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC
2797 * @param DMAx DMAx Instance
2798 * @param Stream This parameter can be one of the following values:
2799 * @arg @ref LL_DMA_STREAM_0
2800 * @arg @ref LL_DMA_STREAM_1
2801 * @arg @ref LL_DMA_STREAM_2
2802 * @arg @ref LL_DMA_STREAM_3
2803 * @arg @ref LL_DMA_STREAM_4
2804 * @arg @ref LL_DMA_STREAM_5
2805 * @arg @ref LL_DMA_STREAM_6
2806 * @arg @ref LL_DMA_STREAM_7
2807 * @retval State of bit (1 or 0).
2808 */
LL_DMA_IsEnabledIT_TC(DMA_TypeDef * DMAx,uint32_t Stream)2809 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
2810 {
2811 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE);
2812 }
2813
2814 /**
2815 * @brief Check if Direct mode error interrupt is enabled.
2816 * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME
2817 * @param DMAx DMAx Instance
2818 * @param Stream This parameter can be one of the following values:
2819 * @arg @ref LL_DMA_STREAM_0
2820 * @arg @ref LL_DMA_STREAM_1
2821 * @arg @ref LL_DMA_STREAM_2
2822 * @arg @ref LL_DMA_STREAM_3
2823 * @arg @ref LL_DMA_STREAM_4
2824 * @arg @ref LL_DMA_STREAM_5
2825 * @arg @ref LL_DMA_STREAM_6
2826 * @arg @ref LL_DMA_STREAM_7
2827 * @retval State of bit (1 or 0).
2828 */
LL_DMA_IsEnabledIT_DME(DMA_TypeDef * DMAx,uint32_t Stream)2829 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
2830 {
2831 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE);
2832 }
2833
2834 /**
2835 * @brief Check if FIFO error interrup is enabled.
2836 * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE
2837 * @param DMAx DMAx Instance
2838 * @param Stream This parameter can be one of the following values:
2839 * @arg @ref LL_DMA_STREAM_0
2840 * @arg @ref LL_DMA_STREAM_1
2841 * @arg @ref LL_DMA_STREAM_2
2842 * @arg @ref LL_DMA_STREAM_3
2843 * @arg @ref LL_DMA_STREAM_4
2844 * @arg @ref LL_DMA_STREAM_5
2845 * @arg @ref LL_DMA_STREAM_6
2846 * @arg @ref LL_DMA_STREAM_7
2847 * @retval State of bit (1 or 0).
2848 */
LL_DMA_IsEnabledIT_FE(DMA_TypeDef * DMAx,uint32_t Stream)2849 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
2850 {
2851 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE);
2852 }
2853
2854 /**
2855 * @}
2856 */
2857
2858 #if defined(USE_FULL_LL_DRIVER)
2859 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
2860 * @{
2861 */
2862
2863 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct);
2864 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);
2865 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
2866
2867 /**
2868 * @}
2869 */
2870 #endif /* USE_FULL_LL_DRIVER */
2871
2872 /**
2873 * @}
2874 */
2875
2876 /**
2877 * @}
2878 */
2879
2880 #endif /* DMA1 || DMA2 */
2881
2882 /**
2883 * @}
2884 */
2885
2886 #ifdef __cplusplus
2887 }
2888 #endif
2889
2890 #endif /* __STM32F7xx_LL_DMA_H */
2891
2892
