1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_dac.h
4 * @author MCD Application Team
5 * @brief Header file of DAC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32F7xx_LL_DAC_H
21 #define STM32F7xx_LL_DAC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f7xx.h"
29
30 /** @addtogroup STM32F7xx_LL_Driver
31 * @{
32 */
33
34 #if defined(DAC)
35
36 /** @defgroup DAC_LL DAC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
45 * @{
46 */
47
48 /* Internal masks for DAC channels definition */
49 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
50 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
51 /* - channel bits position into register SWTRIG */
52 /* - channel register offset of data holding register DHRx */
53 /* - channel register offset of data output register DORx */
54 #define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
55 CR, MCR, CCR, SHHR, SHRR of channel 1 */
56 #define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers
57 CR, MCR, CCR, SHHR, SHRR of channel 2 */
58 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
59
60 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
61 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
62 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
63
64 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
65 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
66 DHR12Rx channel 1 (shifted left of 20 bits) */
67 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
68 DHR12Rx channel 1 (shifted left of 24 bits) */
69
70 #define DAC_REG_DHR12R2_REGOFFSET 0x00030000UL /* Register offset of DHR12Rx channel 2 versus
71 DHR12Rx channel 1 (shifted left of 16 bits) */
72 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus
73 DHR12Rx channel 1 (shifted left of 20 bits) */
74 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus
75 DHR12Rx channel 1 (shifted left of 24 bits) */
76
77 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000UL
78 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
79 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
80 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
81 | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
82
83 #define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
84
85 #define DAC_REG_DOR2_REGOFFSET 0x10000000UL /* Register offset of DORx channel 1 versus
86 DORx channel 2 (shifted left of 28 bits) */
87 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
88
89
90
91 #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
92 DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
93 #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
94 to position 0 */
95 #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
96 to position 0 */
97
98 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16UL /* Position of bits register offset of DHR12Rx
99 channel 1 or 2 versus DHR12Rx channel 1
100 (shifted left of 16 bits) */
101 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
102 channel 1 or 2 versus DHR12Rx channel 1
103 (shifted left of 20 bits) */
104 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
105 channel 1 or 2 versus DHR12Rx channel 1
106 (shifted left of 24 bits) */
107 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DORx
108 channel 1 or 2 versus DORx channel 1
109 (shifted left of 28 bits) */
110
111 /* DAC registers bits positions */
112 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
113 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
114 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
115
116 /* Miscellaneous data */
117 #define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
118 bits (voltage range determined by analog voltage
119 references Vref+ and Vref-, refer to reference manual) */
120
121 /**
122 * @}
123 */
124
125
126 /* Private macros ------------------------------------------------------------*/
127 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
128 * @{
129 */
130
131 /**
132 * @brief Driver macro reserved for internal use: set a pointer to
133 * a register from a register basis from which an offset
134 * is applied.
135 * @param __REG__ Register basis from which the offset is applied.
136 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
137 * @retval Pointer to register address
138 */
139 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
140 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
141
142 /**
143 * @}
144 */
145
146
147 /* Exported types ------------------------------------------------------------*/
148 #if defined(USE_FULL_LL_DRIVER)
149 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
150 * @{
151 */
152
153 /**
154 * @brief Structure definition of some features of DAC instance.
155 */
156 typedef struct
157 {
158 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel:
159 internal (SW start) or from external peripheral
160 (timer event, external interrupt line).
161 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
162
163 This feature can be modified afterwards using unitary
164 function @ref LL_DAC_SetTriggerSource(). */
165
166 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
167 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
168
169 This feature can be modified afterwards using unitary
170 function @ref LL_DAC_SetWaveAutoGeneration(). */
171
172 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
173 If waveform automatic generation mode is set to noise, this parameter
174 can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
175 If waveform automatic generation mode is set to triangle,
176 this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
177 @note If waveform automatic generation mode is disabled,
178 this parameter is discarded.
179
180 This feature can be modified afterwards using unitary
181 function @ref LL_DAC_SetWaveNoiseLFSR(),
182 @ref LL_DAC_SetWaveTriangleAmplitude()
183 depending on the wave automatic generation selected. */
184
185 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
186 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
187
188 This feature can be modified afterwards using unitary
189 function @ref LL_DAC_SetOutputBuffer(). */
190 } LL_DAC_InitTypeDef;
191
192 /**
193 * @}
194 */
195 #endif /* USE_FULL_LL_DRIVER */
196
197 /* Exported constants --------------------------------------------------------*/
198 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
199 * @{
200 */
201
202 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
203 * @brief Flags defines which can be used with LL_DAC_ReadReg function
204 * @{
205 */
206 /* DAC channel 1 flags */
207 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
208
209 /* DAC channel 2 flags */
210 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
211
212 /**
213 * @}
214 */
215
216 /** @defgroup DAC_LL_EC_IT DAC interruptions
217 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
218 * @{
219 */
220 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
221
222 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
223
224 /**
225 * @}
226 */
227
228 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
229 * @{
230 */
231 #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
232
233 #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
234
235 /**
236 * @}
237 */
238
239 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
240 * @{
241 */
242 #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
243 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */
244 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */
245 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */
246 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000UL /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */
247 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */
248 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */
249 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
250 /**
251 * @}
252 */
253
254 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
255 * @{
256 */
257 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */
258 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
259 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
260 /**
261 * @}
262 */
263
264 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
265 * @{
266 */
267 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
268 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
269 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
270 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
271 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
272 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
273 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
274 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
275 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
276 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
277 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
278 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
279 /**
280 * @}
281 */
282
283 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
284 * @{
285 */
286 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
287 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
288 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
289 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
290 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
291 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
292 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
293 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
294 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
295 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
296 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
297 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
298 /**
299 * @}
300 */
301
302 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
303 * @{
304 */
305 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
306 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
307 /**
308 * @}
309 */
310
311 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
312 * @{
313 */
314 #define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */
315 #define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */
316 /**
317 * @}
318 */
319
320 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
321 * @{
322 */
323 /* List of DAC registers intended to be used (most commonly) with */
324 /* DMA transfer. */
325 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
326 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
327 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
328 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
329 /**
330 * @}
331 */
332
333 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
334 * @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
335 * not timeout values.
336 * For details on delays values, refer to descriptions in source code
337 * above each literal definition.
338 * @{
339 */
340
341 /* Delay for DAC channel voltage settling time from DAC channel startup */
342 /* (transition from disable to enable). */
343 /* Note: DAC channel startup time depends on board application environment: */
344 /* impedance connected to DAC channel output. */
345 /* The delay below is specified under conditions: */
346 /* - voltage maximum transition (lowest to highest value) */
347 /* - until voltage reaches final value +-1LSB */
348 /* - DAC channel output buffer enabled */
349 /* - load impedance of 5kOhm (min), 50pF (max) */
350 /* Literal set to maximum value (refer to device datasheet, */
351 /* parameter "tWAKEUP"). */
352 /* Unit: us */
353 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
354
355 /* Delay for DAC channel voltage settling time. */
356 /* Note: DAC channel startup time depends on board application environment: */
357 /* impedance connected to DAC channel output. */
358 /* The delay below is specified under conditions: */
359 /* - voltage maximum transition (lowest to highest value) */
360 /* - until voltage reaches final value +-1LSB */
361 /* - DAC channel output buffer enabled */
362 /* - load impedance of 5kOhm min, 50pF max */
363 /* Literal set to maximum value (refer to device datasheet, */
364 /* parameter "tSETTLING"). */
365 /* Unit: us */
366 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12UL /*!< Delay for DAC channel voltage settling time */
367
368 /**
369 * @}
370 */
371
372 /**
373 * @}
374 */
375
376 /* Exported macro ------------------------------------------------------------*/
377 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
378 * @{
379 */
380
381 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
382 * @{
383 */
384
385 /**
386 * @brief Write a value in DAC register
387 * @param __INSTANCE__ DAC Instance
388 * @param __REG__ Register to be written
389 * @param __VALUE__ Value to be written in the register
390 * @retval None
391 */
392 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
393
394 /**
395 * @brief Read a value in DAC register
396 * @param __INSTANCE__ DAC Instance
397 * @param __REG__ Register to be read
398 * @retval Register value
399 */
400 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
401
402 /**
403 * @}
404 */
405
406 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
407 * @{
408 */
409
410 /**
411 * @brief Helper macro to get DAC channel number in decimal format
412 * from literals LL_DAC_CHANNEL_x.
413 * Example:
414 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
415 * will return decimal number "1".
416 * @note The input can be a value from functions where a channel
417 * number is returned.
418 * @param __CHANNEL__ This parameter can be one of the following values:
419 * @arg @ref LL_DAC_CHANNEL_1
420 * @arg @ref LL_DAC_CHANNEL_2
421 * @retval 1...2
422 */
423 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
424 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
425
426 /**
427 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
428 * from number in decimal format.
429 * Example:
430 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
431 * will return a data equivalent to "LL_DAC_CHANNEL_1".
432 * @note If the input parameter does not correspond to a DAC channel,
433 * this macro returns value '0'.
434 * @param __DECIMAL_NB__ 1...2
435 * @retval Returned value can be one of the following values:
436 * @arg @ref LL_DAC_CHANNEL_1
437 * @arg @ref LL_DAC_CHANNEL_2
438 */
439 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\
440 (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))
441
442 /**
443 * @brief Helper macro to define the DAC conversion data full-scale digital
444 * value corresponding to the selected DAC resolution.
445 * @note DAC conversion data full-scale corresponds to voltage range
446 * determined by analog voltage references Vref+ and Vref-
447 * (refer to reference manual).
448 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
449 * @arg @ref LL_DAC_RESOLUTION_12B
450 * @arg @ref LL_DAC_RESOLUTION_8B
451 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
452 */
453 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
454 ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
455
456 /**
457 * @brief Helper macro to calculate the DAC conversion data (unit: digital
458 * value) corresponding to a voltage (unit: mVolt).
459 * @note This helper macro is intended to provide input data in voltage
460 * rather than digital value,
461 * to be used with LL DAC functions such as
462 * @ref LL_DAC_ConvertData12RightAligned().
463 * @note Analog reference voltage (Vref+) must be either known from
464 * user board environment or can be calculated using ADC measurement
465 * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
466 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
467 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
468 * (unit: mVolt).
469 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
470 * @arg @ref LL_DAC_RESOLUTION_12B
471 * @arg @ref LL_DAC_RESOLUTION_8B
472 * @retval DAC conversion data (unit: digital value)
473 */
474 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
475 __DAC_VOLTAGE__,\
476 __DAC_RESOLUTION__) \
477 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
478 / (__VREFANALOG_VOLTAGE__) \
479 )
480
481 /**
482 * @}
483 */
484
485 /**
486 * @}
487 */
488
489
490 /* Exported functions --------------------------------------------------------*/
491 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
492 * @{
493 */
494 /**
495 * @brief Set the conversion trigger source for the selected DAC channel.
496 * @note For conversion trigger source to be effective, DAC trigger
497 * must be enabled using function @ref LL_DAC_EnableTrigger().
498 * @note To set conversion trigger source, DAC channel must be disabled.
499 * Otherwise, the setting is discarded.
500 * @note Availability of parameters of trigger sources from timer
501 * depends on timers availability on the selected device.
502 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
503 * CR TSEL2 LL_DAC_SetTriggerSource
504 * @param DACx DAC instance
505 * @param DAC_Channel This parameter can be one of the following values:
506 * @arg @ref LL_DAC_CHANNEL_1
507 * @arg @ref LL_DAC_CHANNEL_2
508 * @param TriggerSource This parameter can be one of the following values:
509 * @arg @ref LL_DAC_TRIG_SOFTWARE
510 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
511 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
512 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
513 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
514 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
515 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
516 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
517 * @retval None
518 */
LL_DAC_SetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriggerSource)519 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
520 {
521 MODIFY_REG(DACx->CR,
522 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
523 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
524 }
525
526 /**
527 * @brief Get the conversion trigger source for the selected DAC channel.
528 * @note For conversion trigger source to be effective, DAC trigger
529 * must be enabled using function @ref LL_DAC_EnableTrigger().
530 * @note Availability of parameters of trigger sources from timer
531 * depends on timers availability on the selected device.
532 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
533 * CR TSEL2 LL_DAC_GetTriggerSource
534 * @param DACx DAC instance
535 * @param DAC_Channel This parameter can be one of the following values:
536 * @arg @ref LL_DAC_CHANNEL_1
537 * @arg @ref LL_DAC_CHANNEL_2
538 * @retval Returned value can be one of the following values:
539 * @arg @ref LL_DAC_TRIG_SOFTWARE
540 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
541 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
542 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
543 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
544 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
545 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
546 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
547 */
LL_DAC_GetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel)548 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
549 {
550 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
551 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
552 );
553 }
554
555 /**
556 * @brief Set the waveform automatic generation mode
557 * for the selected DAC channel.
558 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
559 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
560 * @param DACx DAC instance
561 * @param DAC_Channel This parameter can be one of the following values:
562 * @arg @ref LL_DAC_CHANNEL_1
563 * @arg @ref LL_DAC_CHANNEL_2
564 * @param WaveAutoGeneration This parameter can be one of the following values:
565 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
566 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
567 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
568 * @retval None
569 */
LL_DAC_SetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t WaveAutoGeneration)570 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
571 {
572 MODIFY_REG(DACx->CR,
573 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
574 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
575 }
576
577 /**
578 * @brief Get the waveform automatic generation mode
579 * for the selected DAC channel.
580 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
581 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
582 * @param DACx DAC instance
583 * @param DAC_Channel This parameter can be one of the following values:
584 * @arg @ref LL_DAC_CHANNEL_1
585 * @arg @ref LL_DAC_CHANNEL_2
586 * @retval Returned value can be one of the following values:
587 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
588 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
589 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
590 */
LL_DAC_GetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel)591 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
592 {
593 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
594 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
595 );
596 }
597
598 /**
599 * @brief Set the noise waveform generation for the selected DAC channel:
600 * Noise mode and parameters LFSR (linear feedback shift register).
601 * @note For wave generation to be effective, DAC channel
602 * wave generation mode must be enabled using
603 * function @ref LL_DAC_SetWaveAutoGeneration().
604 * @note This setting can be set when the selected DAC channel is disabled
605 * (otherwise, the setting operation is ignored).
606 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
607 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
608 * @param DACx DAC instance
609 * @param DAC_Channel This parameter can be one of the following values:
610 * @arg @ref LL_DAC_CHANNEL_1
611 * @arg @ref LL_DAC_CHANNEL_2
612 * @param NoiseLFSRMask This parameter can be one of the following values:
613 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
614 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
615 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
616 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
617 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
618 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
619 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
620 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
621 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
622 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
623 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
624 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
625 * @retval None
626 */
LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t NoiseLFSRMask)627 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
628 {
629 MODIFY_REG(DACx->CR,
630 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
631 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
632 }
633
634 /**
635 * @brief Get the noise waveform generation for the selected DAC channel:
636 * Noise mode and parameters LFSR (linear feedback shift register).
637 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
638 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
639 * @param DACx DAC instance
640 * @param DAC_Channel This parameter can be one of the following values:
641 * @arg @ref LL_DAC_CHANNEL_1
642 * @arg @ref LL_DAC_CHANNEL_2
643 * @retval Returned value can be one of the following values:
644 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
645 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
646 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
647 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
648 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
649 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
650 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
651 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
652 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
653 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
654 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
655 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
656 */
LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel)657 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
658 {
659 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
660 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
661 );
662 }
663
664 /**
665 * @brief Set the triangle waveform generation for the selected DAC channel:
666 * triangle mode and amplitude.
667 * @note For wave generation to be effective, DAC channel
668 * wave generation mode must be enabled using
669 * function @ref LL_DAC_SetWaveAutoGeneration().
670 * @note This setting can be set when the selected DAC channel is disabled
671 * (otherwise, the setting operation is ignored).
672 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
673 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
674 * @param DACx DAC instance
675 * @param DAC_Channel This parameter can be one of the following values:
676 * @arg @ref LL_DAC_CHANNEL_1
677 * @arg @ref LL_DAC_CHANNEL_2
678 * @param TriangleAmplitude This parameter can be one of the following values:
679 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
680 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
681 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
682 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
683 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
684 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
685 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
686 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
687 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
688 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
689 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
690 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
691 * @retval None
692 */
LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriangleAmplitude)693 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
694 uint32_t TriangleAmplitude)
695 {
696 MODIFY_REG(DACx->CR,
697 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
698 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
699 }
700
701 /**
702 * @brief Get the triangle waveform generation for the selected DAC channel:
703 * triangle mode and amplitude.
704 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
705 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
706 * @param DACx DAC instance
707 * @param DAC_Channel This parameter can be one of the following values:
708 * @arg @ref LL_DAC_CHANNEL_1
709 * @arg @ref LL_DAC_CHANNEL_2
710 * @retval Returned value can be one of the following values:
711 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
712 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
713 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
714 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
715 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
716 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
717 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
718 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
719 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
720 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
721 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
722 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
723 */
LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel)724 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
725 {
726 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
727 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
728 );
729 }
730
731 /**
732 * @brief Set the output buffer for the selected DAC channel.
733 * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
734 * CR BOFF2 LL_DAC_SetOutputBuffer
735 * @param DACx DAC instance
736 * @param DAC_Channel This parameter can be one of the following values:
737 * @arg @ref LL_DAC_CHANNEL_1
738 * @arg @ref LL_DAC_CHANNEL_2
739 * @param OutputBuffer This parameter can be one of the following values:
740 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
741 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
742 * @retval None
743 */
LL_DAC_SetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputBuffer)744 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
745 {
746 MODIFY_REG(DACx->CR,
747 DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
748 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
749 }
750
751 /**
752 * @brief Get the output buffer state for the selected DAC channel.
753 * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
754 * CR BOFF2 LL_DAC_GetOutputBuffer
755 * @param DACx DAC instance
756 * @param DAC_Channel This parameter can be one of the following values:
757 * @arg @ref LL_DAC_CHANNEL_1
758 * @arg @ref LL_DAC_CHANNEL_2
759 * @retval Returned value can be one of the following values:
760 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
761 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
762 */
LL_DAC_GetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel)763 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
764 {
765 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
766 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
767 );
768 }
769
770 /**
771 * @}
772 */
773
774 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
775 * @{
776 */
777
778 /**
779 * @brief Enable DAC DMA transfer request of the selected channel.
780 * @note To configure DMA source address (peripheral address),
781 * use function @ref LL_DAC_DMA_GetRegAddr().
782 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
783 * CR DMAEN2 LL_DAC_EnableDMAReq
784 * @param DACx DAC instance
785 * @param DAC_Channel This parameter can be one of the following values:
786 * @arg @ref LL_DAC_CHANNEL_1
787 * @arg @ref LL_DAC_CHANNEL_2
788 * @retval None
789 */
LL_DAC_EnableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)790 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
791 {
792 SET_BIT(DACx->CR,
793 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
794 }
795
796 /**
797 * @brief Disable DAC DMA transfer request of the selected channel.
798 * @note To configure DMA source address (peripheral address),
799 * use function @ref LL_DAC_DMA_GetRegAddr().
800 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
801 * CR DMAEN2 LL_DAC_DisableDMAReq
802 * @param DACx DAC instance
803 * @param DAC_Channel This parameter can be one of the following values:
804 * @arg @ref LL_DAC_CHANNEL_1
805 * @arg @ref LL_DAC_CHANNEL_2
806 * @retval None
807 */
LL_DAC_DisableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)808 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
809 {
810 CLEAR_BIT(DACx->CR,
811 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
812 }
813
814 /**
815 * @brief Get DAC DMA transfer request state of the selected channel.
816 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
817 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
818 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
819 * @param DACx DAC instance
820 * @param DAC_Channel This parameter can be one of the following values:
821 * @arg @ref LL_DAC_CHANNEL_1
822 * @arg @ref LL_DAC_CHANNEL_2
823 * @retval State of bit (1 or 0).
824 */
LL_DAC_IsDMAReqEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)825 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
826 {
827 return ((READ_BIT(DACx->CR,
828 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
829 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
830 }
831
832 /**
833 * @brief Function to help to configure DMA transfer to DAC: retrieve the
834 * DAC register address from DAC instance and a list of DAC registers
835 * intended to be used (most commonly) with DMA transfer.
836 * @note These DAC registers are data holding registers:
837 * when DAC conversion is requested, DAC generates a DMA transfer
838 * request to have data available in DAC data holding registers.
839 * @note This macro is intended to be used with LL DMA driver, refer to
840 * function "LL_DMA_ConfigAddresses()".
841 * Example:
842 * LL_DMA_ConfigAddresses(DMA1,
843 * LL_DMA_CHANNEL_1,
844 * (uint32_t)&< array or variable >,
845 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
846 * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
847 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
848 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
849 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
850 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
851 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
852 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
853 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
854 * @param DACx DAC instance
855 * @param DAC_Channel This parameter can be one of the following values:
856 * @arg @ref LL_DAC_CHANNEL_1
857 * @arg @ref LL_DAC_CHANNEL_2
858 * @param Register This parameter can be one of the following values:
859 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
860 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
861 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
862 * @retval DAC register address
863 */
LL_DAC_DMA_GetRegAddr(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Register)864 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
865 {
866 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
867 /* DAC channel selected. */
868 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
869 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
870 }
871 /**
872 * @}
873 */
874
875 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
876 * @{
877 */
878
879 /**
880 * @brief Enable DAC selected channel.
881 * @rmtoll CR EN1 LL_DAC_Enable\n
882 * CR EN2 LL_DAC_Enable
883 * @note After enable from off state, DAC channel requires a delay
884 * for output voltage to reach accuracy +/- 1 LSB.
885 * Refer to device datasheet, parameter "tWAKEUP".
886 * @param DACx DAC instance
887 * @param DAC_Channel This parameter can be one of the following values:
888 * @arg @ref LL_DAC_CHANNEL_1
889 * @arg @ref LL_DAC_CHANNEL_2
890 * @retval None
891 */
LL_DAC_Enable(DAC_TypeDef * DACx,uint32_t DAC_Channel)892 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
893 {
894 SET_BIT(DACx->CR,
895 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
896 }
897
898 /**
899 * @brief Disable DAC selected channel.
900 * @rmtoll CR EN1 LL_DAC_Disable\n
901 * CR EN2 LL_DAC_Disable
902 * @param DACx DAC instance
903 * @param DAC_Channel This parameter can be one of the following values:
904 * @arg @ref LL_DAC_CHANNEL_1
905 * @arg @ref LL_DAC_CHANNEL_2
906 * @retval None
907 */
LL_DAC_Disable(DAC_TypeDef * DACx,uint32_t DAC_Channel)908 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
909 {
910 CLEAR_BIT(DACx->CR,
911 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
912 }
913
914 /**
915 * @brief Get DAC enable state of the selected channel.
916 * (0: DAC channel is disabled, 1: DAC channel is enabled)
917 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
918 * CR EN2 LL_DAC_IsEnabled
919 * @param DACx DAC instance
920 * @param DAC_Channel This parameter can be one of the following values:
921 * @arg @ref LL_DAC_CHANNEL_1
922 * @arg @ref LL_DAC_CHANNEL_2
923 * @retval State of bit (1 or 0).
924 */
LL_DAC_IsEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)925 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
926 {
927 return ((READ_BIT(DACx->CR,
928 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
929 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
930 }
931
932 /**
933 * @brief Enable DAC trigger of the selected channel.
934 * @note - If DAC trigger is disabled, DAC conversion is performed
935 * automatically once the data holding register is updated,
936 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
937 * @ref LL_DAC_ConvertData12RightAligned(), ...
938 * - If DAC trigger is enabled, DAC conversion is performed
939 * only when a hardware of software trigger event is occurring.
940 * Select trigger source using
941 * function @ref LL_DAC_SetTriggerSource().
942 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
943 * CR TEN2 LL_DAC_EnableTrigger
944 * @param DACx DAC instance
945 * @param DAC_Channel This parameter can be one of the following values:
946 * @arg @ref LL_DAC_CHANNEL_1
947 * @arg @ref LL_DAC_CHANNEL_2
948 * @retval None
949 */
LL_DAC_EnableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)950 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
951 {
952 SET_BIT(DACx->CR,
953 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
954 }
955
956 /**
957 * @brief Disable DAC trigger of the selected channel.
958 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
959 * CR TEN2 LL_DAC_DisableTrigger
960 * @param DACx DAC instance
961 * @param DAC_Channel This parameter can be one of the following values:
962 * @arg @ref LL_DAC_CHANNEL_1
963 * @arg @ref LL_DAC_CHANNEL_2
964 * @retval None
965 */
LL_DAC_DisableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)966 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
967 {
968 CLEAR_BIT(DACx->CR,
969 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
970 }
971
972 /**
973 * @brief Get DAC trigger state of the selected channel.
974 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
975 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
976 * CR TEN2 LL_DAC_IsTriggerEnabled
977 * @param DACx DAC instance
978 * @param DAC_Channel This parameter can be one of the following values:
979 * @arg @ref LL_DAC_CHANNEL_1
980 * @arg @ref LL_DAC_CHANNEL_2
981 * @retval State of bit (1 or 0).
982 */
LL_DAC_IsTriggerEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)983 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
984 {
985 return ((READ_BIT(DACx->CR,
986 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
987 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
988 }
989
990 /**
991 * @brief Trig DAC conversion by software for the selected DAC channel.
992 * @note Preliminarily, DAC trigger must be set to software trigger
993 * using function
994 * @ref LL_DAC_Init()
995 * @ref LL_DAC_SetTriggerSource()
996 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
997 * and DAC trigger must be enabled using
998 * function @ref LL_DAC_EnableTrigger().
999 * @note For devices featuring DAC with 2 channels: this function
1000 * can perform a SW start of both DAC channels simultaneously.
1001 * Two channels can be selected as parameter.
1002 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
1003 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
1004 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
1005 * @param DACx DAC instance
1006 * @param DAC_Channel This parameter can a combination of the following values:
1007 * @arg @ref LL_DAC_CHANNEL_1
1008 * @arg @ref LL_DAC_CHANNEL_2
1009 * @retval None
1010 */
LL_DAC_TrigSWConversion(DAC_TypeDef * DACx,uint32_t DAC_Channel)1011 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1012 {
1013 SET_BIT(DACx->SWTRIGR,
1014 (DAC_Channel & DAC_SWTR_CHX_MASK));
1015 }
1016
1017 /**
1018 * @brief Set the data to be loaded in the data holding register
1019 * in format 12 bits left alignment (LSB aligned on bit 0),
1020 * for the selected DAC channel.
1021 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
1022 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
1023 * @param DACx DAC instance
1024 * @param DAC_Channel This parameter can be one of the following values:
1025 * @arg @ref LL_DAC_CHANNEL_1
1026 * @arg @ref LL_DAC_CHANNEL_2
1027 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1028 * @retval None
1029 */
LL_DAC_ConvertData12RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1030 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1031 {
1032 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
1033 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1034
1035 MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
1036 }
1037
1038 /**
1039 * @brief Set the data to be loaded in the data holding register
1040 * in format 12 bits left alignment (MSB aligned on bit 15),
1041 * for the selected DAC channel.
1042 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
1043 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
1044 * @param DACx DAC instance
1045 * @param DAC_Channel This parameter can be one of the following values:
1046 * @arg @ref LL_DAC_CHANNEL_1
1047 * @arg @ref LL_DAC_CHANNEL_2
1048 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1049 * @retval None
1050 */
LL_DAC_ConvertData12LeftAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1051 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1052 {
1053 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
1054 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1055
1056 MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
1057 }
1058
1059 /**
1060 * @brief Set the data to be loaded in the data holding register
1061 * in format 8 bits left alignment (LSB aligned on bit 0),
1062 * for the selected DAC channel.
1063 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
1064 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
1065 * @param DACx DAC instance
1066 * @param DAC_Channel This parameter can be one of the following values:
1067 * @arg @ref LL_DAC_CHANNEL_1
1068 * @arg @ref LL_DAC_CHANNEL_2
1069 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1070 * @retval None
1071 */
LL_DAC_ConvertData8RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1072 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1073 {
1074 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
1075 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1076
1077 MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
1078 }
1079
1080
1081 /**
1082 * @brief Set the data to be loaded in the data holding register
1083 * in format 12 bits left alignment (LSB aligned on bit 0),
1084 * for both DAC channels.
1085 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
1086 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
1087 * @param DACx DAC instance
1088 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1089 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1090 * @retval None
1091 */
LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1092 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1093 uint32_t DataChannel2)
1094 {
1095 MODIFY_REG(DACx->DHR12RD,
1096 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
1097 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1098 }
1099
1100 /**
1101 * @brief Set the data to be loaded in the data holding register
1102 * in format 12 bits left alignment (MSB aligned on bit 15),
1103 * for both DAC channels.
1104 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
1105 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
1106 * @param DACx DAC instance
1107 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1108 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1109 * @retval None
1110 */
LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1111 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1112 uint32_t DataChannel2)
1113 {
1114 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
1115 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
1116 /* the 4 LSB must be taken into account for the shift value. */
1117 MODIFY_REG(DACx->DHR12LD,
1118 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
1119 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
1120 }
1121
1122 /**
1123 * @brief Set the data to be loaded in the data holding register
1124 * in format 8 bits left alignment (LSB aligned on bit 0),
1125 * for both DAC channels.
1126 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
1127 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
1128 * @param DACx DAC instance
1129 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
1130 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
1131 * @retval None
1132 */
LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1133 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1134 uint32_t DataChannel2)
1135 {
1136 MODIFY_REG(DACx->DHR8RD,
1137 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
1138 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1139 }
1140
1141
1142 /**
1143 * @brief Retrieve output data currently generated for the selected DAC channel.
1144 * @note Whatever alignment and resolution settings
1145 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1146 * @ref LL_DAC_ConvertData12RightAligned(), ...),
1147 * output data format is 12 bits right aligned (LSB aligned on bit 0).
1148 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
1149 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
1150 * @param DACx DAC instance
1151 * @param DAC_Channel This parameter can be one of the following values:
1152 * @arg @ref LL_DAC_CHANNEL_1
1153 * @arg @ref LL_DAC_CHANNEL_2
1154 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1155 */
LL_DAC_RetrieveOutputData(DAC_TypeDef * DACx,uint32_t DAC_Channel)1156 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1157 {
1158 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
1159 & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
1160
1161 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1162 }
1163
1164 /**
1165 * @}
1166 */
1167
1168 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
1169 * @{
1170 */
1171
1172 /**
1173 * @brief Get DAC underrun flag for DAC channel 1
1174 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
1175 * @param DACx DAC instance
1176 * @retval State of bit (1 or 0).
1177 */
LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef * DACx)1178 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
1179 {
1180 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
1181 }
1182
1183
1184 /**
1185 * @brief Get DAC underrun flag for DAC channel 2
1186 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
1187 * @param DACx DAC instance
1188 * @retval State of bit (1 or 0).
1189 */
LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef * DACx)1190 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
1191 {
1192 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
1193 }
1194
1195
1196 /**
1197 * @brief Clear DAC underrun flag for DAC channel 1
1198 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
1199 * @param DACx DAC instance
1200 * @retval None
1201 */
LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef * DACx)1202 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1203 {
1204 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1205 }
1206
1207
1208 /**
1209 * @brief Clear DAC underrun flag for DAC channel 2
1210 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
1211 * @param DACx DAC instance
1212 * @retval None
1213 */
LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef * DACx)1214 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1215 {
1216 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1217 }
1218
1219
1220 /**
1221 * @}
1222 */
1223
1224 /** @defgroup DAC_LL_EF_IT_Management IT management
1225 * @{
1226 */
1227
1228 /**
1229 * @brief Enable DMA underrun interrupt for DAC channel 1
1230 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
1231 * @param DACx DAC instance
1232 * @retval None
1233 */
LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef * DACx)1234 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1235 {
1236 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1237 }
1238
1239
1240 /**
1241 * @brief Enable DMA underrun interrupt for DAC channel 2
1242 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
1243 * @param DACx DAC instance
1244 * @retval None
1245 */
LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef * DACx)1246 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1247 {
1248 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1249 }
1250
1251
1252 /**
1253 * @brief Disable DMA underrun interrupt for DAC channel 1
1254 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
1255 * @param DACx DAC instance
1256 * @retval None
1257 */
LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef * DACx)1258 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1259 {
1260 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1261 }
1262
1263
1264 /**
1265 * @brief Disable DMA underrun interrupt for DAC channel 2
1266 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
1267 * @param DACx DAC instance
1268 * @retval None
1269 */
LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef * DACx)1270 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1271 {
1272 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1273 }
1274
1275
1276 /**
1277 * @brief Get DMA underrun interrupt for DAC channel 1
1278 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
1279 * @param DACx DAC instance
1280 * @retval State of bit (1 or 0).
1281 */
LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef * DACx)1282 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
1283 {
1284 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
1285 }
1286
1287
1288 /**
1289 * @brief Get DMA underrun interrupt for DAC channel 2
1290 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
1291 * @param DACx DAC instance
1292 * @retval State of bit (1 or 0).
1293 */
LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef * DACx)1294 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
1295 {
1296 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
1297 }
1298
1299
1300 /**
1301 * @}
1302 */
1303
1304 #if defined(USE_FULL_LL_DRIVER)
1305 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
1306 * @{
1307 */
1308
1309 ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
1310 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);
1311 void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
1312
1313 /**
1314 * @}
1315 */
1316 #endif /* USE_FULL_LL_DRIVER */
1317
1318 /**
1319 * @}
1320 */
1321
1322 /**
1323 * @}
1324 */
1325
1326 #endif /* DAC */
1327
1328 /**
1329 * @}
1330 */
1331
1332 #ifdef __cplusplus
1333 }
1334 #endif
1335
1336 #endif /* STM32F7xx_LL_DAC_H */
1337
1338
