1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32F7xx_LL_ADC_H
21 #define __STM32F7xx_LL_ADC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f7xx.h"
29
30 /** @addtogroup STM32F7xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
35
36 /** @defgroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
45 * @{
46 */
47
48 /* Internal mask for ADC group regular sequencer: */
49 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
50 /* - sequencer register offset */
51 /* - sequencer rank bits position into the selected register */
52
53 /* Internal register offset for ADC group regular sequencer configuration */
54 /* (offset placed into a spare area of literal definition) */
55 #define ADC_SQR1_REGOFFSET 0x00000000U
56 #define ADC_SQR2_REGOFFSET 0x00000100U
57 #define ADC_SQR3_REGOFFSET 0x00000200U
58 #define ADC_SQR4_REGOFFSET 0x00000300U
59
60 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
61 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
62
63 /* Definition of ADC group regular sequencer bits information to be inserted */
64 /* into ADC group regular sequencer ranks literals definition. */
65 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
66 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
67 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
68 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
69 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
70 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
71 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
72 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
73 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
74 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
75 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
76 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
77 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
78 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
79 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
80 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
81
82 /* Internal mask for ADC group injected sequencer: */
83 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
84 /* - data register offset */
85 /* - offset register offset */
86 /* - sequencer rank bits position into the selected register */
87
88 /* Internal register offset for ADC group injected data register */
89 /* (offset placed into a spare area of literal definition) */
90 #define ADC_JDR1_REGOFFSET 0x00000000U
91 #define ADC_JDR2_REGOFFSET 0x00000100U
92 #define ADC_JDR3_REGOFFSET 0x00000200U
93 #define ADC_JDR4_REGOFFSET 0x00000300U
94
95 /* Internal register offset for ADC group injected offset configuration */
96 /* (offset placed into a spare area of literal definition) */
97 #define ADC_JOFR1_REGOFFSET 0x00000000U
98 #define ADC_JOFR2_REGOFFSET 0x00001000U
99 #define ADC_JOFR3_REGOFFSET 0x00002000U
100 #define ADC_JOFR4_REGOFFSET 0x00003000U
101
102 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
103 #define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
104 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
105
106 /* Internal mask for ADC group regular trigger: */
107 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
108 /* - regular trigger source */
109 /* - regular trigger edge */
110 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
111
112 /* Mask containing trigger source masks for each of possible */
113 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
114 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
115 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4U * 0U)) | \
116 ((ADC_CR2_EXTSEL) >> (4U * 1U)) | \
117 ((ADC_CR2_EXTSEL) >> (4U * 2U)) | \
118 ((ADC_CR2_EXTSEL) >> (4U * 3U)))
119
120 /* Mask containing trigger edge masks for each of possible */
121 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
122 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
123 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4U * 0U)) | \
124 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \
125 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \
126 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U)))
127
128 /* Definition of ADC group regular trigger bits information. */
129 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */
130 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (28U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */
131
132
133
134 /* Internal mask for ADC group injected trigger: */
135 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
136 /* - injected trigger source */
137 /* - injected trigger edge */
138 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
139
140 /* Mask containing trigger source masks for each of possible */
141 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
142 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
143 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4U * 0U)) | \
144 ((ADC_CR2_JEXTSEL) >> (4U * 1U)) | \
145 ((ADC_CR2_JEXTSEL) >> (4U * 2U)) | \
146 ((ADC_CR2_JEXTSEL) >> (4U * 3U)))
147
148 /* Mask containing trigger edge masks for each of possible */
149 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
150 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
151 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4U * 0U)) | \
152 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \
153 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \
154 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U)))
155
156 /* Definition of ADC group injected trigger bits information. */
157 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */
158 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */
159
160 /* Internal mask for ADC channel: */
161 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
162 /* - channel identifier defined by number */
163 /* - channel differentiation between external channels (connected to */
164 /* GPIO pins) and internal channels (connected to internal paths) */
165 /* - channel sampling time defined by SMPRx register offset */
166 /* and SMPx bits positions into SMPRx register */
167 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
168 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
169 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
170 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
171 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
172
173 /* Channel differentiation between external and internal channels */
174 #define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000U /* Marker of internal channel */
175 #define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000U /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
176 #define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */
177 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)
178
179 /* Internal register offset for ADC channel sampling time configuration */
180 /* (offset placed into a spare area of literal definition) */
181 #define ADC_SMPR1_REGOFFSET 0x00000000U
182 #define ADC_SMPR2_REGOFFSET 0x02000000U
183 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
184
185 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000U
186 #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
187
188 /* Definition of channels ID number information to be inserted into */
189 /* channels literals definition. */
190 #define ADC_CHANNEL_0_NUMBER 0x00000000U
191 #define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)
192 #define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )
193 #define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
194 #define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )
195 #define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
196 #define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
197 #define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
198 #define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )
199 #define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)
200 #define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 )
201 #define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
202 #define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 )
203 #define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
204 #define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
205 #define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
206 #define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )
207 #define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)
208 #define ADC_CHANNEL_18_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1 )
209
210 /* Definition of channels sampling time information to be inserted into */
211 /* channels literals definition. */
212 #define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
213 #define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
214 #define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
215 #define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
216 #define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
217 #define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
218 #define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
219 #define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
220 #define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
221 #define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
222 #define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
223 #define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
224 #define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
225 #define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
226 #define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
227 #define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
228 #define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
229 #define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
230 #define ADC_CHANNEL_18_SMP (ADC_SMPR1_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP18) */
231
232 /* Internal mask for ADC analog watchdog: */
233 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
234 /* (concatenation of multiple bits used in different analog watchdogs, */
235 /* (feature of several watchdogs not available on all STM32 families)). */
236 /* - analog watchdog 1: monitored channel defined by number, */
237 /* selection of ADC group (ADC groups regular and-or injected). */
238
239 /* Internal register offset for ADC analog watchdog channel configuration */
240 #define ADC_AWD_CR1_REGOFFSET 0x00000000U
241
242 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
243
244 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
245 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
246
247 /* Internal register offset for ADC analog watchdog threshold configuration */
248 #define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000U
249 #define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001U
250 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
251
252 /* ADC registers bits positions */
253 #define ADC_CR1_RES_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */
254 #define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
255 /* ADC internal channels related definitions */
256 /* Internal voltage reference VrefInt */
257 #define VREFINT_CAL_ADDR VREFINT_CAL_ADDR_CMSIS /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
258 #define VREFINT_CAL_VREF ( 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
259 /* Temperature sensor */
260 #define TEMPSENSOR_CAL1_ADDR TEMPSENSOR_CAL1_ADDR_CMSIS /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
261 #define TEMPSENSOR_CAL2_ADDR TEMPSENSOR_CAL2_ADDR_CMSIS /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
262 #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
263 #define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
264 #define TEMPSENSOR_CAL_VREFANALOG ( 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
265 /**
266 * @}
267 */
268
269
270 /* Private macros ------------------------------------------------------------*/
271 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
272 * @{
273 */
274
275 /**
276 * @brief Driver macro reserved for internal use: isolate bits with the
277 * selected mask and shift them to the register LSB
278 * (shift mask on register position bit 0).
279 * @param __BITS__ Bits in register 32 bits
280 * @param __MASK__ Mask in register 32 bits
281 * @retval Bits in register 32 bits
282 */
283 #define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
284 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
285
286 /**
287 * @brief Driver macro reserved for internal use: set a pointer to
288 * a register from a register basis from which an offset
289 * is applied.
290 * @param __REG__ Register basis from which the offset is applied.
291 * @param __REG_OFFFSET__ Offset to be applied (unit number of registers).
292 * @retval Pointer to register address
293 */
294 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
295 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
296
297 /**
298 * @}
299 */
300
301
302 /* Exported types ------------------------------------------------------------*/
303 #if defined(USE_FULL_LL_DRIVER)
304 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
305 * @{
306 */
307
308 /**
309 * @brief Structure definition of some features of ADC common parameters
310 * and multimode
311 * (all ADC instances belonging to the same ADC common instance).
312 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
313 * is conditioned to ADC instances state (all ADC instances
314 * sharing the same ADC common instance):
315 * All ADC instances sharing the same ADC common instance must be
316 * disabled.
317 */
318 typedef struct
319 {
320 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
321 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
322
323 This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
324
325 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
326 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
327
328 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
329
330 uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
331 This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
332
333 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
334
335 uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
336 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
337
338 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
339
340 } LL_ADC_CommonInitTypeDef;
341
342 /**
343 * @brief Structure definition of some features of ADC instance.
344 * @note These parameters have an impact on ADC scope: ADC instance.
345 * Affects both group regular and group injected (availability
346 * of ADC group injected depends on STM32 families).
347 * Refer to corresponding unitary functions into
348 * @ref ADC_LL_EF_Configuration_ADC_Instance .
349 * @note The setting of these parameters by function @ref LL_ADC_Init()
350 * is conditioned to ADC state:
351 * ADC instance must be disabled.
352 * This condition is applied to all ADC features, for efficiency
353 * and compatibility over all STM32 families. However, the different
354 * features can be set under different ADC state conditions
355 * (setting possible with ADC enabled without conversion on going,
356 * ADC enabled with conversion on going, ...)
357 * Each feature can be updated afterwards with a unitary function
358 * and potentially with ADC in a different state than disabled,
359 * refer to description of each function for setting
360 * conditioned to ADC state.
361 */
362 typedef struct
363 {
364 uint32_t Resolution; /*!< Set ADC resolution.
365 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
366
367 This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
368
369 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
370 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
371
372 This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
373
374 uint32_t SequencersScanMode; /*!< Set ADC scan selection.
375 This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION
376
377 This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */
378
379 } LL_ADC_InitTypeDef;
380
381 /**
382 * @brief Structure definition of some features of ADC group regular.
383 * @note These parameters have an impact on ADC scope: ADC group regular.
384 * Refer to corresponding unitary functions into
385 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
386 * (functions with prefix "REG").
387 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
388 * is conditioned to ADC state:
389 * ADC instance must be disabled.
390 * This condition is applied to all ADC features, for efficiency
391 * and compatibility over all STM32 families. However, the different
392 * features can be set under different ADC state conditions
393 * (setting possible with ADC enabled without conversion on going,
394 * ADC enabled with conversion on going, ...)
395 * Each feature can be updated afterwards with a unitary function
396 * and potentially with ADC in a different state than disabled,
397 * refer to description of each function for setting
398 * conditioned to ADC state.
399 */
400 typedef struct
401 {
402 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
403 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
404 @note On this STM32 series, setting of external trigger edge is performed
405 using function @ref LL_ADC_REG_StartConversionExtTrig().
406
407 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
408
409 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
410 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
411 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
412
413 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
414
415 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
416 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
417 @note This parameter has an effect only if group regular sequencer is enabled
418 (scan length of 2 ranks or more).
419
420 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
421
422 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
423 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
424 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
425
426 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
427
428 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
429 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
430
431 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
432
433 } LL_ADC_REG_InitTypeDef;
434
435 /**
436 * @brief Structure definition of some features of ADC group injected.
437 * @note These parameters have an impact on ADC scope: ADC group injected.
438 * Refer to corresponding unitary functions into
439 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
440 * (functions with prefix "INJ").
441 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
442 * is conditioned to ADC state:
443 * ADC instance must be disabled.
444 * This condition is applied to all ADC features, for efficiency
445 * and compatibility over all STM32 families. However, the different
446 * features can be set under different ADC state conditions
447 * (setting possible with ADC enabled without conversion on going,
448 * ADC enabled with conversion on going, ...)
449 * Each feature can be updated afterwards with a unitary function
450 * and potentially with ADC in a different state than disabled,
451 * refer to description of each function for setting
452 * conditioned to ADC state.
453 */
454 typedef struct
455 {
456 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
457 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
458 @note On this STM32 series, setting of external trigger edge is performed
459 using function @ref LL_ADC_INJ_StartConversionExtTrig().
460
461 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
462
463 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
464 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
465 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
466
467 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
468
469 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
470 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
471 @note This parameter has an effect only if group injected sequencer is enabled
472 (scan length of 2 ranks or more).
473
474 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
475
476 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
477 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
478 Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
479
480 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
481
482 } LL_ADC_INJ_InitTypeDef;
483
484 /**
485 * @}
486 */
487 #endif /* USE_FULL_LL_DRIVER */
488
489 /* Exported constants --------------------------------------------------------*/
490 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
491 * @{
492 */
493
494 /** @defgroup ADC_LL_EC_FLAG ADC flags
495 * @brief Flags defines which can be used with LL_ADC_ReadReg function
496 * @{
497 */
498 #define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */
499 #define LL_ADC_FLAG_EOCS ADC_SR_EOC /*!< ADC flag ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
500 #define LL_ADC_FLAG_OVR ADC_SR_OVR /*!< ADC flag ADC group regular overrun */
501 #define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */
502 #define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
503 #define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */
504 #define LL_ADC_FLAG_EOCS_MST ADC_CSR_EOC1 /*!< ADC flag ADC multimode master group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
505 #define LL_ADC_FLAG_EOCS_SLV1 ADC_CSR_EOC2 /*!< ADC flag ADC multimode slave 1 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
506 #define LL_ADC_FLAG_EOCS_SLV2 ADC_CSR_EOC3 /*!< ADC flag ADC multimode slave 2 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
507 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR1 /*!< ADC flag ADC multimode master group regular overrun */
508 #define LL_ADC_FLAG_OVR_SLV1 ADC_CSR_OVR2 /*!< ADC flag ADC multimode slave 1 group regular overrun */
509 #define LL_ADC_FLAG_OVR_SLV2 ADC_CSR_OVR3 /*!< ADC flag ADC multimode slave 2 group regular overrun */
510 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOC1 /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
511 #define LL_ADC_FLAG_JEOS_SLV1 ADC_CSR_JEOC2 /*!< ADC flag ADC multimode slave 1 group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
512 #define LL_ADC_FLAG_JEOS_SLV2 ADC_CSR_JEOC3 /*!< ADC flag ADC multimode slave 2 group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
513 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1 /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
514 #define LL_ADC_FLAG_AWD1_SLV1 ADC_CSR_AWD2 /*!< ADC flag ADC multimode slave 1 analog watchdog 1 */
515 #define LL_ADC_FLAG_AWD1_SLV2 ADC_CSR_AWD3 /*!< ADC flag ADC multimode slave 2 analog watchdog 1 */
516 /**
517 * @}
518 */
519
520 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
521 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
522 * @{
523 */
524 #define LL_ADC_IT_EOCS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
525 #define LL_ADC_IT_OVR ADC_CR1_OVRIE /*!< ADC interruption ADC group regular overrun */
526 #define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
527 #define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */
528 /**
529 * @}
530 */
531
532 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
533 * @{
534 */
535 /* List of ADC registers intended to be used (most commonly) with */
536 /* DMA transfer. */
537 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
538 #define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000U /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
539 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001U /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
540 /**
541 * @}
542 */
543
544 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
545 * @{
546 */
547 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
548 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 ( ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
549 #define LL_ADC_CLOCK_SYNC_PCLK_DIV6 (ADC_CCR_ADCPRE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 6 */
550 #define LL_ADC_CLOCK_SYNC_PCLK_DIV8 (ADC_CCR_ADCPRE_1 | ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 8 */
551 /**
552 * @}
553 */
554
555 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
556 * @{
557 */
558 /* Note: Other measurement paths to internal channels may be available */
559 /* (connections to other peripherals). */
560 /* If they are not listed below, they do not require any specific */
561 /* path enable. In this case, Access to measurement path is done */
562 /* only by selecting the corresponding ADC internal channel. */
563 #define LL_ADC_PATH_INTERNAL_NONE 0x00000000U /*!< ADC measurement paths all disabled */
564 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */
565 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */
566 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATE) /*!< ADC measurement path to internal channel Vbat */
567 /**
568 * @}
569 */
570
571 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
572 * @{
573 */
574 #define LL_ADC_RESOLUTION_12B 0x00000000U /*!< ADC resolution 12 bits */
575 #define LL_ADC_RESOLUTION_10B ( ADC_CR1_RES_0) /*!< ADC resolution 10 bits */
576 #define LL_ADC_RESOLUTION_8B (ADC_CR1_RES_1 ) /*!< ADC resolution 8 bits */
577 #define LL_ADC_RESOLUTION_6B (ADC_CR1_RES_1 | ADC_CR1_RES_0) /*!< ADC resolution 6 bits */
578 /**
579 * @}
580 */
581
582 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
583 * @{
584 */
585 #define LL_ADC_DATA_ALIGN_RIGHT 0x00000000U /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
586 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
587 /**
588 * @}
589 */
590
591 /** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection
592 * @{
593 */
594 #define LL_ADC_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/
595 #define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */
596 /**
597 * @}
598 */
599
600 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
601 * @{
602 */
603 #define LL_ADC_GROUP_REGULAR 0x00000001U /*!< ADC group regular (available on all STM32 devices) */
604 #define LL_ADC_GROUP_INJECTED 0x00000002U /*!< ADC group injected (not available on all STM32 devices)*/
605 #define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003U /*!< ADC both groups regular and injected */
606 /**
607 * @}
608 */
609
610 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
611 * @{
612 */
613 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
614 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
615 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
616 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
617 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
618 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
619 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
620 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
621 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
622 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
623 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
624 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
625 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
626 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
627 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
628 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
629 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
630 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
631 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
632 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F7, ADC channel available only on ADC instance: ADC1. */
633 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32F7, ADC channel available only on ADC instance: ADC1. */
634 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32F7, ADC channel available only on ADC instance: ADC1. */
635
636 /**
637 * @}
638 */
639
640 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
641 * @{
642 */
643 #define LL_ADC_REG_TRIG_SOFTWARE 0x00000000U /*!< ADC group regular conversion trigger internal: SW start. */
644 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 ((uint32_t)ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
645 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
646 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
647 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
648 #define LL_ADC_REG_TRIG_EXT_TIM5_TRGO (ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */
649 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
650 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
651 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
652 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CR2_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
653 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
654 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
655 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
656 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
657 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CR2_EXTSEL_3 |ADC_CR2_EXTSEL_2| ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
658 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
659
660 /**
661 * @}
662 */
663
664 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
665 * @{
666 */
667 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
668 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CR2_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
669 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CR2_EXTEN_1 | ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
670 /**
671 * @}
672 */
673
674 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
675 * @{
676 */
677 #define LL_ADC_REG_CONV_SINGLE 0x00000000U /*!< ADC conversions are performed in single mode: one conversion per trigger */
678 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
679 /**
680 * @}
681 */
682
683 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
684 * @{
685 */
686 #define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000U /*!< ADC conversions are not transferred by DMA */
687 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
688 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DDS | ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
689 /**
690 * @}
691 */
692
693 /** @defgroup ADC_LL_EC_REG_FLAG_EOC_SELECTION ADC group regular - Flag EOC selection (unitary or sequence conversions)
694 * @{
695 */
696 #define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV 0x00000000U /*!< ADC flag EOC (end of unitary conversion) selected */
697 #define LL_ADC_REG_FLAG_EOC_UNITARY_CONV (ADC_CR2_EOCS) /*!< ADC flag EOS (end of sequence conversions) selected */
698 /**
699 * @}
700 */
701
702 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
703 * @{
704 */
705 #define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
706 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
707 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
708 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
709 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
710 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
711 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
712 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
713 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
714 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
715 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
716 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
717 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
718 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
719 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
720 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
721 /**
722 * @}
723 */
724
725 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
726 * @{
727 */
728 #define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group regular sequencer discontinuous mode disable */
729 #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
730 #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
731 #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
732 #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
733 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
734 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
735 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
736 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
737 /**
738 * @}
739 */
740
741 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
742 * @{
743 */
744 #define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
745 #define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
746 #define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
747 #define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
748 #define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
749 #define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
750 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
751 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
752 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
753 #define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
754 #define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
755 #define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
756 #define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
757 #define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
758 #define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
759 #define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
760 /**
761 * @}
762 */
763
764 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
765 * @{
766 */
767 #define LL_ADC_INJ_TRIG_SOFTWARE 0x00000000U /*!< ADC group injected conversion trigger internal: SW start. */
768 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
769 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
770 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
771 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
772 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
773 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
774 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
775 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_CR2_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
776 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
777 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
778 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
779 #define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */
780 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
781 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
782
783 /**
784 * @}
785 */
786
787 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
788 * @{
789 */
790 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
791 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_CR2_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
792 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_CR2_JEXTEN_1 | ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
793 /**
794 * @}
795 */
796
797 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
798 * @{
799 */
800 #define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000U /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
801 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
802 /**
803 * @}
804 */
805
806
807 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
808 * @{
809 */
810 #define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
811 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
812 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
813 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
814 /**
815 * @}
816 */
817
818 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
819 * @{
820 */
821 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group injected sequencer discontinuous mode disable */
822 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
823 /**
824 * @}
825 */
826
827 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
828 * @{
829 */
830 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001U) /*!< ADC group injected sequencer rank 1 */
831 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002U) /*!< ADC group injected sequencer rank 2 */
832 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003U) /*!< ADC group injected sequencer rank 3 */
833 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004U) /*!< ADC group injected sequencer rank 4 */
834 /**
835 * @}
836 */
837
838 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
839 * @{
840 */
841 #define LL_ADC_SAMPLINGTIME_3CYCLES 0x00000000U /*!< Sampling time 3 ADC clock cycles */
842 #define LL_ADC_SAMPLINGTIME_15CYCLES (ADC_SMPR1_SMP10_0) /*!< Sampling time 15 ADC clock cycles */
843 #define LL_ADC_SAMPLINGTIME_28CYCLES (ADC_SMPR1_SMP10_1) /*!< Sampling time 28 ADC clock cycles */
844 #define LL_ADC_SAMPLINGTIME_56CYCLES (ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0) /*!< Sampling time 56 ADC clock cycles */
845 #define LL_ADC_SAMPLINGTIME_84CYCLES (ADC_SMPR1_SMP10_2) /*!< Sampling time 84 ADC clock cycles */
846 #define LL_ADC_SAMPLINGTIME_112CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0) /*!< Sampling time 112 ADC clock cycles */
847 #define LL_ADC_SAMPLINGTIME_144CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1) /*!< Sampling time 144 ADC clock cycles */
848 #define LL_ADC_SAMPLINGTIME_480CYCLES (ADC_SMPR1_SMP10) /*!< Sampling time 480 ADC clock cycles */
849 /**
850 * @}
851 */
852
853 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
854 * @{
855 */
856 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
857 /**
858 * @}
859 */
860
861 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
862 * @{
863 */
864 #define LL_ADC_AWD_DISABLE 0x00000000U /*!< ADC analog watchdog monitoring disabled */
865 #define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
866 #define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
867 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
868 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
869 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
870 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
871 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
872 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
873 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
874 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
875 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
876 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
877 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
878 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
879 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
880 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
881 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
882 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
883 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
884 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
885 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
886 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
887 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
888 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
889 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
890 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
891 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
892 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
893 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
894 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
895 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
896 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
897 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
898 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
899 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
900 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
901 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
902 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
903 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
904 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
905 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
906 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
907 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
908 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
909 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
910 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
911 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
912 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
913 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
914 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
915 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
916 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
917 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
918 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
919 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
920 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
921 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
922 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
923 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
924 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
925 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
926 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
927 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
928 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
929 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
930 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */
931 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
932 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
933 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
934 /**
935 * @}
936 */
937
938 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
939 * @{
940 */
941 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */
942 #define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */
943 /**
944 * @}
945 */
946
947 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
948 * @{
949 */
950 #define LL_ADC_MULTI_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */
951 #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
952 #define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
953 #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected simultaneous */
954 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
955 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
956 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
957 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
958 #if defined(ADC3)
959 #define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected simultaneous */
960 #define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected alternate trigger */
961 #define LL_ADC_MULTI_TRIPLE_INJ_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected simultaneous */
962 #define LL_ADC_MULTI_TRIPLE_REG_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: group regular simultaneous */
963 #define LL_ADC_MULTI_TRIPLE_REG_INTERL (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular interleaved */
964 #define LL_ADC_MULTI_TRIPLE_INJ_ALTERN (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
965 #endif
966 /**
967 * @}
968 */
969
970 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
971 * @{
972 */
973 #define LL_ADC_MULTI_REG_DMA_EACH_ADC 0x00000000U /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
974 #define LL_ADC_MULTI_REG_DMA_LIMIT_1 ( ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */
975 #define LL_ADC_MULTI_REG_DMA_LIMIT_2 ( ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words one by one, ADC2&1 then ADC1&3 then ADC3&2. */
976 #define LL_ADC_MULTI_REG_DMA_LIMIT_3 ( ADC_CCR_DMA_0 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */
977 #define LL_ADC_MULTI_REG_DMA_UNLMT_1 (ADC_CCR_DDS | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */
978 #define LL_ADC_MULTI_REG_DMA_UNLMT_2 (ADC_CCR_DDS | ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words by pairs, ADC2&1 then ADC1&3 then ADC3&2. */
979 #define LL_ADC_MULTI_REG_DMA_UNLMT_3 (ADC_CCR_DDS | ADC_CCR_DMA_0 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */
980 /**
981 * @}
982 */
983
984 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
985 * @{
986 */
987 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES 0x00000000U /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles*/
988 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
989 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
990 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
991 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
992 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
993 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
994 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
995 #define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles */
996 #define LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 14 ADC clock cycles */
997 #define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles */
998 #define LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 16 ADC clock cycles */
999 #define LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 17 ADC clock cycles */
1000 #define LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 18 ADC clock cycles */
1001 #define LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 19 ADC clock cycles */
1002 #define LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 20 ADC clock cycles */
1003 /**
1004 * @}
1005 */
1006
1007 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
1008 * @{
1009 */
1010 #define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
1011 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */
1012 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
1013 /**
1014 * @}
1015 */
1016
1017
1018
1019 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
1020 * @note Only ADC IP HW delays are defined in ADC LL driver driver,
1021 * not timeout values.
1022 * For details on delays values, refer to descriptions in source code
1023 * above each literal definition.
1024 * @{
1025 */
1026
1027 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
1028 /* not timeout values. */
1029 /* Timeout values for ADC operations are dependent to device clock */
1030 /* configuration (system clock versus ADC clock), */
1031 /* and therefore must be defined in user application. */
1032 /* Indications for estimation of ADC timeout delays, for this */
1033 /* STM32 series: */
1034 /* - ADC enable time: maximum delay is 2us */
1035 /* (refer to device datasheet, parameter "tSTAB") */
1036 /* - ADC conversion time: duration depending on ADC clock and ADC */
1037 /* configuration. */
1038 /* (refer to device reference manual, section "Timing") */
1039
1040 /* Delay for internal voltage reference stabilization time. */
1041 /* Delay set to maximum value (refer to device datasheet, */
1042 /* parameter "tSTART"). */
1043 /* Unit: us */
1044 #define LL_ADC_DELAY_VREFINT_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */
1045
1046 /* Delay for temperature sensor stabilization time. */
1047 /* Literal set to maximum value (refer to device datasheet, */
1048 /* parameter "tSTART"). */
1049 /* Unit: us */
1050 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */
1051
1052 /**
1053 * @}
1054 */
1055
1056 /**
1057 * @}
1058 */
1059
1060
1061 /* Exported macro ------------------------------------------------------------*/
1062 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
1063 * @{
1064 */
1065
1066 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
1067 * @{
1068 */
1069
1070 /**
1071 * @brief Write a value in ADC register
1072 * @param __INSTANCE__ ADC Instance
1073 * @param __REG__ Register to be written
1074 * @param __VALUE__ Value to be written in the register
1075 * @retval None
1076 */
1077 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1078
1079 /**
1080 * @brief Read a value in ADC register
1081 * @param __INSTANCE__ ADC Instance
1082 * @param __REG__ Register to be read
1083 * @retval Register value
1084 */
1085 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1086 /**
1087 * @}
1088 */
1089
1090 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
1091 * @{
1092 */
1093
1094 /**
1095 * @brief Helper macro to get ADC channel number in decimal format
1096 * from literals LL_ADC_CHANNEL_x.
1097 * @note Example:
1098 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
1099 * will return decimal number "4".
1100 * @note The input can be a value from functions where a channel
1101 * number is returned, either defined with number
1102 * or with bitfield (only one bit must be set).
1103 * @param __CHANNEL__ This parameter can be one of the following values:
1104 * @arg @ref LL_ADC_CHANNEL_0
1105 * @arg @ref LL_ADC_CHANNEL_1
1106 * @arg @ref LL_ADC_CHANNEL_2
1107 * @arg @ref LL_ADC_CHANNEL_3
1108 * @arg @ref LL_ADC_CHANNEL_4
1109 * @arg @ref LL_ADC_CHANNEL_5
1110 * @arg @ref LL_ADC_CHANNEL_6
1111 * @arg @ref LL_ADC_CHANNEL_7
1112 * @arg @ref LL_ADC_CHANNEL_8
1113 * @arg @ref LL_ADC_CHANNEL_9
1114 * @arg @ref LL_ADC_CHANNEL_10
1115 * @arg @ref LL_ADC_CHANNEL_11
1116 * @arg @ref LL_ADC_CHANNEL_12
1117 * @arg @ref LL_ADC_CHANNEL_13
1118 * @arg @ref LL_ADC_CHANNEL_14
1119 * @arg @ref LL_ADC_CHANNEL_15
1120 * @arg @ref LL_ADC_CHANNEL_16
1121 * @arg @ref LL_ADC_CHANNEL_17
1122 * @arg @ref LL_ADC_CHANNEL_18
1123 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1124 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1125 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1126 *
1127 * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
1128 * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1129 * @retval Value between Min_Data=0 and Max_Data=18
1130 */
1131 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1132 (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
1133
1134 /**
1135 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
1136 * from number in decimal format.
1137 * @note Example:
1138 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1139 * will return a data equivalent to "LL_ADC_CHANNEL_4".
1140 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
1141 * @retval Returned value can be one of the following values:
1142 * @arg @ref LL_ADC_CHANNEL_0
1143 * @arg @ref LL_ADC_CHANNEL_1
1144 * @arg @ref LL_ADC_CHANNEL_2
1145 * @arg @ref LL_ADC_CHANNEL_3
1146 * @arg @ref LL_ADC_CHANNEL_4
1147 * @arg @ref LL_ADC_CHANNEL_5
1148 * @arg @ref LL_ADC_CHANNEL_6
1149 * @arg @ref LL_ADC_CHANNEL_7
1150 * @arg @ref LL_ADC_CHANNEL_8
1151 * @arg @ref LL_ADC_CHANNEL_9
1152 * @arg @ref LL_ADC_CHANNEL_10
1153 * @arg @ref LL_ADC_CHANNEL_11
1154 * @arg @ref LL_ADC_CHANNEL_12
1155 * @arg @ref LL_ADC_CHANNEL_13
1156 * @arg @ref LL_ADC_CHANNEL_14
1157 * @arg @ref LL_ADC_CHANNEL_15
1158 * @arg @ref LL_ADC_CHANNEL_16
1159 * @arg @ref LL_ADC_CHANNEL_17
1160 * @arg @ref LL_ADC_CHANNEL_18
1161 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1162 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1163 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1164 *
1165 * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
1166 * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
1167 * (1) For ADC channel read back from ADC register,
1168 * comparison with internal channel parameter to be done
1169 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1170 */
1171 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1172 (((__DECIMAL_NB__) <= 9U) \
1173 ? ( \
1174 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1175 (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1176 ) \
1177 : \
1178 ( \
1179 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1180 (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1181 ) \
1182 )
1183
1184 /**
1185 * @brief Helper macro to determine whether the selected channel
1186 * corresponds to literal definitions of driver.
1187 * @note The different literal definitions of ADC channels are:
1188 * - ADC internal channel:
1189 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
1190 * - ADC external channel (channel connected to a GPIO pin):
1191 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
1192 * @note The channel parameter must be a value defined from literal
1193 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1194 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1195 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
1196 * must not be a value from functions where a channel number is
1197 * returned from ADC registers,
1198 * because internal and external channels share the same channel
1199 * number in ADC registers. The differentiation is made only with
1200 * parameters definitions of driver.
1201 * @param __CHANNEL__ This parameter can be one of the following values:
1202 * @arg @ref LL_ADC_CHANNEL_0
1203 * @arg @ref LL_ADC_CHANNEL_1
1204 * @arg @ref LL_ADC_CHANNEL_2
1205 * @arg @ref LL_ADC_CHANNEL_3
1206 * @arg @ref LL_ADC_CHANNEL_4
1207 * @arg @ref LL_ADC_CHANNEL_5
1208 * @arg @ref LL_ADC_CHANNEL_6
1209 * @arg @ref LL_ADC_CHANNEL_7
1210 * @arg @ref LL_ADC_CHANNEL_8
1211 * @arg @ref LL_ADC_CHANNEL_9
1212 * @arg @ref LL_ADC_CHANNEL_10
1213 * @arg @ref LL_ADC_CHANNEL_11
1214 * @arg @ref LL_ADC_CHANNEL_12
1215 * @arg @ref LL_ADC_CHANNEL_13
1216 * @arg @ref LL_ADC_CHANNEL_14
1217 * @arg @ref LL_ADC_CHANNEL_15
1218 * @arg @ref LL_ADC_CHANNEL_16
1219 * @arg @ref LL_ADC_CHANNEL_17
1220 * @arg @ref LL_ADC_CHANNEL_18
1221 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1222 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1223 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1224 *
1225 * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
1226 * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1227 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
1228 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1229 */
1230 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1231 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
1232
1233 /**
1234 * @brief Helper macro to convert a channel defined from parameter
1235 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1236 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1237 * to its equivalent parameter definition of a ADC external channel
1238 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
1239 * @note The channel parameter can be, additionally to a value
1240 * defined from parameter definition of a ADC internal channel
1241 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
1242 * a value defined from parameter definition of
1243 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1244 * or a value from functions where a channel number is returned
1245 * from ADC registers.
1246 * @param __CHANNEL__ This parameter can be one of the following values:
1247 * @arg @ref LL_ADC_CHANNEL_0
1248 * @arg @ref LL_ADC_CHANNEL_1
1249 * @arg @ref LL_ADC_CHANNEL_2
1250 * @arg @ref LL_ADC_CHANNEL_3
1251 * @arg @ref LL_ADC_CHANNEL_4
1252 * @arg @ref LL_ADC_CHANNEL_5
1253 * @arg @ref LL_ADC_CHANNEL_6
1254 * @arg @ref LL_ADC_CHANNEL_7
1255 * @arg @ref LL_ADC_CHANNEL_8
1256 * @arg @ref LL_ADC_CHANNEL_9
1257 * @arg @ref LL_ADC_CHANNEL_10
1258 * @arg @ref LL_ADC_CHANNEL_11
1259 * @arg @ref LL_ADC_CHANNEL_12
1260 * @arg @ref LL_ADC_CHANNEL_13
1261 * @arg @ref LL_ADC_CHANNEL_14
1262 * @arg @ref LL_ADC_CHANNEL_15
1263 * @arg @ref LL_ADC_CHANNEL_16
1264 * @arg @ref LL_ADC_CHANNEL_17
1265 * @arg @ref LL_ADC_CHANNEL_18
1266 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1267 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1268 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1269 *
1270 * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
1271 * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1272 * @retval Returned value can be one of the following values:
1273 * @arg @ref LL_ADC_CHANNEL_0
1274 * @arg @ref LL_ADC_CHANNEL_1
1275 * @arg @ref LL_ADC_CHANNEL_2
1276 * @arg @ref LL_ADC_CHANNEL_3
1277 * @arg @ref LL_ADC_CHANNEL_4
1278 * @arg @ref LL_ADC_CHANNEL_5
1279 * @arg @ref LL_ADC_CHANNEL_6
1280 * @arg @ref LL_ADC_CHANNEL_7
1281 * @arg @ref LL_ADC_CHANNEL_8
1282 * @arg @ref LL_ADC_CHANNEL_9
1283 * @arg @ref LL_ADC_CHANNEL_10
1284 * @arg @ref LL_ADC_CHANNEL_11
1285 * @arg @ref LL_ADC_CHANNEL_12
1286 * @arg @ref LL_ADC_CHANNEL_13
1287 * @arg @ref LL_ADC_CHANNEL_14
1288 * @arg @ref LL_ADC_CHANNEL_15
1289 * @arg @ref LL_ADC_CHANNEL_16
1290 * @arg @ref LL_ADC_CHANNEL_17
1291 * @arg @ref LL_ADC_CHANNEL_18
1292 */
1293 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1294 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1295
1296 /**
1297 * @brief Helper macro to determine whether the internal channel
1298 * selected is available on the ADC instance selected.
1299 * @note The channel parameter must be a value defined from parameter
1300 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1301 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1302 * must not be a value defined from parameter definition of
1303 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1304 * or a value from functions where a channel number is
1305 * returned from ADC registers,
1306 * because internal and external channels share the same channel
1307 * number in ADC registers. The differentiation is made only with
1308 * parameters definitions of driver.
1309 * @param __ADC_INSTANCE__ ADC instance
1310 * @param __CHANNEL__ This parameter can be one of the following values:
1311 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1312 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1313 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1314 *
1315 * (1) On STM32F7, parameter available only on ADC instance: ADC1.
1316 * (2) On devices STM32F7x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1317 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1318 * Value "1" if the internal channel selected is available on the ADC instance selected.
1319 */
1320 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1321 ( \
1322 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1323 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
1324 )
1325 /**
1326 * @brief Helper macro to define ADC analog watchdog parameter:
1327 * define a single channel to monitor with analog watchdog
1328 * from sequencer channel and groups definition.
1329 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1330 * Example:
1331 * LL_ADC_SetAnalogWDMonitChannels(
1332 * ADC1, LL_ADC_AWD1,
1333 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
1334 * @param __CHANNEL__ This parameter can be one of the following values:
1335 * @arg @ref LL_ADC_CHANNEL_0
1336 * @arg @ref LL_ADC_CHANNEL_1
1337 * @arg @ref LL_ADC_CHANNEL_2
1338 * @arg @ref LL_ADC_CHANNEL_3
1339 * @arg @ref LL_ADC_CHANNEL_4
1340 * @arg @ref LL_ADC_CHANNEL_5
1341 * @arg @ref LL_ADC_CHANNEL_6
1342 * @arg @ref LL_ADC_CHANNEL_7
1343 * @arg @ref LL_ADC_CHANNEL_8
1344 * @arg @ref LL_ADC_CHANNEL_9
1345 * @arg @ref LL_ADC_CHANNEL_10
1346 * @arg @ref LL_ADC_CHANNEL_11
1347 * @arg @ref LL_ADC_CHANNEL_12
1348 * @arg @ref LL_ADC_CHANNEL_13
1349 * @arg @ref LL_ADC_CHANNEL_14
1350 * @arg @ref LL_ADC_CHANNEL_15
1351 * @arg @ref LL_ADC_CHANNEL_16
1352 * @arg @ref LL_ADC_CHANNEL_17
1353 * @arg @ref LL_ADC_CHANNEL_18
1354 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1355 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1356 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1357 *
1358 * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
1359 * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
1360 * (1) For ADC channel read back from ADC register,
1361 * comparison with internal channel parameter to be done
1362 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1363 * @param __GROUP__ This parameter can be one of the following values:
1364 * @arg @ref LL_ADC_GROUP_REGULAR
1365 * @arg @ref LL_ADC_GROUP_INJECTED
1366 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
1367 * @retval Returned value can be one of the following values:
1368 * @arg @ref LL_ADC_AWD_DISABLE
1369 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
1370 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
1371 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
1372 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
1373 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
1374 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
1375 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
1376 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
1377 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
1378 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
1379 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
1380 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
1381 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
1382 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
1383 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
1384 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
1385 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
1386 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
1387 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
1388 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
1389 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
1390 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
1391 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
1392 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
1393 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
1394 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
1395 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
1396 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
1397 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
1398 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
1399 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
1400 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
1401 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
1402 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
1403 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
1404 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
1405 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
1406 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
1407 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
1408 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
1409 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
1410 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
1411 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
1412 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
1413 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
1414 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
1415 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
1416 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
1417 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
1418 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
1419 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
1420 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
1421 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
1422 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
1423 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
1424 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
1425 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
1426 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
1427 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
1428 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
1429 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
1430 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
1431 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
1432 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2)
1433 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2)
1434 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2)
1435 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
1436 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1)
1437 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
1438 *
1439 * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
1440 * (2) On devices STM32F7xx,a limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1441 */
1442 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
1443 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
1444 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
1445 : \
1446 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
1447 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \
1448 : \
1449 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
1450 )
1451
1452 /**
1453 * @brief Helper macro to set the value of ADC analog watchdog threshold high
1454 * or low in function of ADC resolution, when ADC resolution is
1455 * different of 12 bits.
1456 * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
1457 * Example, with a ADC resolution of 8 bits, to set the value of
1458 * analog watchdog threshold high (on 8 bits):
1459 * LL_ADC_SetAnalogWDThresholds
1460 * (< ADCx param >,
1461 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
1462 * );
1463 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1464 * @arg @ref LL_ADC_RESOLUTION_12B
1465 * @arg @ref LL_ADC_RESOLUTION_10B
1466 * @arg @ref LL_ADC_RESOLUTION_8B
1467 * @arg @ref LL_ADC_RESOLUTION_6B
1468 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
1469 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1470 */
1471 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
1472 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U )))
1473
1474 /**
1475 * @brief Helper macro to get the value of ADC analog watchdog threshold high
1476 * or low in function of ADC resolution, when ADC resolution is
1477 * different of 12 bits.
1478 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1479 * Example, with a ADC resolution of 8 bits, to get the value of
1480 * analog watchdog threshold high (on 8 bits):
1481 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
1482 * (LL_ADC_RESOLUTION_8B,
1483 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
1484 * );
1485 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1486 * @arg @ref LL_ADC_RESOLUTION_12B
1487 * @arg @ref LL_ADC_RESOLUTION_10B
1488 * @arg @ref LL_ADC_RESOLUTION_8B
1489 * @arg @ref LL_ADC_RESOLUTION_6B
1490 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
1491 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1492 */
1493 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
1494 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U )))
1495
1496 /**
1497 * @brief Helper macro to get the ADC multimode conversion data of ADC master
1498 * or ADC slave from raw value with both ADC conversion data concatenated.
1499 * @note This macro is intended to be used when multimode transfer by DMA
1500 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
1501 * In this case the transferred data need to processed with this macro
1502 * to separate the conversion data of ADC master and ADC slave.
1503 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
1504 * @arg @ref LL_ADC_MULTI_MASTER
1505 * @arg @ref LL_ADC_MULTI_SLAVE
1506 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
1507 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1508 */
1509 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
1510 (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
1511
1512 /**
1513 * @brief Helper macro to select the ADC common instance
1514 * to which is belonging the selected ADC instance.
1515 * @note ADC common register instance can be used for:
1516 * - Set parameters common to several ADC instances
1517 * - Multimode (for devices with several ADC instances)
1518 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1519 * @param __ADCx__ ADC instance
1520 * @retval ADC common register instance
1521 */
1522 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
1523 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1524 (ADC123_COMMON)
1525 #elif defined(ADC1) && defined(ADC2)
1526 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1527 (ADC12_COMMON)
1528 #else
1529 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1530 (ADC1_COMMON)
1531 #endif
1532
1533 /**
1534 * @brief Helper macro to check if all ADC instances sharing the same
1535 * ADC common instance are disabled.
1536 * @note This check is required by functions with setting conditioned to
1537 * ADC state:
1538 * All ADC instances of the ADC common group must be disabled.
1539 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1540 * @note On devices with only 1 ADC common instance, parameter of this macro
1541 * is useless and can be ignored (parameter kept for compatibility
1542 * with devices featuring several ADC common instances).
1543 * @param __ADCXY_COMMON__ ADC common instance
1544 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1545 * @retval Value "0" if all ADC instances sharing the same ADC common instance
1546 * are disabled.
1547 * Value "1" if at least one ADC instance sharing the same ADC common instance
1548 * is enabled.
1549 */
1550 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
1551 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1552 (LL_ADC_IsEnabled(ADC1) | \
1553 LL_ADC_IsEnabled(ADC2) | \
1554 LL_ADC_IsEnabled(ADC3) )
1555 #elif defined(ADC1) && defined(ADC2)
1556 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1557 (LL_ADC_IsEnabled(ADC1) | \
1558 LL_ADC_IsEnabled(ADC2) )
1559 #else
1560 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1561 (LL_ADC_IsEnabled(ADC1))
1562 #endif
1563
1564 /**
1565 * @brief Helper macro to define the ADC conversion data full-scale digital
1566 * value corresponding to the selected ADC resolution.
1567 * @note ADC conversion data full-scale corresponds to voltage range
1568 * determined by analog voltage references Vref+ and Vref-
1569 * (refer to reference manual).
1570 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1571 * @arg @ref LL_ADC_RESOLUTION_12B
1572 * @arg @ref LL_ADC_RESOLUTION_10B
1573 * @arg @ref LL_ADC_RESOLUTION_8B
1574 * @arg @ref LL_ADC_RESOLUTION_6B
1575 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1576 */
1577 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1578 (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)))
1579
1580 /**
1581 * @brief Helper macro to convert the ADC conversion data from
1582 * a resolution to another resolution.
1583 * @param __DATA__ ADC conversion data to be converted
1584 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
1585 * This parameter can be one of the following values:
1586 * @arg @ref LL_ADC_RESOLUTION_12B
1587 * @arg @ref LL_ADC_RESOLUTION_10B
1588 * @arg @ref LL_ADC_RESOLUTION_8B
1589 * @arg @ref LL_ADC_RESOLUTION_6B
1590 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
1591 * This parameter can be one of the following values:
1592 * @arg @ref LL_ADC_RESOLUTION_12B
1593 * @arg @ref LL_ADC_RESOLUTION_10B
1594 * @arg @ref LL_ADC_RESOLUTION_8B
1595 * @arg @ref LL_ADC_RESOLUTION_6B
1596 * @retval ADC conversion data to the requested resolution
1597 */
1598 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \
1599 (((__DATA__) \
1600 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U))) \
1601 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)) \
1602 )
1603
1604 /**
1605 * @brief Helper macro to calculate the voltage (unit: mVolt)
1606 * corresponding to a ADC conversion data (unit: digital value).
1607 * @note Analog reference voltage (Vref+) must be either known from
1608 * user board environment or can be calculated using ADC measurement
1609 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1610 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV)
1611 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
1612 * (unit: digital value).
1613 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1614 * @arg @ref LL_ADC_RESOLUTION_12B
1615 * @arg @ref LL_ADC_RESOLUTION_10B
1616 * @arg @ref LL_ADC_RESOLUTION_8B
1617 * @arg @ref LL_ADC_RESOLUTION_6B
1618 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1619 */
1620 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
1621 __ADC_DATA__,\
1622 __ADC_RESOLUTION__) \
1623 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
1624 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1625 )
1626
1627 /**
1628 * @brief Helper macro to calculate analog reference voltage (Vref+)
1629 * (unit: mVolt) from ADC conversion data of internal voltage
1630 * reference VrefInt.
1631 * @note Computation is using VrefInt calibration value
1632 * stored in system memory for each device during production.
1633 * @note This voltage depends on user board environment: voltage level
1634 * connected to pin Vref+.
1635 * On devices with small package, the pin Vref+ is not present
1636 * and internally bonded to pin Vdda.
1637 * @note On this STM32 series, calibration data of internal voltage reference
1638 * VrefInt corresponds to a resolution of 12 bits,
1639 * this is the recommended ADC resolution to convert voltage of
1640 * internal voltage reference VrefInt.
1641 * Otherwise, this macro performs the processing to scale
1642 * ADC conversion data to 12 bits.
1643 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
1644 * of internal voltage reference VrefInt (unit: digital value).
1645 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1646 * @arg @ref LL_ADC_RESOLUTION_12B
1647 * @arg @ref LL_ADC_RESOLUTION_10B
1648 * @arg @ref LL_ADC_RESOLUTION_8B
1649 * @arg @ref LL_ADC_RESOLUTION_6B
1650 * @retval Analog reference voltage (unit: mV)
1651 */
1652 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
1653 __ADC_RESOLUTION__) \
1654 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
1655 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
1656 (__ADC_RESOLUTION__), \
1657 LL_ADC_RESOLUTION_12B) \
1658 )
1659
1660 /**
1661 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1662 * from ADC conversion data of internal temperature sensor.
1663 * @note Computation is using temperature sensor calibration values
1664 * stored in system memory for each device during production.
1665 * @note Calculation formula:
1666 * Temperature = ((TS_ADC_DATA - TS_CAL1)
1667 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
1668 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
1669 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1670 * Avg_Slope = (TS_CAL2 - TS_CAL1)
1671 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
1672 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
1673 * TEMP_DEGC_CAL1 (calibrated in factory)
1674 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
1675 * TEMP_DEGC_CAL2 (calibrated in factory)
1676 * Caution: Calculation relevancy under reserve that calibration
1677 * parameters are correct (address and data).
1678 * To calculate temperature using temperature sensor
1679 * datasheet typical values (generic values less, therefore
1680 * less accurate than calibrated values),
1681 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
1682 * @note As calculation input, the analog reference voltage (Vref+) must be
1683 * defined as it impacts the ADC LSB equivalent voltage.
1684 * @note Analog reference voltage (Vref+) must be either known from
1685 * user board environment or can be calculated using ADC measurement
1686 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1687 * @note On this STM32 series, calibration data of temperature sensor
1688 * corresponds to a resolution of 12 bits,
1689 * this is the recommended ADC resolution to convert voltage of
1690 * temperature sensor.
1691 * Otherwise, this macro performs the processing to scale
1692 * ADC conversion data to 12 bits.
1693 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV)
1694 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
1695 * temperature sensor (unit: digital value).
1696 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
1697 * sensor voltage has been measured.
1698 * This parameter can be one of the following values:
1699 * @arg @ref LL_ADC_RESOLUTION_12B
1700 * @arg @ref LL_ADC_RESOLUTION_10B
1701 * @arg @ref LL_ADC_RESOLUTION_8B
1702 * @arg @ref LL_ADC_RESOLUTION_6B
1703 * @retval Temperature (unit: degree Celsius)
1704 */
1705 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
1706 __TEMPSENSOR_ADC_DATA__,\
1707 __ADC_RESOLUTION__) \
1708 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
1709 (__ADC_RESOLUTION__), \
1710 LL_ADC_RESOLUTION_12B) \
1711 * (__VREFANALOG_VOLTAGE__)) \
1712 / TEMPSENSOR_CAL_VREFANALOG) \
1713 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
1714 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
1715 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
1716 ) + TEMPSENSOR_CAL1_TEMP \
1717 )
1718
1719 /**
1720 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1721 * from ADC conversion data of internal temperature sensor.
1722 * @note Computation is using temperature sensor typical values
1723 * (refer to device datasheet).
1724 * @note Calculation formula:
1725 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
1726 * / Avg_Slope + CALx_TEMP
1727 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1728 * (unit: digital value)
1729 * Avg_Slope = temperature sensor slope
1730 * (unit: uV/Degree Celsius)
1731 * TS_TYP_CALx_VOLT = temperature sensor digital value at
1732 * temperature CALx_TEMP (unit: mV)
1733 * Caution: Calculation relevancy under reserve the temperature sensor
1734 * of the current device has characteristics in line with
1735 * datasheet typical values.
1736 * If temperature sensor calibration values are available on
1737 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
1738 * temperature calculation will be more accurate using
1739 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
1740 * @note As calculation input, the analog reference voltage (Vref+) must be
1741 * defined as it impacts the ADC LSB equivalent voltage.
1742 * @note Analog reference voltage (Vref+) must be either known from
1743 * user board environment or can be calculated using ADC measurement
1744 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1745 * @note ADC measurement data must correspond to a resolution of 12bits
1746 * (full scale digital value 4095). If not the case, the data must be
1747 * preliminarily rescaled to an equivalent resolution of 12 bits.
1748 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data Temperature sensor slope typical value (unit uV/DegCelsius).
1749 * On STM32F7, refer to device datasheet parameter "Avg_Slope".
1750 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit mV).
1751 * On STM32F4, refer to device datasheet parameter "V25".
1752 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit mV)
1753 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit mV)
1754 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit digital value).
1755 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
1756 * This parameter can be one of the following values:
1757 * @arg @ref LL_ADC_RESOLUTION_12B
1758 * @arg @ref LL_ADC_RESOLUTION_10B
1759 * @arg @ref LL_ADC_RESOLUTION_8B
1760 * @arg @ref LL_ADC_RESOLUTION_6B
1761 * @retval Temperature (unit: degree Celsius)
1762 */
1763 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
1764 __TEMPSENSOR_TYP_CALX_V__,\
1765 __TEMPSENSOR_CALX_TEMP__,\
1766 __VREFANALOG_VOLTAGE__,\
1767 __TEMPSENSOR_ADC_DATA__,\
1768 __ADC_RESOLUTION__) \
1769 ((( ( \
1770 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
1771 * 1000) \
1772 - \
1773 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
1774 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
1775 * 1000) \
1776 ) \
1777 ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
1778 ) + (__TEMPSENSOR_CALX_TEMP__) \
1779 )
1780
1781 /**
1782 * @}
1783 */
1784
1785 /**
1786 * @}
1787 */
1788
1789
1790 /* Exported functions --------------------------------------------------------*/
1791 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
1792 * @{
1793 */
1794
1795 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
1796 * @{
1797 */
1798 /* Note: LL ADC functions to set DMA transfer are located into sections of */
1799 /* configuration of ADC instance, groups and multimode (if available): */
1800 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
1801
1802 /**
1803 * @brief Function to help to configure DMA transfer from ADC: retrieve the
1804 * ADC register address from ADC instance and a list of ADC registers
1805 * intended to be used (most commonly) with DMA transfer.
1806 * @note These ADC registers are data registers:
1807 * when ADC conversion data is available in ADC data registers,
1808 * ADC generates a DMA transfer request.
1809 * @note This macro is intended to be used with LL DMA driver, refer to
1810 * function "LL_DMA_ConfigAddresses()".
1811 * Example:
1812 * LL_DMA_ConfigAddresses(DMA1,
1813 * LL_DMA_CHANNEL_1,
1814 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
1815 * (uint32_t)&< array or variable >,
1816 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
1817 * @note For devices with several ADC: in multimode, some devices
1818 * use a different data register outside of ADC instance scope
1819 * (common data register). This macro manages this register difference,
1820 * only ADC instance has to be set as parameter.
1821 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
1822 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
1823 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
1824 * @param ADCx ADC instance
1825 * @param Register This parameter can be one of the following values:
1826 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
1827 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
1828 *
1829 * (1) Available on devices with several ADC instances.
1830 * @retval ADC register address
1831 */
LL_ADC_DMA_GetRegAddr(ADC_TypeDef * ADCx,uint32_t Register)1832 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
1833 {
1834 uint32_t data_reg_addr = 0U;
1835
1836 if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
1837 {
1838 /* Retrieve address of register DR */
1839 data_reg_addr = (uint32_t)&(ADCx->DR);
1840 }
1841 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
1842 {
1843 /* Retrieve address of register CDR */
1844 data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
1845 }
1846
1847 return data_reg_addr;
1848 }
1849
1850 /**
1851 * @}
1852 */
1853
1854 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
1855 * @{
1856 */
1857
1858 /**
1859 * @brief Set parameter common to several ADC: Clock source and prescaler.
1860 * @rmtoll CCR ADCPRE LL_ADC_SetCommonClock
1861 * @param ADCxy_COMMON ADC common instance
1862 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1863 * @param CommonClock This parameter can be one of the following values:
1864 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
1865 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
1866 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6
1867 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8
1868 * @retval None
1869 */
LL_ADC_SetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t CommonClock)1870 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
1871 {
1872 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE, CommonClock);
1873 }
1874
1875 /**
1876 * @brief Get parameter common to several ADC: Clock source and prescaler.
1877 * @rmtoll CCR ADCPRE LL_ADC_GetCommonClock
1878 * @param ADCxy_COMMON ADC common instance
1879 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1880 * @retval Returned value can be one of the following values:
1881 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
1882 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
1883 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6
1884 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8
1885 */
LL_ADC_GetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON)1886 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
1887 {
1888 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE));
1889 }
1890
1891 /**
1892 * @brief Set parameter common to several ADC: measurement path to internal
1893 * channels (VrefInt, temperature sensor, ...).
1894 * @note One or several values can be selected.
1895 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1896 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1897 * @note Stabilization time of measurement path to internal channel:
1898 * After enabling internal paths, before starting ADC conversion,
1899 * a delay is required for internal voltage reference and
1900 * temperature sensor stabilization time.
1901 * Refer to device datasheet.
1902 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
1903 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
1904 * @note ADC internal channel sampling time constraint:
1905 * For ADC conversion of internal channels,
1906 * a sampling time minimum value is required.
1907 * Refer to device datasheet.
1908 * @rmtoll CCR TSVREFE LL_ADC_SetCommonPathInternalCh\n
1909 * CCR VBATE LL_ADC_SetCommonPathInternalCh
1910 * @param ADCxy_COMMON ADC common instance
1911 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1912 * @param PathInternal This parameter can be a combination of the following values:
1913 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1914 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1915 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1916 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
1917 * @retval None
1918 */
LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)1919 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
1920 {
1921 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE, PathInternal);
1922 }
1923
1924 /**
1925 * @brief Get parameter common to several ADC: measurement path to internal
1926 * channels (VrefInt, temperature sensor, ...).
1927 * @note One or several values can be selected.
1928 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1929 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1930 * @rmtoll CCR TSVREFE LL_ADC_GetCommonPathInternalCh\n
1931 * CCR VBATE LL_ADC_GetCommonPathInternalCh
1932 * @param ADCxy_COMMON ADC common instance
1933 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1934 * @retval Returned value can be a combination of the following values:
1935 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1936 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1937 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1938 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
1939 */
LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON)1940 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
1941 {
1942 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE));
1943 }
1944
1945 /**
1946 * @}
1947 */
1948
1949 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
1950 * @{
1951 */
1952
1953 /**
1954 * @brief Set ADC resolution.
1955 * Refer to reference manual for alignments formats
1956 * dependencies to ADC resolutions.
1957 * @rmtoll CR1 RES LL_ADC_SetResolution
1958 * @param ADCx ADC instance
1959 * @param Resolution This parameter can be one of the following values:
1960 * @arg @ref LL_ADC_RESOLUTION_12B
1961 * @arg @ref LL_ADC_RESOLUTION_10B
1962 * @arg @ref LL_ADC_RESOLUTION_8B
1963 * @arg @ref LL_ADC_RESOLUTION_6B
1964 * @retval None
1965 */
LL_ADC_SetResolution(ADC_TypeDef * ADCx,uint32_t Resolution)1966 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
1967 {
1968 MODIFY_REG(ADCx->CR1, ADC_CR1_RES, Resolution);
1969 }
1970
1971 /**
1972 * @brief Get ADC resolution.
1973 * Refer to reference manual for alignments formats
1974 * dependencies to ADC resolutions.
1975 * @rmtoll CR1 RES LL_ADC_GetResolution
1976 * @param ADCx ADC instance
1977 * @retval Returned value can be one of the following values:
1978 * @arg @ref LL_ADC_RESOLUTION_12B
1979 * @arg @ref LL_ADC_RESOLUTION_10B
1980 * @arg @ref LL_ADC_RESOLUTION_8B
1981 * @arg @ref LL_ADC_RESOLUTION_6B
1982 */
LL_ADC_GetResolution(ADC_TypeDef * ADCx)1983 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
1984 {
1985 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_RES));
1986 }
1987
1988 /**
1989 * @brief Set ADC conversion data alignment.
1990 * @note Refer to reference manual for alignments formats
1991 * dependencies to ADC resolutions.
1992 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
1993 * @param ADCx ADC instance
1994 * @param DataAlignment This parameter can be one of the following values:
1995 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
1996 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
1997 * @retval None
1998 */
LL_ADC_SetDataAlignment(ADC_TypeDef * ADCx,uint32_t DataAlignment)1999 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
2000 {
2001 MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment);
2002 }
2003
2004 /**
2005 * @brief Get ADC conversion data alignment.
2006 * @note Refer to reference manual for alignments formats
2007 * dependencies to ADC resolutions.
2008 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
2009 * @param ADCx ADC instance
2010 * @retval Returned value can be one of the following values:
2011 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2012 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2013 */
LL_ADC_GetDataAlignment(ADC_TypeDef * ADCx)2014 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
2015 {
2016 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN));
2017 }
2018
2019 /**
2020 * @brief Set ADC sequencers scan mode, for all ADC groups
2021 * (group regular, group injected).
2022 * @note According to sequencers scan mode :
2023 * - If disabled: ADC conversion is performed in unitary conversion
2024 * mode (one channel converted, that defined in rank 1).
2025 * Configuration of sequencers of all ADC groups
2026 * (sequencer scan length, ...) is discarded: equivalent to
2027 * scan length of 1 rank.
2028 * - If enabled: ADC conversions are performed in sequence conversions
2029 * mode, according to configuration of sequencers of
2030 * each ADC group (sequencer scan length, ...).
2031 * Refer to function @ref LL_ADC_REG_SetSequencerLength()
2032 * and to function @ref LL_ADC_INJ_SetSequencerLength().
2033 * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode
2034 * @param ADCx ADC instance
2035 * @param ScanMode This parameter can be one of the following values:
2036 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
2037 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
2038 * @retval None
2039 */
LL_ADC_SetSequencersScanMode(ADC_TypeDef * ADCx,uint32_t ScanMode)2040 __STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode)
2041 {
2042 MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode);
2043 }
2044
2045 /**
2046 * @brief Get ADC sequencers scan mode, for all ADC groups
2047 * (group regular, group injected).
2048 * @note According to sequencers scan mode :
2049 * - If disabled: ADC conversion is performed in unitary conversion
2050 * mode (one channel converted, that defined in rank 1).
2051 * Configuration of sequencers of all ADC groups
2052 * (sequencer scan length, ...) is discarded: equivalent to
2053 * scan length of 1 rank.
2054 * - If enabled: ADC conversions are performed in sequence conversions
2055 * mode, according to configuration of sequencers of
2056 * each ADC group (sequencer scan length, ...).
2057 * Refer to function @ref LL_ADC_REG_SetSequencerLength()
2058 * and to function @ref LL_ADC_INJ_SetSequencerLength().
2059 * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode
2060 * @param ADCx ADC instance
2061 * @retval Returned value can be one of the following values:
2062 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
2063 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
2064 */
LL_ADC_GetSequencersScanMode(ADC_TypeDef * ADCx)2065 __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)
2066 {
2067 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN));
2068 }
2069
2070 /**
2071 * @}
2072 */
2073
2074 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
2075 * @{
2076 */
2077
2078 /**
2079 * @brief Set ADC group regular conversion trigger source:
2080 * internal (SW start) or from external IP (timer event,
2081 * external interrupt line).
2082 * @note On this STM32 series, setting of external trigger edge is performed
2083 * using function @ref LL_ADC_REG_StartConversionExtTrig().
2084 * @note Availability of parameters of trigger sources from timer
2085 * depends on timers availability on the selected device.
2086 * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource\n
2087 * CR2 EXTEN LL_ADC_REG_SetTriggerSource
2088 * @param ADCx ADC instance
2089 * @param TriggerSource This parameter can be one of the following values:
2090 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2091 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
2092 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
2093 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
2094 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
2095 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_TRGO
2096 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
2097 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
2098 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
2099 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
2100 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
2101 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
2102 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
2103 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
2104 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
2105 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
2106 * @retval None
2107 */
LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)2108 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
2109 {
2110 /* Note: On this STM32 series, ADC group regular external trigger edge */
2111 /* is used to perform a ADC conversion start. */
2112 /* This function does not set external trigger edge. */
2113 /* This feature is set using function */
2114 /* @ref LL_ADC_REG_StartConversionExtTrig(). */
2115 MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL));
2116 }
2117
2118 /**
2119 * @brief Get ADC group regular conversion trigger source:
2120 * internal (SW start) or from external IP (timer event,
2121 * external interrupt line).
2122 * @note To determine whether group regular trigger source is
2123 * internal (SW start) or external, without detail
2124 * of which peripheral is selected as external trigger,
2125 * (equivalent to
2126 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
2127 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
2128 * @note Availability of parameters of trigger sources from timer
2129 * depends on timers availability on the selected device.
2130 * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource\n
2131 * CR2 EXTEN LL_ADC_REG_GetTriggerSource
2132 * @param ADCx ADC instance
2133 * @retval Returned value can be one of the following values:
2134 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2135 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
2136 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
2137 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
2138 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
2139 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_TRGO
2140 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
2141 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
2142 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
2143 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
2144 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
2145 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
2146 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
2147 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
2148 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
2149 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
2150 */
LL_ADC_REG_GetTriggerSource(ADC_TypeDef * ADCx)2151 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
2152 {
2153 uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN);
2154
2155 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
2156 /* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}. */
2157 uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
2158
2159 /* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL */
2160 /* to match with triggers literals definition. */
2161 return ((TriggerSource
2162 & (ADC_REG_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_EXTSEL)
2163 | ((ADC_REG_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_EXTEN)
2164 );
2165 }
2166
2167 /**
2168 * @brief Get ADC group regular conversion trigger source internal (SW start)
2169 or external.
2170 * @note In case of group regular trigger source set to external trigger,
2171 * to determine which peripheral is selected as external trigger,
2172 * use function @ref LL_ADC_REG_GetTriggerSource().
2173 * @rmtoll CR2 EXTEN LL_ADC_REG_IsTriggerSourceSWStart
2174 * @param ADCx ADC instance
2175 * @retval Value "0" if trigger source external trigger
2176 * Value "1" if trigger source SW start.
2177 */
LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef * ADCx)2178 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
2179 {
2180 return (READ_BIT(ADCx->CR2, ADC_CR2_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN));
2181 }
2182
2183 /**
2184 * @brief Get ADC group regular conversion trigger polarity.
2185 * @note Applicable only for trigger source set to external trigger.
2186 * @note On this STM32 series, setting of external trigger edge is performed
2187 * using function @ref LL_ADC_REG_StartConversionExtTrig().
2188 * @rmtoll CR2 EXTEN LL_ADC_REG_GetTriggerEdge
2189 * @param ADCx ADC instance
2190 * @retval Returned value can be one of the following values:
2191 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
2192 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
2193 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
2194 */
LL_ADC_REG_GetTriggerEdge(ADC_TypeDef * ADCx)2195 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
2196 {
2197 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTEN));
2198 }
2199
2200
2201 /**
2202 * @brief Set ADC group regular sequencer length and scan direction.
2203 * @note Description of ADC group regular sequencer features:
2204 * - For devices with sequencer fully configurable
2205 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2206 * sequencer length and each rank affectation to a channel
2207 * are configurable.
2208 * This function performs configuration of:
2209 * - Sequence length: Number of ranks in the scan sequence.
2210 * - Sequence direction: Unless specified in parameters, sequencer
2211 * scan direction is forward (from rank 1 to rank n).
2212 * Sequencer ranks are selected using
2213 * function "LL_ADC_REG_SetSequencerRanks()".
2214 * - For devices with sequencer not fully configurable
2215 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2216 * sequencer length and each rank affectation to a channel
2217 * are defined by channel number.
2218 * This function performs configuration of:
2219 * - Sequence length: Number of ranks in the scan sequence is
2220 * defined by number of channels set in the sequence,
2221 * rank of each channel is fixed by channel HW number.
2222 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2223 * - Sequence direction: Unless specified in parameters, sequencer
2224 * scan direction is forward (from lowest channel number to
2225 * highest channel number).
2226 * Sequencer ranks are selected using
2227 * function "LL_ADC_REG_SetSequencerChannels()".
2228 * @note On this STM32 series, group regular sequencer configuration
2229 * is conditioned to ADC instance sequencer mode.
2230 * If ADC instance sequencer mode is disabled, sequencers of
2231 * all groups (group regular, group injected) can be configured
2232 * but their execution is disabled (limited to rank 1).
2233 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2234 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2235 * ADC conversion on only 1 channel.
2236 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
2237 * @param ADCx ADC instance
2238 * @param SequencerNbRanks This parameter can be one of the following values:
2239 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2240 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2241 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2242 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2243 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2244 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2245 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2246 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2247 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
2248 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
2249 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
2250 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
2251 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
2252 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
2253 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
2254 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
2255 * @retval None
2256 */
LL_ADC_REG_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)2257 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
2258 {
2259 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
2260 }
2261
2262 /**
2263 * @brief Get ADC group regular sequencer length and scan direction.
2264 * @note Description of ADC group regular sequencer features:
2265 * - For devices with sequencer fully configurable
2266 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2267 * sequencer length and each rank affectation to a channel
2268 * are configurable.
2269 * This function retrieves:
2270 * - Sequence length: Number of ranks in the scan sequence.
2271 * - Sequence direction: Unless specified in parameters, sequencer
2272 * scan direction is forward (from rank 1 to rank n).
2273 * Sequencer ranks are selected using
2274 * function "LL_ADC_REG_SetSequencerRanks()".
2275 * - For devices with sequencer not fully configurable
2276 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2277 * sequencer length and each rank affectation to a channel
2278 * are defined by channel number.
2279 * This function retrieves:
2280 * - Sequence length: Number of ranks in the scan sequence is
2281 * defined by number of channels set in the sequence,
2282 * rank of each channel is fixed by channel HW number.
2283 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2284 * - Sequence direction: Unless specified in parameters, sequencer
2285 * scan direction is forward (from lowest channel number to
2286 * highest channel number).
2287 * Sequencer ranks are selected using
2288 * function "LL_ADC_REG_SetSequencerChannels()".
2289 * @note On this STM32 series, group regular sequencer configuration
2290 * is conditioned to ADC instance sequencer mode.
2291 * If ADC instance sequencer mode is disabled, sequencers of
2292 * all groups (group regular, group injected) can be configured
2293 * but their execution is disabled (limited to rank 1).
2294 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2295 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2296 * ADC conversion on only 1 channel.
2297 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
2298 * @param ADCx ADC instance
2299 * @retval Returned value can be one of the following values:
2300 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2301 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2302 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2303 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2304 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2305 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2306 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2307 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2308 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
2309 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
2310 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
2311 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
2312 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
2313 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
2314 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
2315 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
2316 */
LL_ADC_REG_GetSequencerLength(ADC_TypeDef * ADCx)2317 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
2318 {
2319 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
2320 }
2321
2322 /**
2323 * @brief Set ADC group regular sequencer discontinuous mode:
2324 * sequence subdivided and scan conversions interrupted every selected
2325 * number of ranks.
2326 * @note It is not possible to enable both ADC group regular
2327 * continuous mode and sequencer discontinuous mode.
2328 * @note It is not possible to enable both ADC auto-injected mode
2329 * and ADC group regular sequencer discontinuous mode.
2330 * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
2331 * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont
2332 * @param ADCx ADC instance
2333 * @param SeqDiscont This parameter can be one of the following values:
2334 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2335 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2336 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
2337 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
2338 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
2339 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
2340 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
2341 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
2342 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
2343 * @retval None
2344 */
LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)2345 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
2346 {
2347 MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont);
2348 }
2349
2350 /**
2351 * @brief Get ADC group regular sequencer discontinuous mode:
2352 * sequence subdivided and scan conversions interrupted every selected
2353 * number of ranks.
2354 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
2355 * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont
2356 * @param ADCx ADC instance
2357 * @retval Returned value can be one of the following values:
2358 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2359 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2360 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
2361 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
2362 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
2363 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
2364 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
2365 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
2366 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
2367 */
LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef * ADCx)2368 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
2369 {
2370 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM));
2371 }
2372
2373 /**
2374 * @brief Set ADC group regular sequence: channel on the selected
2375 * scan sequence rank.
2376 * @note This function performs configuration of:
2377 * - Channels ordering into each rank of scan sequence:
2378 * whatever channel can be placed into whatever rank.
2379 * @note On this STM32 series, ADC group regular sequencer is
2380 * fully configurable: sequencer length and each rank
2381 * affectation to a channel are configurable.
2382 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
2383 * @note Depending on devices and packages, some channels may not be available.
2384 * Refer to device datasheet for channels availability.
2385 * @note On this STM32 series, to measure internal channels (VrefInt,
2386 * TempSensor, ...), measurement paths to internal channels must be
2387 * enabled separately.
2388 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2389 * @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n
2390 * SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n
2391 * SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n
2392 * SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n
2393 * SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n
2394 * SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n
2395 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
2396 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
2397 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
2398 * SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n
2399 * SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n
2400 * SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n
2401 * SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n
2402 * SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n
2403 * SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n
2404 * SQR1 SQ16 LL_ADC_REG_SetSequencerRanks
2405 * @param ADCx ADC instance
2406 * @param Rank This parameter can be one of the following values:
2407 * @arg @ref LL_ADC_REG_RANK_1
2408 * @arg @ref LL_ADC_REG_RANK_2
2409 * @arg @ref LL_ADC_REG_RANK_3
2410 * @arg @ref LL_ADC_REG_RANK_4
2411 * @arg @ref LL_ADC_REG_RANK_5
2412 * @arg @ref LL_ADC_REG_RANK_6
2413 * @arg @ref LL_ADC_REG_RANK_7
2414 * @arg @ref LL_ADC_REG_RANK_8
2415 * @arg @ref LL_ADC_REG_RANK_9
2416 * @arg @ref LL_ADC_REG_RANK_10
2417 * @arg @ref LL_ADC_REG_RANK_11
2418 * @arg @ref LL_ADC_REG_RANK_12
2419 * @arg @ref LL_ADC_REG_RANK_13
2420 * @arg @ref LL_ADC_REG_RANK_14
2421 * @arg @ref LL_ADC_REG_RANK_15
2422 * @arg @ref LL_ADC_REG_RANK_16
2423 * @param Channel This parameter can be one of the following values:
2424 * @arg @ref LL_ADC_CHANNEL_0
2425 * @arg @ref LL_ADC_CHANNEL_1
2426 * @arg @ref LL_ADC_CHANNEL_2
2427 * @arg @ref LL_ADC_CHANNEL_3
2428 * @arg @ref LL_ADC_CHANNEL_4
2429 * @arg @ref LL_ADC_CHANNEL_5
2430 * @arg @ref LL_ADC_CHANNEL_6
2431 * @arg @ref LL_ADC_CHANNEL_7
2432 * @arg @ref LL_ADC_CHANNEL_8
2433 * @arg @ref LL_ADC_CHANNEL_9
2434 * @arg @ref LL_ADC_CHANNEL_10
2435 * @arg @ref LL_ADC_CHANNEL_11
2436 * @arg @ref LL_ADC_CHANNEL_12
2437 * @arg @ref LL_ADC_CHANNEL_13
2438 * @arg @ref LL_ADC_CHANNEL_14
2439 * @arg @ref LL_ADC_CHANNEL_15
2440 * @arg @ref LL_ADC_CHANNEL_16
2441 * @arg @ref LL_ADC_CHANNEL_17
2442 * @arg @ref LL_ADC_CHANNEL_18
2443 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2444 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
2445 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2446 *
2447 * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
2448 * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
2449 * @retval None
2450 */
LL_ADC_REG_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)2451 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
2452 {
2453 /* Set bits with content of parameter "Channel" with bits position */
2454 /* in register and register position depending on parameter "Rank". */
2455 /* Parameters "Rank" and "Channel" are used with masks because containing */
2456 /* other bits reserved for other purpose. */
2457 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
2458
2459 MODIFY_REG(*preg,
2460 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
2461 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
2462 }
2463
2464 /**
2465 * @brief Get ADC group regular sequence: channel on the selected
2466 * scan sequence rank.
2467 * @note On this STM32 series, ADC group regular sequencer is
2468 * fully configurable: sequencer length and each rank
2469 * affectation to a channel are configurable.
2470 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
2471 * @note Depending on devices and packages, some channels may not be available.
2472 * Refer to device datasheet for channels availability.
2473 * @note Usage of the returned channel number:
2474 * - To reinject this channel into another function LL_ADC_xxx:
2475 * the returned channel number is only partly formatted on definition
2476 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
2477 * with parts of literals LL_ADC_CHANNEL_x or using
2478 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2479 * Then the selected literal LL_ADC_CHANNEL_x can be used
2480 * as parameter for another function.
2481 * - To get the channel number in decimal format:
2482 * process the returned value with the helper macro
2483 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2484 * @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n
2485 * SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n
2486 * SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n
2487 * SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n
2488 * SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n
2489 * SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n
2490 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
2491 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
2492 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
2493 * SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n
2494 * SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n
2495 * SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n
2496 * SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n
2497 * SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n
2498 * SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n
2499 * SQR1 SQ16 LL_ADC_REG_GetSequencerRanks
2500 * @param ADCx ADC instance
2501 * @param Rank This parameter can be one of the following values:
2502 * @arg @ref LL_ADC_REG_RANK_1
2503 * @arg @ref LL_ADC_REG_RANK_2
2504 * @arg @ref LL_ADC_REG_RANK_3
2505 * @arg @ref LL_ADC_REG_RANK_4
2506 * @arg @ref LL_ADC_REG_RANK_5
2507 * @arg @ref LL_ADC_REG_RANK_6
2508 * @arg @ref LL_ADC_REG_RANK_7
2509 * @arg @ref LL_ADC_REG_RANK_8
2510 * @arg @ref LL_ADC_REG_RANK_9
2511 * @arg @ref LL_ADC_REG_RANK_10
2512 * @arg @ref LL_ADC_REG_RANK_11
2513 * @arg @ref LL_ADC_REG_RANK_12
2514 * @arg @ref LL_ADC_REG_RANK_13
2515 * @arg @ref LL_ADC_REG_RANK_14
2516 * @arg @ref LL_ADC_REG_RANK_15
2517 * @arg @ref LL_ADC_REG_RANK_16
2518 * @retval Returned value can be one of the following values:
2519 * @arg @ref LL_ADC_CHANNEL_0
2520 * @arg @ref LL_ADC_CHANNEL_1
2521 * @arg @ref LL_ADC_CHANNEL_2
2522 * @arg @ref LL_ADC_CHANNEL_3
2523 * @arg @ref LL_ADC_CHANNEL_4
2524 * @arg @ref LL_ADC_CHANNEL_5
2525 * @arg @ref LL_ADC_CHANNEL_6
2526 * @arg @ref LL_ADC_CHANNEL_7
2527 * @arg @ref LL_ADC_CHANNEL_8
2528 * @arg @ref LL_ADC_CHANNEL_9
2529 * @arg @ref LL_ADC_CHANNEL_10
2530 * @arg @ref LL_ADC_CHANNEL_11
2531 * @arg @ref LL_ADC_CHANNEL_12
2532 * @arg @ref LL_ADC_CHANNEL_13
2533 * @arg @ref LL_ADC_CHANNEL_14
2534 * @arg @ref LL_ADC_CHANNEL_15
2535 * @arg @ref LL_ADC_CHANNEL_16
2536 * @arg @ref LL_ADC_CHANNEL_17
2537 * @arg @ref LL_ADC_CHANNEL_18
2538 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2539 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
2540 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2541 *
2542 * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
2543 * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
2544 * (1) For ADC channel read back from ADC register,
2545 * comparison with internal channel parameter to be done
2546 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2547 */
LL_ADC_REG_GetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank)2548 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
2549 {
2550 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
2551
2552 return (uint32_t) (READ_BIT(*preg,
2553 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
2554 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
2555 );
2556 }
2557
2558 /**
2559 * @brief Set ADC continuous conversion mode on ADC group regular.
2560 * @note Description of ADC continuous conversion mode:
2561 * - single mode: one conversion per trigger
2562 * - continuous mode: after the first trigger, following
2563 * conversions launched successively automatically.
2564 * @note It is not possible to enable both ADC group regular
2565 * continuous mode and sequencer discontinuous mode.
2566 * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode
2567 * @param ADCx ADC instance
2568 * @param Continuous This parameter can be one of the following values:
2569 * @arg @ref LL_ADC_REG_CONV_SINGLE
2570 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
2571 * @retval None
2572 */
LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)2573 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
2574 {
2575 MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous);
2576 }
2577
2578 /**
2579 * @brief Get ADC continuous conversion mode on ADC group regular.
2580 * @note Description of ADC continuous conversion mode:
2581 * - single mode: one conversion per trigger
2582 * - continuous mode: after the first trigger, following
2583 * conversions launched successively automatically.
2584 * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode
2585 * @param ADCx ADC instance
2586 * @retval Returned value can be one of the following values:
2587 * @arg @ref LL_ADC_REG_CONV_SINGLE
2588 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
2589 */
LL_ADC_REG_GetContinuousMode(ADC_TypeDef * ADCx)2590 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
2591 {
2592 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT));
2593 }
2594
2595 /**
2596 * @brief Set ADC group regular conversion data transfer: no transfer or
2597 * transfer by DMA, and DMA requests mode.
2598 * @note If transfer by DMA selected, specifies the DMA requests
2599 * mode:
2600 * - Limited mode (One shot mode): DMA transfer requests are stopped
2601 * when number of DMA data transfers (number of
2602 * ADC conversions) is reached.
2603 * This ADC mode is intended to be used with DMA mode non-circular.
2604 * - Unlimited mode: DMA transfer requests are unlimited,
2605 * whatever number of DMA data transfers (number of
2606 * ADC conversions).
2607 * This ADC mode is intended to be used with DMA mode circular.
2608 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
2609 * mode non-circular:
2610 * when DMA transfers size will be reached, DMA will stop transfers of
2611 * ADC conversions data ADC will raise an overrun error
2612 * (overrun flag and interruption if enabled).
2613 * @note For devices with several ADC instances: ADC multimode DMA
2614 * settings are available using function @ref LL_ADC_SetMultiDMATransfer().
2615 * @note To configure DMA source address (peripheral address),
2616 * use function @ref LL_ADC_DMA_GetRegAddr().
2617 * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer\n
2618 * CR2 DDS LL_ADC_REG_SetDMATransfer
2619 * @param ADCx ADC instance
2620 * @param DMATransfer This parameter can be one of the following values:
2621 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
2622 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
2623 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
2624 * @retval None
2625 */
LL_ADC_REG_SetDMATransfer(ADC_TypeDef * ADCx,uint32_t DMATransfer)2626 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
2627 {
2628 MODIFY_REG(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS, DMATransfer);
2629 }
2630
2631 /**
2632 * @brief Get ADC group regular conversion data transfer: no transfer or
2633 * transfer by DMA, and DMA requests mode.
2634 * @note If transfer by DMA selected, specifies the DMA requests
2635 * mode:
2636 * - Limited mode (One shot mode): DMA transfer requests are stopped
2637 * when number of DMA data transfers (number of
2638 * ADC conversions) is reached.
2639 * This ADC mode is intended to be used with DMA mode non-circular.
2640 * - Unlimited mode: DMA transfer requests are unlimited,
2641 * whatever number of DMA data transfers (number of
2642 * ADC conversions).
2643 * This ADC mode is intended to be used with DMA mode circular.
2644 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
2645 * mode non-circular:
2646 * when DMA transfers size will be reached, DMA will stop transfers of
2647 * ADC conversions data ADC will raise an overrun error
2648 * (overrun flag and interruption if enabled).
2649 * @note For devices with several ADC instances: ADC multimode DMA
2650 * settings are available using function @ref LL_ADC_GetMultiDMATransfer().
2651 * @note To configure DMA source address (peripheral address),
2652 * use function @ref LL_ADC_DMA_GetRegAddr().
2653 * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer\n
2654 * CR2 DDS LL_ADC_REG_GetDMATransfer
2655 * @param ADCx ADC instance
2656 * @retval Returned value can be one of the following values:
2657 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
2658 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
2659 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
2660 */
LL_ADC_REG_GetDMATransfer(ADC_TypeDef * ADCx)2661 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
2662 {
2663 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS));
2664 }
2665
2666 /**
2667 * @brief Specify which ADC flag between EOC (end of unitary conversion)
2668 * or EOS (end of sequence conversions) is used to indicate
2669 * the end of conversion.
2670 * @note This feature is aimed to be set when using ADC with
2671 * programming model by polling or interruption
2672 * (programming model by DMA usually uses DMA interruptions
2673 * to indicate end of conversion and data transfer).
2674 * @note For ADC group injected, end of conversion (flag&IT) is raised
2675 * only at the end of the sequence.
2676 * @rmtoll CR2 EOCS LL_ADC_REG_SetFlagEndOfConversion
2677 * @param ADCx ADC instance
2678 * @param EocSelection This parameter can be one of the following values:
2679 * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
2680 * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV
2681 * @retval None
2682 */
LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef * ADCx,uint32_t EocSelection)2683 __STATIC_INLINE void LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef *ADCx, uint32_t EocSelection)
2684 {
2685 MODIFY_REG(ADCx->CR2, ADC_CR2_EOCS, EocSelection);
2686 }
2687
2688 /**
2689 * @brief Get which ADC flag between EOC (end of unitary conversion)
2690 * or EOS (end of sequence conversions) is used to indicate
2691 * the end of conversion.
2692 * @rmtoll CR2 EOCS LL_ADC_REG_GetFlagEndOfConversion
2693 * @param ADCx ADC instance
2694 * @retval Returned value can be one of the following values:
2695 * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
2696 * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV
2697 */
LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef * ADCx)2698 __STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx)
2699 {
2700 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EOCS));
2701 }
2702
2703 /**
2704 * @}
2705 */
2706
2707 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
2708 * @{
2709 */
2710
2711 /**
2712 * @brief Set ADC group injected conversion trigger source:
2713 * internal (SW start) or from external IP (timer event,
2714 * external interrupt line).
2715 * @note On this STM32 series, setting of external trigger edge is performed
2716 * using function @ref LL_ADC_INJ_StartConversionExtTrig().
2717 * @note Availability of parameters of trigger sources from timer
2718 * depends on timers availability on the selected device.
2719 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource\n
2720 * CR2 JEXTEN LL_ADC_INJ_SetTriggerSource
2721 * @param ADCx ADC instance
2722 * @param TriggerSource This parameter can be one of the following values:
2723 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
2724 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
2725 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
2726 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
2727 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
2728 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
2729 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
2730 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
2731 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
2732 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
2733 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
2734 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
2735 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO
2736 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
2737 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
2738 * @retval None
2739 */
LL_ADC_INJ_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)2740 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
2741 {
2742 /* Note: On this STM32 series, ADC group injected external trigger edge */
2743 /* is used to perform a ADC conversion start. */
2744 /* This function does not set external trigger edge. */
2745 /* This feature is set using function */
2746 /* @ref LL_ADC_INJ_StartConversionExtTrig(). */
2747 MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL));
2748 }
2749
2750 /**
2751 * @brief Get ADC group injected conversion trigger source:
2752 * internal (SW start) or from external IP (timer event,
2753 * external interrupt line).
2754 * @note To determine whether group injected trigger source is
2755 * internal (SW start) or external, without detail
2756 * of which peripheral is selected as external trigger,
2757 * (equivalent to
2758 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
2759 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
2760 * @note Availability of parameters of trigger sources from timer
2761 * depends on timers availability on the selected device.
2762 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource\n
2763 * CR2 JEXTEN LL_ADC_INJ_GetTriggerSource
2764 * @param ADCx ADC instance
2765 * @retval Returned value can be one of the following values:
2766 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
2767 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
2768 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
2769 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
2770 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
2771 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
2772 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
2773 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
2774 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
2775 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
2776 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
2777 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
2778 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO
2779 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
2780 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
2781 */
LL_ADC_INJ_GetTriggerSource(ADC_TypeDef * ADCx)2782 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
2783 {
2784 uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN);
2785
2786 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
2787 /* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}. */
2788 uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U));
2789
2790 /* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL */
2791 /* to match with triggers literals definition. */
2792 return ((TriggerSource
2793 & (ADC_INJ_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_JEXTSEL)
2794 | ((ADC_INJ_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_JEXTEN)
2795 );
2796 }
2797
2798 /**
2799 * @brief Get ADC group injected conversion trigger source internal (SW start)
2800 or external
2801 * @note In case of group injected trigger source set to external trigger,
2802 * to determine which peripheral is selected as external trigger,
2803 * use function @ref LL_ADC_INJ_GetTriggerSource.
2804 * @rmtoll CR2 JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
2805 * @param ADCx ADC instance
2806 * @retval Value "0" if trigger source external trigger
2807 * Value "1" if trigger source SW start.
2808 */
LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef * ADCx)2809 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
2810 {
2811 return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN));
2812 }
2813
2814 /**
2815 * @brief Get ADC group injected conversion trigger polarity.
2816 * Applicable only for trigger source set to external trigger.
2817 * @rmtoll CR2 JEXTEN LL_ADC_INJ_GetTriggerEdge
2818 * @param ADCx ADC instance
2819 * @retval Returned value can be one of the following values:
2820 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
2821 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
2822 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
2823 */
LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef * ADCx)2824 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
2825 {
2826 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN));
2827 }
2828
2829 /**
2830 * @brief Set ADC group injected sequencer length and scan direction.
2831 * @note This function performs configuration of:
2832 * - Sequence length: Number of ranks in the scan sequence.
2833 * - Sequence direction: Unless specified in parameters, sequencer
2834 * scan direction is forward (from rank 1 to rank n).
2835 * @note On this STM32 series, group injected sequencer configuration
2836 * is conditioned to ADC instance sequencer mode.
2837 * If ADC instance sequencer mode is disabled, sequencers of
2838 * all groups (group regular, group injected) can be configured
2839 * but their execution is disabled (limited to rank 1).
2840 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2841 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2842 * ADC conversion on only 1 channel.
2843 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
2844 * @param ADCx ADC instance
2845 * @param SequencerNbRanks This parameter can be one of the following values:
2846 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
2847 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
2848 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
2849 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
2850 * @retval None
2851 */
LL_ADC_INJ_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)2852 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
2853 {
2854 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
2855 }
2856
2857 /**
2858 * @brief Get ADC group injected sequencer length and scan direction.
2859 * @note This function retrieves:
2860 * - Sequence length: Number of ranks in the scan sequence.
2861 * - Sequence direction: Unless specified in parameters, sequencer
2862 * scan direction is forward (from rank 1 to rank n).
2863 * @note On this STM32 series, group injected sequencer configuration
2864 * is conditioned to ADC instance sequencer mode.
2865 * If ADC instance sequencer mode is disabled, sequencers of
2866 * all groups (group regular, group injected) can be configured
2867 * but their execution is disabled (limited to rank 1).
2868 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2869 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2870 * ADC conversion on only 1 channel.
2871 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
2872 * @param ADCx ADC instance
2873 * @retval Returned value can be one of the following values:
2874 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
2875 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
2876 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
2877 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
2878 */
LL_ADC_INJ_GetSequencerLength(ADC_TypeDef * ADCx)2879 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
2880 {
2881 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
2882 }
2883
2884 /**
2885 * @brief Set ADC group injected sequencer discontinuous mode:
2886 * sequence subdivided and scan conversions interrupted every selected
2887 * number of ranks.
2888 * @note It is not possible to enable both ADC group injected
2889 * auto-injected mode and sequencer discontinuous mode.
2890 * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont
2891 * @param ADCx ADC instance
2892 * @param SeqDiscont This parameter can be one of the following values:
2893 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
2894 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
2895 * @retval None
2896 */
LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)2897 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
2898 {
2899 MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont);
2900 }
2901
2902 /**
2903 * @brief Get ADC group injected sequencer discontinuous mode:
2904 * sequence subdivided and scan conversions interrupted every selected
2905 * number of ranks.
2906 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont
2907 * @param ADCx ADC instance
2908 * @retval Returned value can be one of the following values:
2909 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
2910 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
2911 */
LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef * ADCx)2912 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
2913 {
2914 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN));
2915 }
2916
2917 /**
2918 * @brief Set ADC group injected sequence: channel on the selected
2919 * sequence rank.
2920 * @note Depending on devices and packages, some channels may not be available.
2921 * Refer to device datasheet for channels availability.
2922 * @note On this STM32 series, to measure internal channels (VrefInt,
2923 * TempSensor, ...), measurement paths to internal channels must be
2924 * enabled separately.
2925 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2926 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
2927 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
2928 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
2929 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
2930 * @param ADCx ADC instance
2931 * @param Rank This parameter can be one of the following values:
2932 * @arg @ref LL_ADC_INJ_RANK_1
2933 * @arg @ref LL_ADC_INJ_RANK_2
2934 * @arg @ref LL_ADC_INJ_RANK_3
2935 * @arg @ref LL_ADC_INJ_RANK_4
2936 * @param Channel This parameter can be one of the following values:
2937 * @arg @ref LL_ADC_CHANNEL_0
2938 * @arg @ref LL_ADC_CHANNEL_1
2939 * @arg @ref LL_ADC_CHANNEL_2
2940 * @arg @ref LL_ADC_CHANNEL_3
2941 * @arg @ref LL_ADC_CHANNEL_4
2942 * @arg @ref LL_ADC_CHANNEL_5
2943 * @arg @ref LL_ADC_CHANNEL_6
2944 * @arg @ref LL_ADC_CHANNEL_7
2945 * @arg @ref LL_ADC_CHANNEL_8
2946 * @arg @ref LL_ADC_CHANNEL_9
2947 * @arg @ref LL_ADC_CHANNEL_10
2948 * @arg @ref LL_ADC_CHANNEL_11
2949 * @arg @ref LL_ADC_CHANNEL_12
2950 * @arg @ref LL_ADC_CHANNEL_13
2951 * @arg @ref LL_ADC_CHANNEL_14
2952 * @arg @ref LL_ADC_CHANNEL_15
2953 * @arg @ref LL_ADC_CHANNEL_16
2954 * @arg @ref LL_ADC_CHANNEL_17
2955 * @arg @ref LL_ADC_CHANNEL_18
2956 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2957 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
2958 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2959 *
2960 * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
2961 * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
2962 * @retval None
2963 */
LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)2964 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
2965 {
2966 /* Set bits with content of parameter "Channel" with bits position */
2967 /* in register depending on parameter "Rank". */
2968 /* Parameters "Rank" and "Channel" are used with masks because containing */
2969 /* other bits reserved for other purpose. */
2970 uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
2971
2972 MODIFY_REG(ADCx->JSQR,
2973 ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))),
2974 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))));
2975 }
2976
2977 /**
2978 * @brief Get ADC group injected sequence: channel on the selected
2979 * sequence rank.
2980 * @note Depending on devices and packages, some channels may not be available.
2981 * Refer to device datasheet for channels availability.
2982 * @note Usage of the returned channel number:
2983 * - To reinject this channel into another function LL_ADC_xxx:
2984 * the returned channel number is only partly formatted on definition
2985 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
2986 * with parts of literals LL_ADC_CHANNEL_x or using
2987 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2988 * Then the selected literal LL_ADC_CHANNEL_x can be used
2989 * as parameter for another function.
2990 * - To get the channel number in decimal format:
2991 * process the returned value with the helper macro
2992 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2993 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
2994 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
2995 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
2996 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
2997 * @param ADCx ADC instance
2998 * @param Rank This parameter can be one of the following values:
2999 * @arg @ref LL_ADC_INJ_RANK_1
3000 * @arg @ref LL_ADC_INJ_RANK_2
3001 * @arg @ref LL_ADC_INJ_RANK_3
3002 * @arg @ref LL_ADC_INJ_RANK_4
3003 * @retval Returned value can be one of the following values:
3004 * @arg @ref LL_ADC_CHANNEL_0
3005 * @arg @ref LL_ADC_CHANNEL_1
3006 * @arg @ref LL_ADC_CHANNEL_2
3007 * @arg @ref LL_ADC_CHANNEL_3
3008 * @arg @ref LL_ADC_CHANNEL_4
3009 * @arg @ref LL_ADC_CHANNEL_5
3010 * @arg @ref LL_ADC_CHANNEL_6
3011 * @arg @ref LL_ADC_CHANNEL_7
3012 * @arg @ref LL_ADC_CHANNEL_8
3013 * @arg @ref LL_ADC_CHANNEL_9
3014 * @arg @ref LL_ADC_CHANNEL_10
3015 * @arg @ref LL_ADC_CHANNEL_11
3016 * @arg @ref LL_ADC_CHANNEL_12
3017 * @arg @ref LL_ADC_CHANNEL_13
3018 * @arg @ref LL_ADC_CHANNEL_14
3019 * @arg @ref LL_ADC_CHANNEL_15
3020 * @arg @ref LL_ADC_CHANNEL_16
3021 * @arg @ref LL_ADC_CHANNEL_17
3022 * @arg @ref LL_ADC_CHANNEL_18
3023 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3024 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
3025 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3026 *
3027 * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
3028 * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
3029 * (1) For ADC channel read back from ADC register,
3030 * comparison with internal channel parameter to be done
3031 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3032 */
LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank)3033 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
3034 {
3035 uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
3036
3037 return (uint32_t)(READ_BIT(ADCx->JSQR,
3038 ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))))
3039 >> (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))
3040 );
3041 }
3042
3043 /**
3044 * @brief Set ADC group injected conversion trigger:
3045 * independent or from ADC group regular.
3046 * @note This mode can be used to extend number of data registers
3047 * updated after one ADC conversion trigger and with data
3048 * permanently kept (not erased by successive conversions of scan of
3049 * ADC sequencer ranks), up to 5 data registers:
3050 * 1 data register on ADC group regular, 4 data registers
3051 * on ADC group injected.
3052 * @note If ADC group injected injected trigger source is set to an
3053 * external trigger, this feature must be must be set to
3054 * independent trigger.
3055 * ADC group injected automatic trigger is compliant only with
3056 * group injected trigger source set to SW start, without any
3057 * further action on ADC group injected conversion start or stop:
3058 * in this case, ADC group injected is controlled only
3059 * from ADC group regular.
3060 * @note It is not possible to enable both ADC group injected
3061 * auto-injected mode and sequencer discontinuous mode.
3062 * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto
3063 * @param ADCx ADC instance
3064 * @param TrigAuto This parameter can be one of the following values:
3065 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
3066 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
3067 * @retval None
3068 */
LL_ADC_INJ_SetTrigAuto(ADC_TypeDef * ADCx,uint32_t TrigAuto)3069 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
3070 {
3071 MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto);
3072 }
3073
3074 /**
3075 * @brief Get ADC group injected conversion trigger:
3076 * independent or from ADC group regular.
3077 * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto
3078 * @param ADCx ADC instance
3079 * @retval Returned value can be one of the following values:
3080 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
3081 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
3082 */
LL_ADC_INJ_GetTrigAuto(ADC_TypeDef * ADCx)3083 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
3084 {
3085 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO));
3086 }
3087
3088 /**
3089 * @brief Set ADC group injected offset.
3090 * @note It sets:
3091 * - ADC group injected rank to which the offset programmed
3092 * will be applied
3093 * - Offset level (offset to be subtracted from the raw
3094 * converted data).
3095 * Caution: Offset format is dependent to ADC resolution:
3096 * offset has to be left-aligned on bit 11, the LSB (right bits)
3097 * are set to 0.
3098 * @note Offset cannot be enabled or disabled.
3099 * To emulate offset disabled, set an offset value equal to 0.
3100 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n
3101 * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n
3102 * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n
3103 * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset
3104 * @param ADCx ADC instance
3105 * @param Rank This parameter can be one of the following values:
3106 * @arg @ref LL_ADC_INJ_RANK_1
3107 * @arg @ref LL_ADC_INJ_RANK_2
3108 * @arg @ref LL_ADC_INJ_RANK_3
3109 * @arg @ref LL_ADC_INJ_RANK_4
3110 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
3111 * @retval None
3112 */
LL_ADC_INJ_SetOffset(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t OffsetLevel)3113 __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
3114 {
3115 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
3116
3117 MODIFY_REG(*preg,
3118 ADC_JOFR1_JOFFSET1,
3119 OffsetLevel);
3120 }
3121
3122 /**
3123 * @brief Get ADC group injected offset.
3124 * @note It gives offset level (offset to be subtracted from the raw converted data).
3125 * Caution: Offset format is dependent to ADC resolution:
3126 * offset has to be left-aligned on bit 11, the LSB (right bits)
3127 * are set to 0.
3128 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n
3129 * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n
3130 * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n
3131 * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset
3132 * @param ADCx ADC instance
3133 * @param Rank This parameter can be one of the following values:
3134 * @arg @ref LL_ADC_INJ_RANK_1
3135 * @arg @ref LL_ADC_INJ_RANK_2
3136 * @arg @ref LL_ADC_INJ_RANK_3
3137 * @arg @ref LL_ADC_INJ_RANK_4
3138 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3139 */
LL_ADC_INJ_GetOffset(ADC_TypeDef * ADCx,uint32_t Rank)3140 __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
3141 {
3142 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
3143
3144 return (uint32_t)(READ_BIT(*preg,
3145 ADC_JOFR1_JOFFSET1)
3146 );
3147 }
3148
3149 /**
3150 * @}
3151 */
3152
3153 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
3154 * @{
3155 */
3156
3157 /**
3158 * @brief Set sampling time of the selected ADC channel
3159 * Unit: ADC clock cycles.
3160 * @note On this device, sampling time is on channel scope: independently
3161 * of channel mapped on ADC group regular or injected.
3162 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
3163 * converted:
3164 * sampling time constraints must be respected (sampling time can be
3165 * adjusted in function of ADC clock frequency and sampling time
3166 * setting).
3167 * Refer to device datasheet for timings values (parameters TS_vrefint,
3168 * TS_temp, ...).
3169 * @note Conversion time is the addition of sampling time and processing time.
3170 * Refer to reference manual for ADC processing time of
3171 * this STM32 series.
3172 * @note In case of ADC conversion of internal channel (VrefInt,
3173 * temperature sensor, ...), a sampling time minimum value
3174 * is required.
3175 * Refer to device datasheet.
3176 * @rmtoll SMPR1 SMP18 LL_ADC_SetChannelSamplingTime\n
3177 * SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n
3178 * SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n
3179 * SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n
3180 * SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n
3181 * SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n
3182 * SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n
3183 * SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n
3184 * SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n
3185 * SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n
3186 * SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n
3187 * SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n
3188 * SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n
3189 * SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n
3190 * SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n
3191 * SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n
3192 * SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n
3193 * SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n
3194 * SMPR2 SMP0 LL_ADC_SetChannelSamplingTime
3195 * @param ADCx ADC instance
3196 * @param Channel This parameter can be one of the following values:
3197 * @arg @ref LL_ADC_CHANNEL_0
3198 * @arg @ref LL_ADC_CHANNEL_1
3199 * @arg @ref LL_ADC_CHANNEL_2
3200 * @arg @ref LL_ADC_CHANNEL_3
3201 * @arg @ref LL_ADC_CHANNEL_4
3202 * @arg @ref LL_ADC_CHANNEL_5
3203 * @arg @ref LL_ADC_CHANNEL_6
3204 * @arg @ref LL_ADC_CHANNEL_7
3205 * @arg @ref LL_ADC_CHANNEL_8
3206 * @arg @ref LL_ADC_CHANNEL_9
3207 * @arg @ref LL_ADC_CHANNEL_10
3208 * @arg @ref LL_ADC_CHANNEL_11
3209 * @arg @ref LL_ADC_CHANNEL_12
3210 * @arg @ref LL_ADC_CHANNEL_13
3211 * @arg @ref LL_ADC_CHANNEL_14
3212 * @arg @ref LL_ADC_CHANNEL_15
3213 * @arg @ref LL_ADC_CHANNEL_16
3214 * @arg @ref LL_ADC_CHANNEL_17
3215 * @arg @ref LL_ADC_CHANNEL_18
3216 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3217 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
3218 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3219 *
3220 * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
3221 * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
3222 * @param SamplingTime This parameter can be one of the following values:
3223 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES
3224 * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES
3225 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES
3226 * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES
3227 * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES
3228 * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES
3229 * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES
3230 * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES
3231 * @retval None
3232 */
LL_ADC_SetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SamplingTime)3233 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
3234 {
3235 /* Set bits with content of parameter "SamplingTime" with bits position */
3236 /* in register and register position depending on parameter "Channel". */
3237 /* Parameter "Channel" is used with masks because containing */
3238 /* other bits reserved for other purpose. */
3239 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
3240
3241 MODIFY_REG(*preg,
3242 ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
3243 SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
3244 }
3245
3246 /**
3247 * @brief Get sampling time of the selected ADC channel
3248 * Unit: ADC clock cycles.
3249 * @note On this device, sampling time is on channel scope: independently
3250 * of channel mapped on ADC group regular or injected.
3251 * @note Conversion time is the addition of sampling time and processing time.
3252 * Refer to reference manual for ADC processing time of
3253 * this STM32 series.
3254 * @rmtoll SMPR1 SMP18 LL_ADC_GetChannelSamplingTime\n
3255 * SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n
3256 * SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n
3257 * SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n
3258 * SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n
3259 * SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n
3260 * SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n
3261 * SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n
3262 * SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n
3263 * SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n
3264 * SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n
3265 * SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n
3266 * SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n
3267 * SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n
3268 * SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n
3269 * SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n
3270 * SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n
3271 * SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n
3272 * SMPR2 SMP0 LL_ADC_GetChannelSamplingTime
3273 * @param ADCx ADC instance
3274 * @param Channel This parameter can be one of the following values:
3275 * @arg @ref LL_ADC_CHANNEL_0
3276 * @arg @ref LL_ADC_CHANNEL_1
3277 * @arg @ref LL_ADC_CHANNEL_2
3278 * @arg @ref LL_ADC_CHANNEL_3
3279 * @arg @ref LL_ADC_CHANNEL_4
3280 * @arg @ref LL_ADC_CHANNEL_5
3281 * @arg @ref LL_ADC_CHANNEL_6
3282 * @arg @ref LL_ADC_CHANNEL_7
3283 * @arg @ref LL_ADC_CHANNEL_8
3284 * @arg @ref LL_ADC_CHANNEL_9
3285 * @arg @ref LL_ADC_CHANNEL_10
3286 * @arg @ref LL_ADC_CHANNEL_11
3287 * @arg @ref LL_ADC_CHANNEL_12
3288 * @arg @ref LL_ADC_CHANNEL_13
3289 * @arg @ref LL_ADC_CHANNEL_14
3290 * @arg @ref LL_ADC_CHANNEL_15
3291 * @arg @ref LL_ADC_CHANNEL_16
3292 * @arg @ref LL_ADC_CHANNEL_17
3293 * @arg @ref LL_ADC_CHANNEL_18
3294 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3295 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
3296 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3297 *
3298 * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
3299 * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
3300 * @retval Returned value can be one of the following values:
3301 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES
3302 * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES
3303 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES
3304 * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES
3305 * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES
3306 * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES
3307 * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES
3308 * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES
3309 */
LL_ADC_GetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel)3310 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
3311 {
3312 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
3313
3314 return (uint32_t)(READ_BIT(*preg,
3315 ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
3316 >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
3317 );
3318 }
3319
3320 /**
3321 * @}
3322 */
3323
3324 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
3325 * @{
3326 */
3327
3328 /**
3329 * @brief Set ADC analog watchdog monitored channels:
3330 * a single channel or all channels,
3331 * on ADC groups regular and-or injected.
3332 * @note Once monitored channels are selected, analog watchdog
3333 * is enabled.
3334 * @note In case of need to define a single channel to monitor
3335 * with analog watchdog from sequencer channel definition,
3336 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
3337 * @note On this STM32 series, there is only 1 kind of analog watchdog
3338 * instance:
3339 * - AWD standard (instance AWD1):
3340 * - channels monitored: can monitor 1 channel or all channels.
3341 * - groups monitored: ADC groups regular and-or injected.
3342 * - resolution: resolution is not limited (corresponds to
3343 * ADC resolution configured).
3344 * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
3345 * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
3346 * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels
3347 * @param ADCx ADC instance
3348 * @param AWDChannelGroup This parameter can be one of the following values:
3349 * @arg @ref LL_ADC_AWD_DISABLE
3350 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
3351 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
3352 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
3353 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
3354 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
3355 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
3356 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
3357 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
3358 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
3359 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
3360 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
3361 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
3362 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
3363 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
3364 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
3365 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
3366 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
3367 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
3368 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
3369 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
3370 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
3371 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
3372 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
3373 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
3374 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
3375 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
3376 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
3377 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
3378 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
3379 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
3380 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
3381 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
3382 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
3383 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
3384 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
3385 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
3386 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
3387 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
3388 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
3389 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
3390 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
3391 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
3392 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
3393 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
3394 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
3395 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
3396 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
3397 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
3398 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
3399 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
3400 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
3401 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
3402 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
3403 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
3404 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
3405 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
3406 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
3407 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
3408 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
3409 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
3410 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
3411 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
3412 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
3413 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2)
3414 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2)
3415 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2)
3416 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
3417 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1)
3418 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
3419 *
3420 * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
3421 * (2) On devices STM32F7xx,a limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
3422 * @retval None
3423 */
LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDChannelGroup)3424 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
3425 {
3426 MODIFY_REG(ADCx->CR1,
3427 (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH),
3428 AWDChannelGroup);
3429 }
3430
3431 /**
3432 * @brief Get ADC analog watchdog monitored channel.
3433 * @note Usage of the returned channel number:
3434 * - To reinject this channel into another function LL_ADC_xxx:
3435 * the returned channel number is only partly formatted on definition
3436 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3437 * with parts of literals LL_ADC_CHANNEL_x or using
3438 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3439 * Then the selected literal LL_ADC_CHANNEL_x can be used
3440 * as parameter for another function.
3441 * - To get the channel number in decimal format:
3442 * process the returned value with the helper macro
3443 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3444 * Applicable only when the analog watchdog is set to monitor
3445 * one channel.
3446 * @note On this STM32 series, there is only 1 kind of analog watchdog
3447 * instance:
3448 * - AWD standard (instance AWD1):
3449 * - channels monitored: can monitor 1 channel or all channels.
3450 * - groups monitored: ADC groups regular and-or injected.
3451 * - resolution: resolution is not limited (corresponds to
3452 * ADC resolution configured).
3453 * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
3454 * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
3455 * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels
3456 * @param ADCx ADC instance
3457 * @retval Returned value can be one of the following values:
3458 * @arg @ref LL_ADC_AWD_DISABLE
3459 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
3460 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
3461 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
3462 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
3463 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
3464 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
3465 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
3466 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
3467 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
3468 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
3469 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
3470 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
3471 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
3472 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
3473 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
3474 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
3475 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
3476 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
3477 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
3478 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
3479 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
3480 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
3481 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
3482 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
3483 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
3484 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
3485 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
3486 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
3487 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
3488 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
3489 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
3490 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
3491 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
3492 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
3493 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
3494 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
3495 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
3496 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
3497 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
3498 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
3499 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
3500 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
3501 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
3502 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
3503 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
3504 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
3505 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
3506 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
3507 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
3508 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
3509 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
3510 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
3511 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
3512 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
3513 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
3514 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
3515 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
3516 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
3517 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
3518 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
3519 */
LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef * ADCx)3520 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
3521 {
3522 return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH)));
3523 }
3524
3525 /**
3526 * @brief Set ADC analog watchdog threshold value of threshold
3527 * high or low.
3528 * @note In case of ADC resolution different of 12 bits,
3529 * analog watchdog thresholds data require a specific shift.
3530 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
3531 * @note On this STM32 series, there is only 1 kind of analog watchdog
3532 * instance:
3533 * - AWD standard (instance AWD1):
3534 * - channels monitored: can monitor 1 channel or all channels.
3535 * - groups monitored: ADC groups regular and-or injected.
3536 * - resolution: resolution is not limited (corresponds to
3537 * ADC resolution configured).
3538 * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n
3539 * LTR LT LL_ADC_SetAnalogWDThresholds
3540 * @param ADCx ADC instance
3541 * @param AWDThresholdsHighLow This parameter can be one of the following values:
3542 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
3543 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
3544 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
3545 * @retval None
3546 */
LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)3547 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
3548 {
3549 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
3550
3551 MODIFY_REG(*preg,
3552 ADC_HTR_HT,
3553 AWDThresholdValue);
3554 }
3555
3556 /**
3557 * @brief Get ADC analog watchdog threshold value of threshold high or
3558 * threshold low.
3559 * @note In case of ADC resolution different of 12 bits,
3560 * analog watchdog thresholds data require a specific shift.
3561 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
3562 * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n
3563 * LTR LT LL_ADC_GetAnalogWDThresholds
3564 * @param ADCx ADC instance
3565 * @param AWDThresholdsHighLow This parameter can be one of the following values:
3566 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
3567 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
3568 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3569 */
LL_ADC_GetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDThresholdsHighLow)3570 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
3571 {
3572 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
3573
3574 return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
3575 }
3576
3577 /**
3578 * @}
3579 */
3580
3581 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
3582 * @{
3583 */
3584
3585 /**
3586 * @brief Set ADC multimode configuration to operate in independent mode
3587 * or multimode (for devices with several ADC instances).
3588 * @note If multimode configuration: the selected ADC instance is
3589 * either master or slave depending on hardware.
3590 * Refer to reference manual.
3591 * @rmtoll CCR MULTI LL_ADC_SetMultimode
3592 * @param ADCxy_COMMON ADC common instance
3593 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3594 * @param Multimode This parameter can be one of the following values:
3595 * @arg @ref LL_ADC_MULTI_INDEPENDENT
3596 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
3597 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
3598 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
3599 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
3600 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
3601 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
3602 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
3603 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM
3604 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT
3605 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT
3606 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT
3607 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL
3608 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN
3609 * @retval None
3610 */
LL_ADC_SetMultimode(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t Multimode)3611 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
3612 {
3613 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MULTI, Multimode);
3614 }
3615
3616 /**
3617 * @brief Get ADC multimode configuration to operate in independent mode
3618 * or multimode (for devices with several ADC instances).
3619 * @note If multimode configuration: the selected ADC instance is
3620 * either master or slave depending on hardware.
3621 * Refer to reference manual.
3622 * @rmtoll CCR MULTI LL_ADC_GetMultimode
3623 * @param ADCxy_COMMON ADC common instance
3624 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3625 * @retval Returned value can be one of the following values:
3626 * @arg @ref LL_ADC_MULTI_INDEPENDENT
3627 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
3628 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
3629 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
3630 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
3631 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
3632 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
3633 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
3634 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM
3635 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT
3636 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT
3637 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT
3638 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL
3639 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN
3640 */
LL_ADC_GetMultimode(ADC_Common_TypeDef * ADCxy_COMMON)3641 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
3642 {
3643 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MULTI));
3644 }
3645
3646 /**
3647 * @brief Set ADC multimode conversion data transfer: no transfer
3648 * or transfer by DMA.
3649 * @note If ADC multimode transfer by DMA is not selected:
3650 * each ADC uses its own DMA channel, with its individual
3651 * DMA transfer settings.
3652 * If ADC multimode transfer by DMA is selected:
3653 * One DMA channel is used for both ADC (DMA of ADC master)
3654 * Specifies the DMA requests mode:
3655 * - Limited mode (One shot mode): DMA transfer requests are stopped
3656 * when number of DMA data transfers (number of
3657 * ADC conversions) is reached.
3658 * This ADC mode is intended to be used with DMA mode non-circular.
3659 * - Unlimited mode: DMA transfer requests are unlimited,
3660 * whatever number of DMA data transfers (number of
3661 * ADC conversions).
3662 * This ADC mode is intended to be used with DMA mode circular.
3663 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3664 * mode non-circular:
3665 * when DMA transfers size will be reached, DMA will stop transfers of
3666 * ADC conversions data ADC will raise an overrun error
3667 * (overrun flag and interruption if enabled).
3668 * @note How to retrieve multimode conversion data:
3669 * Whatever multimode transfer by DMA setting: using function
3670 * @ref LL_ADC_REG_ReadMultiConversionData32().
3671 * If ADC multimode transfer by DMA is selected: conversion data
3672 * is a raw data with ADC master and slave concatenated.
3673 * A macro is available to get the conversion data of
3674 * ADC master or ADC slave: see helper macro
3675 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
3676 * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n
3677 * CCR DDS LL_ADC_SetMultiDMATransfer
3678 * @param ADCxy_COMMON ADC common instance
3679 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3680 * @param MultiDMATransfer This parameter can be one of the following values:
3681 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
3682 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1
3683 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2
3684 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3
3685 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1
3686 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2
3687 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3
3688 * @retval None
3689 */
LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiDMATransfer)3690 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
3691 {
3692 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS, MultiDMATransfer);
3693 }
3694
3695 /**
3696 * @brief Get ADC multimode conversion data transfer: no transfer
3697 * or transfer by DMA.
3698 * @note If ADC multimode transfer by DMA is not selected:
3699 * each ADC uses its own DMA channel, with its individual
3700 * DMA transfer settings.
3701 * If ADC multimode transfer by DMA is selected:
3702 * One DMA channel is used for both ADC (DMA of ADC master)
3703 * Specifies the DMA requests mode:
3704 * - Limited mode (One shot mode): DMA transfer requests are stopped
3705 * when number of DMA data transfers (number of
3706 * ADC conversions) is reached.
3707 * This ADC mode is intended to be used with DMA mode non-circular.
3708 * - Unlimited mode: DMA transfer requests are unlimited,
3709 * whatever number of DMA data transfers (number of
3710 * ADC conversions).
3711 * This ADC mode is intended to be used with DMA mode circular.
3712 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3713 * mode non-circular:
3714 * when DMA transfers size will be reached, DMA will stop transfers of
3715 * ADC conversions data ADC will raise an overrun error
3716 * (overrun flag and interruption if enabled).
3717 * @note How to retrieve multimode conversion data:
3718 * Whatever multimode transfer by DMA setting: using function
3719 * @ref LL_ADC_REG_ReadMultiConversionData32().
3720 * If ADC multimode transfer by DMA is selected: conversion data
3721 * is a raw data with ADC master and slave concatenated.
3722 * A macro is available to get the conversion data of
3723 * ADC master or ADC slave: see helper macro
3724 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
3725 * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n
3726 * CCR DDS LL_ADC_GetMultiDMATransfer
3727 * @param ADCxy_COMMON ADC common instance
3728 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3729 * @retval Returned value can be one of the following values:
3730 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
3731 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1
3732 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2
3733 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3
3734 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1
3735 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2
3736 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3
3737 */
LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef * ADCxy_COMMON)3738 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
3739 {
3740 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS));
3741 }
3742
3743 /**
3744 * @brief Set ADC multimode delay between 2 sampling phases.
3745 * @note The sampling delay range depends on ADC resolution:
3746 * - ADC resolution 12 bits can have maximum delay of 12 cycles.
3747 * - ADC resolution 10 bits can have maximum delay of 10 cycles.
3748 * - ADC resolution 8 bits can have maximum delay of 8 cycles.
3749 * - ADC resolution 6 bits can have maximum delay of 6 cycles.
3750 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
3751 * @param ADCxy_COMMON ADC common instance
3752 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3753 * @param MultiTwoSamplingDelay This parameter can be one of the following values:
3754 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
3755 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
3756 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
3757 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
3758 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
3759 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
3760 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
3761 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
3762 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
3763 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES
3764 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES
3765 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES
3766 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES
3767 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES
3768 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES
3769 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES
3770 * @retval None
3771 */
LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiTwoSamplingDelay)3772 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
3773 {
3774 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
3775 }
3776
3777 /**
3778 * @brief Get ADC multimode delay between 2 sampling phases.
3779 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
3780 * @param ADCxy_COMMON ADC common instance
3781 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3782 * @retval Returned value can be one of the following values:
3783 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
3784 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
3785 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
3786 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
3787 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
3788 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
3789 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
3790 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
3791 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
3792 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES
3793 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES
3794 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES
3795 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES
3796 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES
3797 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES
3798 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES
3799 */
LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON)3800 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
3801 {
3802 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
3803 }
3804
3805 /**
3806 * @}
3807 */
3808 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
3809 * @{
3810 */
3811
3812 /**
3813 * @brief Enable the selected ADC instance.
3814 * @note On this STM32 series, after ADC enable, a delay for
3815 * ADC internal analog stabilization is required before performing a
3816 * ADC conversion start.
3817 * Refer to device datasheet, parameter tSTAB.
3818 * @rmtoll CR2 ADON LL_ADC_Enable
3819 * @param ADCx ADC instance
3820 * @retval None
3821 */
LL_ADC_Enable(ADC_TypeDef * ADCx)3822 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
3823 {
3824 SET_BIT(ADCx->CR2, ADC_CR2_ADON);
3825 }
3826
3827 /**
3828 * @brief Disable the selected ADC instance.
3829 * @rmtoll CR2 ADON LL_ADC_Disable
3830 * @param ADCx ADC instance
3831 * @retval None
3832 */
LL_ADC_Disable(ADC_TypeDef * ADCx)3833 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
3834 {
3835 CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON);
3836 }
3837
3838 /**
3839 * @brief Get the selected ADC instance enable state.
3840 * @rmtoll CR2 ADON LL_ADC_IsEnabled
3841 * @param ADCx ADC instance
3842 * @retval 0: ADC is disabled, 1: ADC is enabled.
3843 */
LL_ADC_IsEnabled(ADC_TypeDef * ADCx)3844 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
3845 {
3846 return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON));
3847 }
3848
3849 /**
3850 * @}
3851 */
3852
3853 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
3854 * @{
3855 */
3856
3857 /**
3858 * @brief Start ADC group regular conversion.
3859 * @note On this STM32 series, this function is relevant only for
3860 * internal trigger (SW start), not for external trigger:
3861 * - If ADC trigger has been set to software start, ADC conversion
3862 * starts immediately.
3863 * - If ADC trigger has been set to external trigger, ADC conversion
3864 * start must be performed using function
3865 * @ref LL_ADC_REG_StartConversionExtTrig().
3866 * (if external trigger edge would have been set during ADC other
3867 * settings, ADC conversion would start at trigger event
3868 * as soon as ADC is enabled).
3869 * @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart
3870 * @param ADCx ADC instance
3871 * @retval None
3872 */
LL_ADC_REG_StartConversionSWStart(ADC_TypeDef * ADCx)3873 __STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx)
3874 {
3875 SET_BIT(ADCx->CR2, ADC_CR2_SWSTART);
3876 }
3877
3878 /**
3879 * @brief Start ADC group regular conversion from external trigger.
3880 * @note ADC conversion will start at next trigger event (on the selected
3881 * trigger edge) following the ADC start conversion command.
3882 * @note On this STM32 series, this function is relevant for
3883 * ADC conversion start from external trigger.
3884 * If internal trigger (SW start) is needed, perform ADC conversion
3885 * start using function @ref LL_ADC_REG_StartConversionSWStart().
3886 * @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig
3887 * @param ExternalTriggerEdge This parameter can be one of the following values:
3888 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3889 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3890 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3891 * @param ADCx ADC instance
3892 * @retval None
3893 */
LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)3894 __STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3895 {
3896 SET_BIT(ADCx->CR2, ExternalTriggerEdge);
3897 }
3898
3899 /**
3900 * @brief Stop ADC group regular conversion from external trigger.
3901 * @note No more ADC conversion will start at next trigger event
3902 * following the ADC stop conversion command.
3903 * If a conversion is on-going, it will be completed.
3904 * @note On this STM32 series, there is no specific command
3905 * to stop a conversion on-going or to stop ADC converting
3906 * in continuous mode. These actions can be performed
3907 * using function @ref LL_ADC_Disable().
3908 * @rmtoll CR2 EXTEN LL_ADC_REG_StopConversionExtTrig
3909 * @param ADCx ADC instance
3910 * @retval None
3911 */
LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef * ADCx)3912 __STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)
3913 {
3914 CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTEN);
3915 }
3916
3917 /**
3918 * @brief Get ADC group regular conversion data, range fit for
3919 * all ADC configurations: all ADC resolutions and
3920 * all oversampling increased data width (for devices
3921 * with feature oversampling).
3922 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
3923 * @param ADCx ADC instance
3924 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
3925 */
LL_ADC_REG_ReadConversionData32(ADC_TypeDef * ADCx)3926 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
3927 {
3928 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3929 }
3930
3931 /**
3932 * @brief Get ADC group regular conversion data, range fit for
3933 * ADC resolution 12 bits.
3934 * @note For devices with feature oversampling: Oversampling
3935 * can increase data width, function for extended range
3936 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
3937 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
3938 * @param ADCx ADC instance
3939 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3940 */
LL_ADC_REG_ReadConversionData12(ADC_TypeDef * ADCx)3941 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
3942 {
3943 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3944 }
3945
3946 /**
3947 * @brief Get ADC group regular conversion data, range fit for
3948 * ADC resolution 10 bits.
3949 * @note For devices with feature oversampling: Oversampling
3950 * can increase data width, function for extended range
3951 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
3952 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
3953 * @param ADCx ADC instance
3954 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
3955 */
LL_ADC_REG_ReadConversionData10(ADC_TypeDef * ADCx)3956 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
3957 {
3958 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3959 }
3960
3961 /**
3962 * @brief Get ADC group regular conversion data, range fit for
3963 * ADC resolution 8 bits.
3964 * @note For devices with feature oversampling: Oversampling
3965 * can increase data width, function for extended range
3966 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
3967 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
3968 * @param ADCx ADC instance
3969 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
3970 */
LL_ADC_REG_ReadConversionData8(ADC_TypeDef * ADCx)3971 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
3972 {
3973 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3974 }
3975
3976 /**
3977 * @brief Get ADC group regular conversion data, range fit for
3978 * ADC resolution 6 bits.
3979 * @note For devices with feature oversampling: Oversampling
3980 * can increase data width, function for extended range
3981 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
3982 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
3983 * @param ADCx ADC instance
3984 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
3985 */
LL_ADC_REG_ReadConversionData6(ADC_TypeDef * ADCx)3986 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
3987 {
3988 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3989 }
3990
3991 /**
3992 * @brief Get ADC multimode conversion data of ADC master, ADC slave
3993 * or raw data with ADC master and slave concatenated.
3994 * @note If raw data with ADC master and slave concatenated is retrieved,
3995 * a macro is available to get the conversion data of
3996 * ADC master or ADC slave: see helper macro
3997 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
3998 * (however this macro is mainly intended for multimode
3999 * transfer by DMA, because this function can do the same
4000 * by getting multimode conversion data of ADC master or ADC slave
4001 * separately).
4002 * @rmtoll CDR DATA1 LL_ADC_REG_ReadMultiConversionData32\n
4003 * CDR DATA2 LL_ADC_REG_ReadMultiConversionData32
4004 * @param ADCxy_COMMON ADC common instance
4005 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4006 * @param ConversionData This parameter can be one of the following values:
4007 * @arg @ref LL_ADC_MULTI_MASTER
4008 * @arg @ref LL_ADC_MULTI_SLAVE
4009 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
4010 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
4011 */
LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t ConversionData)4012 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
4013 {
4014 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
4015 ADC_DR_ADC2DATA)
4016 >> POSITION_VAL(ConversionData)
4017 );
4018 }
4019
4020 /**
4021 * @}
4022 */
4023
4024 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
4025 * @{
4026 */
4027
4028 /**
4029 * @brief Start ADC group injected conversion.
4030 * @note On this STM32 series, this function is relevant only for
4031 * internal trigger (SW start), not for external trigger:
4032 * - If ADC trigger has been set to software start, ADC conversion
4033 * starts immediately.
4034 * - If ADC trigger has been set to external trigger, ADC conversion
4035 * start must be performed using function
4036 * @ref LL_ADC_INJ_StartConversionExtTrig().
4037 * (if external trigger edge would have been set during ADC other
4038 * settings, ADC conversion would start at trigger event
4039 * as soon as ADC is enabled).
4040 * @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart
4041 * @param ADCx ADC instance
4042 * @retval None
4043 */
LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef * ADCx)4044 __STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx)
4045 {
4046 SET_BIT(ADCx->CR2, ADC_CR2_JSWSTART);
4047 }
4048
4049 /**
4050 * @brief Start ADC group injected conversion from external trigger.
4051 * @note ADC conversion will start at next trigger event (on the selected
4052 * trigger edge) following the ADC start conversion command.
4053 * @note On this STM32 series, this function is relevant for
4054 * ADC conversion start from external trigger.
4055 * If internal trigger (SW start) is needed, perform ADC conversion
4056 * start using function @ref LL_ADC_INJ_StartConversionSWStart().
4057 * @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig
4058 * @param ExternalTriggerEdge This parameter can be one of the following values:
4059 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4060 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4061 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4062 * @param ADCx ADC instance
4063 * @retval None
4064 */
LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)4065 __STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4066 {
4067 SET_BIT(ADCx->CR2, ExternalTriggerEdge);
4068 }
4069
4070 /**
4071 * @brief Stop ADC group injected conversion from external trigger.
4072 * @note No more ADC conversion will start at next trigger event
4073 * following the ADC stop conversion command.
4074 * If a conversion is on-going, it will be completed.
4075 * @note On this STM32 series, there is no specific command
4076 * to stop a conversion on-going or to stop ADC converting
4077 * in continuous mode. These actions can be performed
4078 * using function @ref LL_ADC_Disable().
4079 * @rmtoll CR2 JEXTEN LL_ADC_INJ_StopConversionExtTrig
4080 * @param ADCx ADC instance
4081 * @retval None
4082 */
LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef * ADCx)4083 __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
4084 {
4085 CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTEN);
4086 }
4087
4088 /**
4089 * @brief Get ADC group regular conversion data, range fit for
4090 * all ADC configurations: all ADC resolutions and
4091 * all oversampling increased data width (for devices
4092 * with feature oversampling).
4093 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
4094 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
4095 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
4096 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
4097 * @param ADCx ADC instance
4098 * @param Rank This parameter can be one of the following values:
4099 * @arg @ref LL_ADC_INJ_RANK_1
4100 * @arg @ref LL_ADC_INJ_RANK_2
4101 * @arg @ref LL_ADC_INJ_RANK_3
4102 * @arg @ref LL_ADC_INJ_RANK_4
4103 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
4104 */
LL_ADC_INJ_ReadConversionData32(ADC_TypeDef * ADCx,uint32_t Rank)4105 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
4106 {
4107 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4108
4109 return (uint32_t)(READ_BIT(*preg,
4110 ADC_JDR1_JDATA)
4111 );
4112 }
4113
4114 /**
4115 * @brief Get ADC group injected conversion data, range fit for
4116 * ADC resolution 12 bits.
4117 * @note For devices with feature oversampling: Oversampling
4118 * can increase data width, function for extended range
4119 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4120 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
4121 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
4122 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
4123 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
4124 * @param ADCx ADC instance
4125 * @param Rank This parameter can be one of the following values:
4126 * @arg @ref LL_ADC_INJ_RANK_1
4127 * @arg @ref LL_ADC_INJ_RANK_2
4128 * @arg @ref LL_ADC_INJ_RANK_3
4129 * @arg @ref LL_ADC_INJ_RANK_4
4130 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
4131 */
LL_ADC_INJ_ReadConversionData12(ADC_TypeDef * ADCx,uint32_t Rank)4132 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
4133 {
4134 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4135
4136 return (uint16_t)(READ_BIT(*preg,
4137 ADC_JDR1_JDATA)
4138 );
4139 }
4140
4141 /**
4142 * @brief Get ADC group injected conversion data, range fit for
4143 * ADC resolution 10 bits.
4144 * @note For devices with feature oversampling: Oversampling
4145 * can increase data width, function for extended range
4146 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4147 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
4148 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
4149 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
4150 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
4151 * @param ADCx ADC instance
4152 * @param Rank This parameter can be one of the following values:
4153 * @arg @ref LL_ADC_INJ_RANK_1
4154 * @arg @ref LL_ADC_INJ_RANK_2
4155 * @arg @ref LL_ADC_INJ_RANK_3
4156 * @arg @ref LL_ADC_INJ_RANK_4
4157 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
4158 */
LL_ADC_INJ_ReadConversionData10(ADC_TypeDef * ADCx,uint32_t Rank)4159 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
4160 {
4161 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4162
4163 return (uint16_t)(READ_BIT(*preg,
4164 ADC_JDR1_JDATA)
4165 );
4166 }
4167
4168 /**
4169 * @brief Get ADC group injected conversion data, range fit for
4170 * ADC resolution 8 bits.
4171 * @note For devices with feature oversampling: Oversampling
4172 * can increase data width, function for extended range
4173 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4174 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
4175 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
4176 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
4177 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
4178 * @param ADCx ADC instance
4179 * @param Rank This parameter can be one of the following values:
4180 * @arg @ref LL_ADC_INJ_RANK_1
4181 * @arg @ref LL_ADC_INJ_RANK_2
4182 * @arg @ref LL_ADC_INJ_RANK_3
4183 * @arg @ref LL_ADC_INJ_RANK_4
4184 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
4185 */
LL_ADC_INJ_ReadConversionData8(ADC_TypeDef * ADCx,uint32_t Rank)4186 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
4187 {
4188 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4189
4190 return (uint8_t)(READ_BIT(*preg,
4191 ADC_JDR1_JDATA)
4192 );
4193 }
4194
4195 /**
4196 * @brief Get ADC group injected conversion data, range fit for
4197 * ADC resolution 6 bits.
4198 * @note For devices with feature oversampling: Oversampling
4199 * can increase data width, function for extended range
4200 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4201 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
4202 * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
4203 * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
4204 * JDR4 JDATA LL_ADC_INJ_ReadConversionData6
4205 * @param ADCx ADC instance
4206 * @param Rank This parameter can be one of the following values:
4207 * @arg @ref LL_ADC_INJ_RANK_1
4208 * @arg @ref LL_ADC_INJ_RANK_2
4209 * @arg @ref LL_ADC_INJ_RANK_3
4210 * @arg @ref LL_ADC_INJ_RANK_4
4211 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
4212 */
LL_ADC_INJ_ReadConversionData6(ADC_TypeDef * ADCx,uint32_t Rank)4213 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
4214 {
4215 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4216
4217 return (uint8_t)(READ_BIT(*preg,
4218 ADC_JDR1_JDATA)
4219 );
4220 }
4221
4222 /**
4223 * @}
4224 */
4225
4226 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
4227 * @{
4228 */
4229
4230 /**
4231 * @brief Get flag ADC group regular end of unitary conversion
4232 * or end of sequence conversions, depending on
4233 * ADC configuration.
4234 * @note To configure flag of end of conversion,
4235 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4236 * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOCS
4237 * @param ADCx ADC instance
4238 * @retval State of bit (1 or 0).
4239 */
LL_ADC_IsActiveFlag_EOCS(ADC_TypeDef * ADCx)4240 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCS(ADC_TypeDef *ADCx)
4241 {
4242 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS));
4243 }
4244
4245 /**
4246 * @brief Get flag ADC group regular overrun.
4247 * @rmtoll SR OVR LL_ADC_IsActiveFlag_OVR
4248 * @param ADCx ADC instance
4249 * @retval State of bit (1 or 0).
4250 */
LL_ADC_IsActiveFlag_OVR(ADC_TypeDef * ADCx)4251 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
4252 {
4253 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
4254 }
4255
4256
4257 /**
4258 * @brief Get flag ADC group injected end of sequence conversions.
4259 * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS
4260 * @param ADCx ADC instance
4261 * @retval State of bit (1 or 0).
4262 */
LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef * ADCx)4263 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
4264 {
4265 /* Note: on this STM32 series, there is no flag ADC group injected */
4266 /* end of unitary conversion. */
4267 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4268 /* in other STM32 families). */
4269 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
4270 }
4271
4272 /**
4273 * @brief Get flag ADC analog watchdog 1 flag
4274 * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1
4275 * @param ADCx ADC instance
4276 * @retval State of bit (1 or 0).
4277 */
LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef * ADCx)4278 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
4279 {
4280 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
4281 }
4282
4283 /**
4284 * @brief Clear flag ADC group regular end of unitary conversion
4285 * or end of sequence conversions, depending on
4286 * ADC configuration.
4287 * @note To configure flag of end of conversion,
4288 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4289 * @rmtoll SR EOC LL_ADC_ClearFlag_EOCS
4290 * @param ADCx ADC instance
4291 * @retval None
4292 */
LL_ADC_ClearFlag_EOCS(ADC_TypeDef * ADCx)4293 __STATIC_INLINE void LL_ADC_ClearFlag_EOCS(ADC_TypeDef *ADCx)
4294 {
4295 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOCS);
4296 }
4297
4298 /**
4299 * @brief Clear flag ADC group regular overrun.
4300 * @rmtoll SR OVR LL_ADC_ClearFlag_OVR
4301 * @param ADCx ADC instance
4302 * @retval None
4303 */
LL_ADC_ClearFlag_OVR(ADC_TypeDef * ADCx)4304 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
4305 {
4306 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_OVR);
4307 }
4308
4309
4310 /**
4311 * @brief Clear flag ADC group injected end of sequence conversions.
4312 * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS
4313 * @param ADCx ADC instance
4314 * @retval None
4315 */
LL_ADC_ClearFlag_JEOS(ADC_TypeDef * ADCx)4316 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
4317 {
4318 /* Note: on this STM32 series, there is no flag ADC group injected */
4319 /* end of unitary conversion. */
4320 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4321 /* in other STM32 families). */
4322 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS);
4323 }
4324
4325 /**
4326 * @brief Clear flag ADC analog watchdog 1.
4327 * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1
4328 * @param ADCx ADC instance
4329 * @retval None
4330 */
LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)4331 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
4332 {
4333 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1);
4334 }
4335
4336 /**
4337 * @brief Get flag multimode ADC group regular end of unitary conversion
4338 * or end of sequence conversions, depending on
4339 * ADC configuration, of the ADC master.
4340 * @note To configure flag of end of conversion,
4341 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4342 * @rmtoll CSR EOC1 LL_ADC_IsActiveFlag_MST_EOCS
4343 * @param ADCxy_COMMON ADC common instance
4344 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4345 * @retval State of bit (1 or 0).
4346 */
LL_ADC_IsActiveFlag_MST_EOCS(ADC_Common_TypeDef * ADCxy_COMMON)4347 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
4348 {
4349 return (READ_BIT(ADC1->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS));
4350 }
4351
4352 /**
4353 * @brief Get flag multimode ADC group regular end of unitary conversion
4354 * or end of sequence conversions, depending on
4355 * ADC configuration, of the ADC slave 1.
4356 * @note To configure flag of end of conversion,
4357 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4358 * @rmtoll CSR EOC2 LL_ADC_IsActiveFlag_SLV1_EOCS
4359 * @param ADCxy_COMMON ADC common instance
4360 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4361 * @retval State of bit (1 or 0).
4362 */
LL_ADC_IsActiveFlag_SLV1_EOCS(ADC_Common_TypeDef * ADCxy_COMMON)4363 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
4364 {
4365 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV1) == (LL_ADC_FLAG_EOCS_SLV1));
4366 }
4367
4368 /**
4369 * @brief Get flag multimode ADC group regular end of unitary conversion
4370 * or end of sequence conversions, depending on
4371 * ADC configuration, of the ADC slave 2.
4372 * @note To configure flag of end of conversion,
4373 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4374 * @rmtoll CSR EOC3 LL_ADC_IsActiveFlag_SLV2_EOCS
4375 * @param ADCxy_COMMON ADC common instance
4376 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4377 * @retval State of bit (1 or 0).
4378 */
LL_ADC_IsActiveFlag_SLV2_EOCS(ADC_Common_TypeDef * ADCxy_COMMON)4379 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
4380 {
4381 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV2) == (LL_ADC_FLAG_EOCS_SLV2));
4382 }
4383 /**
4384 * @brief Get flag multimode ADC group regular overrun of the ADC master.
4385 * @rmtoll CSR OVR1 LL_ADC_IsActiveFlag_MST_OVR
4386 * @param ADCxy_COMMON ADC common instance
4387 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4388 * @retval State of bit (1 or 0).
4389 */
LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef * ADCxy_COMMON)4390 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
4391 {
4392 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST));
4393 }
4394
4395 /**
4396 * @brief Get flag multimode ADC group regular overrun of the ADC slave 1.
4397 * @rmtoll CSR OVR2 LL_ADC_IsActiveFlag_SLV1_OVR
4398 * @param ADCxy_COMMON ADC common instance
4399 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4400 * @retval State of bit (1 or 0).
4401 */
LL_ADC_IsActiveFlag_SLV1_OVR(ADC_Common_TypeDef * ADCxy_COMMON)4402 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
4403 {
4404 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV1) == (LL_ADC_FLAG_OVR_SLV1));
4405 }
4406
4407 /**
4408 * @brief Get flag multimode ADC group regular overrun of the ADC slave 2.
4409 * @rmtoll CSR OVR3 LL_ADC_IsActiveFlag_SLV2_OVR
4410 * @param ADCxy_COMMON ADC common instance
4411 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4412 * @retval State of bit (1 or 0).
4413 */
LL_ADC_IsActiveFlag_SLV2_OVR(ADC_Common_TypeDef * ADCxy_COMMON)4414 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
4415 {
4416 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV2) == (LL_ADC_FLAG_OVR_SLV2));
4417 }
4418
4419
4420 /**
4421 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
4422 * @rmtoll CSR JEOC LL_ADC_IsActiveFlag_MST_EOCS
4423 * @param ADCxy_COMMON ADC common instance
4424 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4425 * @retval State of bit (1 or 0).
4426 */
LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef * ADCxy_COMMON)4427 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
4428 {
4429 /* Note: on this STM32 series, there is no flag ADC group injected */
4430 /* end of unitary conversion. */
4431 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4432 /* in other STM32 families). */
4433 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC1) == (ADC_CSR_JEOC1));
4434 }
4435
4436 /**
4437 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 1.
4438 * @rmtoll CSR JEOC2 LL_ADC_IsActiveFlag_SLV1_JEOS
4439 * @param ADCxy_COMMON ADC common instance
4440 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4441 * @retval State of bit (1 or 0).
4442 */
LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef * ADCxy_COMMON)4443 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
4444 {
4445 /* Note: on this STM32 series, there is no flag ADC group injected */
4446 /* end of unitary conversion. */
4447 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4448 /* in other STM32 families). */
4449 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC2) == (ADC_CSR_JEOC2));
4450 }
4451
4452 /**
4453 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 2.
4454 * @rmtoll CSR JEOC3 LL_ADC_IsActiveFlag_SLV2_JEOS
4455 * @param ADCxy_COMMON ADC common instance
4456 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4457 * @retval State of bit (1 or 0).
4458 */
LL_ADC_IsActiveFlag_SLV2_JEOS(ADC_Common_TypeDef * ADCxy_COMMON)4459 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
4460 {
4461 /* Note: on this STM32 series, there is no flag ADC group injected */
4462 /* end of unitary conversion. */
4463 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4464 /* in other STM32 families). */
4465 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC3) == (ADC_CSR_JEOC3));
4466 }
4467
4468 /**
4469 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
4470 * @rmtoll CSR AWD1 LL_ADC_IsActiveFlag_MST_AWD1
4471 * @param ADCxy_COMMON ADC common instance
4472 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4473 * @retval State of bit (1 or 0).
4474 */
LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef * ADCxy_COMMON)4475 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
4476 {
4477 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST));
4478 }
4479
4480 /**
4481 * @brief Get flag multimode analog watchdog 1 of the ADC slave 1.
4482 * @rmtoll CSR AWD2 LL_ADC_IsActiveFlag_SLV1_AWD1
4483 * @param ADCxy_COMMON ADC common instance
4484 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4485 * @retval State of bit (1 or 0).
4486 */
LL_ADC_IsActiveFlag_SLV1_AWD1(ADC_Common_TypeDef * ADCxy_COMMON)4487 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
4488 {
4489 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV1) == (LL_ADC_FLAG_AWD1_SLV1));
4490 }
4491
4492 /**
4493 * @brief Get flag multimode analog watchdog 1 of the ADC slave 2.
4494 * @rmtoll CSR AWD3 LL_ADC_IsActiveFlag_SLV2_AWD1
4495 * @param ADCxy_COMMON ADC common instance
4496 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4497 * @retval State of bit (1 or 0).
4498 */
LL_ADC_IsActiveFlag_SLV2_AWD1(ADC_Common_TypeDef * ADCxy_COMMON)4499 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
4500 {
4501 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV2) == (LL_ADC_FLAG_AWD1_SLV2));
4502 }
4503
4504
4505 /**
4506 * @}
4507 */
4508
4509 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
4510 * @{
4511 */
4512
4513 /**
4514 * @brief Enable interruption ADC group regular end of unitary conversion
4515 * or end of sequence conversions, depending on
4516 * ADC configuration.
4517 * @note To configure flag of end of conversion,
4518 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4519 * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOCS
4520 * @param ADCx ADC instance
4521 * @retval None
4522 */
LL_ADC_EnableIT_EOCS(ADC_TypeDef * ADCx)4523 __STATIC_INLINE void LL_ADC_EnableIT_EOCS(ADC_TypeDef *ADCx)
4524 {
4525 SET_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
4526 }
4527
4528 /**
4529 * @brief Enable ADC group regular interruption overrun.
4530 * @rmtoll CR1 OVRIE LL_ADC_EnableIT_OVR
4531 * @param ADCx ADC instance
4532 * @retval None
4533 */
LL_ADC_EnableIT_OVR(ADC_TypeDef * ADCx)4534 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
4535 {
4536 SET_BIT(ADCx->CR1, LL_ADC_IT_OVR);
4537 }
4538
4539
4540 /**
4541 * @brief Enable interruption ADC group injected end of sequence conversions.
4542 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
4543 * @param ADCx ADC instance
4544 * @retval None
4545 */
LL_ADC_EnableIT_JEOS(ADC_TypeDef * ADCx)4546 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
4547 {
4548 /* Note: on this STM32 series, there is no flag ADC group injected */
4549 /* end of unitary conversion. */
4550 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4551 /* in other STM32 families). */
4552 SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
4553 }
4554
4555 /**
4556 * @brief Enable interruption ADC analog watchdog 1.
4557 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
4558 * @param ADCx ADC instance
4559 * @retval None
4560 */
LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)4561 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
4562 {
4563 SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
4564 }
4565
4566 /**
4567 * @brief Disable interruption ADC group regular end of unitary conversion
4568 * or end of sequence conversions, depending on
4569 * ADC configuration.
4570 * @note To configure flag of end of conversion,
4571 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4572 * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOCS
4573 * @param ADCx ADC instance
4574 * @retval None
4575 */
LL_ADC_DisableIT_EOCS(ADC_TypeDef * ADCx)4576 __STATIC_INLINE void LL_ADC_DisableIT_EOCS(ADC_TypeDef *ADCx)
4577 {
4578 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
4579 }
4580
4581 /**
4582 * @brief Disable interruption ADC group regular overrun.
4583 * @rmtoll CR1 OVRIE LL_ADC_DisableIT_OVR
4584 * @param ADCx ADC instance
4585 * @retval None
4586 */
LL_ADC_DisableIT_OVR(ADC_TypeDef * ADCx)4587 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
4588 {
4589 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_OVR);
4590 }
4591
4592
4593 /**
4594 * @brief Disable interruption ADC group injected end of sequence conversions.
4595 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
4596 * @param ADCx ADC instance
4597 * @retval None
4598 */
LL_ADC_DisableIT_JEOS(ADC_TypeDef * ADCx)4599 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
4600 {
4601 /* Note: on this STM32 series, there is no flag ADC group injected */
4602 /* end of unitary conversion. */
4603 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4604 /* in other STM32 families). */
4605 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
4606 }
4607
4608 /**
4609 * @brief Disable interruption ADC analog watchdog 1.
4610 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
4611 * @param ADCx ADC instance
4612 * @retval None
4613 */
LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)4614 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
4615 {
4616 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
4617 }
4618
4619 /**
4620 * @brief Get state of interruption ADC group regular end of unitary conversion
4621 * or end of sequence conversions, depending on
4622 * ADC configuration.
4623 * @note To configure flag of end of conversion,
4624 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4625 * (0: interrupt disabled, 1: interrupt enabled)
4626 * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOCS
4627 * @param ADCx ADC instance
4628 * @retval State of bit (1 or 0).
4629 */
LL_ADC_IsEnabledIT_EOCS(ADC_TypeDef * ADCx)4630 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCS(ADC_TypeDef *ADCx)
4631 {
4632 return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOCS) == (LL_ADC_IT_EOCS));
4633 }
4634
4635 /**
4636 * @brief Get state of interruption ADC group regular overrun
4637 * (0: interrupt disabled, 1: interrupt enabled).
4638 * @rmtoll CR1 OVRIE LL_ADC_IsEnabledIT_OVR
4639 * @param ADCx ADC instance
4640 * @retval State of bit (1 or 0).
4641 */
LL_ADC_IsEnabledIT_OVR(ADC_TypeDef * ADCx)4642 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
4643 {
4644 return (READ_BIT(ADCx->CR1, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
4645 }
4646
4647
4648 /**
4649 * @brief Get state of interruption ADC group injected end of sequence conversions
4650 * (0: interrupt disabled, 1: interrupt enabled).
4651 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
4652 * @param ADCx ADC instance
4653 * @retval State of bit (1 or 0).
4654 */
LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef * ADCx)4655 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
4656 {
4657 /* Note: on this STM32 series, there is no flag ADC group injected */
4658 /* end of unitary conversion. */
4659 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4660 /* in other STM32 families). */
4661 return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
4662 }
4663
4664 /**
4665 * @brief Get state of interruption ADC analog watchdog 1
4666 * (0: interrupt disabled, 1: interrupt enabled).
4667 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
4668 * @param ADCx ADC instance
4669 * @retval State of bit (1 or 0).
4670 */
LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef * ADCx)4671 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
4672 {
4673 return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
4674 }
4675
4676 /**
4677 * @}
4678 */
4679
4680 #if defined(USE_FULL_LL_DRIVER)
4681 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
4682 * @{
4683 */
4684
4685 /* Initialization of some features of ADC common parameters and multimode */
4686 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
4687 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
4688 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
4689
4690 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
4691 /* (availability of ADC group injected depends on STM32 families) */
4692 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
4693
4694 /* Initialization of some features of ADC instance */
4695 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
4696 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
4697
4698 /* Initialization of some features of ADC instance and ADC group regular */
4699 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
4700 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
4701
4702 /* Initialization of some features of ADC instance and ADC group injected */
4703 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
4704 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
4705
4706 /**
4707 * @}
4708 */
4709 #endif /* USE_FULL_LL_DRIVER */
4710
4711 /**
4712 * @}
4713 */
4714
4715 /**
4716 * @}
4717 */
4718
4719 #endif /* ADC1 || ADC2 || ADC3 */
4720
4721 /**
4722 * @}
4723 */
4724
4725 #ifdef __cplusplus
4726 }
4727 #endif
4728
4729 #endif /* __STM32F7xx_LL_ADC_H */
4730
4731
