1 /** 2 ****************************************************************************** 3 * @file stm32f7xx_hal_tim.h 4 * @author MCD Application Team 5 * @brief Header file of TIM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32F7xx_HAL_TIM_H 21 #define STM32F7xx_HAL_TIM_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f7xx_hal_def.h" 29 30 /** @addtogroup STM32F7xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup TIM 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup TIM_Exported_Types TIM Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief TIM Time base Configuration Structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 49 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 50 51 uint32_t CounterMode; /*!< Specifies the counter mode. 52 This parameter can be a value of @ref TIM_Counter_Mode */ 53 54 uint32_t Period; /*!< Specifies the period value to be loaded into the active 55 Auto-Reload Register at the next update event. 56 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 57 58 uint32_t ClockDivision; /*!< Specifies the clock division. 59 This parameter can be a value of @ref TIM_ClockDivision */ 60 61 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 62 reaches zero, an update event is generated and counting restarts 63 from the RCR value (N). 64 This means in PWM mode that (N+1) corresponds to: 65 - the number of PWM periods in edge-aligned mode 66 - the number of half PWM period in center-aligned mode 67 GP timers: this parameter must be a number between Min_Data = 0x00 and 68 Max_Data = 0xFF. 69 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and 70 Max_Data = 0xFFFF. */ 71 72 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. 73 This parameter can be a value of @ref TIM_AutoReloadPreload */ 74 } TIM_Base_InitTypeDef; 75 76 /** 77 * @brief TIM Output Compare Configuration Structure definition 78 */ 79 typedef struct 80 { 81 uint32_t OCMode; /*!< Specifies the TIM mode. 82 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 83 84 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 85 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 86 87 uint32_t OCPolarity; /*!< Specifies the output polarity. 88 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 89 90 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 91 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 92 @note This parameter is valid only for timer instances supporting break feature. */ 93 94 uint32_t OCFastMode; /*!< Specifies the Fast mode state. 95 This parameter can be a value of @ref TIM_Output_Fast_State 96 @note This parameter is valid only in PWM1 and PWM2 mode. */ 97 98 99 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 100 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 101 @note This parameter is valid only for timer instances supporting break feature. */ 102 103 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 104 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 105 @note This parameter is valid only for timer instances supporting break feature. */ 106 } TIM_OC_InitTypeDef; 107 108 /** 109 * @brief TIM One Pulse Mode Configuration Structure definition 110 */ 111 typedef struct 112 { 113 uint32_t OCMode; /*!< Specifies the TIM mode. 114 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 115 116 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 117 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 118 119 uint32_t OCPolarity; /*!< Specifies the output polarity. 120 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 121 122 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 123 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 124 @note This parameter is valid only for timer instances supporting break feature. */ 125 126 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 127 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 128 @note This parameter is valid only for timer instances supporting break feature. */ 129 130 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 131 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 132 @note This parameter is valid only for timer instances supporting break feature. */ 133 134 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 135 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 136 137 uint32_t ICSelection; /*!< Specifies the input. 138 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 139 140 uint32_t ICFilter; /*!< Specifies the input capture filter. 141 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 142 } TIM_OnePulse_InitTypeDef; 143 144 /** 145 * @brief TIM Input Capture Configuration Structure definition 146 */ 147 typedef struct 148 { 149 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 150 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 151 152 uint32_t ICSelection; /*!< Specifies the input. 153 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 154 155 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 156 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 157 158 uint32_t ICFilter; /*!< Specifies the input capture filter. 159 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 160 } TIM_IC_InitTypeDef; 161 162 /** 163 * @brief TIM Encoder Configuration Structure definition 164 */ 165 typedef struct 166 { 167 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. 168 This parameter can be a value of @ref TIM_Encoder_Mode */ 169 170 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. 171 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ 172 173 uint32_t IC1Selection; /*!< Specifies the input. 174 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 175 176 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. 177 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 178 179 uint32_t IC1Filter; /*!< Specifies the input capture filter. 180 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 181 182 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. 183 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ 184 185 uint32_t IC2Selection; /*!< Specifies the input. 186 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 187 188 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. 189 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 190 191 uint32_t IC2Filter; /*!< Specifies the input capture filter. 192 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 193 } TIM_Encoder_InitTypeDef; 194 195 /** 196 * @brief Clock Configuration Handle Structure definition 197 */ 198 typedef struct 199 { 200 uint32_t ClockSource; /*!< TIM clock sources 201 This parameter can be a value of @ref TIM_Clock_Source */ 202 uint32_t ClockPolarity; /*!< TIM clock polarity 203 This parameter can be a value of @ref TIM_Clock_Polarity */ 204 uint32_t ClockPrescaler; /*!< TIM clock prescaler 205 This parameter can be a value of @ref TIM_Clock_Prescaler */ 206 uint32_t ClockFilter; /*!< TIM clock filter 207 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 208 } TIM_ClockConfigTypeDef; 209 210 /** 211 * @brief TIM Clear Input Configuration Handle Structure definition 212 */ 213 typedef struct 214 { 215 uint32_t ClearInputState; /*!< TIM clear Input state 216 This parameter can be ENABLE or DISABLE */ 217 uint32_t ClearInputSource; /*!< TIM clear Input sources 218 This parameter can be a value of @ref TIM_ClearInput_Source */ 219 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity 220 This parameter can be a value of @ref TIM_ClearInput_Polarity */ 221 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler 222 This parameter must be 0: When OCRef clear feature is used with ETR source, 223 ETR prescaler must be off */ 224 uint32_t ClearInputFilter; /*!< TIM Clear Input filter 225 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 226 } TIM_ClearInputConfigTypeDef; 227 228 /** 229 * @brief TIM Master configuration Structure definition 230 * @note Advanced timers provide TRGO2 internal line which is redirected 231 * to the ADC 232 */ 233 typedef struct 234 { 235 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection 236 This parameter can be a value of @ref TIM_Master_Mode_Selection */ 237 uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection 238 This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ 239 uint32_t MasterSlaveMode; /*!< Master/slave mode selection 240 This parameter can be a value of @ref TIM_Master_Slave_Mode 241 @note When the Master/slave mode is enabled, the effect of 242 an event on the trigger input (TRGI) is delayed to allow a 243 perfect synchronization between the current timer and its 244 slaves (through TRGO). It is not mandatory in case of timer 245 synchronization mode. */ 246 } TIM_MasterConfigTypeDef; 247 248 /** 249 * @brief TIM Slave configuration Structure definition 250 */ 251 typedef struct 252 { 253 uint32_t SlaveMode; /*!< Slave mode selection 254 This parameter can be a value of @ref TIM_Slave_Mode */ 255 uint32_t InputTrigger; /*!< Input Trigger source 256 This parameter can be a value of @ref TIM_Trigger_Selection */ 257 uint32_t TriggerPolarity; /*!< Input Trigger polarity 258 This parameter can be a value of @ref TIM_Trigger_Polarity */ 259 uint32_t TriggerPrescaler; /*!< Input trigger prescaler 260 This parameter can be a value of @ref TIM_Trigger_Prescaler */ 261 uint32_t TriggerFilter; /*!< Input trigger filter 262 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 263 264 } TIM_SlaveConfigTypeDef; 265 266 /** 267 * @brief TIM Break input(s) and Dead time configuration Structure definition 268 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable 269 * filter and polarity. 270 */ 271 typedef struct 272 { 273 uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ 274 275 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ 276 277 uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ 278 279 uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 280 281 uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ 282 283 uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ 284 285 uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 286 287 uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ 288 289 uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */ 290 291 uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 292 293 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ 294 295 } TIM_BreakDeadTimeConfigTypeDef; 296 297 /** 298 * @brief HAL State structures definition 299 */ 300 typedef enum 301 { 302 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ 303 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 304 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 305 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 306 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ 307 } HAL_TIM_StateTypeDef; 308 309 /** 310 * @brief TIM Channel States definition 311 */ 312 typedef enum 313 { 314 HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ 315 HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ 316 HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ 317 } HAL_TIM_ChannelStateTypeDef; 318 319 /** 320 * @brief DMA Burst States definition 321 */ 322 typedef enum 323 { 324 HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ 325 HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ 326 HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ 327 } HAL_TIM_DMABurstStateTypeDef; 328 329 /** 330 * @brief HAL Active channel structures definition 331 */ 332 typedef enum 333 { 334 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ 335 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ 336 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ 337 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ 338 HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ 339 HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ 340 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ 341 } HAL_TIM_ActiveChannel; 342 343 /** 344 * @brief TIM Time Base Handle Structure definition 345 */ 346 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 347 typedef struct __TIM_HandleTypeDef 348 #else 349 typedef struct 350 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 351 { 352 TIM_TypeDef *Instance; /*!< Register base address */ 353 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ 354 HAL_TIM_ActiveChannel Channel; /*!< Active channel */ 355 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array 356 This array is accessed by a @ref DMA_Handle_index */ 357 HAL_LockTypeDef Lock; /*!< Locking object */ 358 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ 359 __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ 360 __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ 361 __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ 362 363 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 364 void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ 365 void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ 366 void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ 367 void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ 368 void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ 369 void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ 370 void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ 371 void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ 372 void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ 373 void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ 374 void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ 375 void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ 376 void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ 377 void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ 378 void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ 379 void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ 380 void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ 381 void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ 382 void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ 383 void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ 384 void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ 385 void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ 386 void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ 387 void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ 388 void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ 389 void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ 390 void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ 391 void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ 392 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 393 } TIM_HandleTypeDef; 394 395 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 396 /** 397 * @brief HAL TIM Callback ID enumeration definition 398 */ 399 typedef enum 400 { 401 HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ 402 , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ 403 , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ 404 , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ 405 , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ 406 , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ 407 , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ 408 , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ 409 , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ 410 , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ 411 , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ 412 , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ 413 , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ 414 , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ 415 , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ 416 , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ 417 , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ 418 , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ 419 420 , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ 421 , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ 422 , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ 423 , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ 424 , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ 425 , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ 426 , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ 427 , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ 428 , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ 429 , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ 430 } HAL_TIM_CallbackIDTypeDef; 431 432 /** 433 * @brief HAL TIM Callback pointer definition 434 */ 435 typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ 436 437 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 438 439 /** 440 * @} 441 */ 442 /* End of exported types -----------------------------------------------------*/ 443 444 /* Exported constants --------------------------------------------------------*/ 445 /** @defgroup TIM_Exported_Constants TIM Exported Constants 446 * @{ 447 */ 448 449 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source 450 * @{ 451 */ 452 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ 453 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ 454 /** 455 * @} 456 */ 457 458 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address 459 * @{ 460 */ 461 #define TIM_DMABASE_CR1 0x00000000U 462 #define TIM_DMABASE_CR2 0x00000001U 463 #define TIM_DMABASE_SMCR 0x00000002U 464 #define TIM_DMABASE_DIER 0x00000003U 465 #define TIM_DMABASE_SR 0x00000004U 466 #define TIM_DMABASE_EGR 0x00000005U 467 #define TIM_DMABASE_CCMR1 0x00000006U 468 #define TIM_DMABASE_CCMR2 0x00000007U 469 #define TIM_DMABASE_CCER 0x00000008U 470 #define TIM_DMABASE_CNT 0x00000009U 471 #define TIM_DMABASE_PSC 0x0000000AU 472 #define TIM_DMABASE_ARR 0x0000000BU 473 #define TIM_DMABASE_RCR 0x0000000CU 474 #define TIM_DMABASE_CCR1 0x0000000DU 475 #define TIM_DMABASE_CCR2 0x0000000EU 476 #define TIM_DMABASE_CCR3 0x0000000FU 477 #define TIM_DMABASE_CCR4 0x00000010U 478 #define TIM_DMABASE_BDTR 0x00000011U 479 #define TIM_DMABASE_DCR 0x00000012U 480 #define TIM_DMABASE_DMAR 0x00000013U 481 #define TIM_DMABASE_OR 0x00000014U 482 #define TIM_DMABASE_CCMR3 0x00000015U 483 #define TIM_DMABASE_CCR5 0x00000016U 484 #define TIM_DMABASE_CCR6 0x00000017U 485 #if defined(TIM_BREAK_INPUT_SUPPORT) 486 #define TIM_DMABASE_AF1 0x00000018U 487 #define TIM_DMABASE_AF2 0x00000019U 488 #endif /* TIM_BREAK_INPUT_SUPPORT */ 489 /** 490 * @} 491 */ 492 493 /** @defgroup TIM_Event_Source TIM Event Source 494 * @{ 495 */ 496 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ 497 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ 498 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ 499 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ 500 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ 501 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ 502 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ 503 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ 504 #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ 505 /** 506 * @} 507 */ 508 509 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity 510 * @{ 511 */ 512 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ 513 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ 514 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ 515 /** 516 * @} 517 */ 518 519 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity 520 * @{ 521 */ 522 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ 523 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ 524 /** 525 * @} 526 */ 527 528 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler 529 * @{ 530 */ 531 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ 532 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ 533 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ 534 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ 535 /** 536 * @} 537 */ 538 539 /** @defgroup TIM_Counter_Mode TIM Counter Mode 540 * @{ 541 */ 542 #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ 543 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ 544 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ 545 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ 546 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ 547 /** 548 * @} 549 */ 550 551 /** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap 552 * @{ 553 */ 554 #define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ 555 #define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ 556 /** 557 * @} 558 */ 559 560 /** @defgroup TIM_ClockDivision TIM Clock Division 561 * @{ 562 */ 563 #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ 564 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ 565 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ 566 /** 567 * @} 568 */ 569 570 /** @defgroup TIM_Output_Compare_State TIM Output Compare State 571 * @{ 572 */ 573 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ 574 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ 575 /** 576 * @} 577 */ 578 579 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload 580 * @{ 581 */ 582 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ 583 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ 584 585 /** 586 * @} 587 */ 588 589 /** @defgroup TIM_Output_Fast_State TIM Output Fast State 590 * @{ 591 */ 592 #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ 593 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ 594 /** 595 * @} 596 */ 597 598 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State 599 * @{ 600 */ 601 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ 602 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ 603 /** 604 * @} 605 */ 606 607 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity 608 * @{ 609 */ 610 #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ 611 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ 612 /** 613 * @} 614 */ 615 616 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity 617 * @{ 618 */ 619 #define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ 620 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ 621 /** 622 * @} 623 */ 624 625 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State 626 * @{ 627 */ 628 #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ 629 #define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ 630 /** 631 * @} 632 */ 633 634 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State 635 * @{ 636 */ 637 #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ 638 #define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ 639 /** 640 * @} 641 */ 642 643 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity 644 * @{ 645 */ 646 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ 647 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ 648 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ 649 /** 650 * @} 651 */ 652 653 /** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity 654 * @{ 655 */ 656 #define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ 657 #define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ 658 /** 659 * @} 660 */ 661 662 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection 663 * @{ 664 */ 665 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ 666 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ 667 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ 668 /** 669 * @} 670 */ 671 672 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler 673 * @{ 674 */ 675 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ 676 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ 677 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ 678 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ 679 /** 680 * @} 681 */ 682 683 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode 684 * @{ 685 */ 686 #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ 687 #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ 688 /** 689 * @} 690 */ 691 692 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode 693 * @{ 694 */ 695 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ 696 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ 697 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ 698 /** 699 * @} 700 */ 701 702 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition 703 * @{ 704 */ 705 #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ 706 #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ 707 #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ 708 #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ 709 #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ 710 #define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ 711 #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ 712 #define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ 713 /** 714 * @} 715 */ 716 717 /** @defgroup TIM_Commutation_Source TIM Commutation Source 718 * @{ 719 */ 720 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ 721 #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ 722 /** 723 * @} 724 */ 725 726 /** @defgroup TIM_DMA_sources TIM DMA Sources 727 * @{ 728 */ 729 #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ 730 #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ 731 #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ 732 #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ 733 #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ 734 #define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ 735 #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ 736 /** 737 * @} 738 */ 739 740 /** @defgroup TIM_CC_DMA_Request CCx DMA request selection 741 * @{ 742 */ 743 #define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */ 744 #define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ 745 /** 746 * @} 747 */ 748 749 /** @defgroup TIM_Flag_definition TIM Flag Definition 750 * @{ 751 */ 752 #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ 753 #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ 754 #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ 755 #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ 756 #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ 757 #define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ 758 #define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ 759 #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ 760 #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ 761 #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ 762 #define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ 763 #define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ 764 #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ 765 #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ 766 #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ 767 #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ 768 /** 769 * @} 770 */ 771 772 /** @defgroup TIM_Channel TIM Channel 773 * @{ 774 */ 775 #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ 776 #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ 777 #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ 778 #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ 779 #define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ 780 #define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ 781 #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ 782 /** 783 * @} 784 */ 785 786 /** @defgroup TIM_Clock_Source TIM Clock Source 787 * @{ 788 */ 789 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ 790 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ 791 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ 792 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ 793 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ 794 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ 795 #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ 796 #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ 797 #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ 798 #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ 799 /** 800 * @} 801 */ 802 803 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity 804 * @{ 805 */ 806 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ 807 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ 808 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ 809 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ 810 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ 811 /** 812 * @} 813 */ 814 815 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler 816 * @{ 817 */ 818 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 819 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ 820 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ 821 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ 822 /** 823 * @} 824 */ 825 826 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity 827 * @{ 828 */ 829 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ 830 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ 831 /** 832 * @} 833 */ 834 835 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler 836 * @{ 837 */ 838 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 839 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ 840 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ 841 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ 842 /** 843 * @} 844 */ 845 846 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state 847 * @{ 848 */ 849 #define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 850 #define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 851 /** 852 * @} 853 */ 854 855 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state 856 * @{ 857 */ 858 #define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 859 #define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 860 /** 861 * @} 862 */ 863 /** @defgroup TIM_Lock_level TIM Lock level 864 * @{ 865 */ 866 #define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ 867 #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ 868 #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ 869 #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ 870 /** 871 * @} 872 */ 873 874 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable 875 * @{ 876 */ 877 #define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ 878 #define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ 879 /** 880 * @} 881 */ 882 883 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity 884 * @{ 885 */ 886 #define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ 887 #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ 888 /** 889 * @} 890 */ 891 892 /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable 893 * @{ 894 */ 895 #define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ 896 #define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ 897 /** 898 * @} 899 */ 900 901 /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity 902 * @{ 903 */ 904 #define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ 905 #define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ 906 /** 907 * @} 908 */ 909 910 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable 911 * @{ 912 */ 913 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ 914 #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ 915 /** 916 * @} 917 */ 918 919 /** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3 920 * @{ 921 */ 922 #define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ 923 #define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ 924 #define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ 925 #define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ 926 /** 927 * @} 928 */ 929 930 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection 931 * @{ 932 */ 933 #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ 934 #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ 935 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ 936 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ 937 #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ 938 #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ 939 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ 940 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ 941 /** 942 * @} 943 */ 944 945 /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) 946 * @{ 947 */ 948 #define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ 949 #define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ 950 #define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ 951 #define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ 952 #define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ 953 #define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ 954 #define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ 955 #define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ 956 #define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ 957 #define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ 958 #define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ 959 #define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ 960 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ 961 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ 962 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ 963 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ 964 /** 965 * @} 966 */ 967 968 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode 969 * @{ 970 */ 971 #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ 972 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ 973 /** 974 * @} 975 */ 976 977 /** @defgroup TIM_Slave_Mode TIM Slave mode 978 * @{ 979 */ 980 #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ 981 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ 982 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ 983 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ 984 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ 985 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ 986 /** 987 * @} 988 */ 989 990 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes 991 * @{ 992 */ 993 #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ 994 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ 995 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ 996 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ 997 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ 998 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ 999 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ 1000 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ 1001 #define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ 1002 #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ 1003 #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ 1004 #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ 1005 #define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ 1006 #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ 1007 /** 1008 * @} 1009 */ 1010 1011 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection 1012 * @{ 1013 */ 1014 #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ 1015 #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ 1016 #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ 1017 #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ 1018 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ 1019 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ 1020 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ 1021 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ 1022 #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ 1023 /** 1024 * @} 1025 */ 1026 1027 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity 1028 * @{ 1029 */ 1030 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ 1031 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ 1032 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1033 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1034 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1035 /** 1036 * @} 1037 */ 1038 1039 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler 1040 * @{ 1041 */ 1042 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 1043 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ 1044 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ 1045 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ 1046 /** 1047 * @} 1048 */ 1049 1050 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection 1051 * @{ 1052 */ 1053 #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ 1054 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ 1055 /** 1056 * @} 1057 */ 1058 1059 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length 1060 * @{ 1061 */ 1062 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ 1063 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1064 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1065 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1066 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1067 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1068 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1069 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1070 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1071 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1072 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1073 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1074 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1075 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1076 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1077 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1078 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1079 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1080 /** 1081 * @} 1082 */ 1083 1084 /** @defgroup DMA_Handle_index TIM DMA Handle Index 1085 * @{ 1086 */ 1087 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ 1088 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ 1089 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ 1090 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ 1091 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ 1092 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ 1093 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ 1094 /** 1095 * @} 1096 */ 1097 1098 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State 1099 * @{ 1100 */ 1101 #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ 1102 #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ 1103 #define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ 1104 #define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ 1105 /** 1106 * @} 1107 */ 1108 1109 /** @defgroup TIM_Break_System TIM Break System 1110 * @{ 1111 */ 1112 #define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */ 1113 #define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */ 1114 #define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */ 1115 #define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */ 1116 /** 1117 * @} 1118 */ 1119 1120 /** 1121 * @} 1122 */ 1123 /* End of exported constants -------------------------------------------------*/ 1124 1125 /* Exported macros -----------------------------------------------------------*/ 1126 /** @defgroup TIM_Exported_Macros TIM Exported Macros 1127 * @{ 1128 */ 1129 1130 /** @brief Reset TIM handle state. 1131 * @param __HANDLE__ TIM handle. 1132 * @retval None 1133 */ 1134 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 1135 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 1136 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 1137 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1138 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1139 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1140 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1141 (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ 1142 (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ 1143 (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1144 (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1145 (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1146 (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1147 (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ 1148 (__HANDLE__)->Base_MspInitCallback = NULL; \ 1149 (__HANDLE__)->Base_MspDeInitCallback = NULL; \ 1150 (__HANDLE__)->IC_MspInitCallback = NULL; \ 1151 (__HANDLE__)->IC_MspDeInitCallback = NULL; \ 1152 (__HANDLE__)->OC_MspInitCallback = NULL; \ 1153 (__HANDLE__)->OC_MspDeInitCallback = NULL; \ 1154 (__HANDLE__)->PWM_MspInitCallback = NULL; \ 1155 (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ 1156 (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ 1157 (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ 1158 (__HANDLE__)->Encoder_MspInitCallback = NULL; \ 1159 (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ 1160 (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ 1161 (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ 1162 } while(0) 1163 #else 1164 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 1165 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 1166 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1167 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1168 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1169 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1170 (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ 1171 (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ 1172 (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1173 (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1174 (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1175 (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1176 (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ 1177 } while(0) 1178 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 1179 1180 /** 1181 * @brief Enable the TIM peripheral. 1182 * @param __HANDLE__ TIM handle 1183 * @retval None 1184 */ 1185 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) 1186 1187 /** 1188 * @brief Enable the TIM main Output. 1189 * @param __HANDLE__ TIM handle 1190 * @retval None 1191 */ 1192 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) 1193 1194 /** 1195 * @brief Disable the TIM peripheral. 1196 * @param __HANDLE__ TIM handle 1197 * @retval None 1198 */ 1199 #define __HAL_TIM_DISABLE(__HANDLE__) \ 1200 do { \ 1201 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 1202 { \ 1203 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 1204 { \ 1205 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ 1206 } \ 1207 } \ 1208 } while(0) 1209 1210 /** 1211 * @brief Disable the TIM main Output. 1212 * @param __HANDLE__ TIM handle 1213 * @retval None 1214 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been 1215 * disabled 1216 */ 1217 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ 1218 do { \ 1219 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 1220 { \ 1221 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 1222 { \ 1223 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ 1224 } \ 1225 } \ 1226 } while(0) 1227 1228 /** 1229 * @brief Disable the TIM main Output. 1230 * @param __HANDLE__ TIM handle 1231 * @retval None 1232 * @note The Main Output Enable of a timer instance is disabled unconditionally 1233 */ 1234 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) 1235 1236 /** @brief Enable the specified TIM interrupt. 1237 * @param __HANDLE__ specifies the TIM Handle. 1238 * @param __INTERRUPT__ specifies the TIM interrupt source to enable. 1239 * This parameter can be one of the following values: 1240 * @arg TIM_IT_UPDATE: Update interrupt 1241 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1242 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1243 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1244 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1245 * @arg TIM_IT_COM: Commutation interrupt 1246 * @arg TIM_IT_TRIGGER: Trigger interrupt 1247 * @arg TIM_IT_BREAK: Break interrupt 1248 * @retval None 1249 */ 1250 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) 1251 1252 /** @brief Disable the specified TIM interrupt. 1253 * @param __HANDLE__ specifies the TIM Handle. 1254 * @param __INTERRUPT__ specifies the TIM interrupt source to disable. 1255 * This parameter can be one of the following values: 1256 * @arg TIM_IT_UPDATE: Update interrupt 1257 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1258 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1259 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1260 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1261 * @arg TIM_IT_COM: Commutation interrupt 1262 * @arg TIM_IT_TRIGGER: Trigger interrupt 1263 * @arg TIM_IT_BREAK: Break interrupt 1264 * @retval None 1265 */ 1266 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) 1267 1268 /** @brief Enable the specified DMA request. 1269 * @param __HANDLE__ specifies the TIM Handle. 1270 * @param __DMA__ specifies the TIM DMA request to enable. 1271 * This parameter can be one of the following values: 1272 * @arg TIM_DMA_UPDATE: Update DMA request 1273 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 1274 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 1275 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 1276 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 1277 * @arg TIM_DMA_COM: Commutation DMA request 1278 * @arg TIM_DMA_TRIGGER: Trigger DMA request 1279 * @retval None 1280 */ 1281 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) 1282 1283 /** @brief Disable the specified DMA request. 1284 * @param __HANDLE__ specifies the TIM Handle. 1285 * @param __DMA__ specifies the TIM DMA request to disable. 1286 * This parameter can be one of the following values: 1287 * @arg TIM_DMA_UPDATE: Update DMA request 1288 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 1289 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 1290 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 1291 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 1292 * @arg TIM_DMA_COM: Commutation DMA request 1293 * @arg TIM_DMA_TRIGGER: Trigger DMA request 1294 * @retval None 1295 */ 1296 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) 1297 1298 /** @brief Check whether the specified TIM interrupt flag is set or not. 1299 * @param __HANDLE__ specifies the TIM Handle. 1300 * @param __FLAG__ specifies the TIM interrupt flag to check. 1301 * This parameter can be one of the following values: 1302 * @arg TIM_FLAG_UPDATE: Update interrupt flag 1303 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 1304 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 1305 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 1306 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 1307 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag 1308 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag 1309 * @arg TIM_FLAG_COM: Commutation interrupt flag 1310 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 1311 * @arg TIM_FLAG_BREAK: Break interrupt flag 1312 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag 1313 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag 1314 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1315 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1316 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1317 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1318 * @retval The new state of __FLAG__ (TRUE or FALSE). 1319 */ 1320 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) 1321 1322 /** @brief Clear the specified TIM interrupt flag. 1323 * @param __HANDLE__ specifies the TIM Handle. 1324 * @param __FLAG__ specifies the TIM interrupt flag to clear. 1325 * This parameter can be one of the following values: 1326 * @arg TIM_FLAG_UPDATE: Update interrupt flag 1327 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 1328 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 1329 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 1330 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 1331 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag 1332 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag 1333 * @arg TIM_FLAG_COM: Commutation interrupt flag 1334 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 1335 * @arg TIM_FLAG_BREAK: Break interrupt flag 1336 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag 1337 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag 1338 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1339 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1340 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1341 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1342 * @retval The new state of __FLAG__ (TRUE or FALSE). 1343 */ 1344 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) 1345 1346 /** 1347 * @brief Check whether the specified TIM interrupt source is enabled or not. 1348 * @param __HANDLE__ TIM handle 1349 * @param __INTERRUPT__ specifies the TIM interrupt source to check. 1350 * This parameter can be one of the following values: 1351 * @arg TIM_IT_UPDATE: Update interrupt 1352 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1353 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1354 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1355 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1356 * @arg TIM_IT_COM: Commutation interrupt 1357 * @arg TIM_IT_TRIGGER: Trigger interrupt 1358 * @arg TIM_IT_BREAK: Break interrupt 1359 * @retval The state of TIM_IT (SET or RESET). 1360 */ 1361 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ 1362 == (__INTERRUPT__)) ? SET : RESET) 1363 1364 /** @brief Clear the TIM interrupt pending bits. 1365 * @param __HANDLE__ TIM handle 1366 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1367 * This parameter can be one of the following values: 1368 * @arg TIM_IT_UPDATE: Update interrupt 1369 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1370 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1371 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1372 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1373 * @arg TIM_IT_COM: Commutation interrupt 1374 * @arg TIM_IT_TRIGGER: Trigger interrupt 1375 * @arg TIM_IT_BREAK: Break interrupt 1376 * @retval None 1377 */ 1378 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) 1379 1380 /** 1381 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). 1382 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read 1383 * in an atomic way. 1384 * @param __HANDLE__ TIM handle. 1385 * @retval None 1386 mode. 1387 */ 1388 #define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) 1389 1390 /** 1391 * @brief Disable update interrupt flag (UIF) remapping. 1392 * @param __HANDLE__ TIM handle. 1393 * @retval None 1394 mode. 1395 */ 1396 #define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) 1397 1398 /** 1399 * @brief Get update interrupt flag (UIF) copy status. 1400 * @param __COUNTER__ Counter value. 1401 * @retval The state of UIFCPY (TRUE or FALSE). 1402 mode. 1403 */ 1404 #define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) 1405 1406 /** 1407 * @brief Indicates whether or not the TIM Counter is used as downcounter. 1408 * @param __HANDLE__ TIM handle. 1409 * @retval False (Counter used as upcounter) or True (Counter used as downcounter) 1410 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode 1411 * or Encoder mode. 1412 */ 1413 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) 1414 1415 /** 1416 * @brief Set the TIM Prescaler on runtime. 1417 * @param __HANDLE__ TIM handle. 1418 * @param __PRESC__ specifies the Prescaler new value. 1419 * @retval None 1420 */ 1421 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) 1422 1423 /** 1424 * @brief Set the TIM Counter Register value on runtime. 1425 * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in 1426 * case of 32 bits counter TIM instance. 1427 * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. 1428 * @param __HANDLE__ TIM handle. 1429 * @param __COUNTER__ specifies the Counter register new value. 1430 * @retval None 1431 */ 1432 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) 1433 1434 /** 1435 * @brief Get the TIM Counter Register value on runtime. 1436 * @param __HANDLE__ TIM handle. 1437 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) 1438 */ 1439 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) 1440 1441 /** 1442 * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. 1443 * @param __HANDLE__ TIM handle. 1444 * @param __AUTORELOAD__ specifies the Counter register new value. 1445 * @retval None 1446 */ 1447 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ 1448 do{ \ 1449 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ 1450 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ 1451 } while(0) 1452 1453 /** 1454 * @brief Get the TIM Autoreload Register value on runtime. 1455 * @param __HANDLE__ TIM handle. 1456 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) 1457 */ 1458 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) 1459 1460 /** 1461 * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. 1462 * @param __HANDLE__ TIM handle. 1463 * @param __CKD__ specifies the clock division value. 1464 * This parameter can be one of the following value: 1465 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1466 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1467 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1468 * @retval None 1469 */ 1470 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ 1471 do{ \ 1472 (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ 1473 (__HANDLE__)->Instance->CR1 |= (__CKD__); \ 1474 (__HANDLE__)->Init.ClockDivision = (__CKD__); \ 1475 } while(0) 1476 1477 /** 1478 * @brief Get the TIM Clock Division value on runtime. 1479 * @param __HANDLE__ TIM handle. 1480 * @retval The clock division can be one of the following values: 1481 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1482 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1483 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1484 */ 1485 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) 1486 1487 /** 1488 * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() 1489 * function. 1490 * @param __HANDLE__ TIM handle. 1491 * @param __CHANNEL__ TIM Channels to be configured. 1492 * This parameter can be one of the following values: 1493 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1494 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1495 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1496 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1497 * @param __ICPSC__ specifies the Input Capture4 prescaler new value. 1498 * This parameter can be one of the following values: 1499 * @arg TIM_ICPSC_DIV1: no prescaler 1500 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1501 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1502 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1503 * @retval None 1504 */ 1505 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ 1506 do{ \ 1507 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ 1508 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ 1509 } while(0) 1510 1511 /** 1512 * @brief Get the TIM Input Capture prescaler on runtime. 1513 * @param __HANDLE__ TIM handle. 1514 * @param __CHANNEL__ TIM Channels to be configured. 1515 * This parameter can be one of the following values: 1516 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value 1517 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value 1518 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value 1519 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value 1520 * @retval The input capture prescaler can be one of the following values: 1521 * @arg TIM_ICPSC_DIV1: no prescaler 1522 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1523 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1524 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1525 */ 1526 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ 1527 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ 1528 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ 1529 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ 1530 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) 1531 1532 /** 1533 * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. 1534 * @param __HANDLE__ TIM handle. 1535 * @param __CHANNEL__ TIM Channels to be configured. 1536 * This parameter can be one of the following values: 1537 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1538 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1539 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1540 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1541 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1542 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1543 * @param __COMPARE__ specifies the Capture Compare register new value. 1544 * @retval None 1545 */ 1546 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ 1547 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ 1548 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ 1549 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ 1550 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ 1551 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ 1552 ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) 1553 1554 /** 1555 * @brief Get the TIM Capture Compare Register value on runtime. 1556 * @param __HANDLE__ TIM handle. 1557 * @param __CHANNEL__ TIM Channel associated with the capture compare register 1558 * This parameter can be one of the following values: 1559 * @arg TIM_CHANNEL_1: get capture/compare 1 register value 1560 * @arg TIM_CHANNEL_2: get capture/compare 2 register value 1561 * @arg TIM_CHANNEL_3: get capture/compare 3 register value 1562 * @arg TIM_CHANNEL_4: get capture/compare 4 register value 1563 * @arg TIM_CHANNEL_5: get capture/compare 5 register value 1564 * @arg TIM_CHANNEL_6: get capture/compare 6 register value 1565 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) 1566 */ 1567 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ 1568 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ 1569 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ 1570 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ 1571 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ 1572 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ 1573 ((__HANDLE__)->Instance->CCR6)) 1574 1575 /** 1576 * @brief Set the TIM Output compare preload. 1577 * @param __HANDLE__ TIM handle. 1578 * @param __CHANNEL__ TIM Channels to be configured. 1579 * This parameter can be one of the following values: 1580 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1581 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1582 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1583 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1584 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1585 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1586 * @retval None 1587 */ 1588 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1589 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ 1590 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ 1591 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ 1592 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ 1593 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ 1594 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) 1595 1596 /** 1597 * @brief Reset the TIM Output compare preload. 1598 * @param __HANDLE__ TIM handle. 1599 * @param __CHANNEL__ TIM Channels to be configured. 1600 * This parameter can be one of the following values: 1601 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1602 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1603 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1604 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1605 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1606 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1607 * @retval None 1608 */ 1609 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1610 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ 1611 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ 1612 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ 1613 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ 1614 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ 1615 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) 1616 1617 /** 1618 * @brief Enable fast mode for a given channel. 1619 * @param __HANDLE__ TIM handle. 1620 * @param __CHANNEL__ TIM Channels to be configured. 1621 * This parameter can be one of the following values: 1622 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1623 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1624 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1625 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1626 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1627 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1628 * @note When fast mode is enabled an active edge on the trigger input acts 1629 * like a compare match on CCx output. Delay to sample the trigger 1630 * input and to activate CCx output is reduced to 3 clock cycles. 1631 * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. 1632 * @retval None 1633 */ 1634 #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1635 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ 1636 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ 1637 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ 1638 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ 1639 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ 1640 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) 1641 1642 /** 1643 * @brief Disable fast mode for a given channel. 1644 * @param __HANDLE__ TIM handle. 1645 * @param __CHANNEL__ TIM Channels to be configured. 1646 * This parameter can be one of the following values: 1647 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1648 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1649 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1650 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1651 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1652 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1653 * @note When fast mode is disabled CCx output behaves normally depending 1654 * on counter and CCRx values even when the trigger is ON. The minimum 1655 * delay to activate CCx output when an active edge occurs on the 1656 * trigger input is 5 clock cycles. 1657 * @retval None 1658 */ 1659 #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1660 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ 1661 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ 1662 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ 1663 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ 1664 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ 1665 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) 1666 1667 /** 1668 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. 1669 * @param __HANDLE__ TIM handle. 1670 * @note When the URS bit of the TIMx_CR1 register is set, only counter 1671 * overflow/underflow generates an update interrupt or DMA request (if 1672 * enabled) 1673 * @retval None 1674 */ 1675 #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) 1676 1677 /** 1678 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. 1679 * @param __HANDLE__ TIM handle. 1680 * @note When the URS bit of the TIMx_CR1 register is reset, any of the 1681 * following events generate an update interrupt or DMA request (if 1682 * enabled): 1683 * _ Counter overflow underflow 1684 * _ Setting the UG bit 1685 * _ Update generation through the slave mode controller 1686 * @retval None 1687 */ 1688 #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) 1689 1690 /** 1691 * @brief Set the TIM Capture x input polarity on runtime. 1692 * @param __HANDLE__ TIM handle. 1693 * @param __CHANNEL__ TIM Channels to be configured. 1694 * This parameter can be one of the following values: 1695 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1696 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1697 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1698 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1699 * @param __POLARITY__ Polarity for TIx source 1700 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge 1701 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge 1702 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge 1703 * @retval None 1704 */ 1705 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 1706 do{ \ 1707 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ 1708 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ 1709 }while(0) 1710 1711 /** @brief Select the Capture/compare DMA request source. 1712 * @param __HANDLE__ specifies the TIM Handle. 1713 * @param __CCDMA__ specifies Capture/compare DMA request source 1714 * This parameter can be one of the following values: 1715 * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event 1716 * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event 1717 * @retval None 1718 */ 1719 #define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \ 1720 MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__)) 1721 1722 /** 1723 * @} 1724 */ 1725 /* End of exported macros ----------------------------------------------------*/ 1726 1727 /* Private constants ---------------------------------------------------------*/ 1728 /** @defgroup TIM_Private_Constants TIM Private Constants 1729 * @{ 1730 */ 1731 /* The counter of a timer instance is disabled only if all the CCx and CCxN 1732 channels have been disabled */ 1733 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) 1734 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) 1735 /** 1736 * @} 1737 */ 1738 /* End of private constants --------------------------------------------------*/ 1739 1740 /* Private macros ------------------------------------------------------------*/ 1741 /** @defgroup TIM_Private_Macros TIM Private Macros 1742 * @{ 1743 */ 1744 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ 1745 ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) 1746 1747 #if defined(TIM_AF1_BKINE)&&defined(TIM_AF2_BKINE) 1748 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ 1749 ((__BASE__) == TIM_DMABASE_CR2) || \ 1750 ((__BASE__) == TIM_DMABASE_SMCR) || \ 1751 ((__BASE__) == TIM_DMABASE_DIER) || \ 1752 ((__BASE__) == TIM_DMABASE_SR) || \ 1753 ((__BASE__) == TIM_DMABASE_EGR) || \ 1754 ((__BASE__) == TIM_DMABASE_CCMR1) || \ 1755 ((__BASE__) == TIM_DMABASE_CCMR2) || \ 1756 ((__BASE__) == TIM_DMABASE_CCER) || \ 1757 ((__BASE__) == TIM_DMABASE_CNT) || \ 1758 ((__BASE__) == TIM_DMABASE_PSC) || \ 1759 ((__BASE__) == TIM_DMABASE_ARR) || \ 1760 ((__BASE__) == TIM_DMABASE_RCR) || \ 1761 ((__BASE__) == TIM_DMABASE_CCR1) || \ 1762 ((__BASE__) == TIM_DMABASE_CCR2) || \ 1763 ((__BASE__) == TIM_DMABASE_CCR3) || \ 1764 ((__BASE__) == TIM_DMABASE_CCR4) || \ 1765 ((__BASE__) == TIM_DMABASE_BDTR) || \ 1766 ((__BASE__) == TIM_DMABASE_OR) || \ 1767 ((__BASE__) == TIM_DMABASE_CCMR3) || \ 1768 ((__BASE__) == TIM_DMABASE_CCR5) || \ 1769 ((__BASE__) == TIM_DMABASE_CCR6) || \ 1770 ((__BASE__) == TIM_DMABASE_AF1) || \ 1771 ((__BASE__) == TIM_DMABASE_AF2)) 1772 #else 1773 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ 1774 ((__BASE__) == TIM_DMABASE_CR2) || \ 1775 ((__BASE__) == TIM_DMABASE_SMCR) || \ 1776 ((__BASE__) == TIM_DMABASE_DIER) || \ 1777 ((__BASE__) == TIM_DMABASE_SR) || \ 1778 ((__BASE__) == TIM_DMABASE_EGR) || \ 1779 ((__BASE__) == TIM_DMABASE_CCMR1) || \ 1780 ((__BASE__) == TIM_DMABASE_CCMR2) || \ 1781 ((__BASE__) == TIM_DMABASE_CCER) || \ 1782 ((__BASE__) == TIM_DMABASE_CNT) || \ 1783 ((__BASE__) == TIM_DMABASE_PSC) || \ 1784 ((__BASE__) == TIM_DMABASE_ARR) || \ 1785 ((__BASE__) == TIM_DMABASE_RCR) || \ 1786 ((__BASE__) == TIM_DMABASE_CCR1) || \ 1787 ((__BASE__) == TIM_DMABASE_CCR2) || \ 1788 ((__BASE__) == TIM_DMABASE_CCR3) || \ 1789 ((__BASE__) == TIM_DMABASE_CCR4) || \ 1790 ((__BASE__) == TIM_DMABASE_BDTR) || \ 1791 ((__BASE__) == TIM_DMABASE_OR) || \ 1792 ((__BASE__) == TIM_DMABASE_CCMR3) || \ 1793 ((__BASE__) == TIM_DMABASE_CCR5) || \ 1794 ((__BASE__) == TIM_DMABASE_CCR6)) 1795 #endif /* TIM_AF1_BKINE && TIM_AF1_BKINE */ 1796 1797 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1798 1799 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ 1800 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ 1801 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ 1802 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ 1803 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) 1804 1805 #define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ 1806 ((__MODE__) == TIM_UIFREMAP_ENABLE)) 1807 1808 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ 1809 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ 1810 ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) 1811 1812 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ 1813 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) 1814 1815 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ 1816 ((__STATE__) == TIM_OCFAST_ENABLE)) 1817 1818 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ 1819 ((__POLARITY__) == TIM_OCPOLARITY_LOW)) 1820 1821 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ 1822 ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) 1823 1824 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ 1825 ((__STATE__) == TIM_OCIDLESTATE_RESET)) 1826 1827 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ 1828 ((__STATE__) == TIM_OCNIDLESTATE_RESET)) 1829 1830 #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ 1831 ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) 1832 1833 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ 1834 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ 1835 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) 1836 1837 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ 1838 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ 1839 ((__SELECTION__) == TIM_ICSELECTION_TRC)) 1840 1841 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ 1842 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ 1843 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ 1844 ((__PRESCALER__) == TIM_ICPSC_DIV8)) 1845 1846 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ 1847 ((__MODE__) == TIM_OPMODE_REPETITIVE)) 1848 1849 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ 1850 ((__MODE__) == TIM_ENCODERMODE_TI2) || \ 1851 ((__MODE__) == TIM_ENCODERMODE_TI12)) 1852 1853 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1854 1855 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1856 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1857 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 1858 ((__CHANNEL__) == TIM_CHANNEL_4) || \ 1859 ((__CHANNEL__) == TIM_CHANNEL_5) || \ 1860 ((__CHANNEL__) == TIM_CHANNEL_6) || \ 1861 ((__CHANNEL__) == TIM_CHANNEL_ALL)) 1862 1863 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1864 ((__CHANNEL__) == TIM_CHANNEL_2)) 1865 1866 #define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \ 1867 ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U)) 1868 1869 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1870 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1871 ((__CHANNEL__) == TIM_CHANNEL_3)) 1872 1873 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 1874 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ 1875 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 1876 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 1877 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 1878 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 1879 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ 1880 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ 1881 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ 1882 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)) 1883 1884 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ 1885 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ 1886 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ 1887 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ 1888 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) 1889 1890 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ 1891 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ 1892 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ 1893 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) 1894 1895 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1896 1897 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ 1898 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) 1899 1900 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ 1901 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ 1902 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ 1903 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) 1904 1905 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1906 1907 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ 1908 ((__STATE__) == TIM_OSSR_DISABLE)) 1909 1910 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ 1911 ((__STATE__) == TIM_OSSI_DISABLE)) 1912 1913 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ 1914 ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ 1915 ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ 1916 ((__LEVEL__) == TIM_LOCKLEVEL_3)) 1917 1918 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) 1919 1920 1921 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ 1922 ((__STATE__) == TIM_BREAK_DISABLE)) 1923 1924 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ 1925 ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) 1926 1927 #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ 1928 ((__STATE__) == TIM_BREAK2_DISABLE)) 1929 1930 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ 1931 ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) 1932 1933 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ 1934 ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) 1935 1936 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) 1937 1938 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ 1939 ((__SOURCE__) == TIM_TRGO_ENABLE) || \ 1940 ((__SOURCE__) == TIM_TRGO_UPDATE) || \ 1941 ((__SOURCE__) == TIM_TRGO_OC1) || \ 1942 ((__SOURCE__) == TIM_TRGO_OC1REF) || \ 1943 ((__SOURCE__) == TIM_TRGO_OC2REF) || \ 1944 ((__SOURCE__) == TIM_TRGO_OC3REF) || \ 1945 ((__SOURCE__) == TIM_TRGO_OC4REF)) 1946 1947 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ 1948 ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ 1949 ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ 1950 ((__SOURCE__) == TIM_TRGO2_OC1) || \ 1951 ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ 1952 ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ 1953 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ 1954 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ 1955 ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ 1956 ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ 1957 ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ 1958 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ 1959 ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ 1960 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ 1961 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ 1962 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ 1963 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) 1964 1965 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ 1966 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) 1967 1968 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ 1969 ((__MODE__) == TIM_SLAVEMODE_RESET) || \ 1970 ((__MODE__) == TIM_SLAVEMODE_GATED) || \ 1971 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ 1972 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ 1973 ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) 1974 1975 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ 1976 ((__MODE__) == TIM_OCMODE_PWM2) || \ 1977 ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ 1978 ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ 1979 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ 1980 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) 1981 1982 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ 1983 ((__MODE__) == TIM_OCMODE_ACTIVE) || \ 1984 ((__MODE__) == TIM_OCMODE_INACTIVE) || \ 1985 ((__MODE__) == TIM_OCMODE_TOGGLE) || \ 1986 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ 1987 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ 1988 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ 1989 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2)) 1990 1991 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 1992 ((__SELECTION__) == TIM_TS_ITR1) || \ 1993 ((__SELECTION__) == TIM_TS_ITR2) || \ 1994 ((__SELECTION__) == TIM_TS_ITR3) || \ 1995 ((__SELECTION__) == TIM_TS_TI1F_ED) || \ 1996 ((__SELECTION__) == TIM_TS_TI1FP1) || \ 1997 ((__SELECTION__) == TIM_TS_TI2FP2) || \ 1998 ((__SELECTION__) == TIM_TS_ETRF)) 1999 2000 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 2001 ((__SELECTION__) == TIM_TS_ITR1) || \ 2002 ((__SELECTION__) == TIM_TS_ITR2) || \ 2003 ((__SELECTION__) == TIM_TS_ITR3) || \ 2004 ((__SELECTION__) == TIM_TS_NONE)) 2005 2006 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ 2007 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ 2008 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ 2009 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ 2010 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) 2011 2012 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ 2013 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ 2014 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ 2015 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) 2016 2017 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 2018 2019 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ 2020 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) 2021 2022 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ 2023 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ 2024 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ 2025 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ 2026 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ 2027 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ 2028 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ 2029 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ 2030 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ 2031 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ 2032 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ 2033 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ 2034 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ 2035 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ 2036 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ 2037 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ 2038 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ 2039 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) 2040 2041 #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) 2042 2043 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 2044 2045 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) 2046 2047 #define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ 2048 ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ 2049 ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \ 2050 ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) 2051 2052 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ 2053 ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) 2054 2055 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ 2056 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ 2057 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ 2058 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ 2059 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) 2060 2061 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ 2062 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ 2063 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ 2064 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ 2065 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) 2066 2067 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 2068 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ 2069 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ 2070 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ 2071 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) 2072 2073 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ 2074 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ 2075 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ 2076 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ 2077 ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) 2078 2079 #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ 2080 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ 2081 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ 2082 ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ 2083 ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ 2084 ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ 2085 (__HANDLE__)->ChannelState[5]) 2086 2087 #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ 2088 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ 2089 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ 2090 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ 2091 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\ 2092 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ 2093 ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) 2094 2095 #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ 2096 (__HANDLE__)->ChannelState[0] = \ 2097 (__CHANNEL_STATE__); \ 2098 (__HANDLE__)->ChannelState[1] = \ 2099 (__CHANNEL_STATE__); \ 2100 (__HANDLE__)->ChannelState[2] = \ 2101 (__CHANNEL_STATE__); \ 2102 (__HANDLE__)->ChannelState[3] = \ 2103 (__CHANNEL_STATE__); \ 2104 (__HANDLE__)->ChannelState[4] = \ 2105 (__CHANNEL_STATE__); \ 2106 (__HANDLE__)->ChannelState[5] = \ 2107 (__CHANNEL_STATE__); \ 2108 } while(0) 2109 2110 #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ 2111 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ 2112 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ 2113 ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ 2114 (__HANDLE__)->ChannelNState[3]) 2115 2116 #define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ 2117 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ 2118 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ 2119 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ 2120 ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) 2121 2122 #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ 2123 (__HANDLE__)->ChannelNState[0] = \ 2124 (__CHANNEL_STATE__); \ 2125 (__HANDLE__)->ChannelNState[1] = \ 2126 (__CHANNEL_STATE__); \ 2127 (__HANDLE__)->ChannelNState[2] = \ 2128 (__CHANNEL_STATE__); \ 2129 (__HANDLE__)->ChannelNState[3] = \ 2130 (__CHANNEL_STATE__); \ 2131 } while(0) 2132 2133 /** 2134 * @} 2135 */ 2136 /* End of private macros -----------------------------------------------------*/ 2137 2138 /* Include TIM HAL Extended module */ 2139 #include "stm32f7xx_hal_tim_ex.h" 2140 2141 /* Exported functions --------------------------------------------------------*/ 2142 /** @addtogroup TIM_Exported_Functions TIM Exported Functions 2143 * @{ 2144 */ 2145 2146 /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions 2147 * @brief Time Base functions 2148 * @{ 2149 */ 2150 /* Time Base functions ********************************************************/ 2151 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); 2152 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); 2153 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); 2154 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); 2155 /* Blocking mode: Polling */ 2156 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); 2157 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); 2158 /* Non-Blocking mode: Interrupt */ 2159 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); 2160 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); 2161 /* Non-Blocking mode: DMA */ 2162 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length); 2163 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); 2164 /** 2165 * @} 2166 */ 2167 2168 /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions 2169 * @brief TIM Output Compare functions 2170 * @{ 2171 */ 2172 /* Timer Output Compare functions *********************************************/ 2173 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); 2174 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); 2175 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); 2176 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); 2177 /* Blocking mode: Polling */ 2178 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2179 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2180 /* Non-Blocking mode: Interrupt */ 2181 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2182 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2183 /* Non-Blocking mode: DMA */ 2184 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, 2185 uint16_t Length); 2186 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2187 /** 2188 * @} 2189 */ 2190 2191 /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions 2192 * @brief TIM PWM functions 2193 * @{ 2194 */ 2195 /* Timer PWM functions ********************************************************/ 2196 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); 2197 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); 2198 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); 2199 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); 2200 /* Blocking mode: Polling */ 2201 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2202 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2203 /* Non-Blocking mode: Interrupt */ 2204 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2205 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2206 /* Non-Blocking mode: DMA */ 2207 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, 2208 uint16_t Length); 2209 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2210 /** 2211 * @} 2212 */ 2213 2214 /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions 2215 * @brief TIM Input Capture functions 2216 * @{ 2217 */ 2218 /* Timer Input Capture functions **********************************************/ 2219 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); 2220 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); 2221 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); 2222 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); 2223 /* Blocking mode: Polling */ 2224 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2225 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2226 /* Non-Blocking mode: Interrupt */ 2227 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2228 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2229 /* Non-Blocking mode: DMA */ 2230 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 2231 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2232 /** 2233 * @} 2234 */ 2235 2236 /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions 2237 * @brief TIM One Pulse functions 2238 * @{ 2239 */ 2240 /* Timer One Pulse functions **************************************************/ 2241 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); 2242 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); 2243 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); 2244 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); 2245 /* Blocking mode: Polling */ 2246 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2247 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2248 /* Non-Blocking mode: Interrupt */ 2249 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2250 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2251 /** 2252 * @} 2253 */ 2254 2255 /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions 2256 * @brief TIM Encoder functions 2257 * @{ 2258 */ 2259 /* Timer Encoder functions ****************************************************/ 2260 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); 2261 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); 2262 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); 2263 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); 2264 /* Blocking mode: Polling */ 2265 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2266 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2267 /* Non-Blocking mode: Interrupt */ 2268 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2269 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2270 /* Non-Blocking mode: DMA */ 2271 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, 2272 uint32_t *pData2, uint16_t Length); 2273 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2274 /** 2275 * @} 2276 */ 2277 2278 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management 2279 * @brief IRQ handler management 2280 * @{ 2281 */ 2282 /* Interrupt Handler functions ***********************************************/ 2283 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); 2284 /** 2285 * @} 2286 */ 2287 2288 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions 2289 * @brief Peripheral Control functions 2290 * @{ 2291 */ 2292 /* Control functions *********************************************************/ 2293 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, 2294 uint32_t Channel); 2295 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, 2296 uint32_t Channel); 2297 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, 2298 uint32_t Channel); 2299 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, 2300 uint32_t OutputChannel, uint32_t InputChannel); 2301 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, 2302 const TIM_ClearInputConfigTypeDef *sClearInputConfig, 2303 uint32_t Channel); 2304 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig); 2305 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); 2306 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); 2307 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); 2308 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2309 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength); 2310 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2311 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, 2312 uint32_t BurstLength, uint32_t DataLength); 2313 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 2314 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2315 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); 2316 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2317 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, 2318 uint32_t BurstLength, uint32_t DataLength); 2319 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 2320 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); 2321 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel); 2322 /** 2323 * @} 2324 */ 2325 2326 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions 2327 * @brief TIM Callbacks functions 2328 * @{ 2329 */ 2330 /* Callback in non blocking modes (Interrupt and DMA) *************************/ 2331 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); 2332 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); 2333 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); 2334 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); 2335 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); 2336 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); 2337 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); 2338 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); 2339 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); 2340 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); 2341 2342 /* Callbacks Register/UnRegister functions ***********************************/ 2343 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 2344 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, 2345 pTIM_CallbackTypeDef pCallback); 2346 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); 2347 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 2348 2349 /** 2350 * @} 2351 */ 2352 2353 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions 2354 * @brief Peripheral State functions 2355 * @{ 2356 */ 2357 /* Peripheral State functions ************************************************/ 2358 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim); 2359 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim); 2360 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim); 2361 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim); 2362 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim); 2363 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim); 2364 2365 /* Peripheral Channel state functions ************************************************/ 2366 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim); 2367 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel); 2368 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim); 2369 /** 2370 * @} 2371 */ 2372 2373 /** 2374 * @} 2375 */ 2376 /* End of exported functions -------------------------------------------------*/ 2377 2378 /* Private functions----------------------------------------------------------*/ 2379 /** @defgroup TIM_Private_Functions TIM Private Functions 2380 * @{ 2381 */ 2382 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure); 2383 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); 2384 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); 2385 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, 2386 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); 2387 2388 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); 2389 void TIM_DMAError(DMA_HandleTypeDef *hdma); 2390 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); 2391 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); 2392 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); 2393 2394 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 2395 void TIM_ResetCallback(TIM_HandleTypeDef *htim); 2396 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 2397 2398 /** 2399 * @} 2400 */ 2401 /* End of private functions --------------------------------------------------*/ 2402 2403 /** 2404 * @} 2405 */ 2406 2407 /** 2408 * @} 2409 */ 2410 2411 #ifdef __cplusplus 2412 } 2413 #endif 2414 2415 #endif /* STM32F7xx_HAL_TIM_H */ 2416
