1 /** 2 ****************************************************************************** 3 * @file stm32f7xx_hal_sram.h 4 * @author MCD Application Team 5 * @brief Header file of SRAM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32F7xx_HAL_SRAM_H 21 #define STM32F7xx_HAL_SRAM_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32f7xx_ll_fmc.h" 30 31 /** @addtogroup STM32F7xx_HAL_Driver 32 * @{ 33 */ 34 /** @addtogroup SRAM 35 * @{ 36 */ 37 38 /* Exported typedef ----------------------------------------------------------*/ 39 40 /** @defgroup SRAM_Exported_Types SRAM Exported Types 41 * @{ 42 */ 43 /** 44 * @brief HAL SRAM State structures definition 45 */ 46 typedef enum 47 { 48 HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */ 49 HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */ 50 HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */ 51 HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */ 52 HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */ 53 54 } HAL_SRAM_StateTypeDef; 55 56 /** 57 * @brief SRAM handle Structure definition 58 */ 59 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) 60 typedef struct __SRAM_HandleTypeDef 61 #else 62 typedef struct 63 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ 64 { 65 FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ 66 67 FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ 68 69 FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */ 70 71 HAL_LockTypeDef Lock; /*!< SRAM locking object */ 72 73 __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */ 74 75 DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ 76 77 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) 78 void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */ 79 void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */ 80 void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Complete callback */ 81 void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Error callback */ 82 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ 83 } SRAM_HandleTypeDef; 84 85 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) 86 /** 87 * @brief HAL SRAM Callback ID enumeration definition 88 */ 89 typedef enum 90 { 91 HAL_SRAM_MSP_INIT_CB_ID = 0x00U, /*!< SRAM MspInit Callback ID */ 92 HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */ 93 HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */ 94 HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */ 95 } HAL_SRAM_CallbackIDTypeDef; 96 97 /** 98 * @brief HAL SRAM Callback pointer definition 99 */ 100 typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram); 101 typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); 102 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ 103 /** 104 * @} 105 */ 106 107 /* Exported constants --------------------------------------------------------*/ 108 /* Exported macro ------------------------------------------------------------*/ 109 110 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros 111 * @{ 112 */ 113 114 /** @brief Reset SRAM handle state 115 * @param __HANDLE__ SRAM handle 116 * @retval None 117 */ 118 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) 119 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) do { \ 120 (__HANDLE__)->State = HAL_SRAM_STATE_RESET; \ 121 (__HANDLE__)->MspInitCallback = NULL; \ 122 (__HANDLE__)->MspDeInitCallback = NULL; \ 123 } while(0) 124 #else 125 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) 126 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ 127 128 /** 129 * @} 130 */ 131 132 /* Exported functions --------------------------------------------------------*/ 133 /** @addtogroup SRAM_Exported_Functions SRAM Exported Functions 134 * @{ 135 */ 136 137 /** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions 138 * @{ 139 */ 140 141 /* Initialization/de-initialization functions ********************************/ 142 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, 143 FMC_NORSRAM_TimingTypeDef *ExtTiming); 144 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram); 145 void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); 146 void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); 147 148 /** 149 * @} 150 */ 151 152 /** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions 153 * @{ 154 */ 155 156 /* I/O operation functions ***************************************************/ 157 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, 158 uint32_t BufferSize); 159 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, 160 uint32_t BufferSize); 161 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, 162 uint32_t BufferSize); 163 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, 164 uint32_t BufferSize); 165 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, 166 uint32_t BufferSize); 167 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, 168 uint32_t BufferSize); 169 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, 170 uint32_t BufferSize); 171 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, 172 uint32_t BufferSize); 173 174 void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); 175 void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); 176 177 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) 178 /* SRAM callback registering/unregistering */ 179 HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, 180 pSRAM_CallbackTypeDef pCallback); 181 HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId); 182 HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, 183 pSRAM_DmaCallbackTypeDef pCallback); 184 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ 185 186 /** 187 * @} 188 */ 189 190 /** @addtogroup SRAM_Exported_Functions_Group3 Control functions 191 * @{ 192 */ 193 194 /* SRAM Control functions ****************************************************/ 195 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram); 196 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); 197 198 /** 199 * @} 200 */ 201 202 /** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions 203 * @{ 204 */ 205 206 /* SRAM State functions ******************************************************/ 207 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); 208 209 /** 210 * @} 211 */ 212 213 /** 214 * @} 215 */ 216 217 /** 218 * @} 219 */ 220 221 /** 222 * @} 223 */ 224 225 226 #ifdef __cplusplus 227 } 228 #endif 229 230 #endif /* STM32F7xx_HAL_SRAM_H */ 231
