1 /** 2 ****************************************************************************** 3 * @file stm32f7xx_hal_eth.h 4 * @author MCD Application Team 5 * @brief Header file of ETH HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32F7xx_HAL_ETH_H 21 #define STM32F7xx_HAL_ETH_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32f7xx_hal_def.h" 30 31 #if defined(ETH) 32 33 /** @addtogroup STM32F7xx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup ETH 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 #ifndef ETH_TX_DESC_CNT 43 #define ETH_TX_DESC_CNT 4U 44 #endif /* ETH_TX_DESC_CNT */ 45 46 #ifndef ETH_RX_DESC_CNT 47 #define ETH_RX_DESC_CNT 4U 48 #endif /* ETH_RX_DESC_CNT */ 49 50 51 /*********************** Descriptors struct def section ************************/ 52 /** @defgroup ETH_Exported_Types ETH Exported Types 53 * @{ 54 */ 55 56 /** 57 * @brief ETH DMA Descriptor structure definition 58 */ 59 typedef struct 60 { 61 __IO uint32_t DESC0; 62 __IO uint32_t DESC1; 63 __IO uint32_t DESC2; 64 __IO uint32_t DESC3; 65 __IO uint32_t DESC4; 66 __IO uint32_t DESC5; 67 __IO uint32_t DESC6; 68 __IO uint32_t DESC7; 69 uint32_t BackupAddr0; /* used to store rx buffer 1 address */ 70 uint32_t BackupAddr1; /* used to store rx buffer 2 address */ 71 } ETH_DMADescTypeDef; 72 /** 73 * 74 */ 75 76 /** 77 * @brief ETH Buffers List structure definition 78 */ 79 typedef struct __ETH_BufferTypeDef 80 { 81 uint8_t *buffer; /*<! buffer address */ 82 83 uint32_t len; /*<! buffer length */ 84 85 struct __ETH_BufferTypeDef *next; /*<! Pointer to the next buffer in the list */ 86 } ETH_BufferTypeDef; 87 /** 88 * 89 */ 90 91 /** 92 * @brief DMA Transmit Descriptors Wrapper structure definition 93 */ 94 typedef struct 95 { 96 uint32_t TxDesc[ETH_TX_DESC_CNT]; /*<! Tx DMA descriptors addresses */ 97 98 uint32_t CurTxDesc; /*<! Current Tx descriptor index for packet transmission */ 99 100 uint32_t *PacketAddress[ETH_TX_DESC_CNT]; /*<! Ethernet packet addresses array */ 101 102 uint32_t *CurrentPacketAddress; /*<! Current transmit NX_PACKET addresses */ 103 104 uint32_t BuffersInUse; /*<! Buffers in Use */ 105 106 uint32_t releaseIndex; /*<! Release index */ 107 } ETH_TxDescListTypeDef; 108 /** 109 * 110 */ 111 112 /** 113 * @brief Transmit Packet Configuration structure definition 114 */ 115 typedef struct 116 { 117 uint32_t Attributes; /*!< Tx packet HW features capabilities. 118 This parameter can be a combination of @ref ETH_Tx_Packet_Attributes*/ 119 120 uint32_t Length; /*!< Total packet length */ 121 122 ETH_BufferTypeDef *TxBuffer; /*!< Tx buffers pointers */ 123 124 uint32_t SrcAddrCtrl; /*!< Specifies the source address insertion control. 125 This parameter can be a value of @ref ETH_Tx_Packet_Source_Addr_Control */ 126 127 uint32_t CRCPadCtrl; /*!< Specifies the CRC and Pad insertion and replacement control. 128 This parameter can be a value of @ref ETH_Tx_Packet_CRC_Pad_Control */ 129 130 uint32_t ChecksumCtrl; /*!< Specifies the checksum insertion control. 131 This parameter can be a value of @ref ETH_Tx_Packet_Checksum_Control */ 132 133 uint32_t MaxSegmentSize; /*!< Sets TCP maximum segment size only when TCP segmentation is enabled. 134 This parameter can be a value from 0x0 to 0x3FFF */ 135 136 uint32_t PayloadLen; /*!< Sets Total payload length only when TCP segmentation is enabled. 137 This parameter can be a value from 0x0 to 0x3FFFF */ 138 139 uint32_t TCPHeaderLen; /*!< Sets TCP header length only when TCP segmentation is enabled. 140 This parameter can be a value from 0x5 to 0xF */ 141 142 uint32_t VlanTag; /*!< Sets VLAN Tag only when VLAN is enabled. 143 This parameter can be a value from 0x0 to 0xFFFF*/ 144 145 uint32_t VlanCtrl; /*!< Specifies VLAN Tag insertion control only when VLAN is enabled. 146 This parameter can be a value of @ref ETH_Tx_Packet_VLAN_Control */ 147 148 uint32_t InnerVlanTag; /*!< Sets Inner VLAN Tag only when Inner VLAN is enabled. 149 This parameter can be a value from 0x0 to 0x3FFFF */ 150 151 uint32_t InnerVlanCtrl; /*!< Specifies Inner VLAN Tag insertion control only when Inner VLAN is enabled. 152 This parameter can be a value of @ref ETH_Tx_Packet_Inner_VLAN_Control */ 153 154 void *pData; /*!< Specifies Application packet pointer to save */ 155 156 } ETH_TxPacketConfig; 157 /** 158 * 159 */ 160 161 /** 162 * @brief ETH Timestamp structure definition 163 */ 164 typedef struct 165 { 166 uint32_t TimeStampLow; 167 uint32_t TimeStampHigh; 168 169 } ETH_TimeStampTypeDef; 170 /** 171 * 172 */ 173 174 /** 175 * @brief ETH Timeupdate structure definition 176 */ 177 typedef struct 178 { 179 uint32_t Seconds; 180 uint32_t NanoSeconds; 181 } ETH_TimeTypeDef; 182 /** 183 * 184 */ 185 186 /** 187 * @brief DMA Receive Descriptors Wrapper structure definition 188 */ 189 typedef struct 190 { 191 uint32_t RxDesc[ETH_RX_DESC_CNT]; /*<! Rx DMA descriptors addresses. */ 192 193 uint32_t ItMode; /*<! If 1, DMA will generate the Rx complete interrupt. 194 If 0, DMA will not generate the Rx complete interrupt. */ 195 196 uint32_t RxDescIdx; /*<! Current Rx descriptor. */ 197 198 uint32_t RxDescCnt; /*<! Number of descriptors . */ 199 200 uint32_t RxDataLength; /*<! Received Data Length. */ 201 202 uint32_t RxBuildDescIdx; /*<! Current Rx Descriptor for building descriptors. */ 203 204 uint32_t RxBuildDescCnt; /*<! Number of Rx Descriptors awaiting building. */ 205 206 uint32_t pRxLastRxDesc; /*<! Last received descriptor. */ 207 208 ETH_TimeStampTypeDef TimeStamp; /*<! Time Stamp Low value for receive. */ 209 210 void *pRxStart; /*<! Pointer to the first buff. */ 211 212 void *pRxEnd; /*<! Pointer to the last buff. */ 213 214 } ETH_RxDescListTypeDef; 215 /** 216 * 217 */ 218 219 /** 220 * @brief ETH MAC Configuration Structure definition 221 */ 222 typedef struct 223 { 224 uint32_t 225 SourceAddrControl; /*!< Selects the Source Address Insertion or Replacement Control. 226 This parameter can be a value of @ref ETH_Source_Addr_Control */ 227 228 FunctionalState 229 ChecksumOffload; /*!< Enables or Disable the checksum checking for received packet payloads TCP, UDP or ICMP headers */ 230 231 uint32_t InterPacketGapVal; /*!< Sets the minimum IPG between Packet during transmission. 232 This parameter can be a value of @ref ETH_Inter_Packet_Gap */ 233 234 FunctionalState GiantPacketSizeLimitControl; /*!< Enables or disables the Giant Packet Size Limit Control. */ 235 236 FunctionalState Support2KPacket; /*!< Enables or disables the IEEE 802.3as Support for 2K length Packets */ 237 238 FunctionalState CRCStripTypePacket; /*!< Enables or disables the CRC stripping for Type packets.*/ 239 240 FunctionalState AutomaticPadCRCStrip; /*!< Enables or disables the Automatic MAC Pad/CRC Stripping.*/ 241 242 FunctionalState Watchdog; /*!< Enables or disables the Watchdog timer on Rx path.*/ 243 244 FunctionalState Jabber; /*!< Enables or disables Jabber timer on Tx path.*/ 245 246 FunctionalState JumboPacket; /*!< Enables or disables receiving Jumbo Packet 247 When enabled, the MAC allows jumbo packets of 9,018 bytes 248 without reporting a giant packet error */ 249 250 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps. 251 This parameter can be a value of @ref ETH_Speed */ 252 253 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode 254 This parameter can be a value of @ref ETH_Duplex_Mode */ 255 256 FunctionalState LoopbackMode; /*!< Enables or disables the loopback mode */ 257 258 FunctionalState 259 CarrierSenseBeforeTransmit; /*!< Enables or disables the Carrier Sense Before Transmission in Full Duplex Mode. */ 260 261 FunctionalState ReceiveOwn; /*!< Enables or disables the Receive Own in Half Duplex mode. */ 262 263 FunctionalState 264 CarrierSenseDuringTransmit; /*!< Enables or disables the Carrier Sense During Transmission in the Half Duplex mode */ 265 266 FunctionalState 267 RetryTransmission; /*!< Enables or disables the MAC retry transmission, when a collision occurs in Half Duplex mode.*/ 268 269 uint32_t BackOffLimit; /*!< Selects the BackOff limit value. 270 This parameter can be a value of @ref ETH_Back_Off_Limit */ 271 272 FunctionalState 273 DeferralCheck; /*!< Enables or disables the deferral check function in Half Duplex mode. */ 274 275 uint32_t 276 PreambleLength; /*!< Selects or not the Preamble Length for Transmit packets (Full Duplex mode). 277 This parameter can be a value of @ref ETH_Preamble_Length */ 278 279 FunctionalState SlowProtocolDetect; /*!< Enable or disables the Slow Protocol Detection. */ 280 281 FunctionalState CRCCheckingRxPackets; /*!< Enable or disables the CRC Checking for Received Packets. */ 282 283 uint32_t 284 GiantPacketSizeLimit; /*!< Specifies the packet size that the MAC will declare it as Giant, If it's size is 285 greater than the value programmed in this field in units of bytes 286 This parameter must be a number between 287 Min_Data = 0x618 (1518 byte) and Max_Data = 0x3FFF (32 Kbyte). */ 288 289 FunctionalState ExtendedInterPacketGap; /*!< Enable or disables the extended inter packet gap. */ 290 291 uint32_t ExtendedInterPacketGapVal; /*!< Sets the Extended IPG between Packet during transmission. 292 This parameter can be a value from 0x0 to 0xFF */ 293 294 FunctionalState ProgrammableWatchdog; /*!< Enable or disables the Programmable Watchdog.*/ 295 296 uint32_t WatchdogTimeout; /*!< This field is used as watchdog timeout for a received packet 297 This parameter can be a value of @ref ETH_Watchdog_Timeout */ 298 299 uint32_t 300 PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control packet. 301 This parameter must be a number between 302 Min_Data = 0x0 and Max_Data = 0xFFFF.*/ 303 304 FunctionalState 305 ZeroQuantaPause; /*!< Enable or disables the automatic generation of Zero Quanta Pause Control packets.*/ 306 307 uint32_t 308 PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Packet. 309 This parameter can be a value of @ref ETH_Pause_Low_Threshold */ 310 311 FunctionalState 312 TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause packets in Full Duplex mode 313 or the MAC back pressure operation in Half Duplex mode */ 314 315 FunctionalState 316 UnicastPausePacketDetect; /*!< Enables or disables the MAC to detect Pause packets with unicast address of the station */ 317 318 FunctionalState ReceiveFlowControl; /*!< Enables or disables the MAC to decodes the received Pause packet 319 and disables its transmitter for a specified (Pause) time */ 320 321 uint32_t TransmitQueueMode; /*!< Specifies the Transmit Queue operating mode. 322 This parameter can be a value of @ref ETH_Transmit_Mode */ 323 324 uint32_t ReceiveQueueMode; /*!< Specifies the Receive Queue operating mode. 325 This parameter can be a value of @ref ETH_Receive_Mode */ 326 327 FunctionalState DropTCPIPChecksumErrorPacket; /*!< Enables or disables Dropping of TCPIP Checksum Error Packets. */ 328 329 FunctionalState ForwardRxErrorPacket; /*!< Enables or disables forwarding Error Packets. */ 330 331 FunctionalState ForwardRxUndersizedGoodPacket; /*!< Enables or disables forwarding Undersized Good Packets.*/ 332 } ETH_MACConfigTypeDef; 333 /** 334 * 335 */ 336 337 /** 338 * @brief ETH DMA Configuration Structure definition 339 */ 340 typedef struct 341 { 342 uint32_t DMAArbitration; /*!< Sets the arbitration scheme between DMA Tx and Rx 343 This parameter can be a value of @ref ETH_DMA_Arbitration */ 344 345 FunctionalState AddressAlignedBeats; /*!< Enables or disables the AHB Master interface address aligned 346 burst transfers on Read and Write channels */ 347 348 uint32_t BurstMode; /*!< Sets the AHB Master interface burst transfers. 349 This parameter can be a value of @ref ETH_Burst_Mode */ 350 351 FunctionalState DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames */ 352 353 FunctionalState ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode */ 354 355 FunctionalState TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode */ 356 357 358 uint32_t 359 TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction. 360 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ 361 362 uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control. 363 This parameter can be a value of 364 @ref ETH_Transmit_Threshold_Control */ 365 366 uint32_t 367 RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction. 368 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ 369 370 FunctionalState ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames */ 371 FunctionalState FlushRxPacket; /*!< Enables or disables the Rx Packet Flush */ 372 373 FunctionalState 374 ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error 375 and length less than 64 bytes) 376 including pad-bytes and CRC) */ 377 378 uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO. 379 This parameter can be a value of 380 @ref ETH_Receive_Threshold_Control */ 381 382 FunctionalState 383 SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second 384 frame of Transmit data even before obtaining 385 the status for the first frame */ 386 387 FunctionalState EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format */ 388 389 uint32_t 390 DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) 391 This parameter must be a number between 392 Min_Data = 0 and Max_Data = 32 */ 393 } ETH_DMAConfigTypeDef; 394 /** 395 * 396 */ 397 398 /** 399 * @brief HAL ETH Media Interfaces enum definition 400 */ 401 typedef enum 402 { 403 HAL_ETH_MII_MODE = 0x00U, /*!< Media Independent Interface */ 404 HAL_ETH_RMII_MODE = SYSCFG_PMC_MII_RMII_SEL /*!< Reduced Media Independent Interface */ 405 } ETH_MediaInterfaceTypeDef; 406 /** 407 * 408 */ 409 410 /** 411 * @brief HAL ETH PTP Update type enum definition 412 */ 413 typedef enum 414 { 415 HAL_ETH_PTP_POSITIVE_UPDATE = 0x00000000U, /*!< PTP positive time update */ 416 HAL_ETH_PTP_NEGATIVE_UPDATE = 0x00000001U /*!< PTP negative time update */ 417 } ETH_PtpUpdateTypeDef; 418 /** 419 * 420 */ 421 422 /** 423 * @brief ETH Init Structure definition 424 */ 425 typedef struct 426 { 427 428 uint8_t 429 *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */ 430 431 ETH_MediaInterfaceTypeDef MediaInterface; /*!< Selects the MII interface or the RMII interface. */ 432 433 ETH_DMADescTypeDef 434 *TxDesc; /*!< Provides the address of the first DMA Tx descriptor in the list */ 435 436 ETH_DMADescTypeDef 437 *RxDesc; /*!< Provides the address of the first DMA Rx descriptor in the list */ 438 439 uint32_t RxBuffLen; /*!< Provides the length of Rx buffers size */ 440 441 } ETH_InitTypeDef; 442 /** 443 * 444 */ 445 446 /** 447 * @brief ETH PTP Init Structure definition 448 */ 449 typedef struct 450 { 451 uint32_t Timestamp; /*!< Enable Timestamp */ 452 uint32_t TimestampUpdateMode; /*!< Fine or Coarse Timestamp Update */ 453 uint32_t TimestampInitialize; /*!< Initialize Timestamp */ 454 uint32_t TimestampUpdate; /*!< Timestamp Update */ 455 uint32_t TimestampAddendUpdate; /*!< Timestamp Addend Update */ 456 uint32_t TimestampAll; /*!< Enable Timestamp for All Packets */ 457 uint32_t TimestampRolloverMode; /*!< Timestamp Digital or Binary Rollover Control */ 458 uint32_t TimestampV2; /*!< Enable PTP Packet Processing for Version 2 Format */ 459 uint32_t TimestampEthernet; /*!< Enable Processing of PTP over Ethernet Packets */ 460 uint32_t TimestampIPv6; /*!< Enable Processing of PTP Packets Sent over IPv6-UDP */ 461 uint32_t TimestampIPv4; /*!< Enable Processing of PTP Packets Sent over IPv4-UDP */ 462 uint32_t TimestampEvent; /*!< Enable Timestamp Snapshot for Event Messages */ 463 uint32_t TimestampMaster; /*!< Enable Timestamp Snapshot for Event Messages */ 464 uint32_t TimestampFilter; /*!< Enable MAC Address for PTP Packet Filtering */ 465 uint32_t TimestampClockType; /*!< Time stamp clock node type */ 466 uint32_t TimestampAddend; /*!< Timestamp addend value */ 467 uint32_t TimestampSubsecondInc; /*!< Subsecond Increment */ 468 469 } ETH_PTP_ConfigTypeDef; 470 /** 471 * 472 */ 473 474 /** 475 * @brief HAL State structures definition 476 */ 477 typedef uint32_t HAL_ETH_StateTypeDef; 478 /** 479 * 480 */ 481 482 /** 483 * @brief HAL ETH Rx Get Buffer Function definition 484 */ 485 typedef void (*pETH_rxAllocateCallbackTypeDef)(uint8_t **buffer); /*!< pointer to an ETH Rx Get Buffer Function */ 486 /** 487 * 488 */ 489 490 /** 491 * @brief HAL ETH Rx Set App Data Function definition 492 */ 493 typedef void (*pETH_rxLinkCallbackTypeDef)(void **pStart, void **pEnd, uint8_t *buff, 494 uint16_t Length); /*!< pointer to an ETH Rx Set App Data Function */ 495 /** 496 * 497 */ 498 499 /** 500 * @brief HAL ETH Tx Free Function definition 501 */ 502 typedef void (*pETH_txFreeCallbackTypeDef)(uint32_t *buffer); /*!< pointer to an ETH Tx Free function */ 503 /** 504 * 505 */ 506 507 /** 508 * @brief HAL ETH Tx Free Function definition 509 */ 510 typedef void (*pETH_txPtpCallbackTypeDef)(uint32_t *buffer, 511 ETH_TimeStampTypeDef *timestamp); /*!< pointer to an ETH Tx Free function */ 512 /** 513 * 514 */ 515 516 /** 517 * @brief ETH Handle Structure definition 518 */ 519 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 520 typedef struct __ETH_HandleTypeDef 521 #else 522 typedef struct 523 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 524 { 525 ETH_TypeDef *Instance; /*!< Register base address */ 526 527 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */ 528 529 ETH_TxDescListTypeDef TxDescList; /*!< Tx descriptor wrapper: holds all Tx descriptors list 530 addresses and current descriptor index */ 531 532 ETH_RxDescListTypeDef RxDescList; /*!< Rx descriptor wrapper: holds all Rx descriptors list 533 addresses and current descriptor index */ 534 535 #ifdef HAL_ETH_USE_PTP 536 ETH_TimeStampTypeDef TxTimestamp; /*!< Tx Timestamp */ 537 #endif /* HAL_ETH_USE_PTP */ 538 539 __IO HAL_ETH_StateTypeDef gState; /*!< ETH state information related to global Handle management 540 and also related to Tx operations. This parameter can 541 be a value of @ref HAL_ETH_StateTypeDef */ 542 543 __IO uint32_t ErrorCode; /*!< Holds the global Error code of the ETH HAL status machine 544 This parameter can be a value of @ref ETH_Error_Code.*/ 545 546 __IO uint32_t 547 DMAErrorCode; /*!< Holds the DMA Rx Tx Error code when a DMA AIS interrupt occurs 548 This parameter can be a combination of 549 @ref ETH_DMA_Status_Flags */ 550 551 __IO uint32_t 552 MACErrorCode; /*!< Holds the MAC Rx Tx Error code when a MAC Rx or Tx status interrupt occurs 553 This parameter can be a combination of 554 @ref ETH_MAC_Rx_Tx_Status */ 555 556 __IO uint32_t MACWakeUpEvent; /*!< Holds the Wake Up event when the MAC exit the power down mode 557 This parameter can be a value of 558 @ref ETH_MAC_Wake_Up_Event */ 559 560 __IO uint32_t MACLPIEvent; /*!< Holds the LPI event when the an LPI status interrupt occurs. 561 This parameter can be a value of @ref ETHEx_LPI_Event */ 562 563 __IO uint32_t IsPtpConfigured; /*!< Holds the PTP configuration status. 564 This parameter can be a value of 565 @ref ETH_PTP_Config_Status */ 566 567 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 568 569 void (* TxCpltCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Tx Complete Callback */ 570 void (* RxCpltCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Rx Complete Callback */ 571 void (* ErrorCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Error Callback */ 572 void (* PMTCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Power Management Callback */ 573 void (* WakeUpCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Wake UP Callback */ 574 575 void (* MspInitCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Msp Init callback */ 576 void (* MspDeInitCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Msp DeInit callback */ 577 578 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 579 580 pETH_rxAllocateCallbackTypeDef rxAllocateCallback; /*!< ETH Rx Get Buffer Function */ 581 pETH_rxLinkCallbackTypeDef rxLinkCallback; /*!< ETH Rx Set App Data Function */ 582 pETH_txFreeCallbackTypeDef txFreeCallback; /*!< ETH Tx Free Function */ 583 pETH_txPtpCallbackTypeDef txPtpCallback; /*!< ETH Tx Handle Ptp Function */ 584 585 } ETH_HandleTypeDef; 586 /** 587 * 588 */ 589 590 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 591 /** 592 * @brief HAL ETH Callback ID enumeration definition 593 */ 594 typedef enum 595 { 596 HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */ 597 HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */ 598 599 HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */ 600 HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */ 601 HAL_ETH_ERROR_CB_ID = 0x04U, /*!< ETH Error Callback ID */ 602 HAL_ETH_PMT_CB_ID = 0x06U, /*!< ETH Power Management Callback ID */ 603 HAL_ETH_WAKEUP_CB_ID = 0x08U /*!< ETH Wake UP Callback ID */ 604 605 606 } HAL_ETH_CallbackIDTypeDef; 607 608 /** 609 * @brief HAL ETH Callback pointer definition 610 */ 611 typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef *heth); /*!< pointer to an ETH callback function */ 612 613 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 614 615 /** 616 * @brief ETH MAC filter structure definition 617 */ 618 typedef struct 619 { 620 FunctionalState PromiscuousMode; /*!< Enable or Disable Promiscuous Mode */ 621 622 FunctionalState ReceiveAllMode; /*!< Enable or Disable Receive All Mode */ 623 624 FunctionalState HachOrPerfectFilter; /*!< Enable or Disable Perfect filtering in addition to Hash filtering */ 625 626 FunctionalState HashUnicast; /*!< Enable or Disable Hash filtering on unicast packets */ 627 628 FunctionalState HashMulticast; /*!< Enable or Disable Hash filtering on multicast packets */ 629 630 FunctionalState PassAllMulticast; /*!< Enable or Disable passing all multicast packets */ 631 632 FunctionalState SrcAddrFiltering; /*!< Enable or Disable source address filtering module */ 633 634 FunctionalState SrcAddrInverseFiltering; /*!< Enable or Disable source address inverse filtering */ 635 636 FunctionalState DestAddrInverseFiltering; /*!< Enable or Disable destination address inverse filtering */ 637 638 FunctionalState BroadcastFilter; /*!< Enable or Disable broadcast filter */ 639 640 uint32_t ControlPacketsFilter; /*!< Set the control packets filter 641 This parameter can be a value of @ref ETH_Control_Packets_Filter */ 642 } ETH_MACFilterConfigTypeDef; 643 /** 644 * 645 */ 646 647 /** 648 * @brief ETH Power Down structure definition 649 */ 650 typedef struct 651 { 652 FunctionalState WakeUpPacket; /*!< Enable or Disable Wake up packet detection in power down mode */ 653 654 FunctionalState MagicPacket; /*!< Enable or Disable Magic packet detection in power down mode */ 655 656 FunctionalState GlobalUnicast; /*!< Enable or Disable Global unicast packet detection in power down mode */ 657 658 FunctionalState WakeUpForward; /*!< Enable or Disable Forwarding Wake up packets */ 659 660 } ETH_PowerDownConfigTypeDef; 661 /** 662 * 663 */ 664 665 /** 666 * @} 667 */ 668 669 /* Exported constants --------------------------------------------------------*/ 670 /** @defgroup ETH_Exported_Constants ETH Exported Constants 671 * @{ 672 */ 673 674 /** @defgroup ETH_DMA_Tx_Descriptor_Bit_Definition ETH DMA Tx Descriptor Bit Definition 675 * @{ 676 */ 677 678 /* 679 DMA Tx Normal Descriptor Read Format 680 ----------------------------------------------------------------------------------------------- 681 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | 682 ----------------------------------------------------------------------------------------------- 683 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | 684 ----------------------------------------------------------------------------------------------- 685 TDES2 | Buffer1 Address [31:0] | 686 ----------------------------------------------------------------------------------------------- 687 TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | 688 ----------------------------------------------------------------------------------------------- 689 */ 690 691 /** 692 * @brief Bit definition of TDES0 register: DMA Tx descriptor status register 693 */ 694 #define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ 695 #define ETH_DMATXDESC_IC 0x40000000U /*!< Interrupt on Completion */ 696 #define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */ 697 #define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */ 698 #define ETH_DMATXDESC_DC 0x08000000U /*!< Disable CRC */ 699 #define ETH_DMATXDESC_DP 0x04000000U /*!< Disable Padding */ 700 #define ETH_DMATXDESC_TTSE 0x02000000U /*!< Transmit Time Stamp Enable */ 701 #define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */ 702 #define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */ 703 #define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */ 704 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ 705 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ 706 #define ETH_DMATXDESC_TER 0x00200000U /*!< Transmit End of Ring */ 707 #define ETH_DMATXDESC_TCH 0x00100000U /*!< Second Address Chained */ 708 #define ETH_DMATXDESC_TTSS 0x00020000U /*!< Tx Time Stamp Status */ 709 #define ETH_DMATXDESC_IHE 0x00010000U /*!< IP Header Error */ 710 #define ETH_DMATXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ 711 #define ETH_DMATXDESC_JT 0x00004000U /*!< Jabber Timeout */ 712 #define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ 713 #define ETH_DMATXDESC_PCE 0x00001000U /*!< Payload Checksum Error */ 714 #define ETH_DMATXDESC_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */ 715 #define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */ 716 #define ETH_DMATXDESC_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */ 717 #define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */ 718 #define ETH_DMATXDESC_VF 0x00000080U /*!< VLAN Frame */ 719 #define ETH_DMATXDESC_CC 0x00000078U /*!< Collision Count */ 720 #define ETH_DMATXDESC_ED 0x00000004U /*!< Excessive Deferral */ 721 #define ETH_DMATXDESC_UF 0x00000002U /*!< Underflow Error: late data arrival from the memory */ 722 #define ETH_DMATXDESC_DB 0x00000001U /*!< Deferred Bit */ 723 724 /** 725 * @brief Bit definition of TDES1 register 726 */ 727 #define ETH_DMATXDESC_TBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */ 728 #define ETH_DMATXDESC_TBS1 0x00001FFFU /*!< Transmit Buffer1 Size */ 729 730 /** 731 * @brief Bit definition of TDES2 register 732 */ 733 #define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ 734 735 /** 736 * @brief Bit definition of TDES3 register 737 */ 738 #define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ 739 740 /*--------------------------------------------------------------------------------------------- 741 TDES6 | Transmit Time Stamp Low [31:0] | 742 ----------------------------------------------------------------------------------------------- 743 TDES7 | Transmit Time Stamp High [31:0] | 744 ----------------------------------------------------------------------------------------------*/ 745 746 /* Bit definition of TDES6 register */ 747 #define ETH_DMAPTPTXDESC_TTSL 0xFFFFFFFFU /* Transmit Time Stamp Low */ 748 749 /* Bit definition of TDES7 register */ 750 #define ETH_DMAPTPTXDESC_TTSH 0xFFFFFFFFU /* Transmit Time Stamp High */ 751 752 /** 753 * @} 754 */ 755 756 757 /** @defgroup ETH_DMA_Rx_Descriptor_Bit_Definition ETH DMA Rx Descriptor Bit Definition 758 * @{ 759 */ 760 761 /* 762 DMA Rx Normal Descriptor read format 763 -------------------------------------------------------------------------------------------------------------------- 764 RDES0 | OWN(31) | Status [30:0] | 765 --------------------------------------------------------------------------------------------------------------------- 766 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | 767 --------------------------------------------------------------------------------------------------------------------- 768 RDES2 | Buffer1 Address [31:0] | 769 --------------------------------------------------------------------------------------------------------------------- 770 RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | 771 --------------------------------------------------------------------------------------------------------------------- 772 */ 773 774 /** 775 * @brief Bit definition of RDES0 register: DMA Rx descriptor status register 776 */ 777 #define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ 778 #define ETH_DMARXDESC_AFM 0x40000000U /*!< DA Filter Fail for the rx frame */ 779 #define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */ 780 #define ETH_DMARXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ 781 #define ETH_DMARXDESC_DE 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */ 782 #define ETH_DMARXDESC_SAF 0x00002000U /*!< SA Filter Fail for the received frame */ 783 #define ETH_DMARXDESC_LE 0x00001000U /*!< Frame size not matching with length field */ 784 #define ETH_DMARXDESC_OE 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */ 785 #define ETH_DMARXDESC_VLAN 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */ 786 #define ETH_DMARXDESC_FS 0x00000200U /*!< First descriptor of the frame */ 787 #define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */ 788 #define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ 789 #define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */ 790 #define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */ 791 #define ETH_DMARXDESC_RWT 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ 792 #define ETH_DMARXDESC_RE 0x00000008U /*!< Receive error: error reported by MII interface */ 793 #define ETH_DMARXDESC_DBE 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */ 794 #define ETH_DMARXDESC_CE 0x00000002U /*!< CRC error */ 795 #define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ 796 797 /** 798 * @brief Bit definition of RDES1 register 799 */ 800 #define ETH_DMARXDESC_DIC 0x80000000U /*!< Disable Interrupt on Completion */ 801 #define ETH_DMARXDESC_RBS2 0x1FFF0000U /*!< Receive Buffer2 Size */ 802 #define ETH_DMARXDESC_RER 0x00008000U /*!< Receive End of Ring */ 803 #define ETH_DMARXDESC_RCH 0x00004000U /*!< Second Address Chained */ 804 #define ETH_DMARXDESC_RBS1 0x00001FFFU /*!< Receive Buffer1 Size */ 805 806 /** 807 * @brief Bit definition of RDES2 register 808 */ 809 #define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ 810 811 /** 812 * @brief Bit definition of RDES3 register 813 */ 814 #define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ 815 816 /*--------------------------------------------------------------------------------------------------------------------- 817 RDES4 | Reserved[31:15] | Extended Status [14:0] | 818 --------------------------------------------------------------------------------------------------------------------- 819 RDES5 | Reserved[31:0] | 820 --------------------------------------------------------------------------------------------------------------------- 821 RDES6 | Receive Time Stamp Low [31:0] | 822 --------------------------------------------------------------------------------------------------------------------- 823 RDES7 | Receive Time Stamp High [31:0] | 824 --------------------------------------------------------------------------------------------------------------------*/ 825 826 /* Bit definition of RDES4 register */ 827 #define ETH_DMAPTPRXDESC_PTPV 0x00002000U /* PTP Version */ 828 #define ETH_DMAPTPRXDESC_PTPFT 0x00001000U /* PTP Frame Type */ 829 #define ETH_DMAPTPRXDESC_PTPMT 0x00000F00U /* PTP Message Type */ 830 #define ETH_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message 831 (all clock types) */ 832 #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message 833 (all clock types) */ 834 #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message 835 (all clock types) */ 836 #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message 837 (all clock types) */ 838 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message 839 (peer-to-peer transparent clock) 840 or Announce message (Ordinary 841 or Boundary clock) */ 842 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message 843 (peer-to-peer transparent clock) 844 or Management message (Ordinary 845 or Boundary clock) */ 846 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message 847 (peer-to-peer transparent clock) 848 or Signaling message (Ordinary 849 or Boundary clock) */ 850 #define ETH_DMAPTPRXDESC_IPV6PR 0x00000080U /* IPv6 Packet Received */ 851 #define ETH_DMAPTPRXDESC_IPV4PR 0x00000040U /* IPv4 Packet Received */ 852 #define ETH_DMAPTPRXDESC_IPCB 0x00000020U /* IP Checksum Bypassed */ 853 #define ETH_DMAPTPRXDESC_IPPE 0x00000010U /* IP Payload Error */ 854 #define ETH_DMAPTPRXDESC_IPHE 0x00000008U /* IP Header Error */ 855 #define ETH_DMAPTPRXDESC_IPPT 0x00000007U /* IP Payload Type */ 856 #define ETH_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in 857 the IP datagram */ 858 #define ETH_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in 859 the IP datagram */ 860 #define ETH_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in 861 the IP datagram */ 862 863 /* Bit definition of RDES6 register */ 864 #define ETH_DMAPTPRXDESC_RTSL 0xFFFFFFFFU /* Receive Time Stamp Low */ 865 866 /* Bit definition of RDES7 register */ 867 #define ETH_DMAPTPRXDESC_RTSH 0xFFFFFFFFU /* Receive Time Stamp High */ 868 869 /** 870 * @} 871 */ 872 873 /** @defgroup ETH_Frame_settings ETH frame settings 874 * @{ 875 */ 876 #define ETH_MAX_PACKET_SIZE 1528U /*!< ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */ 877 #define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ 878 #define ETH_CRC 4U /*!< Ethernet CRC */ 879 #define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */ 880 #define ETH_MIN_PAYLOAD 46U /*!< Minimum Ethernet payload size */ 881 #define ETH_MAX_PAYLOAD 1500U /*!< Maximum Ethernet payload size */ 882 #define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */ 883 /** 884 * @} 885 */ 886 887 /** @defgroup ETH_Error_Code ETH Error Code 888 * @{ 889 */ 890 #define HAL_ETH_ERROR_NONE 0x00000000U /*!< No error */ 891 #define HAL_ETH_ERROR_PARAM 0x00000001U /*!< Busy error */ 892 #define HAL_ETH_ERROR_BUSY 0x00000002U /*!< Parameter error */ 893 #define HAL_ETH_ERROR_TIMEOUT 0x00000004U /*!< Timeout error */ 894 #define HAL_ETH_ERROR_DMA 0x00000008U /*!< DMA transfer error */ 895 #define HAL_ETH_ERROR_MAC 0x00000010U /*!< MAC transfer error */ 896 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 897 #define HAL_ETH_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */ 898 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 899 /** 900 * @} 901 */ 902 903 /** @defgroup ETH_Tx_Packet_Attributes ETH Tx Packet Attributes 904 * @{ 905 */ 906 #define ETH_TX_PACKETS_FEATURES_CSUM 0x00000001U 907 #define ETH_TX_PACKETS_FEATURES_SAIC 0x00000002U 908 #define ETH_TX_PACKETS_FEATURES_VLANTAG 0x00000004U 909 #define ETH_TX_PACKETS_FEATURES_INNERVLANTAG 0x00000008U 910 #define ETH_TX_PACKETS_FEATURES_TSO 0x00000010U 911 #define ETH_TX_PACKETS_FEATURES_CRCPAD 0x00000020U 912 /** 913 * @} 914 */ 915 916 /** @defgroup ETH_Tx_Packet_Source_Addr_Control ETH Tx Packet Source Addr Control 917 * @{ 918 */ 919 #define ETH_SRC_ADDR_CONTROL_DISABLE ETH_DMATXNDESCRF_SAIC_DISABLE 920 #define ETH_SRC_ADDR_INSERT ETH_DMATXNDESCRF_SAIC_INSERT 921 #define ETH_SRC_ADDR_REPLACE ETH_DMATXNDESCRF_SAIC_REPLACE 922 /** 923 * @} 924 */ 925 926 /** @defgroup ETH_Tx_Packet_CRC_Pad_Control ETH Tx Packet CRC Pad Control 927 * @{ 928 */ 929 #define ETH_CRC_PAD_DISABLE (uint32_t)(ETH_DMATXDESC_DP | ETH_DMATXDESC_DC) 930 #define ETH_CRC_PAD_INSERT 0x00000000U 931 #define ETH_CRC_INSERT ETH_DMATXDESC_DP 932 /** 933 * @} 934 */ 935 936 /** @defgroup ETH_Tx_Packet_Checksum_Control ETH Tx Packet Checksum Control 937 * @{ 938 */ 939 #define ETH_CHECKSUM_DISABLE ETH_DMATXDESC_CIC_BYPASS 940 #define ETH_CHECKSUM_IPHDR_INSERT ETH_DMATXDESC_CIC_IPV4HEADER 941 #define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 942 #define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 943 /** 944 * @} 945 */ 946 947 /** @defgroup ETH_Tx_Packet_VLAN_Control ETH Tx Packet VLAN Control 948 * @{ 949 */ 950 #define ETH_VLAN_DISABLE ETH_DMATXNDESCRF_VTIR_DISABLE 951 #define ETH_VLAN_REMOVE ETH_DMATXNDESCRF_VTIR_REMOVE 952 #define ETH_VLAN_INSERT ETH_DMATXNDESCRF_VTIR_INSERT 953 #define ETH_VLAN_REPLACE ETH_DMATXNDESCRF_VTIR_REPLACE 954 /** 955 * @} 956 */ 957 958 /** @defgroup ETH_Tx_Packet_Inner_VLAN_Control ETH Tx Packet Inner VLAN Control 959 * @{ 960 */ 961 #define ETH_INNER_VLAN_DISABLE ETH_DMATXCDESC_IVTIR_DISABLE 962 #define ETH_INNER_VLAN_REMOVE ETH_DMATXCDESC_IVTIR_REMOVE 963 #define ETH_INNER_VLAN_INSERT ETH_DMATXCDESC_IVTIR_INSERT 964 #define ETH_INNER_VLAN_REPLACE ETH_DMATXCDESC_IVTIR_REPLACE 965 /** 966 * @} 967 */ 968 969 970 /** @defgroup ETH_Rx_MAC_Filter_Status ETH Rx MAC Filter Status 971 * @{ 972 */ 973 #define ETH_VLAN_FILTER_PASS ETH_DMARXDESC_VLAN 974 #define ETH_DEST_ADDRESS_FAIL ETH_DMARXDESC_AFM 975 #define ETH_SOURCE_ADDRESS_FAIL ETH_DMARXDESC_SAF 976 /** 977 * @} 978 */ 979 980 /** @defgroup ETH_Rx_Error_Code ETH Rx Error Code 981 * @{ 982 */ 983 #define ETH_DRIBBLE_BIT_ERROR ETH_DMARXDESC_DBE 984 #define ETH_RECEIVE_ERROR ETH_DMARXDESC_RE 985 #define ETH_RECEIVE_OVERFLOW ETH_DMARXDESC_OE 986 #define ETH_WATCHDOG_TIMEOUT ETH_DMARXDESC_RWT 987 #define ETH_GIANT_PACKET ETH_DMARXDESC_IPV4HC 988 #define ETH_CRC_ERROR ETH_DMARXDESC_CE 989 /** 990 * @} 991 */ 992 993 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration 994 * @{ 995 */ 996 #define ETH_DMAARBITRATION_RX ETH_DMAMR_DA 997 #define ETH_DMAARBITRATION_RX1_TX1 0x00000000U 998 #define ETH_DMAARBITRATION_RX2_TX1 ETH_DMAMR_PR_2_1 999 #define ETH_DMAARBITRATION_RX3_TX1 ETH_DMAMR_PR_3_1 1000 #define ETH_DMAARBITRATION_RX4_TX1 ETH_DMAMR_PR_4_1 1001 #define ETH_DMAARBITRATION_RX5_TX1 ETH_DMAMR_PR_5_1 1002 #define ETH_DMAARBITRATION_RX6_TX1 ETH_DMAMR_PR_6_1 1003 #define ETH_DMAARBITRATION_RX7_TX1 ETH_DMAMR_PR_7_1 1004 #define ETH_DMAARBITRATION_RX8_TX1 ETH_DMAMR_PR_8_1 1005 #define ETH_DMAARBITRATION_TX (ETH_DMAMR_TXPR | ETH_DMAMR_DA) 1006 #define ETH_DMAARBITRATION_TX1_RX1 0x00000000U 1007 #define ETH_DMAARBITRATION_TX2_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_2_1) 1008 #define ETH_DMAARBITRATION_TX3_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_3_1) 1009 #define ETH_DMAARBITRATION_TX4_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_4_1) 1010 #define ETH_DMAARBITRATION_TX5_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_5_1) 1011 #define ETH_DMAARBITRATION_TX6_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_6_1) 1012 #define ETH_DMAARBITRATION_TX7_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_7_1) 1013 #define ETH_DMAARBITRATION_TX8_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_8_1) 1014 /** 1015 * @} 1016 */ 1017 1018 /** @defgroup ETH_Burst_Mode ETH Burst Mode 1019 * @{ 1020 */ 1021 #define ETH_BURSTLENGTH_FIXED ETH_DMABMR_FB 1022 #define ETH_BURSTLENGTH_MIXED ETH_DMABMR_MB 1023 #define ETH_BURSTLENGTH_UNSPECIFIED 0x00000000U 1024 /** 1025 * @} 1026 */ 1027 1028 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length 1029 * @{ 1030 */ 1031 #define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ 1032 #define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ 1033 #define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 1034 #define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 1035 #define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 1036 #define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 1037 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 1038 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 1039 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 1040 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 1041 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ 1042 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ 1043 /** 1044 * @} 1045 */ 1046 1047 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length 1048 * @{ 1049 */ 1050 #define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ 1051 #define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ 1052 #define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ 1053 #define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ 1054 #define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ 1055 #define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ 1056 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ 1057 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ 1058 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ 1059 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ 1060 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ 1061 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ 1062 /** 1063 * @} 1064 */ 1065 1066 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts 1067 * @{ 1068 */ 1069 #define ETH_DMA_NORMAL_IT ETH_DMACIER_NIE 1070 #define ETH_DMA_ABNORMAL_IT ETH_DMACIER_AIE 1071 #define ETH_DMA_CONTEXT_DESC_ERROR_IT ETH_DMACIER_CDEE 1072 #define ETH_DMA_FATAL_BUS_ERROR_IT ETH_DMACIER_FBEE 1073 #define ETH_DMA_EARLY_RX_IT ETH_DMACIER_ERIE 1074 #define ETH_DMA_EARLY_TX_IT ETH_DMACIER_ETIE 1075 #define ETH_DMA_RX_WATCHDOG_TIMEOUT_IT ETH_DMACIER_RWTE 1076 #define ETH_DMA_RX_PROCESS_STOPPED_IT ETH_DMACIER_RSE 1077 #define ETH_DMA_RX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_RBUE 1078 #define ETH_DMA_RX_IT ETH_DMACIER_RIE 1079 #define ETH_DMA_TX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_TBUE 1080 #define ETH_DMA_TX_PROCESS_STOPPED_IT ETH_DMACIER_TXSE 1081 #define ETH_DMA_TX_IT ETH_DMACIER_TIE 1082 /** 1083 * @} 1084 */ 1085 1086 /** @defgroup ETH_DMA_Status_Flags ETH DMA Status Flags 1087 * @{ 1088 */ 1089 #define ETH_DMA_RX_NO_ERROR_FLAG 0x00000000U 1090 #define ETH_DMA_RX_DESC_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1 | ETH_DMACSR_REB_BIT_0) 1091 #define ETH_DMA_RX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1) 1092 #define ETH_DMA_RX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_0) 1093 #define ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_REB_BIT_2 1094 #define ETH_DMA_TX_NO_ERROR_FLAG 0x00000000U 1095 #define ETH_DMA_TX_DESC_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1 | ETH_DMACSR_TEB_BIT_0) 1096 #define ETH_DMA_TX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1) 1097 #define ETH_DMA_TX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_0) 1098 #define ETH_DMA_TX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_TEB_BIT_2 1099 #define ETH_DMA_CONTEXT_DESC_ERROR_FLAG ETH_DMACSR_CDE 1100 #define ETH_DMA_FATAL_BUS_ERROR_FLAG ETH_DMACSR_FBE 1101 #define ETH_DMA_EARLY_TX_IT_FLAG ETH_DMACSR_ERI 1102 #define ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG ETH_DMACSR_RWT 1103 #define ETH_DMA_RX_PROCESS_STOPPED_FLAG ETH_DMACSR_RPS 1104 #define ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG ETH_DMACSR_RBU 1105 #define ETH_DMA_TX_PROCESS_STOPPED_FLAG ETH_DMACSR_TPS 1106 /** 1107 * @} 1108 */ 1109 1110 /** @defgroup ETH_Transmit_Mode ETH Transmit Mode 1111 * @{ 1112 */ 1113 #define ETH_TRANSMITSTOREFORWARD ETH_MTLTQOMR_TSF 1114 #define ETH_TRANSMITTHRESHOLD_32 ETH_MTLTQOMR_TTC_32BITS 1115 #define ETH_TRANSMITTHRESHOLD_64 ETH_MTLTQOMR_TTC_64BITS 1116 #define ETH_TRANSMITTHRESHOLD_96 ETH_MTLTQOMR_TTC_96BITS 1117 #define ETH_TRANSMITTHRESHOLD_128 ETH_MTLTQOMR_TTC_128BITS 1118 #define ETH_TRANSMITTHRESHOLD_192 ETH_MTLTQOMR_TTC_192BITS 1119 #define ETH_TRANSMITTHRESHOLD_256 ETH_MTLTQOMR_TTC_256BITS 1120 #define ETH_TRANSMITTHRESHOLD_384 ETH_MTLTQOMR_TTC_384BITS 1121 #define ETH_TRANSMITTHRESHOLD_512 ETH_MTLTQOMR_TTC_512BITS 1122 /** 1123 * @} 1124 */ 1125 1126 /** @defgroup ETH_Receive_Mode ETH Receive Mode 1127 * @{ 1128 */ 1129 #define ETH_RECEIVESTOREFORWARD ETH_MTLRQOMR_RSF 1130 #define ETH_RECEIVETHRESHOLD8_64 ETH_MTLRQOMR_RTC_64BITS 1131 #define ETH_RECEIVETHRESHOLD8_32 ETH_MTLRQOMR_RTC_32BITS 1132 #define ETH_RECEIVETHRESHOLD8_96 ETH_MTLRQOMR_RTC_96BITS 1133 #define ETH_RECEIVETHRESHOLD8_128 ETH_MTLRQOMR_RTC_128BITS 1134 /** 1135 * @} 1136 */ 1137 1138 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold 1139 * @{ 1140 */ 1141 #define ETH_PAUSELOWTHRESHOLD_MINUS_4 ETH_MACTFCR_PLT_MINUS4 1142 #define ETH_PAUSELOWTHRESHOLD_MINUS_28 ETH_MACTFCR_PLT_MINUS28 1143 #define ETH_PAUSELOWTHRESHOLD_MINUS_36 ETH_MACTFCR_PLT_MINUS36 1144 #define ETH_PAUSELOWTHRESHOLD_MINUS_144 ETH_MACTFCR_PLT_MINUS144 1145 #define ETH_PAUSELOWTHRESHOLD_MINUS_256 ETH_MACTFCR_PLT_MINUS256 1146 #define ETH_PAUSELOWTHRESHOLD_MINUS_512 ETH_MACTFCR_PLT_MINUS512 1147 /** 1148 * @} 1149 */ 1150 1151 /** @defgroup ETH_Watchdog_Timeout ETH Watchdog Timeout 1152 * @{ 1153 */ 1154 #define ETH_WATCHDOGTIMEOUT_2KB ETH_MACWTR_WTO_2KB 1155 #define ETH_WATCHDOGTIMEOUT_3KB ETH_MACWTR_WTO_3KB 1156 #define ETH_WATCHDOGTIMEOUT_4KB ETH_MACWTR_WTO_4KB 1157 #define ETH_WATCHDOGTIMEOUT_5KB ETH_MACWTR_WTO_5KB 1158 #define ETH_WATCHDOGTIMEOUT_6KB ETH_MACWTR_WTO_6KB 1159 #define ETH_WATCHDOGTIMEOUT_7KB ETH_MACWTR_WTO_7KB 1160 #define ETH_WATCHDOGTIMEOUT_8KB ETH_MACWTR_WTO_8KB 1161 #define ETH_WATCHDOGTIMEOUT_9KB ETH_MACWTR_WTO_9KB 1162 #define ETH_WATCHDOGTIMEOUT_10KB ETH_MACWTR_WTO_10KB 1163 #define ETH_WATCHDOGTIMEOUT_11KB ETH_MACWTR_WTO_12KB 1164 #define ETH_WATCHDOGTIMEOUT_12KB ETH_MACWTR_WTO_12KB 1165 #define ETH_WATCHDOGTIMEOUT_13KB ETH_MACWTR_WTO_13KB 1166 #define ETH_WATCHDOGTIMEOUT_14KB ETH_MACWTR_WTO_14KB 1167 #define ETH_WATCHDOGTIMEOUT_15KB ETH_MACWTR_WTO_15KB 1168 #define ETH_WATCHDOGTIMEOUT_16KB ETH_MACWTR_WTO_16KB 1169 /** 1170 * @} 1171 */ 1172 1173 /** @defgroup ETH_Inter_Packet_Gap ETH Inter Packet Gap 1174 * @{ 1175 */ 1176 #define ETH_INTERPACKETGAP_96BIT ETH_MACCR_IPG_96BIT 1177 #define ETH_INTERPACKETGAP_88BIT ETH_MACCR_IPG_88BIT 1178 #define ETH_INTERPACKETGAP_80BIT ETH_MACCR_IPG_80BIT 1179 #define ETH_INTERPACKETGAP_72BIT ETH_MACCR_IPG_72BIT 1180 #define ETH_INTERPACKETGAP_64BIT ETH_MACCR_IPG_64BIT 1181 #define ETH_INTERPACKETGAP_56BIT ETH_MACCR_IPG_56BIT 1182 #define ETH_INTERPACKETGAP_48BIT ETH_MACCR_IPG_48BIT 1183 #define ETH_INTERPACKETGAP_40BIT ETH_MACCR_IPG_40BIT 1184 /** 1185 * @} 1186 */ 1187 1188 /** @defgroup ETH_Speed ETH Speed 1189 * @{ 1190 */ 1191 #define ETH_SPEED_10M 0x00000000U 1192 #define ETH_SPEED_100M 0x00004000U 1193 /** 1194 * @} 1195 */ 1196 1197 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode 1198 * @{ 1199 */ 1200 #define ETH_FULLDUPLEX_MODE ETH_MACCR_DM 1201 #define ETH_HALFDUPLEX_MODE 0x00000000U 1202 /** 1203 * @} 1204 */ 1205 1206 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit 1207 * @{ 1208 */ 1209 #define ETH_BACKOFFLIMIT_10 0x00000000U 1210 #define ETH_BACKOFFLIMIT_8 0x00000020U 1211 #define ETH_BACKOFFLIMIT_4 0x00000040U 1212 #define ETH_BACKOFFLIMIT_1 0x00000060U 1213 /** 1214 * @} 1215 */ 1216 1217 /** @defgroup ETH_Preamble_Length ETH Preamble Length 1218 * @{ 1219 */ 1220 #define ETH_PREAMBLELENGTH_7 ETH_MACCR_PRELEN_7 1221 #define ETH_PREAMBLELENGTH_5 ETH_MACCR_PRELEN_5 1222 #define ETH_PREAMBLELENGTH_3 ETH_MACCR_PRELEN_3 1223 /** 1224 * @} 1225 */ 1226 1227 /** @defgroup ETH_Source_Addr_Control ETH Source Addr Control 1228 * @{ 1229 */ 1230 #define ETH_SOURCEADDRESS_DISABLE 0x00000000U 1231 #define ETH_SOURCEADDRESS_INSERT_ADDR0 ETH_MACCR_SARC_INSADDR0 1232 #define ETH_SOURCEADDRESS_INSERT_ADDR1 ETH_MACCR_SARC_INSADDR1 1233 #define ETH_SOURCEADDRESS_REPLACE_ADDR0 ETH_MACCR_SARC_REPADDR0 1234 #define ETH_SOURCEADDRESS_REPLACE_ADDR1 ETH_MACCR_SARC_REPADDR1 1235 /** 1236 * @} 1237 */ 1238 1239 /** @defgroup ETH_Control_Packets_Filter ETH Control Packets Filter 1240 * @{ 1241 */ 1242 #define ETH_CTRLPACKETS_BLOCK_ALL ETH_MACPFR_PCF_BLOCKALL 1243 #define ETH_CTRLPACKETS_FORWARD_ALL_EXCEPT_PA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA 1244 #define ETH_CTRLPACKETS_FORWARD_ALL ETH_MACPFR_PCF_FORWARDALL 1245 #define ETH_CTRLPACKETS_FORWARD_PASSED_ADDR_FILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER 1246 /** 1247 * @} 1248 */ 1249 1250 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison 1251 * @{ 1252 */ 1253 #define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U 1254 #define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U 1255 /** 1256 * @} 1257 */ 1258 1259 /** @defgroup ETH_MAC_addresses ETH MAC addresses 1260 * @{ 1261 */ 1262 #define ETH_MAC_ADDRESS0 0x00000000U 1263 #define ETH_MAC_ADDRESS1 0x00000008U 1264 #define ETH_MAC_ADDRESS2 0x00000010U 1265 #define ETH_MAC_ADDRESS3 0x00000018U 1266 /** 1267 * @} 1268 */ 1269 1270 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts 1271 * @{ 1272 */ 1273 #define ETH_MAC_PMT_IT ETH_MACSR_PMTS 1274 /** 1275 * @} 1276 */ 1277 1278 /** @defgroup ETH_MAC_Wake_Up_Event ETH MAC Wake Up Event 1279 * @{ 1280 */ 1281 #define ETH_WAKEUP_PACKET_RECIEVED ETH_MACPCSR_RWKPRCVD 1282 #define ETH_MAGIC_PACKET_RECIEVED ETH_MACPCSR_MGKPRCVD 1283 /** 1284 * @} 1285 */ 1286 1287 /** @defgroup ETH_MAC_Rx_Tx_Status ETH MAC Rx Tx Status 1288 * @{ 1289 */ 1290 #define ETH_RECEIVE_WATCHDOG_TIMEOUT ETH_MACRXTXSR_RWT 1291 #define ETH_EXECESSIVE_COLLISIONS ETH_MACRXTXSR_EXCOL 1292 #define ETH_LATE_COLLISIONS ETH_MACRXTXSR_LCOL 1293 #define ETH_EXECESSIVE_DEFERRAL ETH_MACRXTXSR_EXDEF 1294 #define ETH_LOSS_OF_CARRIER ETH_MACRXTXSR_LCARR 1295 #define ETH_NO_CARRIER ETH_MACRXTXSR_NCARR 1296 #define ETH_TRANSMIT_JABBR_TIMEOUT ETH_MACRXTXSR_TJT 1297 /** 1298 * @} 1299 */ 1300 1301 /** @defgroup HAL_ETH_StateTypeDef ETH States 1302 * @{ 1303 */ 1304 #define HAL_ETH_STATE_RESET 0x00000000U /*!< Peripheral not yet Initialized or disabled */ 1305 #define HAL_ETH_STATE_READY 0x00000010U /*!< Peripheral Communication started */ 1306 #define HAL_ETH_STATE_BUSY 0x00000023U /*!< an internal process is ongoing */ 1307 #define HAL_ETH_STATE_STARTED 0x00000023U /*!< an internal process is started */ 1308 #define HAL_ETH_STATE_ERROR 0x000000E0U /*!< Error State */ 1309 /** 1310 * @} 1311 */ 1312 1313 /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation 1314 * @{ 1315 */ 1316 #define ETH_AUTONEGOTIATION_ENABLE 0x00000001U 1317 #define ETH_AUTONEGOTIATION_DISABLE 0x00000000U 1318 1319 /** 1320 * @} 1321 */ 1322 /** @defgroup ETH_Rx_Mode ETH Rx Mode 1323 * @{ 1324 */ 1325 #define ETH_RXPOLLING_MODE 0x00000000U 1326 #define ETH_RXINTERRUPT_MODE 0x00000001U 1327 /** 1328 * @} 1329 */ 1330 1331 /** @defgroup ETH_Checksum_Mode ETH Checksum Mode 1332 * @{ 1333 */ 1334 #define ETH_CHECKSUM_BY_HARDWARE 0x00000000U 1335 #define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U 1336 /** 1337 * @} 1338 */ 1339 1340 /** @defgroup ETH_Media_Interface ETH Media Interface 1341 * @{ 1342 */ 1343 #define ETH_MEDIA_INTERFACE_MII 0x00000000U 1344 #define ETH_MEDIA_INTERFACE_RMII (SYSCFG_PMC_MII_RMII_SEL) 1345 /** 1346 * @} 1347 */ 1348 1349 /** @defgroup ETH_Watchdog ETH Watchdog 1350 * @{ 1351 */ 1352 #define ETH_WATCHDOG_ENABLE 0x00000000U 1353 #define ETH_WATCHDOG_DISABLE 0x00800000U 1354 /** 1355 * @} 1356 */ 1357 1358 /** @defgroup ETH_Jabber ETH Jabber 1359 * @{ 1360 */ 1361 #define ETH_JABBER_ENABLE 0x00000000U 1362 #define ETH_JABBER_DISABLE 0x00400000U 1363 /** 1364 * @} 1365 */ 1366 1367 /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap 1368 * @{ 1369 */ 1370 #define ETH_INTERFRAMEGAP_96BIT 0x00000000U /*!< minimum IFG between frames during transmission is 96Bit */ 1371 #define ETH_INTERFRAMEGAP_88BIT 0x00020000U /*!< minimum IFG between frames during transmission is 88Bit */ 1372 #define ETH_INTERFRAMEGAP_80BIT 0x00040000U /*!< minimum IFG between frames during transmission is 80Bit */ 1373 #define ETH_INTERFRAMEGAP_72BIT 0x00060000U /*!< minimum IFG between frames during transmission is 72Bit */ 1374 #define ETH_INTERFRAMEGAP_64BIT 0x00080000U /*!< minimum IFG between frames during transmission is 64Bit */ 1375 #define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /*!< minimum IFG between frames during transmission is 56Bit */ 1376 #define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /*!< minimum IFG between frames during transmission is 48Bit */ 1377 #define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /*!< minimum IFG between frames during transmission is 40Bit */ 1378 /** 1379 * @} 1380 */ 1381 1382 /** @defgroup ETH_Carrier_Sense ETH Carrier Sense 1383 * @{ 1384 */ 1385 #define ETH_CARRIERSENCE_ENABLE 0x00000000U 1386 #define ETH_CARRIERSENCE_DISABLE 0x00010000U 1387 /** 1388 * @} 1389 */ 1390 1391 /** @defgroup ETH_Receive_Own ETH Receive Own 1392 * @{ 1393 */ 1394 #define ETH_RECEIVEOWN_ENABLE 0x00000000U 1395 #define ETH_RECEIVEOWN_DISABLE 0x00002000U 1396 /** 1397 * @} 1398 */ 1399 1400 /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode 1401 * @{ 1402 */ 1403 #define ETH_LOOPBACKMODE_ENABLE 0x00001000U 1404 #define ETH_LOOPBACKMODE_DISABLE 0x00000000U 1405 /** 1406 * @} 1407 */ 1408 1409 /** @defgroup ETH_Checksum_Offload ETH Checksum Offload 1410 * @{ 1411 */ 1412 #define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U 1413 #define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U 1414 /** 1415 * @} 1416 */ 1417 1418 /** @defgroup ETH_Retry_Transmission ETH Retry Transmission 1419 * @{ 1420 */ 1421 #define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U 1422 #define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U 1423 /** 1424 * @} 1425 */ 1426 1427 /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip 1428 * @{ 1429 */ 1430 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U 1431 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U 1432 /** 1433 * @} 1434 */ 1435 1436 /** @defgroup ETH_Deferral_Check ETH Deferral Check 1437 * @{ 1438 */ 1439 #define ETH_DEFFERRALCHECK_ENABLE 0x00000010U 1440 #define ETH_DEFFERRALCHECK_DISABLE 0x00000000U 1441 /** 1442 * @} 1443 */ 1444 1445 /** @defgroup ETH_Receive_All ETH Receive All 1446 * @{ 1447 */ 1448 #define ETH_RECEIVEALL_ENABLE 0x80000000U 1449 #define ETH_RECEIVEALL_DISABLE 0x00000000U 1450 /** 1451 * @} 1452 */ 1453 1454 /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter 1455 * @{ 1456 */ 1457 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U 1458 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U 1459 #define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U 1460 /** 1461 * @} 1462 */ 1463 1464 /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames 1465 * @{ 1466 */ 1467 #define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /*!< MAC filters all control frames from reaching the application */ 1468 #define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /*!< MAC forwards all control frames to application even if they fail the Address Filter */ 1469 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /*!< MAC forwards control frames that pass the Address Filter. */ 1470 /** 1471 * @} 1472 */ 1473 1474 /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception 1475 * @{ 1476 */ 1477 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U 1478 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U 1479 /** 1480 * @} 1481 */ 1482 1483 /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter 1484 * @{ 1485 */ 1486 #define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U 1487 #define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U 1488 /** 1489 * @} 1490 */ 1491 1492 /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode 1493 * @{ 1494 */ 1495 #define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U 1496 #define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U 1497 /** 1498 * @} 1499 */ 1500 1501 /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter 1502 * @{ 1503 */ 1504 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U 1505 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U 1506 #define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U 1507 #define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U 1508 /** 1509 * @} 1510 */ 1511 1512 /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter 1513 * @{ 1514 */ 1515 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U 1516 #define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U 1517 #define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U 1518 /** 1519 * @} 1520 */ 1521 1522 /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause 1523 * @{ 1524 */ 1525 #define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U 1526 #define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U 1527 /** 1528 * @} 1529 */ 1530 1531 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold 1532 * @{ 1533 */ 1534 #define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /*!< Pause time minus 4 slot times */ 1535 #define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /*!< Pause time minus 28 slot times */ 1536 #define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /*!< Pause time minus 144 slot times */ 1537 #define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /*!< Pause time minus 256 slot times */ 1538 /** 1539 * @} 1540 */ 1541 1542 /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect 1543 * @{ 1544 */ 1545 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U 1546 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U 1547 /** 1548 * @} 1549 */ 1550 1551 /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control 1552 * @{ 1553 */ 1554 #define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U 1555 #define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U 1556 /** 1557 * @} 1558 */ 1559 1560 /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control 1561 * @{ 1562 */ 1563 #define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U 1564 #define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U 1565 /** 1566 * @} 1567 */ 1568 1569 /** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA 1570 * @{ 1571 */ 1572 #define ETH_MAC_ADDRESSFILTER_SA 0x00000000U 1573 #define ETH_MAC_ADDRESSFILTER_DA 0x00000008U 1574 /** 1575 * @} 1576 */ 1577 1578 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes 1579 * @{ 1580 */ 1581 #define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /*!< Mask MAC Address high reg bits [15:8] */ 1582 #define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /*!< Mask MAC Address high reg bits [7:0] */ 1583 #define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /*!< Mask MAC Address low reg bits [31:24] */ 1584 #define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /*!< Mask MAC Address low reg bits [23:16] */ 1585 #define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /*!< Mask MAC Address low reg bits [15:8] */ 1586 #define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /*!< Mask MAC Address low reg bits [70] */ 1587 /** 1588 * @} 1589 */ 1590 1591 /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control 1592 * @{ 1593 */ 1594 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ 1595 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ 1596 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ 1597 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ 1598 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ 1599 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ 1600 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ 1601 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ 1602 /** 1603 * @} 1604 */ 1605 1606 /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control 1607 * @{ 1608 */ 1609 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ 1610 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ 1611 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ 1612 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ 1613 /** 1614 * @} 1615 */ 1616 1617 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration 1618 * @{ 1619 */ 1620 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U 1621 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U 1622 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U 1623 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U 1624 #define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U 1625 /** 1626 * @} 1627 */ 1628 1629 /** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment 1630 * @{ 1631 */ 1632 #define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /*!< Last Segment */ 1633 #define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /*!< First Segment */ 1634 /** 1635 * @} 1636 */ 1637 1638 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control 1639 * @{ 1640 */ 1641 #define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /*!< Checksum engine bypass */ 1642 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /*!< IPv4 header checksum insertion */ 1643 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ 1644 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ 1645 /** 1646 * @} 1647 */ 1648 1649 /** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers 1650 * @{ 1651 */ 1652 #define ETH_DMARXDESC_BUFFER1 0x00000000U /*!< DMA Rx Desc Buffer1 */ 1653 #define ETH_DMARXDESC_BUFFER2 0x00000001U /*!< DMA Rx Desc Buffer2 */ 1654 /** 1655 * @} 1656 */ 1657 1658 /** @defgroup ETH_PMT_Flags ETH PMT Flags 1659 * @{ 1660 */ 1661 #define ETH_PMT_FLAG_WUFFRPR 0x80000000U /*!< Wake-Up Frame Filter Register Pointer Reset */ 1662 #define ETH_PMT_FLAG_WUFR 0x00000040U /*!< Wake-Up Frame Received */ 1663 #define ETH_PMT_FLAG_MPR 0x00000020U /*!< Magic Packet Received */ 1664 /** 1665 * @} 1666 */ 1667 1668 /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts 1669 * @{ 1670 */ 1671 #define ETH_MMC_IT_TGF 0x00200000U /*!< When Tx good frame counter reaches half the maximum value */ 1672 #define ETH_MMC_IT_TGFMSC 0x00008000U /*!< When Tx good multi col counter reaches half the maximum value */ 1673 #define ETH_MMC_IT_TGFSC 0x00004000U /*!< When Tx good single col counter reaches half the maximum value */ 1674 /** 1675 * @} 1676 */ 1677 1678 /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts 1679 * @{ 1680 */ 1681 #define ETH_MMC_IT_RGUF 0x10020000U /*!< When Rx good unicast frames counter reaches half the maximum value */ 1682 #define ETH_MMC_IT_RFAE 0x10000040U /*!< When Rx alignment error counter reaches half the maximum value */ 1683 #define ETH_MMC_IT_RFCE 0x10000020U /*!< When Rx crc error counter reaches half the maximum value */ 1684 /** 1685 * @} 1686 */ 1687 1688 /** @defgroup ETH_MAC_Flags ETH MAC Flags 1689 * @{ 1690 */ 1691 #define ETH_MAC_FLAG_TST 0x00000200U /*!< Time stamp trigger flag (on MAC) */ 1692 #define ETH_MAC_FLAG_MMCT 0x00000040U /*!< MMC transmit flag */ 1693 #define ETH_MAC_FLAG_MMCR 0x00000020U /*!< MMC receive flag */ 1694 #define ETH_MAC_FLAG_MMC 0x00000010U /*!< MMC flag (on MAC) */ 1695 #define ETH_MAC_FLAG_PMT 0x00000008U /*!< PMT flag (on MAC) */ 1696 /** 1697 * @} 1698 */ 1699 1700 /** @defgroup ETH_DMA_Flags ETH DMA Flags 1701 * @{ 1702 */ 1703 #define ETH_DMA_FLAG_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */ 1704 #define ETH_DMA_FLAG_PMT 0x10000000U /*!< PMT interrupt (on DMA) */ 1705 #define ETH_DMA_FLAG_MMC 0x08000000U /*!< MMC interrupt (on DMA) */ 1706 #define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U /*!< Error bits 0-Rx DMA, 1-Tx DMA */ 1707 #define ETH_DMA_FLAG_READWRITEERROR 0x01000000U /*!< Error bits 0-write transfer, 1-read transfer */ 1708 #define ETH_DMA_FLAG_ACCESSERROR 0x02000000U /*!< Error bits 0-data buffer, 1-desc. access */ 1709 #define ETH_DMA_FLAG_NIS 0x00010000U /*!< Normal interrupt summary flag */ 1710 #define ETH_DMA_FLAG_AIS 0x00008000U /*!< Abnormal interrupt summary flag */ 1711 #define ETH_DMA_FLAG_ER 0x00004000U /*!< Early receive flag */ 1712 #define ETH_DMA_FLAG_FBE 0x00002000U /*!< Fatal bus error flag */ 1713 #define ETH_DMA_FLAG_ET 0x00000400U /*!< Early transmit flag */ 1714 #define ETH_DMA_FLAG_RWT 0x00000200U /*!< Receive watchdog timeout flag */ 1715 #define ETH_DMA_FLAG_RPS 0x00000100U /*!< Receive process stopped flag */ 1716 #define ETH_DMA_FLAG_RBU 0x00000080U /*!< Receive buffer unavailable flag */ 1717 #define ETH_DMA_FLAG_R 0x00000040U /*!< Receive flag */ 1718 #define ETH_DMA_FLAG_TU 0x00000020U /*!< Underflow flag */ 1719 #define ETH_DMA_FLAG_RO 0x00000010U /*!< Overflow flag */ 1720 #define ETH_DMA_FLAG_TJT 0x00000008U /*!< Transmit jabber timeout flag */ 1721 #define ETH_DMA_FLAG_TBU 0x00000004U /*!< Transmit buffer unavailable flag */ 1722 #define ETH_DMA_FLAG_TPS 0x00000002U /*!< Transmit process stopped flag */ 1723 #define ETH_DMA_FLAG_T 0x00000001U /*!< Transmit flag */ 1724 /** 1725 * @} 1726 */ 1727 1728 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts 1729 * @{ 1730 */ 1731 #define ETH_MAC_IT_TST 0x00000200U /*!< Time stamp trigger interrupt (on MAC) */ 1732 #define ETH_MAC_IT_MMCT 0x00000040U /*!< MMC transmit interrupt */ 1733 #define ETH_MAC_IT_MMCR 0x00000020U /*!< MMC receive interrupt */ 1734 #define ETH_MAC_IT_MMC 0x00000010U /*!< MMC interrupt (on MAC) */ 1735 #define ETH_MAC_IT_PMT 0x00000008U /*!< PMT interrupt (on MAC) */ 1736 /** 1737 * @} 1738 */ 1739 1740 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts 1741 * @{ 1742 */ 1743 #define ETH_DMA_IT_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */ 1744 #define ETH_DMA_IT_PMT 0x10000000U /*!< PMT interrupt (on DMA) */ 1745 #define ETH_DMA_IT_MMC 0x08000000U /*!< MMC interrupt (on DMA) */ 1746 #define ETH_DMA_IT_NIS 0x00010000U /*!< Normal interrupt summary */ 1747 #define ETH_DMA_IT_AIS 0x00008000U /*!< Abnormal interrupt summary */ 1748 #define ETH_DMA_IT_ER 0x00004000U /*!< Early receive interrupt */ 1749 #define ETH_DMA_IT_FBE 0x00002000U /*!< Fatal bus error interrupt */ 1750 #define ETH_DMA_IT_ET 0x00000400U /*!< Early transmit interrupt */ 1751 #define ETH_DMA_IT_RWT 0x00000200U /*!< Receive watchdog timeout interrupt */ 1752 #define ETH_DMA_IT_RPS 0x00000100U /*!< Receive process stopped interrupt */ 1753 #define ETH_DMA_IT_RBU 0x00000080U /*!< Receive buffer unavailable interrupt */ 1754 #define ETH_DMA_IT_R 0x00000040U /*!< Receive interrupt */ 1755 #define ETH_DMA_IT_TU 0x00000020U /*!< Underflow interrupt */ 1756 #define ETH_DMA_IT_RO 0x00000010U /*!< Overflow interrupt */ 1757 #define ETH_DMA_IT_TJT 0x00000008U /*!< Transmit jabber timeout interrupt */ 1758 #define ETH_DMA_IT_TBU 0x00000004U /*!< Transmit buffer unavailable interrupt */ 1759 #define ETH_DMA_IT_TPS 0x00000002U /*!< Transmit process stopped interrupt */ 1760 #define ETH_DMA_IT_T 0x00000001U /*!< Transmit interrupt */ 1761 /** 1762 * @} 1763 */ 1764 1765 /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state 1766 * @{ 1767 */ 1768 #define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Tx Command issued */ 1769 #define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /*!< Running - fetching the Tx descriptor */ 1770 #define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /*!< Running - waiting for status */ 1771 #define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U /*!< Running - reading the data from host memory */ 1772 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U /*!< Suspended - Tx Descriptor unavailable */ 1773 #define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U /*!< Running - closing Rx descriptor */ 1774 1775 /** 1776 * @} 1777 */ 1778 1779 1780 /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state 1781 * @{ 1782 */ 1783 #define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Rx Command issued */ 1784 #define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /*!< Running - fetching the Rx descriptor */ 1785 #define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /*!< Running - waiting for packet */ 1786 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U /*!< Suspended - Rx Descriptor unavailable */ 1787 #define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U /*!< Running - closing descriptor */ 1788 #define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U /*!< Running - queuing the receive frame into host memory */ 1789 1790 /** 1791 * @} 1792 */ 1793 1794 /** @defgroup ETH_DMA_overflow ETH DMA overflow 1795 * @{ 1796 */ 1797 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /*!< Overflow bit for FIFO overflow counter */ 1798 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /*!< Overflow bit for missed frame counter */ 1799 /** 1800 * @} 1801 */ 1802 /** @defgroup ETH_PTP_Config_Status ETH PTP Config Status 1803 * @{ 1804 */ 1805 #define HAL_ETH_PTP_NOT_CONFIGURATED 0x00000000U /*!< ETH PTP Configuration not done */ 1806 #define HAL_ETH_PTP_CONFIGURATED 0x00000001U /*!< ETH PTP Configuration done */ 1807 /** 1808 * @} 1809 */ 1810 /** 1811 * @} 1812 */ 1813 1814 /* Exported macro ------------------------------------------------------------*/ 1815 /** @defgroup ETH_Exported_Macros ETH Exported Macros 1816 * @{ 1817 */ 1818 1819 /** @brief Reset ETH handle state 1820 * @param __HANDLE__: specifies the ETH handle. 1821 * @retval None 1822 */ 1823 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 1824 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ 1825 (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \ 1826 (__HANDLE__)->MspInitCallback = NULL; \ 1827 (__HANDLE__)->MspDeInitCallback = NULL; \ 1828 } while(0) 1829 #else 1830 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ 1831 (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \ 1832 } while(0) 1833 #endif /*USE_HAL_ETH_REGISTER_CALLBACKS */ 1834 1835 /** 1836 * @brief Enables the specified ETHERNET DMA interrupts. 1837 * @param __HANDLE__ : ETH Handle 1838 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be 1839 * enabled @ref ETH_DMA_Interrupts 1840 * @retval None 1841 */ 1842 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER \ 1843 |= (__INTERRUPT__)) 1844 1845 /** 1846 * @brief Disables the specified ETHERNET DMA interrupts. 1847 * @param __HANDLE__ : ETH Handle 1848 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be 1849 * disabled. @ref ETH_DMA_Interrupts 1850 * @retval None 1851 */ 1852 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER \ 1853 &= ~(__INTERRUPT__)) 1854 1855 /** 1856 * @brief Gets the ETHERNET DMA IT source enabled or disabled. 1857 * @param __HANDLE__ : ETH Handle 1858 * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts 1859 * @retval The ETH DMA IT Source enabled or disabled 1860 */ 1861 #define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMAIER &\ 1862 (__INTERRUPT__)) == (__INTERRUPT__)) 1863 1864 /** 1865 * @brief Gets the ETHERNET DMA IT pending bit. 1866 * @param __HANDLE__ : ETH Handle 1867 * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts 1868 * @retval The state of ETH DMA IT (SET or RESET) 1869 */ 1870 #define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMASR &\ 1871 (__INTERRUPT__)) == (__INTERRUPT__)) 1872 1873 /** 1874 * @brief Clears the ETHERNET DMA IT pending bit. 1875 * @param __HANDLE__ : ETH Handle 1876 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts 1877 * @retval None 1878 */ 1879 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR = (__INTERRUPT__)) 1880 1881 /** 1882 * @brief Checks whether the specified ETHERNET DMA flag is set or not. 1883 * @param __HANDLE__: ETH Handle 1884 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags 1885 * @retval The state of ETH DMA FLAG (SET or RESET). 1886 */ 1887 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMACSR &\ 1888 ( __FLAG__)) == ( __FLAG__)) 1889 1890 /** 1891 * @brief Clears the specified ETHERNET DMA flag. 1892 * @param __HANDLE__: ETH Handle 1893 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags 1894 * @retval The state of ETH DMA FLAG (SET or RESET). 1895 */ 1896 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMACSR = ( __FLAG__)) 1897 1898 /** 1899 * @brief Enables the specified ETHERNET MAC interrupts. 1900 * @param __HANDLE__ : ETH Handle 1901 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be 1902 * enabled @ref ETH_MAC_Interrupts 1903 * @retval None 1904 */ 1905 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER \ 1906 |= (__INTERRUPT__)) 1907 1908 /** 1909 * @brief Disables the specified ETHERNET MAC interrupts. 1910 * @param __HANDLE__ : ETH Handle 1911 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be 1912 * enabled @ref ETH_MAC_Interrupts 1913 * @retval None 1914 */ 1915 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER \ 1916 &= ~(__INTERRUPT__)) 1917 1918 /** 1919 * @brief Checks whether the specified ETHERNET MAC flag is set or not. 1920 * @param __HANDLE__: ETH Handle 1921 * @param __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts 1922 * @retval The state of ETH MAC IT (SET or RESET). 1923 */ 1924 #define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MACSR &\ 1925 ( __INTERRUPT__)) == ( __INTERRUPT__)) 1926 1927 /*!< External interrupt line 19 Connected to the ETH wakeup EXTI Line */ 1928 #define ETH_WAKEUP_EXTI_LINE 0x00080000U 1929 1930 /** 1931 * @brief Enable the ETH WAKEUP Exti Line. 1932 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled. 1933 * @arg ETH_WAKEUP_EXTI_LINE 1934 * @retval None. 1935 */ 1936 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI->IMR |= (__EXTI_LINE__)) 1937 1938 /** 1939 * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not. 1940 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. 1941 * @arg ETH_WAKEUP_EXTI_LINE 1942 * @retval EXTI ETH WAKEUP Line Status. 1943 */ 1944 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) 1945 1946 /** 1947 * @brief Clear the ETH WAKEUP Exti flag. 1948 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. 1949 * @arg ETH_WAKEUP_EXTI_LINE 1950 * @retval None. 1951 */ 1952 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) 1953 1954 1955 /** 1956 * @brief enable rising edge interrupt on selected EXTI line. 1957 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. 1958 * @arg ETH_WAKEUP_EXTI_LINE 1959 * @retval None 1960 */ 1961 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR &= ~(__EXTI_LINE__)); \ 1962 (EXTI->RTSR |= (__EXTI_LINE__)) 1963 1964 /** 1965 * @brief enable falling edge interrupt on selected EXTI line. 1966 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. 1967 * @arg ETH_WAKEUP_EXTI_LINE 1968 * @retval None 1969 */ 1970 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR &= ~(__EXTI_LINE__));\ 1971 (EXTI->FTSR |= (__EXTI_LINE__)) 1972 1973 /** 1974 * @brief enable falling edge interrupt on selected EXTI line. 1975 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. 1976 * @arg ETH_WAKEUP_EXTI_LINE 1977 * @retval None 1978 */ 1979 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR |= (__EXTI_LINE__));\ 1980 (EXTI->FTSR |= (__EXTI_LINE__)) 1981 1982 /** 1983 * @brief Generates a Software interrupt on selected EXTI line. 1984 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. 1985 * @arg ETH_WAKEUP_EXTI_LINE 1986 * @retval None 1987 */ 1988 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) 1989 1990 #define __HAL_ETH_GET_PTP_CONTROL(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->PTPTSCR) & \ 1991 (__FLAG__)) == (__FLAG__)) ? SET : RESET) 1992 1993 #define __HAL_ETH_SET_PTP_CONTROL(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->PTPTSCR |= (__FLAG__)) 1994 /** 1995 * @} 1996 */ 1997 1998 1999 /* Exported functions --------------------------------------------------------*/ 2000 2001 /** @addtogroup ETH_Exported_Functions 2002 * @{ 2003 */ 2004 2005 /** @addtogroup ETH_Exported_Functions_Group1 2006 * @{ 2007 */ 2008 /* Initialization and de initialization functions **********************************/ 2009 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); 2010 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); 2011 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); 2012 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); 2013 2014 /* Callbacks Register/UnRegister functions ***********************************/ 2015 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 2016 HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, 2017 pETH_CallbackTypeDef pCallback); 2018 HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID); 2019 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 2020 2021 /** 2022 * @} 2023 */ 2024 2025 /** @addtogroup ETH_Exported_Functions_Group2 2026 * @{ 2027 */ 2028 /* IO operation functions *******************************************************/ 2029 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); 2030 HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth); 2031 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); 2032 HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth); 2033 2034 HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff); 2035 HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth, 2036 pETH_rxAllocateCallbackTypeDef rxAllocateCallback); 2037 HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth); 2038 HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback); 2039 HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth); 2040 HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(ETH_HandleTypeDef *heth, uint32_t *pErrorCode); 2041 HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback); 2042 HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth); 2043 HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth); 2044 2045 #ifdef HAL_ETH_USE_PTP 2046 HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig); 2047 HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig); 2048 HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time); 2049 HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time); 2050 HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype, 2051 ETH_TimeTypeDef *timeoffset); 2052 HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth); 2053 HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp); 2054 HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp); 2055 HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback); 2056 HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth); 2057 #endif /* HAL_ETH_USE_PTP */ 2058 2059 HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout); 2060 HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig); 2061 2062 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, 2063 uint32_t RegValue); 2064 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, 2065 uint32_t *pRegValue); 2066 2067 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); 2068 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); 2069 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); 2070 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); 2071 void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth); 2072 void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth); 2073 void HAL_ETH_RxAllocateCallback(uint8_t **buff); 2074 void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length); 2075 void HAL_ETH_TxFreeCallback(uint32_t *buff); 2076 void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp); 2077 /** 2078 * @} 2079 */ 2080 2081 /** @addtogroup ETH_Exported_Functions_Group3 2082 * @{ 2083 */ 2084 /* Peripheral Control functions **********************************************/ 2085 /* MAC & DMA Configuration APIs **********************************************/ 2086 HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); 2087 HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); 2088 HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); 2089 HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); 2090 void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth); 2091 2092 /* MAC VLAN Processing APIs ************************************************/ 2093 void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, 2094 uint32_t VLANIdentifier); 2095 2096 /* MAC L2 Packet Filtering APIs **********************************************/ 2097 HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig); 2098 HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig); 2099 HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable); 2100 HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr); 2101 2102 /* MAC Power Down APIs *****************************************************/ 2103 void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig); 2104 void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth); 2105 HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count); 2106 2107 /** 2108 * @} 2109 */ 2110 2111 /** @addtogroup ETH_Exported_Functions_Group4 2112 * @{ 2113 */ 2114 /* Peripheral State functions **************************************************/ 2115 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); 2116 uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth); 2117 uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth); 2118 uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth); 2119 uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth); 2120 /** 2121 * @} 2122 */ 2123 2124 /** 2125 * @} 2126 */ 2127 2128 /** 2129 * @} 2130 */ 2131 2132 /** 2133 * @} 2134 */ 2135 2136 #endif /* ETH */ 2137 2138 #ifdef __cplusplus 2139 } 2140 #endif 2141 2142 #endif /* STM32F7xx_HAL_ETH_H */ 2143 2144 2145
