1 /** 2 ****************************************************************************** 3 * @file stm32f7xx_hal_dsi.h 4 * @author MCD Application Team 5 * @brief Header file of DSI HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32F7xx_HAL_DSI_H 21 #define STM32F7xx_HAL_DSI_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f7xx_hal_def.h" 29 30 #if defined(DSI) 31 32 /** @addtogroup STM32F7xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @defgroup DSI DSI 37 * @brief DSI HAL module driver 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup DSI_Exported_Types DSI Exported Types 43 * @{ 44 */ 45 /** 46 * @brief DSI Init Structure definition 47 */ 48 typedef struct 49 { 50 uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control 51 This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */ 52 53 uint32_t TXEscapeCkdiv; /*!< TX Escape clock division 54 The values 0 and 1 stop the TX_ESC clock generation */ 55 56 uint32_t NumberOfLanes; /*!< Number of lanes 57 This parameter can be any value of @ref DSI_Number_Of_Lanes */ 58 59 } DSI_InitTypeDef; 60 61 /** 62 * @brief DSI PLL Clock structure definition 63 */ 64 typedef struct 65 { 66 uint32_t PLLNDIV; /*!< PLL Loop Division Factor 67 This parameter must be a value between 10 and 125 */ 68 69 uint32_t PLLIDF; /*!< PLL Input Division Factor 70 This parameter can be any value of @ref DSI_PLL_IDF */ 71 72 uint32_t PLLODF; /*!< PLL Output Division Factor 73 This parameter can be any value of @ref DSI_PLL_ODF */ 74 75 } DSI_PLLInitTypeDef; 76 77 /** 78 * @brief DSI Video mode configuration 79 */ 80 typedef struct 81 { 82 uint32_t VirtualChannelID; /*!< Virtual channel ID */ 83 84 uint32_t ColorCoding; /*!< Color coding for LTDC interface 85 This parameter can be any value of @ref DSI_Color_Coding */ 86 87 uint32_t LooselyPacked; /*!< Enable or disable loosely packed stream (needed only when using 88 18-bit configuration). 89 This parameter can be any value of @ref DSI_LooselyPacked */ 90 91 uint32_t Mode; /*!< Video mode type 92 This parameter can be any value of @ref DSI_Video_Mode_Type */ 93 94 uint32_t PacketSize; /*!< Video packet size */ 95 96 uint32_t NumberOfChunks; /*!< Number of chunks */ 97 98 uint32_t NullPacketSize; /*!< Null packet size */ 99 100 uint32_t HSPolarity; /*!< HSYNC pin polarity 101 This parameter can be any value of @ref DSI_HSYNC_Polarity */ 102 103 uint32_t VSPolarity; /*!< VSYNC pin polarity 104 This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */ 105 106 uint32_t DEPolarity; /*!< Data Enable pin polarity 107 This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */ 108 109 uint32_t HorizontalSyncActive; /*!< Horizontal synchronism active duration (in lane byte clock cycles) */ 110 111 uint32_t HorizontalBackPorch; /*!< Horizontal back-porch duration (in lane byte clock cycles) */ 112 113 uint32_t HorizontalLine; /*!< Horizontal line duration (in lane byte clock cycles) */ 114 115 uint32_t VerticalSyncActive; /*!< Vertical synchronism active duration */ 116 117 uint32_t VerticalBackPorch; /*!< Vertical back-porch duration */ 118 119 uint32_t VerticalFrontPorch; /*!< Vertical front-porch duration */ 120 121 uint32_t VerticalActive; /*!< Vertical active duration */ 122 123 uint32_t LPCommandEnable; /*!< Low-power command enable 124 This parameter can be any value of @ref DSI_LP_Command */ 125 126 uint32_t LPLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that 127 can fit in a line during VSA, VBP and VFP regions */ 128 129 uint32_t LPVACTLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that 130 can fit in a line during VACT region */ 131 132 uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable 133 This parameter can be any value of @ref DSI_LP_HFP */ 134 135 uint32_t LPHorizontalBackPorchEnable; /*!< Low-power horizontal back-porch enable 136 This parameter can be any value of @ref DSI_LP_HBP */ 137 138 uint32_t LPVerticalActiveEnable; /*!< Low-power vertical active enable 139 This parameter can be any value of @ref DSI_LP_VACT */ 140 141 uint32_t LPVerticalFrontPorchEnable; /*!< Low-power vertical front-porch enable 142 This parameter can be any value of @ref DSI_LP_VFP */ 143 144 uint32_t LPVerticalBackPorchEnable; /*!< Low-power vertical back-porch enable 145 This parameter can be any value of @ref DSI_LP_VBP */ 146 147 uint32_t LPVerticalSyncActiveEnable; /*!< Low-power vertical sync active enable 148 This parameter can be any value of @ref DSI_LP_VSYNC */ 149 150 uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable 151 This parameter can be any value of @ref DSI_FBTA_acknowledge */ 152 153 } DSI_VidCfgTypeDef; 154 155 /** 156 * @brief DSI Adapted command mode configuration 157 */ 158 typedef struct 159 { 160 uint32_t VirtualChannelID; /*!< Virtual channel ID */ 161 162 uint32_t ColorCoding; /*!< Color coding for LTDC interface 163 This parameter can be any value of @ref DSI_Color_Coding */ 164 165 uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in 166 pixels. This parameter can be any value between 0x00 and 0xFFFFU */ 167 168 uint32_t TearingEffectSource; /*!< Tearing effect source 169 This parameter can be any value of @ref DSI_TearingEffectSource */ 170 171 uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity 172 This parameter can be any value of @ref DSI_TearingEffectPolarity */ 173 174 uint32_t HSPolarity; /*!< HSYNC pin polarity 175 This parameter can be any value of @ref DSI_HSYNC_Polarity */ 176 177 uint32_t VSPolarity; /*!< VSYNC pin polarity 178 This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */ 179 180 uint32_t DEPolarity; /*!< Data Enable pin polarity 181 This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */ 182 183 uint32_t VSyncPol; /*!< VSync edge on which the LTDC is halted 184 This parameter can be any value of @ref DSI_Vsync_Polarity */ 185 186 uint32_t AutomaticRefresh; /*!< Automatic refresh mode 187 This parameter can be any value of @ref DSI_AutomaticRefresh */ 188 189 uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable 190 This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */ 191 192 } DSI_CmdCfgTypeDef; 193 194 /** 195 * @brief DSI command transmission mode configuration 196 */ 197 typedef struct 198 { 199 uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission 200 This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */ 201 202 uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission 203 This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */ 204 205 uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission 206 This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */ 207 208 uint32_t LPGenShortReadNoP; /*!< Generic Short Read Zero parameters Transmission 209 This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP */ 210 211 uint32_t LPGenShortReadOneP; /*!< Generic Short Read One parameter Transmission 212 This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP */ 213 214 uint32_t LPGenShortReadTwoP; /*!< Generic Short Read Two parameters Transmission 215 This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP */ 216 217 uint32_t LPGenLongWrite; /*!< Generic Long Write Transmission 218 This parameter can be any value of @ref DSI_LP_LPGenLongWrite */ 219 220 uint32_t LPDcsShortWriteNoP; /*!< DCS Short Write Zero parameters Transmission 221 This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP */ 222 223 uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission 224 This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */ 225 226 uint32_t LPDcsShortReadNoP; /*!< DCS Short Read Zero parameters Transmission 227 This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP */ 228 229 uint32_t LPDcsLongWrite; /*!< DCS Long Write Transmission 230 This parameter can be any value of @ref DSI_LP_LPDcsLongWrite */ 231 232 uint32_t LPMaxReadPacket; /*!< Maximum Read Packet Size Transmission 233 This parameter can be any value of @ref DSI_LP_LPMaxReadPacket */ 234 235 uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable 236 This parameter can be any value of @ref DSI_AcknowledgeRequest */ 237 238 } DSI_LPCmdTypeDef; 239 240 /** 241 * @brief DSI PHY Timings definition 242 */ 243 typedef struct 244 { 245 uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed 246 to low-power transmission */ 247 248 uint32_t ClockLaneLP2HSTime; /*!< The maximum time that the D-PHY clock lane takes to go from low-power 249 to high-speed transmission */ 250 251 uint32_t DataLaneHS2LPTime; /*!< The maximum time that the D-PHY data lanes takes to go from high-speed 252 to low-power transmission */ 253 254 uint32_t DataLaneLP2HSTime; /*!< The maximum time that the D-PHY data lanes takes to go from low-power 255 to high-speed transmission */ 256 257 uint32_t DataLaneMaxReadTime; /*!< The maximum time required to perform a read command */ 258 259 uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the 260 Stop state */ 261 262 } DSI_PHY_TimerTypeDef; 263 264 /** 265 * @brief DSI HOST Timeouts definition 266 */ 267 typedef struct 268 { 269 uint32_t TimeoutCkdiv; /*!< Time-out clock division */ 270 271 uint32_t HighSpeedTransmissionTimeout; /*!< High-speed transmission time-out */ 272 273 uint32_t LowPowerReceptionTimeout; /*!< Low-power reception time-out */ 274 275 uint32_t HighSpeedReadTimeout; /*!< High-speed read time-out */ 276 277 uint32_t LowPowerReadTimeout; /*!< Low-power read time-out */ 278 279 uint32_t HighSpeedWriteTimeout; /*!< High-speed write time-out */ 280 281 uint32_t HighSpeedWritePrespMode; /*!< High-speed write presp mode 282 This parameter can be any value of @ref DSI_HS_PrespMode */ 283 284 uint32_t LowPowerWriteTimeout; /*!< Low-speed write time-out */ 285 286 uint32_t BTATimeout; /*!< BTA time-out */ 287 288 } DSI_HOST_TimeoutTypeDef; 289 290 /** 291 * @brief DSI States Structure definition 292 */ 293 typedef enum 294 { 295 HAL_DSI_STATE_RESET = 0x00U, 296 HAL_DSI_STATE_READY = 0x01U, 297 HAL_DSI_STATE_ERROR = 0x02U, 298 HAL_DSI_STATE_BUSY = 0x03U, 299 HAL_DSI_STATE_TIMEOUT = 0x04U 300 } HAL_DSI_StateTypeDef; 301 302 /** 303 * @brief DSI Handle Structure definition 304 */ 305 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 306 typedef struct __DSI_HandleTypeDef 307 #else 308 typedef struct 309 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 310 { 311 DSI_TypeDef *Instance; /*!< Register base address */ 312 DSI_InitTypeDef Init; /*!< DSI required parameters */ 313 HAL_LockTypeDef Lock; /*!< DSI peripheral status */ 314 __IO HAL_DSI_StateTypeDef State; /*!< DSI communication state */ 315 __IO uint32_t ErrorCode; /*!< DSI Error code */ 316 uint32_t ErrorMsk; /*!< DSI Error monitoring mask */ 317 318 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 319 void (* TearingEffectCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Tearing Effect Callback */ 320 void (* EndOfRefreshCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI End Of Refresh Callback */ 321 void (* ErrorCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Error Callback */ 322 323 void (* MspInitCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp Init callback */ 324 void (* MspDeInitCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp DeInit callback */ 325 326 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 327 328 } DSI_HandleTypeDef; 329 330 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 331 /** 332 * @brief HAL DSI Callback ID enumeration definition 333 */ 334 typedef enum 335 { 336 HAL_DSI_MSPINIT_CB_ID = 0x00U, /*!< DSI MspInit callback ID */ 337 HAL_DSI_MSPDEINIT_CB_ID = 0x01U, /*!< DSI MspDeInit callback ID */ 338 339 HAL_DSI_TEARING_EFFECT_CB_ID = 0x02U, /*!< DSI Tearing Effect Callback ID */ 340 HAL_DSI_ENDOF_REFRESH_CB_ID = 0x03U, /*!< DSI End Of Refresh Callback ID */ 341 HAL_DSI_ERROR_CB_ID = 0x04U /*!< DSI Error Callback ID */ 342 343 } HAL_DSI_CallbackIDTypeDef; 344 345 /** 346 * @brief HAL DSI Callback pointer definition 347 */ 348 typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to an DSI callback function */ 349 350 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 351 /** 352 * @} 353 */ 354 355 /* Exported constants --------------------------------------------------------*/ 356 /** @defgroup DSI_Exported_Constants DSI Exported Constants 357 * @{ 358 */ 359 /** @defgroup DSI_DCS_Command DSI DCS Command 360 * @{ 361 */ 362 #define DSI_ENTER_IDLE_MODE 0x39U 363 #define DSI_ENTER_INVERT_MODE 0x21U 364 #define DSI_ENTER_NORMAL_MODE 0x13U 365 #define DSI_ENTER_PARTIAL_MODE 0x12U 366 #define DSI_ENTER_SLEEP_MODE 0x10U 367 #define DSI_EXIT_IDLE_MODE 0x38U 368 #define DSI_EXIT_INVERT_MODE 0x20U 369 #define DSI_EXIT_SLEEP_MODE 0x11U 370 #define DSI_GET_3D_CONTROL 0x3FU 371 #define DSI_GET_ADDRESS_MODE 0x0BU 372 #define DSI_GET_BLUE_CHANNEL 0x08U 373 #define DSI_GET_DIAGNOSTIC_RESULT 0x0FU 374 #define DSI_GET_DISPLAY_MODE 0x0DU 375 #define DSI_GET_GREEN_CHANNEL 0x07U 376 #define DSI_GET_PIXEL_FORMAT 0x0CU 377 #define DSI_GET_POWER_MODE 0x0AU 378 #define DSI_GET_RED_CHANNEL 0x06U 379 #define DSI_GET_SCANLINE 0x45U 380 #define DSI_GET_SIGNAL_MODE 0x0EU 381 #define DSI_NOP 0x00U 382 #define DSI_READ_DDB_CONTINUE 0xA8U 383 #define DSI_READ_DDB_START 0xA1U 384 #define DSI_READ_MEMORY_CONTINUE 0x3EU 385 #define DSI_READ_MEMORY_START 0x2EU 386 #define DSI_SET_3D_CONTROL 0x3DU 387 #define DSI_SET_ADDRESS_MODE 0x36U 388 #define DSI_SET_COLUMN_ADDRESS 0x2AU 389 #define DSI_SET_DISPLAY_OFF 0x28U 390 #define DSI_SET_DISPLAY_ON 0x29U 391 #define DSI_SET_GAMMA_CURVE 0x26U 392 #define DSI_SET_PAGE_ADDRESS 0x2BU 393 #define DSI_SET_PARTIAL_COLUMNS 0x31U 394 #define DSI_SET_PARTIAL_ROWS 0x30U 395 #define DSI_SET_PIXEL_FORMAT 0x3AU 396 #define DSI_SET_SCROLL_AREA 0x33U 397 #define DSI_SET_SCROLL_START 0x37U 398 #define DSI_SET_TEAR_OFF 0x34U 399 #define DSI_SET_TEAR_ON 0x35U 400 #define DSI_SET_TEAR_SCANLINE 0x44U 401 #define DSI_SET_VSYNC_TIMING 0x40U 402 #define DSI_SOFT_RESET 0x01U 403 #define DSI_WRITE_LUT 0x2DU 404 #define DSI_WRITE_MEMORY_CONTINUE 0x3CU 405 #define DSI_WRITE_MEMORY_START 0x2CU 406 /** 407 * @} 408 */ 409 410 /** @defgroup DSI_Video_Mode_Type DSI Video Mode Type 411 * @{ 412 */ 413 #define DSI_VID_MODE_NB_PULSES 0U 414 #define DSI_VID_MODE_NB_EVENTS 1U 415 #define DSI_VID_MODE_BURST 2U 416 /** 417 * @} 418 */ 419 420 /** @defgroup DSI_Color_Mode DSI Color Mode 421 * @{ 422 */ 423 #define DSI_COLOR_MODE_FULL 0x00000000U 424 #define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM 425 /** 426 * @} 427 */ 428 429 /** @defgroup DSI_ShutDown DSI ShutDown 430 * @{ 431 */ 432 #define DSI_DISPLAY_ON 0x00000000U 433 #define DSI_DISPLAY_OFF DSI_WCR_SHTDN 434 /** 435 * @} 436 */ 437 438 /** @defgroup DSI_LP_Command DSI LP Command 439 * @{ 440 */ 441 #define DSI_LP_COMMAND_DISABLE 0x00000000U 442 #define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE 443 /** 444 * @} 445 */ 446 447 /** @defgroup DSI_LP_HFP DSI LP HFP 448 * @{ 449 */ 450 #define DSI_LP_HFP_DISABLE 0x00000000U 451 #define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE 452 /** 453 * @} 454 */ 455 456 /** @defgroup DSI_LP_HBP DSI LP HBP 457 * @{ 458 */ 459 #define DSI_LP_HBP_DISABLE 0x00000000U 460 #define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE 461 /** 462 * @} 463 */ 464 465 /** @defgroup DSI_LP_VACT DSI LP VACT 466 * @{ 467 */ 468 #define DSI_LP_VACT_DISABLE 0x00000000U 469 #define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE 470 /** 471 * @} 472 */ 473 474 /** @defgroup DSI_LP_VFP DSI LP VFP 475 * @{ 476 */ 477 #define DSI_LP_VFP_DISABLE 0x00000000U 478 #define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE 479 /** 480 * @} 481 */ 482 483 /** @defgroup DSI_LP_VBP DSI LP VBP 484 * @{ 485 */ 486 #define DSI_LP_VBP_DISABLE 0x00000000U 487 #define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE 488 /** 489 * @} 490 */ 491 492 /** @defgroup DSI_LP_VSYNC DSI LP VSYNC 493 * @{ 494 */ 495 #define DSI_LP_VSYNC_DISABLE 0x00000000U 496 #define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE 497 /** 498 * @} 499 */ 500 501 /** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge 502 * @{ 503 */ 504 #define DSI_FBTAA_DISABLE 0x00000000U 505 #define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE 506 /** 507 * @} 508 */ 509 510 /** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source 511 * @{ 512 */ 513 #define DSI_TE_DSILINK 0x00000000U 514 #define DSI_TE_EXTERNAL DSI_WCFGR_TESRC 515 /** 516 * @} 517 */ 518 519 /** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity 520 * @{ 521 */ 522 #define DSI_TE_RISING_EDGE 0x00000000U 523 #define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL 524 /** 525 * @} 526 */ 527 528 /** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity 529 * @{ 530 */ 531 #define DSI_VSYNC_FALLING 0x00000000U 532 #define DSI_VSYNC_RISING DSI_WCFGR_VSPOL 533 /** 534 * @} 535 */ 536 537 /** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh 538 * @{ 539 */ 540 #define DSI_AR_DISABLE 0x00000000U 541 #define DSI_AR_ENABLE DSI_WCFGR_AR 542 /** 543 * @} 544 */ 545 546 /** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request 547 * @{ 548 */ 549 #define DSI_TE_ACKNOWLEDGE_DISABLE 0x00000000U 550 #define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE 551 /** 552 * @} 553 */ 554 555 /** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request 556 * @{ 557 */ 558 #define DSI_ACKNOWLEDGE_DISABLE 0x00000000U 559 #define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE 560 /** 561 * @} 562 */ 563 564 /** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP 565 * @{ 566 */ 567 #define DSI_LP_GSW0P_DISABLE 0x00000000U 568 #define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX 569 /** 570 * @} 571 */ 572 573 /** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP 574 * @{ 575 */ 576 #define DSI_LP_GSW1P_DISABLE 0x00000000U 577 #define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX 578 /** 579 * @} 580 */ 581 582 /** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP 583 * @{ 584 */ 585 #define DSI_LP_GSW2P_DISABLE 0x00000000U 586 #define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX 587 /** 588 * @} 589 */ 590 591 /** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP 592 * @{ 593 */ 594 #define DSI_LP_GSR0P_DISABLE 0x00000000U 595 #define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX 596 /** 597 * @} 598 */ 599 600 /** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP 601 * @{ 602 */ 603 #define DSI_LP_GSR1P_DISABLE 0x00000000U 604 #define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX 605 /** 606 * @} 607 */ 608 609 /** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP 610 * @{ 611 */ 612 #define DSI_LP_GSR2P_DISABLE 0x00000000U 613 #define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX 614 /** 615 * @} 616 */ 617 618 /** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite 619 * @{ 620 */ 621 #define DSI_LP_GLW_DISABLE 0x00000000U 622 #define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX 623 /** 624 * @} 625 */ 626 627 /** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP 628 * @{ 629 */ 630 #define DSI_LP_DSW0P_DISABLE 0x00000000U 631 #define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX 632 /** 633 * @} 634 */ 635 636 /** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP 637 * @{ 638 */ 639 #define DSI_LP_DSW1P_DISABLE 0x00000000U 640 #define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX 641 /** 642 * @} 643 */ 644 645 /** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP 646 * @{ 647 */ 648 #define DSI_LP_DSR0P_DISABLE 0x00000000U 649 #define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX 650 /** 651 * @} 652 */ 653 654 /** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write 655 * @{ 656 */ 657 #define DSI_LP_DLW_DISABLE 0x00000000U 658 #define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX 659 /** 660 * @} 661 */ 662 663 /** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet 664 * @{ 665 */ 666 #define DSI_LP_MRDP_DISABLE 0x00000000U 667 #define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS 668 /** 669 * @} 670 */ 671 672 /** @defgroup DSI_HS_PrespMode DSI HS Presp Mode 673 * @{ 674 */ 675 #define DSI_HS_PM_DISABLE 0x00000000U 676 #define DSI_HS_PM_ENABLE DSI_TCCR3_PM 677 /** 678 * @} 679 */ 680 681 682 /** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control 683 * @{ 684 */ 685 #define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0x00000000U 686 #define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR 687 /** 688 * @} 689 */ 690 691 /** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes 692 * @{ 693 */ 694 #define DSI_ONE_DATA_LANE 0U 695 #define DSI_TWO_DATA_LANES 1U 696 /** 697 * @} 698 */ 699 700 /** @defgroup DSI_FlowControl DSI Flow Control 701 * @{ 702 */ 703 #define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE 704 #define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE 705 #define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE 706 #define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE 707 #define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE 708 #define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \ 709 DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \ 710 DSI_FLOW_CONTROL_EOTP_TX) 711 /** 712 * @} 713 */ 714 715 /** @defgroup DSI_Color_Coding DSI Color Coding 716 * @{ 717 */ 718 #define DSI_RGB565 0x00000000U /*!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration */ 719 #define DSI_RGB666 0x00000003U /*!< The value 0x00000004 can also be used for the RGB666 color mode configuration */ 720 #define DSI_RGB888 0x00000005U 721 /** 722 * @} 723 */ 724 725 /** @defgroup DSI_LooselyPacked DSI Loosely Packed 726 * @{ 727 */ 728 #define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE 729 #define DSI_LOOSELY_PACKED_DISABLE 0x00000000U 730 /** 731 * @} 732 */ 733 734 /** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity 735 * @{ 736 */ 737 #define DSI_HSYNC_ACTIVE_HIGH 0x00000000U 738 #define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP 739 /** 740 * @} 741 */ 742 743 /** @defgroup DSI_VSYNC_Active_Polarity DSI VSYNC Active Polarity 744 * @{ 745 */ 746 #define DSI_VSYNC_ACTIVE_HIGH 0x00000000U 747 #define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP 748 /** 749 * @} 750 */ 751 752 /** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity 753 * @{ 754 */ 755 #define DSI_DATA_ENABLE_ACTIVE_HIGH 0x00000000U 756 #define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP 757 /** 758 * @} 759 */ 760 761 /** @defgroup DSI_PLL_IDF DSI PLL IDF 762 * @{ 763 */ 764 #define DSI_PLL_IN_DIV1 0x00000001U 765 #define DSI_PLL_IN_DIV2 0x00000002U 766 #define DSI_PLL_IN_DIV3 0x00000003U 767 #define DSI_PLL_IN_DIV4 0x00000004U 768 #define DSI_PLL_IN_DIV5 0x00000005U 769 #define DSI_PLL_IN_DIV6 0x00000006U 770 #define DSI_PLL_IN_DIV7 0x00000007U 771 /** 772 * @} 773 */ 774 775 /** @defgroup DSI_PLL_ODF DSI PLL ODF 776 * @{ 777 */ 778 #define DSI_PLL_OUT_DIV1 0x00000000U 779 #define DSI_PLL_OUT_DIV2 0x00000001U 780 #define DSI_PLL_OUT_DIV4 0x00000002U 781 #define DSI_PLL_OUT_DIV8 0x00000003U 782 /** 783 * @} 784 */ 785 786 /** @defgroup DSI_Flags DSI Flags 787 * @{ 788 */ 789 #define DSI_FLAG_TE DSI_WISR_TEIF 790 #define DSI_FLAG_ER DSI_WISR_ERIF 791 #define DSI_FLAG_BUSY DSI_WISR_BUSY 792 #define DSI_FLAG_PLLLS DSI_WISR_PLLLS 793 #define DSI_FLAG_PLLL DSI_WISR_PLLLIF 794 #define DSI_FLAG_PLLU DSI_WISR_PLLUIF 795 #define DSI_FLAG_RRS DSI_WISR_RRS 796 #define DSI_FLAG_RR DSI_WISR_RRIF 797 /** 798 * @} 799 */ 800 801 /** @defgroup DSI_Interrupts DSI Interrupts 802 * @{ 803 */ 804 #define DSI_IT_TE DSI_WIER_TEIE 805 #define DSI_IT_ER DSI_WIER_ERIE 806 #define DSI_IT_PLLL DSI_WIER_PLLLIE 807 #define DSI_IT_PLLU DSI_WIER_PLLUIE 808 #define DSI_IT_RR DSI_WIER_RRIE 809 /** 810 * @} 811 */ 812 813 /** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type 814 * @{ 815 */ 816 #define DSI_DCS_SHORT_PKT_WRITE_P0 0x00000005U /*!< DCS short write, no parameters */ 817 #define DSI_DCS_SHORT_PKT_WRITE_P1 0x00000015U /*!< DCS short write, one parameter */ 818 #define DSI_GEN_SHORT_PKT_WRITE_P0 0x00000003U /*!< Generic short write, no parameters */ 819 #define DSI_GEN_SHORT_PKT_WRITE_P1 0x00000013U /*!< Generic short write, one parameter */ 820 #define DSI_GEN_SHORT_PKT_WRITE_P2 0x00000023U /*!< Generic short write, two parameters */ 821 /** 822 * @} 823 */ 824 825 /** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type 826 * @{ 827 */ 828 #define DSI_DCS_LONG_PKT_WRITE 0x00000039U /*!< DCS long write */ 829 #define DSI_GEN_LONG_PKT_WRITE 0x00000029U /*!< Generic long write */ 830 /** 831 * @} 832 */ 833 834 /** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type 835 * @{ 836 */ 837 #define DSI_DCS_SHORT_PKT_READ 0x00000006U /*!< DCS short read */ 838 #define DSI_GEN_SHORT_PKT_READ_P0 0x00000004U /*!< Generic short read, no parameters */ 839 #define DSI_GEN_SHORT_PKT_READ_P1 0x00000014U /*!< Generic short read, one parameter */ 840 #define DSI_GEN_SHORT_PKT_READ_P2 0x00000024U /*!< Generic short read, two parameters */ 841 /** 842 * @} 843 */ 844 845 /** @defgroup DSI_Error_Data_Type DSI Error Data Type 846 * @{ 847 */ 848 #define HAL_DSI_ERROR_NONE 0U 849 #define HAL_DSI_ERROR_ACK 0x00000001U /*!< Acknowledge errors */ 850 #define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */ 851 #define HAL_DSI_ERROR_TX 0x00000004U /*!< Transmission error */ 852 #define HAL_DSI_ERROR_RX 0x00000008U /*!< Reception error */ 853 #define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */ 854 #define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */ 855 #define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */ 856 #define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */ 857 #define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */ 858 #define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */ 859 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 860 #define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U /*!< DSI Invalid Callback error */ 861 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 862 /** 863 * @} 864 */ 865 866 /** @defgroup DSI_Lane_Group DSI Lane Group 867 * @{ 868 */ 869 #define DSI_CLOCK_LANE 0x00000000U 870 #define DSI_DATA_LANES 0x00000001U 871 /** 872 * @} 873 */ 874 875 /** @defgroup DSI_Communication_Delay DSI Communication Delay 876 * @{ 877 */ 878 #define DSI_SLEW_RATE_HSTX 0x00000000U 879 #define DSI_SLEW_RATE_LPTX 0x00000001U 880 #define DSI_HS_DELAY 0x00000002U 881 /** 882 * @} 883 */ 884 885 /** @defgroup DSI_CustomLane DSI CustomLane 886 * @{ 887 */ 888 #define DSI_SWAP_LANE_PINS 0x00000000U 889 #define DSI_INVERT_HS_SIGNAL 0x00000001U 890 /** 891 * @} 892 */ 893 894 /** @defgroup DSI_Lane_Select DSI Lane Select 895 * @{ 896 */ 897 #define DSI_CLK_LANE 0x00000000U 898 #define DSI_DATA_LANE0 0x00000001U 899 #define DSI_DATA_LANE1 0x00000002U 900 /** 901 * @} 902 */ 903 904 /** @defgroup DSI_PHY_Timing DSI PHY Timing 905 * @{ 906 */ 907 #define DSI_TCLK_POST 0x00000000U 908 #define DSI_TLPX_CLK 0x00000001U 909 #define DSI_THS_EXIT 0x00000002U 910 #define DSI_TLPX_DATA 0x00000003U 911 #define DSI_THS_ZERO 0x00000004U 912 #define DSI_THS_TRAIL 0x00000005U 913 #define DSI_THS_PREPARE 0x00000006U 914 #define DSI_TCLK_ZERO 0x00000007U 915 #define DSI_TCLK_PREPARE 0x00000008U 916 /** 917 * @} 918 */ 919 920 921 /** 922 * @} 923 */ 924 925 /* Exported macros -----------------------------------------------------------*/ 926 /** @defgroup DSI_Exported_Macros DSI Exported Macros 927 * @{ 928 */ 929 930 /** 931 * @brief Reset DSI handle state. 932 * @param __HANDLE__ DSI handle 933 * @retval None 934 */ 935 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 936 #define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) do{ \ 937 (__HANDLE__)->State = HAL_DSI_STATE_RESET; \ 938 (__HANDLE__)->MspInitCallback = NULL; \ 939 (__HANDLE__)->MspDeInitCallback = NULL; \ 940 } while(0) 941 #else 942 #define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DSI_STATE_RESET) 943 #endif /*USE_HAL_DSI_REGISTER_CALLBACKS */ 944 945 /** 946 * @brief Enables the DSI host. 947 * @param __HANDLE__ DSI handle 948 * @retval None. 949 */ 950 #define __HAL_DSI_ENABLE(__HANDLE__) do { \ 951 __IO uint32_t tmpreg = 0x00U; \ 952 SET_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ 953 /* Delay after an DSI Host enabling */ \ 954 tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ 955 UNUSED(tmpreg); \ 956 } while(0U) 957 958 /** 959 * @brief Disables the DSI host. 960 * @param __HANDLE__ DSI handle 961 * @retval None. 962 */ 963 #define __HAL_DSI_DISABLE(__HANDLE__) do { \ 964 __IO uint32_t tmpreg = 0x00U; \ 965 CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ 966 /* Delay after an DSI Host disabling */ \ 967 tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ 968 UNUSED(tmpreg); \ 969 } while(0U) 970 971 /** 972 * @brief Enables the DSI wrapper. 973 * @param __HANDLE__ DSI handle 974 * @retval None. 975 */ 976 #define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \ 977 __IO uint32_t tmpreg = 0x00U; \ 978 SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ 979 /* Delay after an DSI warpper enabling */ \ 980 tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ 981 UNUSED(tmpreg); \ 982 } while(0U) 983 984 /** 985 * @brief Disable the DSI wrapper. 986 * @param __HANDLE__ DSI handle 987 * @retval None. 988 */ 989 #define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \ 990 __IO uint32_t tmpreg = 0x00U; \ 991 CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ 992 /* Delay after an DSI warpper disabling*/ \ 993 tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ 994 UNUSED(tmpreg); \ 995 } while(0U) 996 997 /** 998 * @brief Enables the DSI PLL. 999 * @param __HANDLE__ DSI handle 1000 * @retval None. 1001 */ 1002 #define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \ 1003 __IO uint32_t tmpreg = 0x00U; \ 1004 SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ 1005 /* Delay after an DSI PLL enabling */ \ 1006 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ 1007 UNUSED(tmpreg); \ 1008 } while(0U) 1009 1010 /** 1011 * @brief Disables the DSI PLL. 1012 * @param __HANDLE__ DSI handle 1013 * @retval None. 1014 */ 1015 #define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \ 1016 __IO uint32_t tmpreg = 0x00U; \ 1017 CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ 1018 /* Delay after an DSI PLL disabling */ \ 1019 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ 1020 UNUSED(tmpreg); \ 1021 } while(0U) 1022 1023 /** 1024 * @brief Enables the DSI regulator. 1025 * @param __HANDLE__ DSI handle 1026 * @retval None. 1027 */ 1028 #define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \ 1029 __IO uint32_t tmpreg = 0x00U; \ 1030 SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ 1031 /* Delay after an DSI regulator enabling */ \ 1032 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ 1033 UNUSED(tmpreg); \ 1034 } while(0U) 1035 1036 /** 1037 * @brief Disables the DSI regulator. 1038 * @param __HANDLE__ DSI handle 1039 * @retval None. 1040 */ 1041 #define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \ 1042 __IO uint32_t tmpreg = 0x00U; \ 1043 CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ 1044 /* Delay after an DSI regulator disabling */ \ 1045 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ 1046 UNUSED(tmpreg); \ 1047 } while(0U) 1048 1049 /** 1050 * @brief Get the DSI pending flags. 1051 * @param __HANDLE__ DSI handle. 1052 * @param __FLAG__ Get the specified flag. 1053 * This parameter can be any combination of the following values: 1054 * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag 1055 * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag 1056 * @arg DSI_FLAG_BUSY : Busy Flag 1057 * @arg DSI_FLAG_PLLLS: PLL Lock Status 1058 * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag 1059 * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag 1060 * @arg DSI_FLAG_RRS : Regulator Ready Flag 1061 * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag 1062 * @retval The state of FLAG (SET or RESET). 1063 */ 1064 #define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__)) 1065 1066 /** 1067 * @brief Clears the DSI pending flags. 1068 * @param __HANDLE__ DSI handle. 1069 * @param __FLAG__ specifies the flag to clear. 1070 * This parameter can be any combination of the following values: 1071 * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag 1072 * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag 1073 * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag 1074 * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag 1075 * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag 1076 * @retval None 1077 */ 1078 #define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__)) 1079 1080 /** 1081 * @brief Enables the specified DSI interrupts. 1082 * @param __HANDLE__ DSI handle. 1083 * @param __INTERRUPT__ specifies the DSI interrupt sources to be enabled. 1084 * This parameter can be any combination of the following values: 1085 * @arg DSI_IT_TE : Tearing Effect Interrupt 1086 * @arg DSI_IT_ER : End of Refresh Interrupt 1087 * @arg DSI_IT_PLLL: PLL Lock Interrupt 1088 * @arg DSI_IT_PLLU: PLL Unlock Interrupt 1089 * @arg DSI_IT_RR : Regulator Ready Interrupt 1090 * @retval None 1091 */ 1092 #define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__)) 1093 1094 /** 1095 * @brief Disables the specified DSI interrupts. 1096 * @param __HANDLE__ DSI handle 1097 * @param __INTERRUPT__ specifies the DSI interrupt sources to be disabled. 1098 * This parameter can be any combination of the following values: 1099 * @arg DSI_IT_TE : Tearing Effect Interrupt 1100 * @arg DSI_IT_ER : End of Refresh Interrupt 1101 * @arg DSI_IT_PLLL: PLL Lock Interrupt 1102 * @arg DSI_IT_PLLU: PLL Unlock Interrupt 1103 * @arg DSI_IT_RR : Regulator Ready Interrupt 1104 * @retval None 1105 */ 1106 #define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__)) 1107 1108 /** 1109 * @brief Checks whether the specified DSI interrupt source is enabled or not. 1110 * @param __HANDLE__ DSI handle 1111 * @param __INTERRUPT__ specifies the DSI interrupt source to check. 1112 * This parameter can be one of the following values: 1113 * @arg DSI_IT_TE : Tearing Effect Interrupt 1114 * @arg DSI_IT_ER : End of Refresh Interrupt 1115 * @arg DSI_IT_PLLL: PLL Lock Interrupt 1116 * @arg DSI_IT_PLLU: PLL Unlock Interrupt 1117 * @arg DSI_IT_RR : Regulator Ready Interrupt 1118 * @retval The state of INTERRUPT (SET or RESET). 1119 */ 1120 #define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__)) 1121 1122 /** 1123 * @} 1124 */ 1125 1126 /* Exported functions --------------------------------------------------------*/ 1127 /** @defgroup DSI_Exported_Functions DSI Exported Functions 1128 * @{ 1129 */ 1130 /** @defgroup DSI_Group1 Initialization and Configuration functions 1131 * @brief Initialization and Configuration functions 1132 * @{ 1133 */ 1134 HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit); 1135 HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi); 1136 void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi); 1137 void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi); 1138 HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors); 1139 /* Callbacks Register/UnRegister functions ***********************************/ 1140 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 1141 HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID, 1142 pDSI_CallbackTypeDef pCallback); 1143 HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID); 1144 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 1145 /** 1146 * @} 1147 */ 1148 1149 /** @defgroup DSI_Group2 IO operation functions 1150 * @brief IO operation functions 1151 * @{ 1152 */ 1153 void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi); 1154 void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi); 1155 void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi); 1156 void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi); 1157 /** 1158 * @} 1159 */ 1160 1161 /** @defgroup DSI_Group3 Peripheral Control functions 1162 * @brief Peripheral Control functions 1163 * @{ 1164 */ 1165 HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID); 1166 HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg); 1167 HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg); 1168 HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd); 1169 HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl); 1170 HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers); 1171 HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts); 1172 HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi); 1173 HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi); 1174 HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi); 1175 HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode); 1176 HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown); 1177 HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, 1178 uint32_t ChannelID, 1179 uint32_t Mode, 1180 uint32_t Param1, 1181 uint32_t Param2); 1182 HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, 1183 uint32_t ChannelID, 1184 uint32_t Mode, 1185 uint32_t NbParams, 1186 uint32_t Param1, 1187 uint8_t *ParametersTable); 1188 HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, 1189 uint32_t ChannelNbr, 1190 uint8_t *Array, 1191 uint32_t Size, 1192 uint32_t Mode, 1193 uint32_t DCSCmd, 1194 uint8_t *ParametersTable); 1195 HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi); 1196 HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi); 1197 HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi); 1198 HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi); 1199 1200 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation); 1201 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi); 1202 1203 HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, 1204 uint32_t Value); 1205 HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency); 1206 HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State); 1207 HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, 1208 FunctionalState State); 1209 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, 1210 uint32_t Value); 1211 HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State); 1212 HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State); 1213 HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State); 1214 HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State); 1215 HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State); 1216 1217 /** 1218 * @} 1219 */ 1220 1221 /** @defgroup DSI_Group4 Peripheral State and Errors functions 1222 * @brief Peripheral State and Errors functions 1223 * @{ 1224 */ 1225 uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi); 1226 HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); 1227 1228 /** 1229 * @} 1230 */ 1231 1232 /** 1233 * @} 1234 */ 1235 1236 /* Private types -------------------------------------------------------------*/ 1237 /* Private defines -----------------------------------------------------------*/ 1238 /* Private variables ---------------------------------------------------------*/ 1239 /* Private constants ---------------------------------------------------------*/ 1240 /** @defgroup DSI_Private_Constants DSI Private Constants 1241 * @{ 1242 */ 1243 #define DSI_MAX_RETURN_PKT_SIZE (0x00000037U) /*!< Maximum return packet configuration */ 1244 /** 1245 * @} 1246 */ 1247 1248 /* Private macros ------------------------------------------------------------*/ 1249 /** @defgroup DSI_Private_Macros DSI Private Macros 1250 * @{ 1251 */ 1252 #define IS_DSI_PLL_NDIV(NDIV) ((10U <= (NDIV)) && ((NDIV) <= 125U)) 1253 #define IS_DSI_PLL_IDF(IDF) (((IDF) == DSI_PLL_IN_DIV1) || \ 1254 ((IDF) == DSI_PLL_IN_DIV2) || \ 1255 ((IDF) == DSI_PLL_IN_DIV3) || \ 1256 ((IDF) == DSI_PLL_IN_DIV4) || \ 1257 ((IDF) == DSI_PLL_IN_DIV5) || \ 1258 ((IDF) == DSI_PLL_IN_DIV6) || \ 1259 ((IDF) == DSI_PLL_IN_DIV7)) 1260 #define IS_DSI_PLL_ODF(ODF) (((ODF) == DSI_PLL_OUT_DIV1) || \ 1261 ((ODF) == DSI_PLL_OUT_DIV2) || \ 1262 ((ODF) == DSI_PLL_OUT_DIV4) || \ 1263 ((ODF) == DSI_PLL_OUT_DIV8)) 1264 #define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE)\ 1265 || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE)) 1266 #define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE)\ 1267 || ((NumberOfLanes) == DSI_TWO_DATA_LANES)) 1268 #define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL) 1269 #define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U) 1270 #define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE)\ 1271 || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE)) 1272 #define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH)\ 1273 || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW)) 1274 #define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH)\ 1275 || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW)) 1276 #define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH)\ 1277 || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW)) 1278 #define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \ 1279 ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \ 1280 ((VideoModeType) == DSI_VID_MODE_BURST)) 1281 #define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL)\ 1282 || ((ColorMode) == DSI_COLOR_MODE_EIGHT)) 1283 #define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF)) 1284 #define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE)\ 1285 || ((LPCommand) == DSI_LP_COMMAND_ENABLE)) 1286 #define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE)) 1287 #define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE)) 1288 #define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE)\ 1289 || ((LPVActive) == DSI_LP_VACT_ENABLE)) 1290 #define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE)) 1291 #define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE)) 1292 #define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE)\ 1293 || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE)) 1294 #define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE)\ 1295 || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE)) 1296 #define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL)) 1297 #define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE)\ 1298 || ((TEPolarity) == DSI_TE_FALLING_EDGE)) 1299 #define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE)\ 1300 || ((AutomaticRefresh) == DSI_AR_ENABLE)) 1301 #define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING)\ 1302 || ((VSPolarity) == DSI_VSYNC_RISING)) 1303 #define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE)\ 1304 || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE)) 1305 #define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE)\ 1306 || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE)) 1307 #define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE)\ 1308 || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE)) 1309 #define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE)\ 1310 || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE)) 1311 #define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE)\ 1312 || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE)) 1313 #define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE)\ 1314 || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE)) 1315 #define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE)\ 1316 || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE)) 1317 #define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE)\ 1318 || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE)) 1319 #define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE)\ 1320 || ((LP_GLW) == DSI_LP_GLW_ENABLE)) 1321 #define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE)\ 1322 || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE)) 1323 #define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE)\ 1324 || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE)) 1325 #define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE)\ 1326 || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE)) 1327 #define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE)\ 1328 || ((LP_DLW) == DSI_LP_DLW_ENABLE)) 1329 #define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE)\ 1330 || ((LP_MRDP) == DSI_LP_MRDP_ENABLE)) 1331 #define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \ 1332 ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \ 1333 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \ 1334 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \ 1335 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2)) 1336 #define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \ 1337 ((MODE) == DSI_GEN_LONG_PKT_WRITE)) 1338 #define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) || \ 1339 ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \ 1340 ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \ 1341 ((MODE) == DSI_GEN_SHORT_PKT_READ_P2)) 1342 #define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || \ 1343 ((CommDelay) == DSI_SLEW_RATE_LPTX) || \ 1344 ((CommDelay) == DSI_HS_DELAY)) 1345 #define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES)) 1346 #define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS)\ 1347 || ((CustomLane) == DSI_INVERT_HS_SIGNAL)) 1348 #define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || \ 1349 ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1)) 1350 #define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \ 1351 ((Timing) == DSI_TLPX_CLK ) || \ 1352 ((Timing) == DSI_THS_EXIT ) || \ 1353 ((Timing) == DSI_TLPX_DATA ) || \ 1354 ((Timing) == DSI_THS_ZERO ) || \ 1355 ((Timing) == DSI_THS_TRAIL ) || \ 1356 ((Timing) == DSI_THS_PREPARE ) || \ 1357 ((Timing) == DSI_TCLK_ZERO ) || \ 1358 ((Timing) == DSI_TCLK_PREPARE)) 1359 1360 /** 1361 * @} 1362 */ 1363 1364 /** 1365 * @} 1366 */ 1367 1368 /** 1369 * @} 1370 */ 1371 #endif /* DSI */ 1372 1373 #ifdef __cplusplus 1374 } 1375 #endif 1376 1377 #endif /* STM32F7xx_HAL_DSI_H */ 1378
