1 /** 2 ****************************************************************************** 3 * @file stm32f7xx_hal_dma2d.h 4 * @author MCD Application Team 5 * @brief Header file of DMA2D HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32F7xx_HAL_DMA2D_H 21 #define STM32F7xx_HAL_DMA2D_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f7xx_hal_def.h" 29 30 /** @addtogroup STM32F7xx_HAL_Driver 31 * @{ 32 */ 33 34 #if defined (DMA2D) 35 36 /** @addtogroup DMA2D DMA2D 37 * @brief DMA2D HAL module driver 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup DMA2D_Exported_Types DMA2D Exported Types 43 * @{ 44 */ 45 #define MAX_DMA2D_LAYER 2U /*!< DMA2D maximum number of layers */ 46 47 /** 48 * @brief DMA2D CLUT Structure definition 49 */ 50 typedef struct 51 { 52 uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/ 53 54 uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode. 55 This parameter can be one value of @ref DMA2D_CLUT_CM. */ 56 57 uint32_t Size; /*!< Configures the DMA2D CLUT size. 58 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/ 59 } DMA2D_CLUTCfgTypeDef; 60 61 /** 62 * @brief DMA2D Init structure definition 63 */ 64 typedef struct 65 { 66 uint32_t Mode; /*!< Configures the DMA2D transfer mode. 67 This parameter can be one value of @ref DMA2D_Mode. */ 68 69 uint32_t ColorMode; /*!< Configures the color format of the output image. 70 This parameter can be one value of @ref DMA2D_Output_Color_Mode. */ 71 72 uint32_t OutputOffset; /*!< Specifies the Offset value. 73 This parameter must be a number between 74 Min_Data = 0x0000 and Max_Data = 0x3FFF. */ 75 #if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) 76 uint32_t AlphaInverted; /*!< Select regular or inverted alpha value 77 for the output pixel format converter. 78 This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ 79 80 uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR) 81 for the output pixel format converter. 82 This parameter can be one value of @ref DMA2D_RB_Swap. */ 83 84 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ 85 86 87 88 89 } DMA2D_InitTypeDef; 90 91 92 /** 93 * @brief DMA2D Layer structure definition 94 */ 95 typedef struct 96 { 97 uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset. 98 This parameter must be a number between 99 Min_Data = 0x0000 and Max_Data = 0x3FFF. */ 100 101 uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode. 102 This parameter can be one value of @ref DMA2D_Input_Color_Mode. */ 103 104 uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode. 105 This parameter can be one value of @ref DMA2D_Alpha_Mode. */ 106 107 uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value 108 in case of A8 or A4 color mode. 109 This parameter must be a number between Min_Data = 0x00 110 and Max_Data = 0xFF except for the color modes detailed below. 111 @note In case of A8 or A4 color mode (ARGB), 112 this parameter must be a number between 113 Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where 114 - InputAlpha[24:31] is the alpha value ALPHA[0:7] 115 - InputAlpha[16:23] is the red value RED[0:7] 116 - InputAlpha[8:15] is the green value GREEN[0:7] 117 - InputAlpha[0:7] is the blue value BLUE[0:7]. */ 118 #if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) 119 uint32_t AlphaInverted; /*!< Select regular or inverted alpha value. 120 This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ 121 122 uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR). 123 This parameter can be one value of @ref DMA2D_RB_Swap. */ 124 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ 125 126 127 } DMA2D_LayerCfgTypeDef; 128 129 /** 130 * @brief HAL DMA2D State structures definition 131 */ 132 typedef enum 133 { 134 HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */ 135 HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 136 HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 137 HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 138 HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */ 139 HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */ 140 } HAL_DMA2D_StateTypeDef; 141 142 /** 143 * @brief DMA2D handle Structure definition 144 */ 145 typedef struct __DMA2D_HandleTypeDef 146 { 147 DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */ 148 149 DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */ 150 151 void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer complete callback. */ 152 153 void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer error callback. */ 154 155 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 156 void (* LineEventCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D line event callback. */ 157 158 void (* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D CLUT loading completion callback */ 159 160 void (* MspInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp Init callback. */ 161 162 void (* MspDeInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp DeInit callback. */ 163 164 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ 165 166 DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ 167 168 HAL_LockTypeDef Lock; /*!< DMA2D lock. */ 169 170 __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */ 171 172 __IO uint32_t ErrorCode; /*!< DMA2D error code. */ 173 } DMA2D_HandleTypeDef; 174 175 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 176 /** 177 * @brief HAL DMA2D Callback pointer definition 178 */ 179 typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointer to a DMA2D common callback function */ 180 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 181 /** 182 * @} 183 */ 184 185 /* Exported constants --------------------------------------------------------*/ 186 /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants 187 * @{ 188 */ 189 190 /** @defgroup DMA2D_Error_Code DMA2D Error Code 191 * @{ 192 */ 193 #define HAL_DMA2D_ERROR_NONE 0x00000000U /*!< No error */ 194 #define HAL_DMA2D_ERROR_TE 0x00000001U /*!< Transfer error */ 195 #define HAL_DMA2D_ERROR_CE 0x00000002U /*!< Configuration error */ 196 #define HAL_DMA2D_ERROR_CAE 0x00000004U /*!< CLUT access error */ 197 #define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 198 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 199 #define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid callback error */ 200 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ 201 202 /** 203 * @} 204 */ 205 206 /** @defgroup DMA2D_Mode DMA2D Mode 207 * @{ 208 */ 209 #define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ 210 #define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ 211 #define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ 212 #define DMA2D_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */ 213 /** 214 * @} 215 */ 216 217 /** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode 218 * @{ 219 */ 220 #define DMA2D_OUTPUT_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D color mode */ 221 #define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */ 222 #define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */ 223 #define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */ 224 #define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */ 225 /** 226 * @} 227 */ 228 229 /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode 230 * @{ 231 */ 232 #define DMA2D_INPUT_ARGB8888 0x00000000U /*!< ARGB8888 color mode */ 233 #define DMA2D_INPUT_RGB888 0x00000001U /*!< RGB888 color mode */ 234 #define DMA2D_INPUT_RGB565 0x00000002U /*!< RGB565 color mode */ 235 #define DMA2D_INPUT_ARGB1555 0x00000003U /*!< ARGB1555 color mode */ 236 #define DMA2D_INPUT_ARGB4444 0x00000004U /*!< ARGB4444 color mode */ 237 #define DMA2D_INPUT_L8 0x00000005U /*!< L8 color mode */ 238 #define DMA2D_INPUT_AL44 0x00000006U /*!< AL44 color mode */ 239 #define DMA2D_INPUT_AL88 0x00000007U /*!< AL88 color mode */ 240 #define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */ 241 #define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */ 242 #define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */ 243 /** 244 * @} 245 */ 246 247 /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode 248 * @{ 249 */ 250 #define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ 251 #define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */ 252 #define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value 253 with original alpha channel value */ 254 /** 255 * @} 256 */ 257 258 #if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) 259 /** @defgroup DMA2D_Alpha_Inverted DMA2D Alpha Inversion 260 * @{ 261 */ 262 #define DMA2D_REGULAR_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ 263 #define DMA2D_INVERTED_ALPHA 0x00000001U /*!< Invert the alpha channel value */ 264 /** 265 * @} 266 */ 267 268 /** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap 269 * @{ 270 */ 271 #define DMA2D_RB_REGULAR 0x00000000U /*!< Select regular mode (RGB or ARGB) */ 272 #define DMA2D_RB_SWAP 0x00000001U /*!< Select swap mode (BGR or ABGR) */ 273 /** 274 * @} 275 */ 276 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ 277 278 279 280 281 282 /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode 283 * @{ 284 */ 285 #define DMA2D_CCM_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D CLUT color mode */ 286 #define DMA2D_CCM_RGB888 0x00000001U /*!< RGB888 DMA2D CLUT color mode */ 287 /** 288 * @} 289 */ 290 291 /** @defgroup DMA2D_Interrupts DMA2D Interrupts 292 * @{ 293 */ 294 #define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ 295 #define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */ 296 #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */ 297 #define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ 298 #define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ 299 #define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ 300 /** 301 * @} 302 */ 303 304 /** @defgroup DMA2D_Flags DMA2D Flags 305 * @{ 306 */ 307 #define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ 308 #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ 309 #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ 310 #define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ 311 #define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ 312 #define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ 313 /** 314 * @} 315 */ 316 317 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 318 /** 319 * @brief HAL DMA2D common Callback ID enumeration definition 320 */ 321 typedef enum 322 { 323 HAL_DMA2D_MSPINIT_CB_ID = 0x00U, /*!< DMA2D MspInit callback ID */ 324 HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U, /*!< DMA2D MspDeInit callback ID */ 325 HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U, /*!< DMA2D transfer complete callback ID */ 326 HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */ 327 HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */ 328 HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */ 329 } HAL_DMA2D_CallbackIDTypeDef; 330 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 331 332 333 /** 334 * @} 335 */ 336 /* Exported macros ------------------------------------------------------------*/ 337 /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros 338 * @{ 339 */ 340 341 /** @brief Reset DMA2D handle state 342 * @param __HANDLE__ specifies the DMA2D handle. 343 * @retval None 344 */ 345 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 346 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \ 347 (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\ 348 (__HANDLE__)->MspInitCallback = NULL; \ 349 (__HANDLE__)->MspDeInitCallback = NULL; \ 350 }while(0) 351 #else 352 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) 353 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 354 355 356 /** 357 * @brief Enable the DMA2D. 358 * @param __HANDLE__ DMA2D handle 359 * @retval None. 360 */ 361 #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) 362 363 364 /* Interrupt & Flag management */ 365 /** 366 * @brief Get the DMA2D pending flags. 367 * @param __HANDLE__ DMA2D handle 368 * @param __FLAG__ flag to check. 369 * This parameter can be any combination of the following values: 370 * @arg DMA2D_FLAG_CE: Configuration error flag 371 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag 372 * @arg DMA2D_FLAG_CAE: CLUT access error flag 373 * @arg DMA2D_FLAG_TW: Transfer Watermark flag 374 * @arg DMA2D_FLAG_TC: Transfer complete flag 375 * @arg DMA2D_FLAG_TE: Transfer error flag 376 * @retval The state of FLAG. 377 */ 378 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) 379 380 /** 381 * @brief Clear the DMA2D pending flags. 382 * @param __HANDLE__ DMA2D handle 383 * @param __FLAG__ specifies the flag to clear. 384 * This parameter can be any combination of the following values: 385 * @arg DMA2D_FLAG_CE: Configuration error flag 386 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag 387 * @arg DMA2D_FLAG_CAE: CLUT access error flag 388 * @arg DMA2D_FLAG_TW: Transfer Watermark flag 389 * @arg DMA2D_FLAG_TC: Transfer complete flag 390 * @arg DMA2D_FLAG_TE: Transfer error flag 391 * @retval None 392 */ 393 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__)) 394 395 /** 396 * @brief Enable the specified DMA2D interrupts. 397 * @param __HANDLE__ DMA2D handle 398 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled. 399 * This parameter can be any combination of the following values: 400 * @arg DMA2D_IT_CE: Configuration error interrupt mask 401 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 402 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 403 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 404 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 405 * @arg DMA2D_IT_TE: Transfer error interrupt mask 406 * @retval None 407 */ 408 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) 409 410 /** 411 * @brief Disable the specified DMA2D interrupts. 412 * @param __HANDLE__ DMA2D handle 413 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled. 414 * This parameter can be any combination of the following values: 415 * @arg DMA2D_IT_CE: Configuration error interrupt mask 416 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 417 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 418 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 419 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 420 * @arg DMA2D_IT_TE: Transfer error interrupt mask 421 * @retval None 422 */ 423 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) 424 425 /** 426 * @brief Check whether the specified DMA2D interrupt source is enabled or not. 427 * @param __HANDLE__ DMA2D handle 428 * @param __INTERRUPT__ specifies the DMA2D interrupt source to check. 429 * This parameter can be one of the following values: 430 * @arg DMA2D_IT_CE: Configuration error interrupt mask 431 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 432 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 433 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 434 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 435 * @arg DMA2D_IT_TE: Transfer error interrupt mask 436 * @retval The state of INTERRUPT source. 437 */ 438 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) 439 440 /** 441 * @} 442 */ 443 444 /* Exported functions --------------------------------------------------------*/ 445 /** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions 446 * @{ 447 */ 448 449 /** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions 450 * @{ 451 */ 452 453 /* Initialization and de-initialization functions *******************************/ 454 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); 455 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d); 456 void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d); 457 void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d); 458 /* Callbacks Register/UnRegister functions ***********************************/ 459 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 460 HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, 461 pDMA2D_CallbackTypeDef pCallback); 462 HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID); 463 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 464 465 /** 466 * @} 467 */ 468 469 470 /** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions 471 * @{ 472 */ 473 474 /* IO operation functions *******************************************************/ 475 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, 476 uint32_t Height); 477 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, 478 uint32_t DstAddress, uint32_t Width, uint32_t Height); 479 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, 480 uint32_t Height); 481 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, 482 uint32_t DstAddress, uint32_t Width, uint32_t Height); 483 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); 484 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); 485 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); 486 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 487 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, 488 uint32_t LayerIdx); 489 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, 490 uint32_t LayerIdx); 491 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 492 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 493 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 494 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 495 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 496 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout); 497 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d); 498 void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d); 499 void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d); 500 501 /** 502 * @} 503 */ 504 505 /** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions 506 * @{ 507 */ 508 509 /* Peripheral Control functions *************************************************/ 510 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 511 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 512 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line); 513 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d); 514 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d); 515 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime); 516 517 /** 518 * @} 519 */ 520 521 /** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions 522 * @{ 523 */ 524 525 /* Peripheral State functions ***************************************************/ 526 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d); 527 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); 528 529 /** 530 * @} 531 */ 532 533 /** 534 * @} 535 */ 536 537 /* Private constants ---------------------------------------------------------*/ 538 539 /** @addtogroup DMA2D_Private_Constants DMA2D Private Constants 540 * @{ 541 */ 542 543 /** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark 544 * @{ 545 */ 546 #define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */ 547 /** 548 * @} 549 */ 550 551 /** @defgroup DMA2D_Color_Value DMA2D Color Value 552 * @{ 553 */ 554 #define DMA2D_COLOR_VALUE 0x000000FFU /*!< Color value mask */ 555 /** 556 * @} 557 */ 558 559 /** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers 560 * @{ 561 */ 562 #define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */ 563 /** 564 * @} 565 */ 566 567 /** @defgroup DMA2D_Layers DMA2D Layers 568 * @{ 569 */ 570 #define DMA2D_BACKGROUND_LAYER 0x00000000U /*!< DMA2D Background Layer (layer 0) */ 571 #define DMA2D_FOREGROUND_LAYER 0x00000001U /*!< DMA2D Foreground Layer (layer 1) */ 572 /** 573 * @} 574 */ 575 576 /** @defgroup DMA2D_Offset DMA2D Offset 577 * @{ 578 */ 579 #define DMA2D_OFFSET DMA2D_FGOR_LO /*!< maximum Line Offset */ 580 /** 581 * @} 582 */ 583 584 /** @defgroup DMA2D_Size DMA2D Size 585 * @{ 586 */ 587 #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D maximum number of pixels per line */ 588 #define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D maximum number of lines */ 589 /** 590 * @} 591 */ 592 593 /** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size 594 * @{ 595 */ 596 #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D maximum CLUT size */ 597 /** 598 * @} 599 */ 600 601 /** 602 * @} 603 */ 604 605 606 /* Private macros ------------------------------------------------------------*/ 607 /** @defgroup DMA2D_Private_Macros DMA2D Private Macros 608 * @{ 609 */ 610 #define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER)\ 611 || ((LAYER) == DMA2D_FOREGROUND_LAYER)) 612 613 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ 614 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) 615 616 #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || \ 617 ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ 618 ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || \ 619 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ 620 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) 621 622 #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE) 623 #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE) 624 #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) 625 #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) 626 627 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \ 628 ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ 629 ((INPUT_CM) == DMA2D_INPUT_RGB565) || \ 630 ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ 631 ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \ 632 ((INPUT_CM) == DMA2D_INPUT_L8) || \ 633 ((INPUT_CM) == DMA2D_INPUT_AL44) || \ 634 ((INPUT_CM) == DMA2D_INPUT_AL88) || \ 635 ((INPUT_CM) == DMA2D_INPUT_L4) || \ 636 ((INPUT_CM) == DMA2D_INPUT_A8) || \ 637 ((INPUT_CM) == DMA2D_INPUT_A4)) 638 639 #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ 640 ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \ 641 ((AlphaMode) == DMA2D_COMBINE_ALPHA)) 642 643 #if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) 644 #define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \ 645 ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA)) 646 647 #define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \ 648 ((RB_Swap) == DMA2D_RB_SWAP)) 649 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ 650 651 652 653 654 #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) 655 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) 656 #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX) 657 #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ 658 ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ 659 ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) 660 #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ 661 ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ 662 ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) 663 /** 664 * @} 665 */ 666 667 /** 668 * @} 669 */ 670 671 #endif /* defined (DMA2D) */ 672 673 /** 674 * @} 675 */ 676 677 #ifdef __cplusplus 678 } 679 #endif 680 681 #endif /* STM32F7xx_HAL_DMA2D_H */ 682
