1 /** 2 ****************************************************************************** 3 * @file stm32f7xx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32F7xx_HAL_DMA_H 21 #define __STM32F7xx_HAL_DMA_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f7xx_hal_def.h" 29 30 /** @addtogroup STM32F7xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup DMA 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 40 /** @defgroup DMA_Exported_Types DMA Exported Types 41 * @brief DMA Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief DMA Configuration Structure definition 47 */ 48 typedef struct 49 { 50 uint32_t Channel; /*!< Specifies the channel used for the specified stream. 51 This parameter can be a value of @ref DMAEx_Channel_selection */ 52 53 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 54 from memory to memory or from peripheral to memory. 55 This parameter can be a value of @ref DMA_Data_transfer_direction */ 56 57 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 58 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 59 60 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 61 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 62 63 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 64 This parameter can be a value of @ref DMA_Peripheral_data_size */ 65 66 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 67 This parameter can be a value of @ref DMA_Memory_data_size */ 68 69 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. 70 This parameter can be a value of @ref DMA_mode 71 @note The circular buffer mode cannot be used if the memory-to-memory 72 data transfer is configured on the selected Stream */ 73 74 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. 75 This parameter can be a value of @ref DMA_Priority_level */ 76 77 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. 78 This parameter can be a value of @ref DMA_FIFO_direct_mode 79 @note The Direct mode (FIFO mode disabled) cannot be used if the 80 memory-to-memory data transfer is configured on the selected stream */ 81 82 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. 83 This parameter can be a value of @ref DMA_FIFO_threshold_level */ 84 85 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. 86 It specifies the amount of data to be transferred in a single non interruptible 87 transaction. 88 This parameter can be a value of @ref DMA_Memory_burst 89 @note The burst mode is possible only if the address Increment mode is enabled. */ 90 91 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. 92 It specifies the amount of data to be transferred in a single non interruptible 93 transaction. 94 This parameter can be a value of @ref DMA_Peripheral_burst 95 @note The burst mode is possible only if the address Increment mode is enabled. */ 96 }DMA_InitTypeDef; 97 98 /** 99 * @brief HAL DMA State structures definition 100 */ 101 typedef enum 102 { 103 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 104 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 105 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 106 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ 107 HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */ 108 HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */ 109 }HAL_DMA_StateTypeDef; 110 111 /** 112 * @brief HAL DMA Error Code structure definition 113 */ 114 typedef enum 115 { 116 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 117 HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */ 118 }HAL_DMA_LevelCompleteTypeDef; 119 120 /** 121 * @brief HAL DMA Error Code structure definition 122 */ 123 typedef enum 124 { 125 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 126 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */ 127 HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */ 128 HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */ 129 HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ 130 HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ 131 HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ 132 }HAL_DMA_CallbackIDTypeDef; 133 134 /** 135 * @brief DMA handle Structure definition 136 */ 137 typedef struct __DMA_HandleTypeDef 138 { 139 DMA_Stream_TypeDef *Instance; /*!< Register base address */ 140 141 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 142 143 HAL_LockTypeDef Lock; /*!< DMA locking object */ 144 145 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 146 147 void *Parent; /*!< Parent object state */ 148 149 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ 150 151 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ 152 153 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ 154 155 void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */ 156 157 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ 158 159 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */ 160 161 __IO uint32_t ErrorCode; /*!< DMA Error code */ 162 163 uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ 164 165 uint32_t StreamIndex; /*!< DMA Stream Index */ 166 167 }DMA_HandleTypeDef; 168 169 /** 170 * @} 171 */ 172 173 174 /* Exported constants --------------------------------------------------------*/ 175 176 /** @defgroup DMA_Exported_Constants DMA Exported Constants 177 * @brief DMA Exported constants 178 * @{ 179 */ 180 181 /** @defgroup DMA_Error_Code DMA Error Code 182 * @brief DMA Error Code 183 * @{ 184 */ 185 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ 186 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ 187 #define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */ 188 #define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */ 189 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 190 #define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */ 191 #define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */ 192 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ 193 /** 194 * @} 195 */ 196 197 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 198 * @brief DMA data transfer direction 199 * @{ 200 */ 201 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 202 #define DMA_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */ 203 #define DMA_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */ 204 /** 205 * @} 206 */ 207 208 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 209 * @brief DMA peripheral incremented mode 210 * @{ 211 */ 212 #define DMA_PINC_ENABLE DMA_SxCR_PINC /*!< Peripheral increment mode enable */ 213 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */ 214 /** 215 * @} 216 */ 217 218 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 219 * @brief DMA memory incremented mode 220 * @{ 221 */ 222 #define DMA_MINC_ENABLE DMA_SxCR_MINC /*!< Memory increment mode enable */ 223 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */ 224 /** 225 * @} 226 */ 227 228 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 229 * @brief DMA peripheral data size 230 * @{ 231 */ 232 #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ 233 #define DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment: HalfWord */ 234 #define DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment: Word */ 235 /** 236 * @} 237 */ 238 239 /** @defgroup DMA_Memory_data_size DMA Memory data size 240 * @brief DMA memory data size 241 * @{ 242 */ 243 #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ 244 #define DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment: HalfWord */ 245 #define DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment: Word */ 246 /** 247 * @} 248 */ 249 250 /** @defgroup DMA_mode DMA mode 251 * @brief DMA mode 252 * @{ 253 */ 254 #define DMA_NORMAL 0x00000000U /*!< Normal mode */ 255 #define DMA_CIRCULAR DMA_SxCR_CIRC /*!< Circular mode */ 256 #define DMA_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */ 257 /** 258 * @} 259 */ 260 261 /** @defgroup DMA_Priority_level DMA Priority level 262 * @brief DMA priority levels 263 * @{ 264 */ 265 #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */ 266 #define DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level: Medium */ 267 #define DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level: High */ 268 #define DMA_PRIORITY_VERY_HIGH DMA_SxCR_PL /*!< Priority level: Very High */ 269 /** 270 * @} 271 */ 272 273 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode 274 * @brief DMA FIFO direct mode 275 * @{ 276 */ 277 #define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ 278 #define DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */ 279 /** 280 * @} 281 */ 282 283 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level 284 * @brief DMA FIFO level 285 * @{ 286 */ 287 #define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */ 288 #define DMA_FIFO_THRESHOLD_HALFFULL DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */ 289 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */ 290 #define DMA_FIFO_THRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */ 291 /** 292 * @} 293 */ 294 295 /** @defgroup DMA_Memory_burst DMA Memory burst 296 * @brief DMA memory burst 297 * @{ 298 */ 299 #define DMA_MBURST_SINGLE 0x00000000U 300 #define DMA_MBURST_INC4 DMA_SxCR_MBURST_0 301 #define DMA_MBURST_INC8 DMA_SxCR_MBURST_1 302 #define DMA_MBURST_INC16 DMA_SxCR_MBURST 303 /** 304 * @} 305 */ 306 307 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst 308 * @brief DMA peripheral burst 309 * @{ 310 */ 311 #define DMA_PBURST_SINGLE 0x00000000U 312 #define DMA_PBURST_INC4 DMA_SxCR_PBURST_0 313 #define DMA_PBURST_INC8 DMA_SxCR_PBURST_1 314 #define DMA_PBURST_INC16 DMA_SxCR_PBURST 315 /** 316 * @} 317 */ 318 319 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 320 * @brief DMA interrupts definition 321 * @{ 322 */ 323 #define DMA_IT_TC DMA_SxCR_TCIE 324 #define DMA_IT_HT DMA_SxCR_HTIE 325 #define DMA_IT_TE DMA_SxCR_TEIE 326 #define DMA_IT_DME DMA_SxCR_DMEIE 327 #define DMA_IT_FE 0x00000080U 328 /** 329 * @} 330 */ 331 332 /** @defgroup DMA_flag_definitions DMA flag definitions 333 * @brief DMA flag definitions 334 * @{ 335 */ 336 #define DMA_FLAG_FEIF0_4 0x00000001U 337 #define DMA_FLAG_DMEIF0_4 0x00000004U 338 #define DMA_FLAG_TEIF0_4 0x00000008U 339 #define DMA_FLAG_HTIF0_4 0x00000010U 340 #define DMA_FLAG_TCIF0_4 0x00000020U 341 #define DMA_FLAG_FEIF1_5 0x00000040U 342 #define DMA_FLAG_DMEIF1_5 0x00000100U 343 #define DMA_FLAG_TEIF1_5 0x00000200U 344 #define DMA_FLAG_HTIF1_5 0x00000400U 345 #define DMA_FLAG_TCIF1_5 0x00000800U 346 #define DMA_FLAG_FEIF2_6 0x00010000U 347 #define DMA_FLAG_DMEIF2_6 0x00040000U 348 #define DMA_FLAG_TEIF2_6 0x00080000U 349 #define DMA_FLAG_HTIF2_6 0x00100000U 350 #define DMA_FLAG_TCIF2_6 0x00200000U 351 #define DMA_FLAG_FEIF3_7 0x00400000U 352 #define DMA_FLAG_DMEIF3_7 0x01000000U 353 #define DMA_FLAG_TEIF3_7 0x02000000U 354 #define DMA_FLAG_HTIF3_7 0x04000000U 355 #define DMA_FLAG_TCIF3_7 0x08000000U 356 /** 357 * @} 358 */ 359 360 /** 361 * @} 362 */ 363 364 /* Exported macro ------------------------------------------------------------*/ 365 366 /** @brief Reset DMA handle state 367 * @param __HANDLE__ specifies the DMA handle. 368 * @retval None 369 */ 370 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 371 372 /** 373 * @brief Return the current DMA Stream FIFO filled level. 374 * @param __HANDLE__ DMA handle 375 * @retval The FIFO filling state. 376 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full 377 * and not empty. 378 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. 379 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. 380 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. 381 * - DMA_FIFOStatus_Empty: when FIFO is empty 382 * - DMA_FIFOStatus_Full: when FIFO is full 383 */ 384 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS))) 385 386 /** 387 * @brief Enable the specified DMA Stream. 388 * @param __HANDLE__ DMA handle 389 * @retval None 390 */ 391 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN) 392 393 /** 394 * @brief Disable the specified DMA Stream. 395 * @param __HANDLE__ DMA handle 396 * @retval None 397 */ 398 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN) 399 400 /* Interrupt & Flag management */ 401 402 /** 403 * @brief Return the current DMA Stream transfer complete flag. 404 * @param __HANDLE__ DMA handle 405 * @retval The specified transfer complete flag index. 406 */ 407 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 408 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ 409 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ 410 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ 411 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ 412 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ 413 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ 414 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ 415 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ 416 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ 417 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ 418 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ 419 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ 420 DMA_FLAG_TCIF3_7) 421 422 /** 423 * @brief Return the current DMA Stream half transfer complete flag. 424 * @param __HANDLE__ DMA handle 425 * @retval The specified half transfer complete flag index. 426 */ 427 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 428 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ 429 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ 430 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ 431 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ 432 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ 433 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ 434 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ 435 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ 436 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ 437 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ 438 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ 439 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ 440 DMA_FLAG_HTIF3_7) 441 442 /** 443 * @brief Return the current DMA Stream transfer error flag. 444 * @param __HANDLE__ DMA handle 445 * @retval The specified transfer error flag index. 446 */ 447 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 448 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ 449 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ 450 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ 451 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ 452 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ 453 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ 454 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ 455 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ 456 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ 457 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ 458 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ 459 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ 460 DMA_FLAG_TEIF3_7) 461 462 /** 463 * @brief Return the current DMA Stream FIFO error flag. 464 * @param __HANDLE__ DMA handle 465 * @retval The specified FIFO error flag index. 466 */ 467 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ 468 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ 469 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ 470 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ 471 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ 472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ 473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ 474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ 475 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ 476 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ 477 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ 478 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ 479 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ 480 DMA_FLAG_FEIF3_7) 481 482 /** 483 * @brief Return the current DMA Stream direct mode error flag. 484 * @param __HANDLE__ DMA handle 485 * @retval The specified direct mode error flag index. 486 */ 487 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ 488 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ 489 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ 490 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ 491 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ 492 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ 493 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ 494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ 495 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ 496 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ 497 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ 498 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ 499 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ 500 DMA_FLAG_DMEIF3_7) 501 502 /** 503 * @brief Get the DMA Stream pending flags. 504 * @param __HANDLE__ DMA handle 505 * @param __FLAG__ Get the specified flag. 506 * This parameter can be any combination of the following values: 507 * @arg DMA_FLAG_TCIFx: Transfer complete flag. 508 * @arg DMA_FLAG_HTIFx: Half transfer complete flag. 509 * @arg DMA_FLAG_TEIFx: Transfer error flag. 510 * @arg DMA_FLAG_DMEIFx: Direct mode error flag. 511 * @arg DMA_FLAG_FEIFx: FIFO error flag. 512 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. 513 * @retval The state of FLAG (SET or RESET). 514 */ 515 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ 516 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ 517 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ 518 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) 519 520 /** 521 * @brief Clear the DMA Stream pending flags. 522 * @param __HANDLE__ DMA handle 523 * @param __FLAG__ specifies the flag to clear. 524 * This parameter can be any combination of the following values: 525 * @arg DMA_FLAG_TCIFx: Transfer complete flag. 526 * @arg DMA_FLAG_HTIFx: Half transfer complete flag. 527 * @arg DMA_FLAG_TEIFx: Transfer error flag. 528 * @arg DMA_FLAG_DMEIFx: Direct mode error flag. 529 * @arg DMA_FLAG_FEIFx: FIFO error flag. 530 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. 531 * @retval None 532 */ 533 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 534 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ 535 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ 536 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) 537 538 /** 539 * @brief Enable the specified DMA Stream interrupts. 540 * @param __HANDLE__ DMA handle 541 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 542 * This parameter can be one of the following values: 543 * @arg DMA_IT_TC: Transfer complete interrupt mask. 544 * @arg DMA_IT_HT: Half transfer complete interrupt mask. 545 * @arg DMA_IT_TE: Transfer error interrupt mask. 546 * @arg DMA_IT_FE: FIFO error interrupt mask. 547 * @arg DMA_IT_DME: Direct mode error interrupt. 548 * @retval None 549 */ 550 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ 551 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__))) 552 553 /** 554 * @brief Disable the specified DMA Stream interrupts. 555 * @param __HANDLE__ DMA handle 556 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 557 * This parameter can be one of the following values: 558 * @arg DMA_IT_TC: Transfer complete interrupt mask. 559 * @arg DMA_IT_HT: Half transfer complete interrupt mask. 560 * @arg DMA_IT_TE: Transfer error interrupt mask. 561 * @arg DMA_IT_FE: FIFO error interrupt mask. 562 * @arg DMA_IT_DME: Direct mode error interrupt. 563 * @retval None 564 */ 565 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ 566 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__))) 567 568 /** 569 * @brief Check whether the specified DMA Stream interrupt is enabled or not. 570 * @param __HANDLE__ DMA handle 571 * @param __INTERRUPT__ specifies the DMA interrupt source to check. 572 * This parameter can be one of the following values: 573 * @arg DMA_IT_TC: Transfer complete interrupt mask. 574 * @arg DMA_IT_HT: Half transfer complete interrupt mask. 575 * @arg DMA_IT_TE: Transfer error interrupt mask. 576 * @arg DMA_IT_FE: FIFO error interrupt mask. 577 * @arg DMA_IT_DME: Direct mode error interrupt. 578 * @retval The state of DMA_IT. 579 */ 580 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ 581 ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \ 582 ((__HANDLE__)->Instance->FCR & (__INTERRUPT__))) 583 584 /** 585 * @brief Writes the number of data units to be transferred on the DMA Stream. 586 * @param __HANDLE__ DMA handle 587 * @param __COUNTER__ Number of data units to be transferred (from 0 to 65535) 588 * Number of data items depends only on the Peripheral data format. 589 * 590 * @note If Peripheral data format is Bytes: number of data units is equal 591 * to total number of bytes to be transferred. 592 * 593 * @note If Peripheral data format is Half-Word: number of data units is 594 * equal to total number of bytes to be transferred / 2. 595 * 596 * @note If Peripheral data format is Word: number of data units is equal 597 * to total number of bytes to be transferred / 4. 598 * 599 * @retval The number of remaining data units in the current DMAy Streamx transfer. 600 */ 601 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__)) 602 603 /** 604 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. 605 * @param __HANDLE__ DMA handle 606 * 607 * @retval The number of remaining data units in the current DMA Stream transfer. 608 */ 609 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR) 610 611 612 /* Include DMA HAL Extension module */ 613 #include "stm32f7xx_hal_dma_ex.h" 614 615 /* Exported functions --------------------------------------------------------*/ 616 617 /** @defgroup DMA_Exported_Functions DMA Exported Functions 618 * @brief DMA Exported functions 619 * @{ 620 */ 621 622 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions 623 * @brief Initialization and de-initialization functions 624 * @{ 625 */ 626 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 627 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); 628 /** 629 * @} 630 */ 631 632 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions 633 * @brief I/O operation functions 634 * @{ 635 */ 636 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 637 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 638 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 639 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 640 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); 641 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 642 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); 643 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 644 645 /** 646 * @} 647 */ 648 649 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions 650 * @brief Peripheral State functions 651 * @{ 652 */ 653 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 654 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 655 /** 656 * @} 657 */ 658 /** 659 * @} 660 */ 661 /* Private Constants -------------------------------------------------------------*/ 662 /** @defgroup DMA_Private_Constants DMA Private Constants 663 * @brief DMA private defines and constants 664 * @{ 665 */ 666 /** 667 * @} 668 */ 669 670 /* Private macros ------------------------------------------------------------*/ 671 /** @defgroup DMA_Private_Macros DMA Private Macros 672 * @brief DMA private macros 673 * @{ 674 */ 675 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 676 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 677 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 678 679 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) 680 681 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 682 ((STATE) == DMA_PINC_DISABLE)) 683 684 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 685 ((STATE) == DMA_MINC_DISABLE)) 686 687 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 688 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 689 ((SIZE) == DMA_PDATAALIGN_WORD)) 690 691 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 692 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 693 ((SIZE) == DMA_MDATAALIGN_WORD )) 694 695 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 696 ((MODE) == DMA_CIRCULAR) || \ 697 ((MODE) == DMA_PFCTRL)) 698 699 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 700 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 701 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 702 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 703 704 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ 705 ((STATE) == DMA_FIFOMODE_ENABLE)) 706 707 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ 708 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ 709 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ 710 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) 711 712 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ 713 ((BURST) == DMA_MBURST_INC4) || \ 714 ((BURST) == DMA_MBURST_INC8) || \ 715 ((BURST) == DMA_MBURST_INC16)) 716 717 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ 718 ((BURST) == DMA_PBURST_INC4) || \ 719 ((BURST) == DMA_PBURST_INC8) || \ 720 ((BURST) == DMA_PBURST_INC16)) 721 /** 722 * @} 723 */ 724 725 /* Private functions ---------------------------------------------------------*/ 726 /** @defgroup DMA_Private_Functions DMA Private Functions 727 * @brief DMA private functions 728 * @{ 729 */ 730 /** 731 * @} 732 */ 733 734 /** 735 * @} 736 */ 737 738 /** 739 * @} 740 */ 741 742 #ifdef __cplusplus 743 } 744 #endif 745 746 #endif /* __STM32F7xx_HAL_DMA_H */ 747 748
