1 /** 2 ****************************************************************************** 3 * @file stm32f7xx_hal_dfsdm.h 4 * @author MCD Application Team 5 * @brief Header file of DFSDM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32F7xx_HAL_DFSDM_H 21 #define __STM32F7xx_HAL_DFSDM_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32f7xx_hal_def.h" 30 31 /** @addtogroup STM32F7xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup DFSDM 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup DFSDM_Exported_Types DFSDM Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief HAL DFSDM Channel states definition 46 */ 47 typedef enum 48 { 49 HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */ 50 HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */ 51 HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */ 52 }HAL_DFSDM_Channel_StateTypeDef; 53 54 /** 55 * @brief DFSDM channel output clock structure definition 56 */ 57 typedef struct 58 { 59 FunctionalState Activation; /*!< Output clock enable/disable */ 60 uint32_t Selection; /*!< Output clock is system clock or audio clock. 61 This parameter can be a value of @ref DFSDM_Channel_OuputClock */ 62 uint32_t Divider; /*!< Output clock divider. 63 This parameter must be a number between Min_Data = 2 and Max_Data = 256 */ 64 }DFSDM_Channel_OutputClockTypeDef; 65 66 /** 67 * @brief DFSDM channel input structure definition 68 */ 69 typedef struct 70 { 71 uint32_t Multiplexer; /*!< Input is external serial inputs or internal register. 72 This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */ 73 uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register. 74 This parameter can be a value of @ref DFSDM_Channel_DataPacking */ 75 uint32_t Pins; /*!< Input pins are taken from same or following channel. 76 This parameter can be a value of @ref DFSDM_Channel_InputPins */ 77 }DFSDM_Channel_InputTypeDef; 78 79 /** 80 * @brief DFSDM channel serial interface structure definition 81 */ 82 typedef struct 83 { 84 uint32_t Type; /*!< SPI or Manchester modes. 85 This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */ 86 uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point). 87 This parameter can be a value of @ref DFSDM_Channel_SpiClock */ 88 }DFSDM_Channel_SerialInterfaceTypeDef; 89 90 /** 91 * @brief DFSDM channel analog watchdog structure definition 92 */ 93 typedef struct 94 { 95 uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order. 96 This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */ 97 uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio. 98 This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ 99 }DFSDM_Channel_AwdTypeDef; 100 101 /** 102 * @brief DFSDM channel init structure definition 103 */ 104 typedef struct 105 { 106 DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */ 107 DFSDM_Channel_InputTypeDef Input; /*!< DFSDM channel input parameters */ 108 DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */ 109 DFSDM_Channel_AwdTypeDef Awd; /*!< DFSDM channel analog watchdog parameters */ 110 int32_t Offset; /*!< DFSDM channel offset. 111 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 112 uint32_t RightBitShift; /*!< DFSDM channel right bit shift. 113 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ 114 }DFSDM_Channel_InitTypeDef; 115 116 /** 117 * @brief DFSDM channel handle structure definition 118 */ 119 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 120 typedef struct __DFSDM_Channel_HandleTypeDef 121 #else 122 typedef struct 123 #endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */ 124 { 125 DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */ 126 DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */ 127 HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */ 128 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 129 void (*CkabCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel clock absence detection callback */ 130 void (*ScdCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel short circuit detection callback */ 131 void (*MspInitCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP init callback */ 132 void (*MspDeInitCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP de-init callback */ 133 #endif 134 }DFSDM_Channel_HandleTypeDef; 135 136 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 137 /** 138 * @brief DFSDM channel callback ID enumeration definition 139 */ 140 typedef enum 141 { 142 HAL_DFSDM_CHANNEL_CKAB_CB_ID = 0x00U, /*!< DFSDM channel clock absence detection callback ID */ 143 HAL_DFSDM_CHANNEL_SCD_CB_ID = 0x01U, /*!< DFSDM channel short circuit detection callback ID */ 144 HAL_DFSDM_CHANNEL_MSPINIT_CB_ID = 0x02U, /*!< DFSDM channel MSP init callback ID */ 145 HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID = 0x03U /*!< DFSDM channel MSP de-init callback ID */ 146 }HAL_DFSDM_Channel_CallbackIDTypeDef; 147 148 /** 149 * @brief DFSDM channel callback pointer definition 150 */ 151 typedef void (*pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 152 #endif 153 /** 154 * @brief HAL DFSDM Filter states definition 155 */ 156 typedef enum 157 { 158 HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */ 159 HAL_DFSDM_FILTER_STATE_READY = 0x01U, /*!< DFSDM filter initialized and ready for use */ 160 HAL_DFSDM_FILTER_STATE_REG = 0x02U, /*!< DFSDM filter regular conversion in progress */ 161 HAL_DFSDM_FILTER_STATE_INJ = 0x03U, /*!< DFSDM filter injected conversion in progress */ 162 HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */ 163 HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */ 164 }HAL_DFSDM_Filter_StateTypeDef; 165 166 /** 167 * @brief DFSDM filter regular conversion parameters structure definition 168 */ 169 typedef struct 170 { 171 uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous. 172 This parameter can be a value of @ref DFSDM_Filter_Trigger */ 173 FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */ 174 FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */ 175 }DFSDM_Filter_RegularParamTypeDef; 176 177 /** 178 * @brief DFSDM filter injected conversion parameters structure definition 179 */ 180 typedef struct 181 { 182 uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous. 183 This parameter can be a value of @ref DFSDM_Filter_Trigger */ 184 FunctionalState ScanMode; /*!< Enable/disable scanning mode for injected conversion */ 185 FunctionalState DmaMode; /*!< Enable/disable DMA for injected conversion */ 186 uint32_t ExtTrigger; /*!< External trigger. 187 This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */ 188 uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both. 189 This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */ 190 }DFSDM_Filter_InjectedParamTypeDef; 191 192 /** 193 * @brief DFSDM filter parameters structure definition 194 */ 195 typedef struct 196 { 197 uint32_t SincOrder; /*!< Sinc filter order. 198 This parameter can be a value of @ref DFSDM_Filter_SincOrder */ 199 uint32_t Oversampling; /*!< Filter oversampling ratio. 200 This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ 201 uint32_t IntOversampling; /*!< Integrator oversampling ratio. 202 This parameter must be a number between Min_Data = 1 and Max_Data = 256 */ 203 }DFSDM_Filter_FilterParamTypeDef; 204 205 /** 206 * @brief DFSDM filter init structure definition 207 */ 208 typedef struct 209 { 210 DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */ 211 DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */ 212 DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */ 213 }DFSDM_Filter_InitTypeDef; 214 215 /** 216 * @brief DFSDM filter handle structure definition 217 */ 218 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 219 typedef struct __DFSDM_Filter_HandleTypeDef 220 #else 221 typedef struct 222 #endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */ 223 { 224 DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */ 225 DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */ 226 DMA_HandleTypeDef *hdmaReg; /*!< Pointer on DMA handler for regular conversions */ 227 DMA_HandleTypeDef *hdmaInj; /*!< Pointer on DMA handler for injected conversions */ 228 uint32_t RegularContMode; /*!< Regular conversion continuous mode */ 229 uint32_t RegularTrigger; /*!< Trigger used for regular conversion */ 230 uint32_t InjectedTrigger; /*!< Trigger used for injected conversion */ 231 uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */ 232 FunctionalState InjectedScanMode; /*!< Injected scanning mode */ 233 uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */ 234 uint32_t InjConvRemaining; /*!< Injected conversions remaining */ 235 HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */ 236 uint32_t ErrorCode; /*!< DFSDM filter error code */ 237 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 238 void (*AwdCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 239 uint32_t Channel, uint32_t Threshold); /*!< DFSDM filter analog watchdog callback */ 240 void (*RegConvCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter regular conversion complete callback */ 241 void (*RegConvHalfCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half regular conversion complete callback */ 242 void (*InjConvCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter injected conversion complete callback */ 243 void (*InjConvHalfCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half injected conversion complete callback */ 244 void (*ErrorCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter error callback */ 245 void (*MspInitCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP init callback */ 246 void (*MspDeInitCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP de-init callback */ 247 #endif 248 }DFSDM_Filter_HandleTypeDef; 249 250 /** 251 * @brief DFSDM filter analog watchdog parameters structure definition 252 */ 253 typedef struct 254 { 255 uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter. 256 This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */ 257 uint32_t Channel; /*!< Analog watchdog channel selection. 258 This parameter can be a values combination of @ref DFSDM_Channel_Selection */ 259 int32_t HighThreshold; /*!< High threshold for the analog watchdog. 260 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 261 int32_t LowThreshold; /*!< Low threshold for the analog watchdog. 262 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 263 uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event. 264 This parameter can be a values combination of @ref DFSDM_BreakSignals */ 265 uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event. 266 This parameter can be a values combination of @ref DFSDM_BreakSignals */ 267 }DFSDM_Filter_AwdParamTypeDef; 268 269 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 270 /** 271 * @brief DFSDM filter callback ID enumeration definition 272 */ 273 typedef enum 274 { 275 HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID = 0x00U, /*!< DFSDM filter regular conversion complete callback ID */ 276 HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID = 0x01U, /*!< DFSDM filter half regular conversion complete callback ID */ 277 HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID = 0x02U, /*!< DFSDM filter injected conversion complete callback ID */ 278 HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID = 0x03U, /*!< DFSDM filter half injected conversion complete callback ID */ 279 HAL_DFSDM_FILTER_ERROR_CB_ID = 0x04U, /*!< DFSDM filter error callback ID */ 280 HAL_DFSDM_FILTER_MSPINIT_CB_ID = 0x05U, /*!< DFSDM filter MSP init callback ID */ 281 HAL_DFSDM_FILTER_MSPDEINIT_CB_ID = 0x06U /*!< DFSDM filter MSP de-init callback ID */ 282 }HAL_DFSDM_Filter_CallbackIDTypeDef; 283 284 /** 285 * @brief DFSDM filter callback pointer definition 286 */ 287 typedef void (*pDFSDM_Filter_CallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 288 typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); 289 #endif 290 /** 291 * @} 292 */ 293 /* End of exported types -----------------------------------------------------*/ 294 295 /* Exported constants --------------------------------------------------------*/ 296 /** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants 297 * @{ 298 */ 299 300 /** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection 301 * @{ 302 */ 303 #define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000U) /*!< Source for output clock is system clock */ 304 #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for output clock is audio clock */ 305 /** 306 * @} 307 */ 308 309 /** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer 310 * @{ 311 */ 312 #define DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000U) /*!< Data are taken from external inputs */ 313 #define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */ 314 /** 315 * @} 316 */ 317 318 /** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing 319 * @{ 320 */ 321 #define DFSDM_CHANNEL_STANDARD_MODE ((uint32_t)0x00000000U) /*!< Standard data packing mode */ 322 #define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */ 323 #define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */ 324 /** 325 * @} 326 */ 327 328 /** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins 329 * @{ 330 */ 331 #define DFSDM_CHANNEL_SAME_CHANNEL_PINS ((uint32_t)0x00000000U) /*!< Input from pins on same channel */ 332 #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */ 333 /** 334 * @} 335 */ 336 337 /** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type 338 * @{ 339 */ 340 #define DFSDM_CHANNEL_SPI_RISING ((uint32_t)0x00000000U) /*!< SPI with rising edge */ 341 #define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */ 342 #define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */ 343 #define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */ 344 /** 345 * @} 346 */ 347 348 /** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection 349 * @{ 350 */ 351 #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL ((uint32_t)0x00000000U) /*!< External SPI clock */ 352 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */ 353 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */ 354 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */ 355 /** 356 * @} 357 */ 358 359 /** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order 360 * @{ 361 */ 362 #define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */ 363 #define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */ 364 #define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */ 365 #define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */ 366 /** 367 * @} 368 */ 369 370 /** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger 371 * @{ 372 */ 373 #define DFSDM_FILTER_SW_TRIGGER ((uint32_t)0x00000000U) /*!< Software trigger */ 374 #define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001U) /*!< Synchronous with DFSDM_FLT0 */ 375 #define DFSDM_FILTER_EXT_TRIGGER ((uint32_t)0x00000002U) /*!< External trigger (only for injected conversion) */ 376 /** 377 * @} 378 */ 379 380 /** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger 381 * @{ 382 */ 383 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For DFSDM filter 0, 1, 2 and 3 */ 384 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */ 385 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */ 386 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1, 2 and 3 */ 387 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM filter 0, 1, 2 and 3 */ 388 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */ 389 #define DFSDM_FILTER_EXT_TRIG_TIM10_OC1 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */ 390 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1 | \ 391 DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */ 392 #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3 /*!< For DFSDM filter 0, 1, 2 and 3 */ 393 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4) /*!< For DFSDM filter 0, 1, 2 and 3 */ 394 #define DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_3 | \ 395 DFSDM_FLTCR1_JEXTSEL_4) /*!< For DFSDM filter 0, 1, 2 and 3 */ 396 #define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | \ 397 DFSDM_FLTCR1_JEXTSEL_4) /*!< For DFSDM filter 0, 1, 2 and 3 */ 398 /** 399 * @} 400 */ 401 402 /** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge 403 * @{ 404 */ 405 #define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */ 406 #define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */ 407 #define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN /*!< External rising and falling edges */ 408 /** 409 * @} 410 */ 411 412 /** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order 413 * @{ 414 */ 415 #define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */ 416 #define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */ 417 #define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */ 418 #define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */ 419 #define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /*!< Sinc 4 filter type */ 420 #define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */ 421 /** 422 * @} 423 */ 424 425 /** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source 426 * @{ 427 */ 428 #define DFSDM_FILTER_AWD_FILTER_DATA ((uint32_t)0x00000000U) /*!< From digital filter */ 429 #define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */ 430 /** 431 * @} 432 */ 433 434 /** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code 435 * @{ 436 */ 437 #define DFSDM_FILTER_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 438 #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001U) /*!< Overrun occurs during regular conversion */ 439 #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002U) /*!< Overrun occurs during injected conversion */ 440 #define DFSDM_FILTER_ERROR_DMA ((uint32_t)0x00000003U) /*!< DMA error occurs */ 441 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 442 #define DFSDM_FILTER_ERROR_INVALID_CALLBACK ((uint32_t)0x00000004U) /*!< Invalid callback error occurs */ 443 #endif 444 /** 445 * @} 446 */ 447 448 /** @defgroup DFSDM_BreakSignals DFSDM break signals 449 * @{ 450 */ 451 #define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000U) /*!< No break signal */ 452 #define DFSDM_BREAK_SIGNAL_0 ((uint32_t)0x00000001U) /*!< Break signal 0 */ 453 #define DFSDM_BREAK_SIGNAL_1 ((uint32_t)0x00000002U) /*!< Break signal 1 */ 454 #define DFSDM_BREAK_SIGNAL_2 ((uint32_t)0x00000004U) /*!< Break signal 2 */ 455 #define DFSDM_BREAK_SIGNAL_3 ((uint32_t)0x00000008U) /*!< Break signal 3 */ 456 /** 457 * @} 458 */ 459 460 /** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection 461 * @{ 462 */ 463 /* DFSDM Channels ------------------------------------------------------------*/ 464 /* The DFSDM channels are defined as follows: 465 - in 16-bit LSB the channel mask is set 466 - in 16-bit MSB the channel number is set 467 e.g. for channel 5 definition: 468 - the channel mask is 0x00000020 (bit 5 is set) 469 - the channel number 5 is 0x00050000 470 --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */ 471 #define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U) 472 #define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U) 473 #define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U) 474 #define DFSDM_CHANNEL_3 ((uint32_t)0x00030008U) 475 #define DFSDM_CHANNEL_4 ((uint32_t)0x00040010U) 476 #define DFSDM_CHANNEL_5 ((uint32_t)0x00050020U) 477 #define DFSDM_CHANNEL_6 ((uint32_t)0x00060040U) 478 #define DFSDM_CHANNEL_7 ((uint32_t)0x00070080U) 479 /** 480 * @} 481 */ 482 483 /** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode 484 * @{ 485 */ 486 #define DFSDM_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000U) /*!< Conversion are not continuous */ 487 #define DFSDM_CONTINUOUS_CONV_ON ((uint32_t)0x00000001U) /*!< Conversion are continuous */ 488 /** 489 * @} 490 */ 491 492 /** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold 493 * @{ 494 */ 495 #define DFSDM_AWD_HIGH_THRESHOLD ((uint32_t)0x00000000U) /*!< Analog watchdog high threshold */ 496 #define DFSDM_AWD_LOW_THRESHOLD ((uint32_t)0x00000001U) /*!< Analog watchdog low threshold */ 497 /** 498 * @} 499 */ 500 501 /** 502 * @} 503 */ 504 /* End of exported constants -------------------------------------------------*/ 505 506 /* Exported macros -----------------------------------------------------------*/ 507 /** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros 508 * @{ 509 */ 510 511 /** @brief Reset DFSDM channel handle state. 512 * @param __HANDLE__: DFSDM channel handle. 513 * @retval None 514 */ 515 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 516 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) do{ \ 517 (__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET; \ 518 (__HANDLE__)->MspInitCallback = NULL; \ 519 (__HANDLE__)->MspDeInitCallback = NULL; \ 520 } while(0) 521 #else 522 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET) 523 #endif 524 525 /** @brief Reset DFSDM filter handle state. 526 * @param __HANDLE__: DFSDM filter handle. 527 * @retval None 528 */ 529 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 530 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) do{ \ 531 (__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET; \ 532 (__HANDLE__)->MspInitCallback = NULL; \ 533 (__HANDLE__)->MspDeInitCallback = NULL; \ 534 } while(0) 535 #else 536 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET) 537 #endif 538 539 /** 540 * @} 541 */ 542 /* End of exported macros ----------------------------------------------------*/ 543 544 /* Exported functions --------------------------------------------------------*/ 545 /** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions 546 * @{ 547 */ 548 549 /** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions 550 * @{ 551 */ 552 /* Channel initialization and de-initialization functions *********************/ 553 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 554 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 555 void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 556 void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 557 558 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 559 /* Channel callbacks register/unregister functions ****************************/ 560 HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, 561 HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID, 562 pDFSDM_Channel_CallbackTypeDef pCallback); 563 HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, 564 HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID); 565 #endif 566 /** 567 * @} 568 */ 569 570 /** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions 571 * @{ 572 */ 573 /* Channel operation functions ************************************************/ 574 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 575 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 576 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 577 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 578 579 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); 580 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); 581 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 582 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 583 584 int16_t HAL_DFSDM_ChannelGetAwdValue(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 585 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset); 586 587 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); 588 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); 589 590 void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 591 void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 592 /** 593 * @} 594 */ 595 596 /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function 597 * @{ 598 */ 599 /* Channel state function *****************************************************/ 600 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 601 /** 602 * @} 603 */ 604 605 /** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions 606 * @{ 607 */ 608 /* Filter initialization and de-initialization functions *********************/ 609 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 610 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 611 void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 612 void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 613 614 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 615 /* Filter callbacks register/unregister functions ****************************/ 616 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 617 HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID, 618 pDFSDM_Filter_CallbackTypeDef pCallback); 619 HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 620 HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID); 621 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 622 pDFSDM_Filter_AwdCallbackTypeDef pCallback); 623 HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 624 #endif 625 /** 626 * @} 627 */ 628 629 /** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions 630 * @{ 631 */ 632 /* Filter control functions *********************/ 633 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 634 uint32_t Channel, 635 uint32_t ContinuousMode); 636 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 637 uint32_t Channel); 638 /** 639 * @} 640 */ 641 642 /** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions 643 * @{ 644 */ 645 /* Filter operation functions *********************/ 646 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 647 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 648 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); 649 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); 650 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 651 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 652 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 653 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 654 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 655 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); 656 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); 657 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 658 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 659 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 660 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 661 const DFSDM_Filter_AwdParamTypeDef* awdParam); 662 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 663 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel); 664 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 665 666 int32_t HAL_DFSDM_FilterGetRegularValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); 667 int32_t HAL_DFSDM_FilterGetInjectedValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); 668 int32_t HAL_DFSDM_FilterGetExdMaxValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); 669 int32_t HAL_DFSDM_FilterGetExdMinValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); 670 uint32_t HAL_DFSDM_FilterGetConvTimeValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 671 672 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 673 674 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); 675 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); 676 677 void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 678 void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 679 void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 680 void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 681 void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); 682 void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 683 /** 684 * @} 685 */ 686 687 /** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions 688 * @{ 689 */ 690 /* Filter state functions *****************************************************/ 691 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 692 uint32_t HAL_DFSDM_FilterGetError(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 693 /** 694 * @} 695 */ 696 697 /** 698 * @} 699 */ 700 /* End of exported functions -------------------------------------------------*/ 701 702 /* Private macros ------------------------------------------------------------*/ 703 /** @defgroup DFSDM_Private_Macros DFSDM Private Macros 704 * @{ 705 */ 706 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \ 707 ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO)) 708 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256)) 709 #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ 710 ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) 711 #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \ 712 ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \ 713 ((MODE) == DFSDM_CHANNEL_DUAL_MODE)) 714 #define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \ 715 ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS)) 716 #define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \ 717 ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \ 718 ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \ 719 ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING)) 720 #define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \ 721 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \ 722 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \ 723 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING)) 724 #define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \ 725 ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \ 726 ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \ 727 ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER)) 728 #define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 32)) 729 #define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) 730 #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1F) 731 #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFF) 732 #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ 733 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER)) 734 #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ 735 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \ 736 ((TRIG) == DFSDM_FILTER_EXT_TRIGGER)) 737 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ 738 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2)|| \ 739 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \ 740 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2)|| \ 741 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ 742 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \ 743 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \ 744 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ 745 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \ 746 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ 747 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) ||\ 748 ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT)) 749 #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \ 750 ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \ 751 ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES)) 752 #define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \ 753 ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \ 754 ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \ 755 ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \ 756 ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \ 757 ((ORDER) == DFSDM_FILTER_SINC5_ORDER)) 758 #define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 1024)) 759 #define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 256)) 760 #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \ 761 ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA)) 762 #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) 763 #define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xFU) 764 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ 765 ((CHANNEL) == DFSDM_CHANNEL_1) || \ 766 ((CHANNEL) == DFSDM_CHANNEL_2) || \ 767 ((CHANNEL) == DFSDM_CHANNEL_3) || \ 768 ((CHANNEL) == DFSDM_CHANNEL_4) || \ 769 ((CHANNEL) == DFSDM_CHANNEL_5) || \ 770 ((CHANNEL) == DFSDM_CHANNEL_6) || \ 771 ((CHANNEL) == DFSDM_CHANNEL_7)) 772 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FFU)) 773 #define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \ 774 ((MODE) == DFSDM_CONTINUOUS_CONV_ON)) 775 /** 776 * @} 777 */ 778 /* End of private macros -----------------------------------------------------*/ 779 780 /** 781 * @} 782 */ 783 784 /** 785 * @} 786 */ 787 #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 788 #ifdef __cplusplus 789 } 790 #endif 791 792 #endif /* __STM32F7xx_HAL_DFSDM_H */ 793
