1 /** 2 ****************************************************************************** 3 * @file stm32f7xx_hal_eth_legacy.h 4 * @author MCD Application Team 5 * @brief Header file of ETH HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32F7xx_HAL_ETH_LEGACY_H 21 #define __STM32F7xx_HAL_ETH_LEGACY_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f7xx_hal_def.h" 29 30 #if defined (ETH) 31 32 /** @addtogroup STM32F7xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup ETH 37 * @{ 38 */ 39 40 /** @addtogroup ETH_Private_Macros 41 * @{ 42 */ 43 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20) 44 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \ 45 ((CMD) == ETH_AUTONEGOTIATION_DISABLE)) 46 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \ 47 ((SPEED) == ETH_SPEED_100M)) 48 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \ 49 ((MODE) == ETH_MODE_HALFDUPLEX)) 50 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \ 51 ((MODE) == ETH_RXINTERRUPT_MODE)) 52 #define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \ 53 ((MODE) == ETH_CHECKSUM_BY_SOFTWARE)) 54 #define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \ 55 ((MODE) == ETH_MEDIA_INTERFACE_RMII)) 56 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \ 57 ((CMD) == ETH_WATCHDOG_DISABLE)) 58 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \ 59 ((CMD) == ETH_JABBER_DISABLE)) 60 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \ 61 ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \ 62 ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \ 63 ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \ 64 ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \ 65 ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \ 66 ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \ 67 ((GAP) == ETH_INTERFRAMEGAP_40BIT)) 68 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \ 69 ((CMD) == ETH_CARRIERSENCE_DISABLE)) 70 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \ 71 ((CMD) == ETH_RECEIVEOWN_DISABLE)) 72 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \ 73 ((CMD) == ETH_LOOPBACKMODE_DISABLE)) 74 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \ 75 ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE)) 76 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \ 77 ((CMD) == ETH_RETRYTRANSMISSION_DISABLE)) 78 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \ 79 ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE)) 80 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \ 81 ((LIMIT) == ETH_BACKOFFLIMIT_8) || \ 82 ((LIMIT) == ETH_BACKOFFLIMIT_4) || \ 83 ((LIMIT) == ETH_BACKOFFLIMIT_1)) 84 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \ 85 ((CMD) == ETH_DEFFERRALCHECK_DISABLE)) 86 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \ 87 ((CMD) == ETH_RECEIVEAll_DISABLE)) 88 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \ 89 ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \ 90 ((CMD) == ETH_SOURCEADDRFILTER_DISABLE)) 91 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \ 92 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \ 93 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER)) 94 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \ 95 ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE)) 96 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \ 97 ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE)) 98 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \ 99 ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE)) 100 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \ 101 ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \ 102 ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \ 103 ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE)) 104 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \ 105 ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \ 106 ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT)) 107 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF) 108 #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \ 109 ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE)) 110 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \ 111 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \ 112 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \ 113 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256)) 114 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \ 115 ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE)) 116 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \ 117 ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE)) 118 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \ 119 ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE)) 120 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \ 121 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT)) 122 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF) 123 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \ 124 ((ADDRESS) == ETH_MAC_ADDRESS1) || \ 125 ((ADDRESS) == ETH_MAC_ADDRESS2) || \ 126 ((ADDRESS) == ETH_MAC_ADDRESS3)) 127 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \ 128 ((ADDRESS) == ETH_MAC_ADDRESS2) || \ 129 ((ADDRESS) == ETH_MAC_ADDRESS3)) 130 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \ 131 ((FILTER) == ETH_MAC_ADDRESSFILTER_DA)) 132 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \ 133 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \ 134 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \ 135 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \ 136 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \ 137 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1)) 138 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \ 139 ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE)) 140 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \ 141 ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE)) 142 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \ 143 ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE)) 144 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \ 145 ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE)) 146 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \ 147 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \ 148 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \ 149 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \ 150 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \ 151 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \ 152 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \ 153 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES)) 154 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \ 155 ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE)) 156 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \ 157 ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE)) 158 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \ 159 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \ 160 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \ 161 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES)) 162 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \ 163 ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE)) 164 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \ 165 ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE)) 166 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \ 167 ((CMD) == ETH_FIXEDBURST_DISABLE)) 168 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \ 169 ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \ 170 ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \ 171 ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \ 172 ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \ 173 ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \ 174 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \ 175 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \ 176 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \ 177 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \ 178 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \ 179 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT)) 180 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \ 181 ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \ 182 ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \ 183 ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \ 184 ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \ 185 ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \ 186 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \ 187 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \ 188 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \ 189 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \ 190 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \ 191 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT)) 192 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F) 193 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \ 194 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \ 195 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \ 196 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \ 197 ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX)) 198 #define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \ 199 ((FLAG) == ETH_DMATXDESC_IC) || \ 200 ((FLAG) == ETH_DMATXDESC_LS) || \ 201 ((FLAG) == ETH_DMATXDESC_FS) || \ 202 ((FLAG) == ETH_DMATXDESC_DC) || \ 203 ((FLAG) == ETH_DMATXDESC_DP) || \ 204 ((FLAG) == ETH_DMATXDESC_TTSE) || \ 205 ((FLAG) == ETH_DMATXDESC_TER) || \ 206 ((FLAG) == ETH_DMATXDESC_TCH) || \ 207 ((FLAG) == ETH_DMATXDESC_TTSS) || \ 208 ((FLAG) == ETH_DMATXDESC_IHE) || \ 209 ((FLAG) == ETH_DMATXDESC_ES) || \ 210 ((FLAG) == ETH_DMATXDESC_JT) || \ 211 ((FLAG) == ETH_DMATXDESC_FF) || \ 212 ((FLAG) == ETH_DMATXDESC_PCE) || \ 213 ((FLAG) == ETH_DMATXDESC_LCA) || \ 214 ((FLAG) == ETH_DMATXDESC_NC) || \ 215 ((FLAG) == ETH_DMATXDESC_LCO) || \ 216 ((FLAG) == ETH_DMATXDESC_EC) || \ 217 ((FLAG) == ETH_DMATXDESC_VF) || \ 218 ((FLAG) == ETH_DMATXDESC_CC) || \ 219 ((FLAG) == ETH_DMATXDESC_ED) || \ 220 ((FLAG) == ETH_DMATXDESC_UF) || \ 221 ((FLAG) == ETH_DMATXDESC_DB)) 222 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \ 223 ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT)) 224 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \ 225 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \ 226 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \ 227 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL)) 228 #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF) 229 #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \ 230 ((FLAG) == ETH_DMARXDESC_AFM) || \ 231 ((FLAG) == ETH_DMARXDESC_ES) || \ 232 ((FLAG) == ETH_DMARXDESC_DE) || \ 233 ((FLAG) == ETH_DMARXDESC_SAF) || \ 234 ((FLAG) == ETH_DMARXDESC_LE) || \ 235 ((FLAG) == ETH_DMARXDESC_OE) || \ 236 ((FLAG) == ETH_DMARXDESC_VLAN) || \ 237 ((FLAG) == ETH_DMARXDESC_FS) || \ 238 ((FLAG) == ETH_DMARXDESC_LS) || \ 239 ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \ 240 ((FLAG) == ETH_DMARXDESC_LC) || \ 241 ((FLAG) == ETH_DMARXDESC_FT) || \ 242 ((FLAG) == ETH_DMARXDESC_RWT) || \ 243 ((FLAG) == ETH_DMARXDESC_RE) || \ 244 ((FLAG) == ETH_DMARXDESC_DBE) || \ 245 ((FLAG) == ETH_DMARXDESC_CE) || \ 246 ((FLAG) == ETH_DMARXDESC_MAMPCE)) 247 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \ 248 ((BUFFER) == ETH_DMARXDESC_BUFFER2)) 249 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ 250 ((FLAG) == ETH_PMT_FLAG_MPR)) 251 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00)) 252 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ 253 ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \ 254 ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \ 255 ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ 256 ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ 257 ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ 258 ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ 259 ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ 260 ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ 261 ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ 262 ((FLAG) == ETH_DMA_FLAG_T)) 263 #define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00)) 264 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ 265 ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ 266 ((IT) == ETH_MAC_IT_PMT)) 267 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ 268 ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ 269 ((FLAG) == ETH_MAC_FLAG_PMT)) 270 #define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00)) 271 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ 272 ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ 273 ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ 274 ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ 275 ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ 276 ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ 277 ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ 278 ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ 279 ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) 280 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \ 281 ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER)) 282 #define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \ 283 ((IT) != 0x00)) 284 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ 285 ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ 286 ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) 287 #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \ 288 ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE)) 289 290 291 /** 292 * @} 293 */ 294 295 /** @addtogroup ETH_Private_Defines 296 * @{ 297 */ 298 /* Delay to wait when writing to some Ethernet registers */ 299 #define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001U) 300 301 /* Ethernet Errors */ 302 #define ETH_SUCCESS ((uint32_t)0U) 303 #define ETH_ERROR ((uint32_t)1U) 304 305 /* Ethernet DMA Tx descriptors Collision Count Shift */ 306 #define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3U) 307 308 /* Ethernet DMA Tx descriptors Buffer2 Size Shift */ 309 #define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16U) 310 311 /* Ethernet DMA Rx descriptors Frame Length Shift */ 312 #define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16U) 313 314 /* Ethernet DMA Rx descriptors Buffer2 Size Shift */ 315 #define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16U) 316 317 /* Ethernet DMA Rx descriptors Frame length Shift */ 318 #define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16) 319 320 /* Ethernet MAC address offsets */ 321 #define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40U) /* Ethernet MAC address high offset */ 322 #define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44U) /* Ethernet MAC address low offset */ 323 324 /* Ethernet MACMIIAR register Mask */ 325 #define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3U) 326 327 /* Ethernet MACCR register Mask */ 328 #define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810FU) 329 330 /* Ethernet MACFCR register Mask */ 331 #define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41U) 332 333 /* Ethernet DMAOMR register Mask */ 334 #define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23U) 335 336 /* Ethernet Remote Wake-up frame register length */ 337 #define ETH_WAKEUP_REGISTER_LENGTH 8U 338 339 /* Ethernet Missed frames counter Shift */ 340 #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U 341 /** 342 * @} 343 */ 344 345 /* Exported types ------------------------------------------------------------*/ 346 /** @defgroup ETH_Exported_Types ETH Exported Types 347 * @{ 348 */ 349 350 /** 351 * @brief HAL State structures definition 352 */ 353 typedef enum 354 { 355 HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */ 356 HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 357 HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ 358 HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ 359 HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ 360 HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */ 361 HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */ 362 HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */ 363 HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 364 HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ 365 }HAL_ETH_StateTypeDef; 366 367 /** 368 * @brief ETH Init Structure definition 369 */ 370 371 typedef struct 372 { 373 uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY 374 The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) 375 and the mode (half/full-duplex). 376 This parameter can be a value of @ref ETH_AutoNegotiation */ 377 378 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps. 379 This parameter can be a value of @ref ETH_Speed */ 380 381 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode 382 This parameter can be a value of @ref ETH_Duplex_Mode */ 383 384 uint16_t PhyAddress; /*!< Ethernet PHY address. 385 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ 386 387 uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */ 388 389 uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode. 390 This parameter can be a value of @ref ETH_Rx_Mode */ 391 392 uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software. 393 This parameter can be a value of @ref ETH_Checksum_Mode */ 394 395 uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface. 396 This parameter can be a value of @ref ETH_Media_Interface */ 397 398 } ETH_InitTypeDef; 399 400 401 /** 402 * @brief ETH MAC Configuration Structure definition 403 */ 404 405 typedef struct 406 { 407 uint32_t Watchdog; /*!< Selects or not the Watchdog timer 408 When enabled, the MAC allows no more then 2048 bytes to be received. 409 When disabled, the MAC can receive up to 16384 bytes. 410 This parameter can be a value of @ref ETH_Watchdog */ 411 412 uint32_t Jabber; /*!< Selects or not Jabber timer 413 When enabled, the MAC allows no more then 2048 bytes to be sent. 414 When disabled, the MAC can send up to 16384 bytes. 415 This parameter can be a value of @ref ETH_Jabber */ 416 417 uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission. 418 This parameter can be a value of @ref ETH_Inter_Frame_Gap */ 419 420 uint32_t CarrierSense; /*!< Selects or not the Carrier Sense. 421 This parameter can be a value of @ref ETH_Carrier_Sense */ 422 423 uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn, 424 ReceiveOwn allows the reception of frames when the TX_EN signal is asserted 425 in Half-Duplex mode. 426 This parameter can be a value of @ref ETH_Receive_Own */ 427 428 uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode. 429 This parameter can be a value of @ref ETH_Loop_Back_Mode */ 430 431 uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. 432 This parameter can be a value of @ref ETH_Checksum_Offload */ 433 434 uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL, 435 when a collision occurs (Half-Duplex mode). 436 This parameter can be a value of @ref ETH_Retry_Transmission */ 437 438 uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping. 439 This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ 440 441 uint32_t BackOffLimit; /*!< Selects the BackOff limit value. 442 This parameter can be a value of @ref ETH_Back_Off_Limit */ 443 444 uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode). 445 This parameter can be a value of @ref ETH_Deferral_Check */ 446 447 uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering). 448 This parameter can be a value of @ref ETH_Receive_All */ 449 450 uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode. 451 This parameter can be a value of @ref ETH_Source_Addr_Filter */ 452 453 uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) 454 This parameter can be a value of @ref ETH_Pass_Control_Frames */ 455 456 uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames. 457 This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ 458 459 uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames. 460 This parameter can be a value of @ref ETH_Destination_Addr_Filter */ 461 462 uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode 463 This parameter can be a value of @ref ETH_Promiscuous_Mode */ 464 465 uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter. 466 This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ 467 468 uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter. 469 This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ 470 471 uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. 472 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ 473 474 uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table. 475 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ 476 477 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame. 478 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ 479 480 uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames. 481 This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ 482 483 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for 484 automatic retransmission of PAUSE Frame. 485 This parameter can be a value of @ref ETH_Pause_Low_Threshold */ 486 487 uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0 488 unicast address and unique multicast address). 489 This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ 490 491 uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and 492 disable its transmitter for a specified time (Pause Time) 493 This parameter can be a value of @ref ETH_Receive_Flow_Control */ 494 495 uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) 496 or the MAC back-pressure operation (Half-Duplex mode) 497 This parameter can be a value of @ref ETH_Transmit_Flow_Control */ 498 499 uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for 500 comparison and filtering. 501 This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ 502 503 uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */ 504 505 } ETH_MACInitTypeDef; 506 507 508 /** 509 * @brief ETH DMA Configuration Structure definition 510 */ 511 512 typedef struct 513 { 514 uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames. 515 This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ 516 517 uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode. 518 This parameter can be a value of @ref ETH_Receive_Store_Forward */ 519 520 uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames. 521 This parameter can be a value of @ref ETH_Flush_Received_Frame */ 522 523 uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode. 524 This parameter can be a value of @ref ETH_Transmit_Store_Forward */ 525 526 uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control. 527 This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ 528 529 uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames. 530 This parameter can be a value of @ref ETH_Forward_Error_Frames */ 531 532 uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error 533 and length less than 64 bytes) including pad-bytes and CRC) 534 This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ 535 536 uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO. 537 This parameter can be a value of @ref ETH_Receive_Threshold_Control */ 538 539 uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second 540 frame of Transmit data even before obtaining the status for the first frame. 541 This parameter can be a value of @ref ETH_Second_Frame_Operate */ 542 543 uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats. 544 This parameter can be a value of @ref ETH_Address_Aligned_Beats */ 545 546 uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers. 547 This parameter can be a value of @ref ETH_Fixed_Burst */ 548 549 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction. 550 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ 551 552 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction. 553 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ 554 555 uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format. 556 This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */ 557 558 uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) 559 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ 560 561 uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration. 562 This parameter can be a value of @ref ETH_DMA_Arbitration */ 563 } ETH_DMAInitTypeDef; 564 565 566 /** 567 * @brief ETH DMA Descriptors data structure definition 568 */ 569 570 typedef struct 571 { 572 __IO uint32_t Status; /*!< Status */ 573 574 uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ 575 576 uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ 577 578 uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ 579 580 /*!< Enhanced Ethernet DMA PTP Descriptors */ 581 uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */ 582 583 uint32_t Reserved1; /*!< Reserved */ 584 585 uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */ 586 587 uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */ 588 589 } ETH_DMADescTypeDef; 590 591 592 /** 593 * @brief Received Frame Information structure definition 594 */ 595 typedef struct 596 { 597 ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */ 598 599 ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */ 600 601 uint32_t SegCount; /*!< Segment count */ 602 603 uint32_t length; /*!< Frame length */ 604 605 uint32_t buffer; /*!< Frame buffer */ 606 607 } ETH_DMARxFrameInfos; 608 609 610 /** 611 * @brief ETH Handle Structure definition 612 */ 613 614 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 615 typedef struct __ETH_HandleTypeDef 616 #else 617 typedef struct 618 #endif 619 { 620 ETH_TypeDef *Instance; /*!< Register base address */ 621 622 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */ 623 624 uint32_t LinkStatus; /*!< Ethernet link status */ 625 626 ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */ 627 628 ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */ 629 630 ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */ 631 632 __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */ 633 634 HAL_LockTypeDef Lock; /*!< ETH Lock */ 635 636 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 637 638 void (* TxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Tx Complete Callback */ 639 void (* RxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Rx Complete Callback */ 640 void (* DMAErrorCallback) ( struct __ETH_HandleTypeDef * heth); /*!< DMA Error Callback */ 641 void (* MspInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp Init callback */ 642 void (* MspDeInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp DeInit callback */ 643 644 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 645 646 } ETH_HandleTypeDef; 647 648 649 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 650 /** 651 * @brief HAL ETH Callback ID enumeration definition 652 */ 653 typedef enum 654 { 655 HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */ 656 HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */ 657 HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */ 658 HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */ 659 HAL_ETH_DMA_ERROR_CB_ID = 0x04U, /*!< ETH DMA Error Callback ID */ 660 661 }HAL_ETH_CallbackIDTypeDef; 662 663 /** 664 * @brief HAL ETH Callback pointer definition 665 */ 666 typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef * heth); /*!< pointer to an ETH callback function */ 667 668 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 669 670 /** 671 * @} 672 */ 673 674 /* Exported constants --------------------------------------------------------*/ 675 /** @defgroup ETH_Exported_Constants ETH Exported Constants 676 * @{ 677 */ 678 679 /** @defgroup ETH_Buffers_setting ETH Buffers setting 680 * @{ 681 */ 682 #define ETH_MAX_PACKET_SIZE ((uint32_t)1524U) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */ 683 #define ETH_HEADER ((uint32_t)14U) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ 684 #define ETH_CRC ((uint32_t)4U) /*!< Ethernet CRC */ 685 #define ETH_EXTRA ((uint32_t)2U) /*!< Extra bytes in some cases */ 686 #define ETH_VLAN_TAG ((uint32_t)4U) /*!< optional 802.1q VLAN Tag */ 687 #define ETH_MIN_ETH_PAYLOAD ((uint32_t)46U) /*!< Minimum Ethernet payload size */ 688 #define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500U) /*!< Maximum Ethernet payload size */ 689 #define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000U) /*!< Jumbo frame payload size */ 690 691 /* Ethernet driver receive buffers are organized in a chained linked-list, when 692 an Ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO 693 to the driver receive buffers memory. 694 695 Depending on the size of the received Ethernet packet and the size of 696 each Ethernet driver receive buffer, the received packet can take one or more 697 Ethernet driver receive buffer. 698 699 In below are defined the size of one Ethernet driver receive buffer ETH_RX_BUF_SIZE 700 and the total count of the driver receive buffers ETH_RXBUFNB. 701 702 The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as 703 example, they can be reconfigured in the application layer to fit the application 704 needs */ 705 706 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet 707 packet */ 708 #ifndef ETH_RX_BUF_SIZE 709 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE 710 #endif 711 712 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ 713 #ifndef ETH_RXBUFNB 714 #define ETH_RXBUFNB ((uint32_t)5U) /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ 715 #endif 716 717 718 /* Ethernet driver transmit buffers are organized in a chained linked-list, when 719 an Ethernet packet is transmitted, Tx-DMA will transfer the packet from the 720 driver transmit buffers memory to the TxFIFO. 721 722 Depending on the size of the Ethernet packet to be transmitted and the size of 723 each Ethernet driver transmit buffer, the packet to be transmitted can take 724 one or more Ethernet driver transmit buffer. 725 726 In below are defined the size of one Ethernet driver transmit buffer ETH_TX_BUF_SIZE 727 and the total count of the driver transmit buffers ETH_TXBUFNB. 728 729 The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as 730 example, they can be reconfigured in the application layer to fit the application 731 needs */ 732 733 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet 734 packet */ 735 #ifndef ETH_TX_BUF_SIZE 736 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE 737 #endif 738 739 /* 5 Ethernet driver transmit buffers are used (in a chained linked list)*/ 740 #ifndef ETH_TXBUFNB 741 #define ETH_TXBUFNB ((uint32_t)5U) /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ 742 #endif 743 744 /** 745 * @} 746 */ 747 748 /** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor 749 * @{ 750 */ 751 752 /* 753 DMA Tx Descriptor 754 ----------------------------------------------------------------------------------------------- 755 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | 756 ----------------------------------------------------------------------------------------------- 757 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | 758 ----------------------------------------------------------------------------------------------- 759 TDES2 | Buffer1 Address [31:0] | 760 ----------------------------------------------------------------------------------------------- 761 TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | 762 ----------------------------------------------------------------------------------------------- 763 */ 764 765 /** 766 * @brief Bit definition of TDES0 register: DMA Tx descriptor status register 767 */ 768 #define ETH_DMATXDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */ 769 #define ETH_DMATXDESC_IC ((uint32_t)0x40000000U) /*!< Interrupt on Completion */ 770 #define ETH_DMATXDESC_LS ((uint32_t)0x20000000U) /*!< Last Segment */ 771 #define ETH_DMATXDESC_FS ((uint32_t)0x10000000U) /*!< First Segment */ 772 #define ETH_DMATXDESC_DC ((uint32_t)0x08000000U) /*!< Disable CRC */ 773 #define ETH_DMATXDESC_DP ((uint32_t)0x04000000U) /*!< Disable Padding */ 774 #define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000U) /*!< Transmit Time Stamp Enable */ 775 #define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000U) /*!< Checksum Insertion Control: 4 cases */ 776 #define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000U) /*!< Do Nothing: Checksum Engine is bypassed */ 777 #define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000U) /*!< IPV4 header Checksum Insertion */ 778 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000U) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ 779 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000U) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ 780 #define ETH_DMATXDESC_TER ((uint32_t)0x00200000U) /*!< Transmit End of Ring */ 781 #define ETH_DMATXDESC_TCH ((uint32_t)0x00100000U) /*!< Second Address Chained */ 782 #define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000U) /*!< Tx Time Stamp Status */ 783 #define ETH_DMATXDESC_IHE ((uint32_t)0x00010000U) /*!< IP Header Error */ 784 #define ETH_DMATXDESC_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ 785 #define ETH_DMATXDESC_JT ((uint32_t)0x00004000U) /*!< Jabber Timeout */ 786 #define ETH_DMATXDESC_FF ((uint32_t)0x00002000U) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ 787 #define ETH_DMATXDESC_PCE ((uint32_t)0x00001000U) /*!< Payload Checksum Error */ 788 #define ETH_DMATXDESC_LCA ((uint32_t)0x00000800U) /*!< Loss of Carrier: carrier lost during transmission */ 789 #define ETH_DMATXDESC_NC ((uint32_t)0x00000400U) /*!< No Carrier: no carrier signal from the transceiver */ 790 #define ETH_DMATXDESC_LCO ((uint32_t)0x00000200U) /*!< Late Collision: transmission aborted due to collision */ 791 #define ETH_DMATXDESC_EC ((uint32_t)0x00000100U) /*!< Excessive Collision: transmission aborted after 16 collisions */ 792 #define ETH_DMATXDESC_VF ((uint32_t)0x00000080U) /*!< VLAN Frame */ 793 #define ETH_DMATXDESC_CC ((uint32_t)0x00000078U) /*!< Collision Count */ 794 #define ETH_DMATXDESC_ED ((uint32_t)0x00000004U) /*!< Excessive Deferral */ 795 #define ETH_DMATXDESC_UF ((uint32_t)0x00000002U) /*!< Underflow Error: late data arrival from the memory */ 796 #define ETH_DMATXDESC_DB ((uint32_t)0x00000001U) /*!< Deferred Bit */ 797 798 /** 799 * @brief Bit definition of TDES1 register 800 */ 801 #define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000U) /*!< Transmit Buffer2 Size */ 802 #define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFFU) /*!< Transmit Buffer1 Size */ 803 804 /** 805 * @brief Bit definition of TDES2 register 806 */ 807 #define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer */ 808 809 /** 810 * @brief Bit definition of TDES3 register 811 */ 812 #define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */ 813 814 /*--------------------------------------------------------------------------------------------- 815 TDES6 | Transmit Time Stamp Low [31:0] | 816 ----------------------------------------------------------------------------------------------- 817 TDES7 | Transmit Time Stamp High [31:0] | 818 ----------------------------------------------------------------------------------------------*/ 819 820 /* Bit definition of TDES6 register */ 821 #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp Low */ 822 823 /* Bit definition of TDES7 register */ 824 #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp High */ 825 826 /** 827 * @} 828 */ 829 /** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor 830 * @{ 831 */ 832 833 /* 834 DMA Rx Descriptor 835 -------------------------------------------------------------------------------------------------------------------- 836 RDES0 | OWN(31) | Status [30:0] | 837 --------------------------------------------------------------------------------------------------------------------- 838 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | 839 --------------------------------------------------------------------------------------------------------------------- 840 RDES2 | Buffer1 Address [31:0] | 841 --------------------------------------------------------------------------------------------------------------------- 842 RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | 843 --------------------------------------------------------------------------------------------------------------------- 844 */ 845 846 /** 847 * @brief Bit definition of RDES0 register: DMA Rx descriptor status register 848 */ 849 #define ETH_DMARXDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */ 850 #define ETH_DMARXDESC_AFM ((uint32_t)0x40000000U) /*!< DA Filter Fail for the rx frame */ 851 #define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000U) /*!< Receive descriptor frame length */ 852 #define ETH_DMARXDESC_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ 853 #define ETH_DMARXDESC_DE ((uint32_t)0x00004000U) /*!< Descriptor error: no more descriptors for receive frame */ 854 #define ETH_DMARXDESC_SAF ((uint32_t)0x00002000U) /*!< SA Filter Fail for the received frame */ 855 #define ETH_DMARXDESC_LE ((uint32_t)0x00001000U) /*!< Frame size not matching with length field */ 856 #define ETH_DMARXDESC_OE ((uint32_t)0x00000800U) /*!< Overflow Error: Frame was damaged due to buffer overflow */ 857 #define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400U) /*!< VLAN Tag: received frame is a VLAN frame */ 858 #define ETH_DMARXDESC_FS ((uint32_t)0x00000200U) /*!< First descriptor of the frame */ 859 #define ETH_DMARXDESC_LS ((uint32_t)0x00000100U) /*!< Last descriptor of the frame */ 860 #define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080U) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ 861 #define ETH_DMARXDESC_LC ((uint32_t)0x00000040U) /*!< Late collision occurred during reception */ 862 #define ETH_DMARXDESC_FT ((uint32_t)0x00000020U) /*!< Frame type - Ethernet, otherwise 802.3 */ 863 #define ETH_DMARXDESC_RWT ((uint32_t)0x00000010U) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ 864 #define ETH_DMARXDESC_RE ((uint32_t)0x00000008U) /*!< Receive error: error reported by MII interface */ 865 #define ETH_DMARXDESC_DBE ((uint32_t)0x00000004U) /*!< Dribble bit error: frame contains non int multiple of 8 bits */ 866 #define ETH_DMARXDESC_CE ((uint32_t)0x00000002U) /*!< CRC error */ 867 #define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001U) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ 868 869 /** 870 * @brief Bit definition of RDES1 register 871 */ 872 #define ETH_DMARXDESC_DIC ((uint32_t)0x80000000U) /*!< Disable Interrupt on Completion */ 873 #define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000U) /*!< Receive Buffer2 Size */ 874 #define ETH_DMARXDESC_RER ((uint32_t)0x00008000U) /*!< Receive End of Ring */ 875 #define ETH_DMARXDESC_RCH ((uint32_t)0x00004000U) /*!< Second Address Chained */ 876 #define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFFU) /*!< Receive Buffer1 Size */ 877 878 /** 879 * @brief Bit definition of RDES2 register 880 */ 881 #define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer */ 882 883 /** 884 * @brief Bit definition of RDES3 register 885 */ 886 #define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */ 887 888 /*--------------------------------------------------------------------------------------------------------------------- 889 RDES4 | Reserved[31:15] | Extended Status [14:0] | 890 --------------------------------------------------------------------------------------------------------------------- 891 RDES5 | Reserved[31:0] | 892 --------------------------------------------------------------------------------------------------------------------- 893 RDES6 | Receive Time Stamp Low [31:0] | 894 --------------------------------------------------------------------------------------------------------------------- 895 RDES7 | Receive Time Stamp High [31:0] | 896 --------------------------------------------------------------------------------------------------------------------*/ 897 898 /* Bit definition of RDES4 register */ 899 #define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000U) /* PTP Version */ 900 #define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000U) /* PTP Frame Type */ 901 #define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00U) /* PTP Message Type */ 902 #define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100U) /* SYNC message (all clock types) */ 903 #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200U) /* FollowUp message (all clock types) */ 904 #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300U) /* DelayReq message (all clock types) */ 905 #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400U) /* DelayResp message (all clock types) */ 906 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500U) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ 907 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600U) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */ 908 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700U) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */ 909 #define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080U) /* IPv6 Packet Received */ 910 #define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040U) /* IPv4 Packet Received */ 911 #define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020U) /* IP Checksum Bypassed */ 912 #define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010U) /* IP Payload Error */ 913 #define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008U) /* IP Header Error */ 914 #define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007U) /* IP Payload Type */ 915 #define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001U) /* UDP payload encapsulated in the IP datagram */ 916 #define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002U) /* TCP payload encapsulated in the IP datagram */ 917 #define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003U) /* ICMP payload encapsulated in the IP datagram */ 918 919 /* Bit definition of RDES6 register */ 920 #define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp Low */ 921 922 /* Bit definition of RDES7 register */ 923 #define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp High */ 924 /** 925 * @} 926 */ 927 /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation 928 * @{ 929 */ 930 #define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001U) 931 #define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000U) 932 933 /** 934 * @} 935 */ 936 /** @defgroup ETH_Speed ETH Speed 937 * @{ 938 */ 939 #define ETH_SPEED_10M ((uint32_t)0x00000000U) 940 #define ETH_SPEED_100M ((uint32_t)0x00004000U) 941 942 /** 943 * @} 944 */ 945 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode 946 * @{ 947 */ 948 #define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800U) 949 #define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000U) 950 /** 951 * @} 952 */ 953 /** @defgroup ETH_Rx_Mode ETH Rx Mode 954 * @{ 955 */ 956 #define ETH_RXPOLLING_MODE ((uint32_t)0x00000000U) 957 #define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001U) 958 /** 959 * @} 960 */ 961 962 /** @defgroup ETH_Checksum_Mode ETH Checksum Mode 963 * @{ 964 */ 965 #define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000U) 966 #define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001U) 967 /** 968 * @} 969 */ 970 971 /** @defgroup ETH_Media_Interface ETH Media Interface 972 * @{ 973 */ 974 #define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000U) 975 #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL) 976 /** 977 * @} 978 */ 979 980 /** @defgroup ETH_Watchdog ETH Watchdog 981 * @{ 982 */ 983 #define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000U) 984 #define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000U) 985 /** 986 * @} 987 */ 988 989 /** @defgroup ETH_Jabber ETH Jabber 990 * @{ 991 */ 992 #define ETH_JABBER_ENABLE ((uint32_t)0x00000000U) 993 #define ETH_JABBER_DISABLE ((uint32_t)0x00400000U) 994 /** 995 * @} 996 */ 997 998 /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap 999 * @{ 1000 */ 1001 #define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000U) /*!< minimum IFG between frames during transmission is 96Bit */ 1002 #define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000U) /*!< minimum IFG between frames during transmission is 88Bit */ 1003 #define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000U) /*!< minimum IFG between frames during transmission is 80Bit */ 1004 #define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000U) /*!< minimum IFG between frames during transmission is 72Bit */ 1005 #define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000U) /*!< minimum IFG between frames during transmission is 64Bit */ 1006 #define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000U) /*!< minimum IFG between frames during transmission is 56Bit */ 1007 #define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000U) /*!< minimum IFG between frames during transmission is 48Bit */ 1008 #define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000U) /*!< minimum IFG between frames during transmission is 40Bit */ 1009 /** 1010 * @} 1011 */ 1012 1013 /** @defgroup ETH_Carrier_Sense ETH Carrier Sense 1014 * @{ 1015 */ 1016 #define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000U) 1017 #define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000U) 1018 /** 1019 * @} 1020 */ 1021 1022 /** @defgroup ETH_Receive_Own ETH Receive Own 1023 * @{ 1024 */ 1025 #define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000U) 1026 #define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000U) 1027 /** 1028 * @} 1029 */ 1030 1031 /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode 1032 * @{ 1033 */ 1034 #define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000U) 1035 #define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000U) 1036 /** 1037 * @} 1038 */ 1039 1040 /** @defgroup ETH_Checksum_Offload ETH Checksum Offload 1041 * @{ 1042 */ 1043 #define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400U) 1044 #define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000U) 1045 /** 1046 * @} 1047 */ 1048 1049 /** @defgroup ETH_Retry_Transmission ETH Retry Transmission 1050 * @{ 1051 */ 1052 #define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000U) 1053 #define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200U) 1054 /** 1055 * @} 1056 */ 1057 1058 /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip 1059 * @{ 1060 */ 1061 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080U) 1062 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000U) 1063 /** 1064 * @} 1065 */ 1066 1067 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit 1068 * @{ 1069 */ 1070 #define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000U) 1071 #define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020U) 1072 #define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040U) 1073 #define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060U) 1074 /** 1075 * @} 1076 */ 1077 1078 /** @defgroup ETH_Deferral_Check ETH Deferral Check 1079 * @{ 1080 */ 1081 #define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010U) 1082 #define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000U) 1083 /** 1084 * @} 1085 */ 1086 1087 /** @defgroup ETH_Receive_All ETH Receive All 1088 * @{ 1089 */ 1090 #define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000U) 1091 #define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000U) 1092 /** 1093 * @} 1094 */ 1095 1096 /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter 1097 * @{ 1098 */ 1099 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200U) 1100 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300U) 1101 #define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000U) 1102 /** 1103 * @} 1104 */ 1105 1106 /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames 1107 * @{ 1108 */ 1109 #define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040U) /*!< MAC filters all control frames from reaching the application */ 1110 #define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080U) /*!< MAC forwards all control frames to application even if they fail the Address Filter */ 1111 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0U) /*!< MAC forwards control frames that pass the Address Filter. */ 1112 /** 1113 * @} 1114 */ 1115 1116 /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception 1117 * @{ 1118 */ 1119 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000U) 1120 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020U) 1121 /** 1122 * @} 1123 */ 1124 1125 /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter 1126 * @{ 1127 */ 1128 #define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000U) 1129 #define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008U) 1130 /** 1131 * @} 1132 */ 1133 1134 /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode 1135 * @{ 1136 */ 1137 #define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001U) 1138 #define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000U) 1139 /** 1140 * @} 1141 */ 1142 1143 /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter 1144 * @{ 1145 */ 1146 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404U) 1147 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004U) 1148 #define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000U) 1149 #define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010U) 1150 /** 1151 * @} 1152 */ 1153 1154 /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter 1155 * @{ 1156 */ 1157 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402U) 1158 #define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002U) 1159 #define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000U) 1160 /** 1161 * @} 1162 */ 1163 1164 /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause 1165 * @{ 1166 */ 1167 #define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000U) 1168 #define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080U) 1169 /** 1170 * @} 1171 */ 1172 1173 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold 1174 * @{ 1175 */ 1176 #define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000U) /*!< Pause time minus 4 slot times */ 1177 #define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010U) /*!< Pause time minus 28 slot times */ 1178 #define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020U) /*!< Pause time minus 144 slot times */ 1179 #define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030U) /*!< Pause time minus 256 slot times */ 1180 /** 1181 * @} 1182 */ 1183 1184 /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect 1185 * @{ 1186 */ 1187 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008U) 1188 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000U) 1189 /** 1190 * @} 1191 */ 1192 1193 /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control 1194 * @{ 1195 */ 1196 #define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004U) 1197 #define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000U) 1198 /** 1199 * @} 1200 */ 1201 1202 /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control 1203 * @{ 1204 */ 1205 #define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002U) 1206 #define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000U) 1207 /** 1208 * @} 1209 */ 1210 1211 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison 1212 * @{ 1213 */ 1214 #define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000U) 1215 #define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U) 1216 /** 1217 * @} 1218 */ 1219 1220 /** @defgroup ETH_MAC_addresses ETH MAC addresses 1221 * @{ 1222 */ 1223 #define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000U) 1224 #define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008U) 1225 #define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010U) 1226 #define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018U) 1227 /** 1228 * @} 1229 */ 1230 1231 /** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA 1232 * @{ 1233 */ 1234 #define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000U) 1235 #define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008U) 1236 /** 1237 * @} 1238 */ 1239 1240 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes 1241 * @{ 1242 */ 1243 #define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000U) /*!< Mask MAC Address high reg bits [15:8] */ 1244 #define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000U) /*!< Mask MAC Address high reg bits [7:0] */ 1245 #define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000U) /*!< Mask MAC Address low reg bits [31:24] */ 1246 #define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000U) /*!< Mask MAC Address low reg bits [23:16] */ 1247 #define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000U) /*!< Mask MAC Address low reg bits [15:8] */ 1248 #define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000U) /*!< Mask MAC Address low reg bits [70] */ 1249 /** 1250 * @} 1251 */ 1252 1253 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame 1254 * @{ 1255 */ 1256 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000U) 1257 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000U) 1258 /** 1259 * @} 1260 */ 1261 1262 /** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward 1263 * @{ 1264 */ 1265 #define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000U) 1266 #define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000U) 1267 /** 1268 * @} 1269 */ 1270 1271 /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame 1272 * @{ 1273 */ 1274 #define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000U) 1275 #define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000U) 1276 /** 1277 * @} 1278 */ 1279 1280 /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward 1281 * @{ 1282 */ 1283 #define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000U) 1284 #define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000U) 1285 /** 1286 * @} 1287 */ 1288 1289 /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control 1290 * @{ 1291 */ 1292 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000U) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ 1293 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000U) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ 1294 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000U) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ 1295 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000U) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ 1296 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000U) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ 1297 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000U) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ 1298 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000U) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ 1299 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000U) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ 1300 /** 1301 * @} 1302 */ 1303 1304 /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames 1305 * @{ 1306 */ 1307 #define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080U) 1308 #define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000U) 1309 /** 1310 * @} 1311 */ 1312 1313 /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames 1314 * @{ 1315 */ 1316 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040U) 1317 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000U) 1318 /** 1319 * @} 1320 */ 1321 1322 /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control 1323 * @{ 1324 */ 1325 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000U) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ 1326 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008U) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ 1327 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010U) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ 1328 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018U) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ 1329 /** 1330 * @} 1331 */ 1332 1333 /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate 1334 * @{ 1335 */ 1336 #define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004U) 1337 #define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000U) 1338 /** 1339 * @} 1340 */ 1341 1342 /** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats 1343 * @{ 1344 */ 1345 #define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000U) 1346 #define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000U) 1347 /** 1348 * @} 1349 */ 1350 1351 /** @defgroup ETH_Fixed_Burst ETH Fixed Burst 1352 * @{ 1353 */ 1354 #define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000U) 1355 #define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000U) 1356 /** 1357 * @} 1358 */ 1359 1360 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length 1361 * @{ 1362 */ 1363 #define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ 1364 #define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ 1365 #define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ 1366 #define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ 1367 #define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ 1368 #define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ 1369 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ 1370 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ 1371 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ 1372 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ 1373 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ 1374 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ 1375 /** 1376 * @} 1377 */ 1378 1379 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length 1380 * @{ 1381 */ 1382 #define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ 1383 #define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ 1384 #define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 1385 #define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 1386 #define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 1387 #define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 1388 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 1389 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 1390 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 1391 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 1392 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ 1393 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ 1394 /** 1395 * @} 1396 */ 1397 1398 /** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format 1399 * @{ 1400 */ 1401 #define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080U) 1402 #define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000U) 1403 /** 1404 * @} 1405 */ 1406 1407 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration 1408 * @{ 1409 */ 1410 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000U) 1411 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000U) 1412 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000U) 1413 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000U) 1414 #define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002U) 1415 /** 1416 * @} 1417 */ 1418 1419 /** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment 1420 * @{ 1421 */ 1422 #define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000U) /*!< Last Segment */ 1423 #define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000U) /*!< First Segment */ 1424 /** 1425 * @} 1426 */ 1427 1428 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control 1429 * @{ 1430 */ 1431 #define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000U) /*!< Checksum engine bypass */ 1432 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000U) /*!< IPv4 header checksum insertion */ 1433 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000U) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ 1434 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000U) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ 1435 /** 1436 * @} 1437 */ 1438 1439 /** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers 1440 * @{ 1441 */ 1442 #define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000U) /*!< DMA Rx Desc Buffer1 */ 1443 #define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001U) /*!< DMA Rx Desc Buffer2 */ 1444 /** 1445 * @} 1446 */ 1447 1448 /** @defgroup ETH_PMT_Flags ETH PMT Flags 1449 * @{ 1450 */ 1451 #define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000U) /*!< Wake-Up Frame Filter Register Pointer Reset */ 1452 #define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040U) /*!< Wake-Up Frame Received */ 1453 #define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020U) /*!< Magic Packet Received */ 1454 /** 1455 * @} 1456 */ 1457 1458 /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts 1459 * @{ 1460 */ 1461 #define ETH_MMC_IT_TGF ((uint32_t)0x00200000U) /*!< When Tx good frame counter reaches half the maximum value */ 1462 #define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000U) /*!< When Tx good multi col counter reaches half the maximum value */ 1463 #define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000U) /*!< When Tx good single col counter reaches half the maximum value */ 1464 /** 1465 * @} 1466 */ 1467 1468 /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts 1469 * @{ 1470 */ 1471 #define ETH_MMC_IT_RGUF ((uint32_t)0x10020000U) /*!< When Rx good unicast frames counter reaches half the maximum value */ 1472 #define ETH_MMC_IT_RFAE ((uint32_t)0x10000040U) /*!< When Rx alignment error counter reaches half the maximum value */ 1473 #define ETH_MMC_IT_RFCE ((uint32_t)0x10000020U) /*!< When Rx crc error counter reaches half the maximum value */ 1474 /** 1475 * @} 1476 */ 1477 1478 /** @defgroup ETH_MAC_Flags ETH MAC Flags 1479 * @{ 1480 */ 1481 #define ETH_MAC_FLAG_TST ((uint32_t)0x00000200U) /*!< Time stamp trigger flag (on MAC) */ 1482 #define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040U) /*!< MMC transmit flag */ 1483 #define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020U) /*!< MMC receive flag */ 1484 #define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010U) /*!< MMC flag (on MAC) */ 1485 #define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008U) /*!< PMT flag (on MAC) */ 1486 /** 1487 * @} 1488 */ 1489 1490 /** @defgroup ETH_DMA_Flags ETH DMA Flags 1491 * @{ 1492 */ 1493 #define ETH_DMA_FLAG_TST ((uint32_t)0x20000000U) /*!< Time-stamp trigger interrupt (on DMA) */ 1494 #define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000U) /*!< PMT interrupt (on DMA) */ 1495 #define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000U) /*!< MMC interrupt (on DMA) */ 1496 #define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000U) /*!< Error bits 0-Rx DMA, 1-Tx DMA */ 1497 #define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000U) /*!< Error bits 0-write transfer, 1-read transfer */ 1498 #define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000U) /*!< Error bits 0-data buffer, 1-desc. access */ 1499 #define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000U) /*!< Normal interrupt summary flag */ 1500 #define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000U) /*!< Abnormal interrupt summary flag */ 1501 #define ETH_DMA_FLAG_ER ((uint32_t)0x00004000U) /*!< Early receive flag */ 1502 #define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000U) /*!< Fatal bus error flag */ 1503 #define ETH_DMA_FLAG_ET ((uint32_t)0x00000400U) /*!< Early transmit flag */ 1504 #define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200U) /*!< Receive watchdog timeout flag */ 1505 #define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100U) /*!< Receive process stopped flag */ 1506 #define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080U) /*!< Receive buffer unavailable flag */ 1507 #define ETH_DMA_FLAG_R ((uint32_t)0x00000040U) /*!< Receive flag */ 1508 #define ETH_DMA_FLAG_TU ((uint32_t)0x00000020U) /*!< Underflow flag */ 1509 #define ETH_DMA_FLAG_RO ((uint32_t)0x00000010U) /*!< Overflow flag */ 1510 #define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008U) /*!< Transmit jabber timeout flag */ 1511 #define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004U) /*!< Transmit buffer unavailable flag */ 1512 #define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002U) /*!< Transmit process stopped flag */ 1513 #define ETH_DMA_FLAG_T ((uint32_t)0x00000001U) /*!< Transmit flag */ 1514 /** 1515 * @} 1516 */ 1517 1518 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts 1519 * @{ 1520 */ 1521 #define ETH_MAC_IT_TST ((uint32_t)0x00000200U) /*!< Time stamp trigger interrupt (on MAC) */ 1522 #define ETH_MAC_IT_MMCT ((uint32_t)0x00000040U) /*!< MMC transmit interrupt */ 1523 #define ETH_MAC_IT_MMCR ((uint32_t)0x00000020U) /*!< MMC receive interrupt */ 1524 #define ETH_MAC_IT_MMC ((uint32_t)0x00000010U) /*!< MMC interrupt (on MAC) */ 1525 #define ETH_MAC_IT_PMT ((uint32_t)0x00000008U) /*!< PMT interrupt (on MAC) */ 1526 /** 1527 * @} 1528 */ 1529 1530 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts 1531 * @{ 1532 */ 1533 #define ETH_DMA_IT_TST ((uint32_t)0x20000000U) /*!< Time-stamp trigger interrupt (on DMA) */ 1534 #define ETH_DMA_IT_PMT ((uint32_t)0x10000000U) /*!< PMT interrupt (on DMA) */ 1535 #define ETH_DMA_IT_MMC ((uint32_t)0x08000000U) /*!< MMC interrupt (on DMA) */ 1536 #define ETH_DMA_IT_NIS ((uint32_t)0x00010000U) /*!< Normal interrupt summary */ 1537 #define ETH_DMA_IT_AIS ((uint32_t)0x00008000U) /*!< Abnormal interrupt summary */ 1538 #define ETH_DMA_IT_ER ((uint32_t)0x00004000U) /*!< Early receive interrupt */ 1539 #define ETH_DMA_IT_FBE ((uint32_t)0x00002000U) /*!< Fatal bus error interrupt */ 1540 #define ETH_DMA_IT_ET ((uint32_t)0x00000400U) /*!< Early transmit interrupt */ 1541 #define ETH_DMA_IT_RWT ((uint32_t)0x00000200U) /*!< Receive watchdog timeout interrupt */ 1542 #define ETH_DMA_IT_RPS ((uint32_t)0x00000100U) /*!< Receive process stopped interrupt */ 1543 #define ETH_DMA_IT_RBU ((uint32_t)0x00000080U) /*!< Receive buffer unavailable interrupt */ 1544 #define ETH_DMA_IT_R ((uint32_t)0x00000040U) /*!< Receive interrupt */ 1545 #define ETH_DMA_IT_TU ((uint32_t)0x00000020U) /*!< Underflow interrupt */ 1546 #define ETH_DMA_IT_RO ((uint32_t)0x00000010U) /*!< Overflow interrupt */ 1547 #define ETH_DMA_IT_TJT ((uint32_t)0x00000008U) /*!< Transmit jabber timeout interrupt */ 1548 #define ETH_DMA_IT_TBU ((uint32_t)0x00000004U) /*!< Transmit buffer unavailable interrupt */ 1549 #define ETH_DMA_IT_TPS ((uint32_t)0x00000002U) /*!< Transmit process stopped interrupt */ 1550 #define ETH_DMA_IT_T ((uint32_t)0x00000001U) /*!< Transmit interrupt */ 1551 /** 1552 * @} 1553 */ 1554 1555 /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state 1556 * @{ 1557 */ 1558 #define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000U) /*!< Stopped - Reset or Stop Tx Command issued */ 1559 #define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000U) /*!< Running - fetching the Tx descriptor */ 1560 #define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000U) /*!< Running - waiting for status */ 1561 #define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000U) /*!< Running - reading the data from host memory */ 1562 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000U) /*!< Suspended - Tx Descriptor unavailable */ 1563 #define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000U) /*!< Running - closing Rx descriptor */ 1564 1565 /** 1566 * @} 1567 */ 1568 1569 1570 /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state 1571 * @{ 1572 */ 1573 #define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000U) /*!< Stopped - Reset or Stop Rx Command issued */ 1574 #define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000U) /*!< Running - fetching the Rx descriptor */ 1575 #define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000U) /*!< Running - waiting for packet */ 1576 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000U) /*!< Suspended - Rx Descriptor unavailable */ 1577 #define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000U) /*!< Running - closing descriptor */ 1578 #define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000U) /*!< Running - queuing the receive frame into host memory */ 1579 1580 /** 1581 * @} 1582 */ 1583 1584 /** @defgroup ETH_DMA_overflow ETH DMA overflow 1585 * @{ 1586 */ 1587 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000U) /*!< Overflow bit for FIFO overflow counter */ 1588 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000U) /*!< Overflow bit for missed frame counter */ 1589 /** 1590 * @} 1591 */ 1592 1593 /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP 1594 * @{ 1595 */ 1596 #define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000U) /*!< External interrupt line 19 Connected to the ETH EXTI Line */ 1597 1598 /** 1599 * @} 1600 */ 1601 1602 /** 1603 * @} 1604 */ 1605 1606 /* Exported macro ------------------------------------------------------------*/ 1607 /** @defgroup ETH_Exported_Macros ETH Exported Macros 1608 * @brief macros to handle interrupts and specific clock configurations 1609 * @{ 1610 */ 1611 1612 /** @brief Reset ETH handle state 1613 * @param __HANDLE__ specifies the ETH handle. 1614 * @retval None 1615 */ 1616 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 1617 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ 1618 (__HANDLE__)->State = HAL_ETH_STATE_RESET; \ 1619 (__HANDLE__)->MspInitCallback = NULL; \ 1620 (__HANDLE__)->MspDeInitCallback = NULL; \ 1621 } while(0) 1622 #else 1623 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET) 1624 #endif /*USE_HAL_ETH_REGISTER_CALLBACKS */ 1625 1626 /** 1627 * @brief Checks whether the specified Ethernet DMA Tx Desc flag is set or not. 1628 * @param __HANDLE__ ETH Handle 1629 * @param __FLAG__ specifies the flag of TDES0 to check. 1630 * @retval the ETH_DMATxDescFlag (SET or RESET). 1631 */ 1632 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__)) 1633 1634 /** 1635 * @brief Checks whether the specified Ethernet DMA Rx Desc flag is set or not. 1636 * @param __HANDLE__ ETH Handle 1637 * @param __FLAG__ specifies the flag of RDES0 to check. 1638 * @retval the ETH_DMATxDescFlag (SET or RESET). 1639 */ 1640 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__)) 1641 1642 /** 1643 * @brief Enables the specified DMA Rx Desc receive interrupt. 1644 * @param __HANDLE__ ETH Handle 1645 * @retval None 1646 */ 1647 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC)) 1648 1649 /** 1650 * @brief Disables the specified DMA Rx Desc receive interrupt. 1651 * @param __HANDLE__ ETH Handle 1652 * @retval None 1653 */ 1654 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC) 1655 1656 /** 1657 * @brief Set the specified DMA Rx Desc Own bit. 1658 * @param __HANDLE__ ETH Handle 1659 * @retval None 1660 */ 1661 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN) 1662 1663 /** 1664 * @brief Returns the specified Ethernet DMA Tx Desc collision count. 1665 * @param __HANDLE__ ETH Handle 1666 * @retval The Transmit descriptor collision counter value. 1667 */ 1668 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT) 1669 1670 /** 1671 * @brief Set the specified DMA Tx Desc Own bit. 1672 * @param __HANDLE__ ETH Handle 1673 * @retval None 1674 */ 1675 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN) 1676 1677 /** 1678 * @brief Enables the specified DMA Tx Desc Transmit interrupt. 1679 * @param __HANDLE__ ETH Handle 1680 * @retval None 1681 */ 1682 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC) 1683 1684 /** 1685 * @brief Disables the specified DMA Tx Desc Transmit interrupt. 1686 * @param __HANDLE__ ETH Handle 1687 * @retval None 1688 */ 1689 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC) 1690 1691 /** 1692 * @brief Selects the specified Ethernet DMA Tx Desc Checksum Insertion. 1693 * @param __HANDLE__ ETH Handle 1694 * @param __CHECKSUM__ specifies is the DMA Tx desc checksum insertion. 1695 * This parameter can be one of the following values: 1696 * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass 1697 * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum 1698 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present 1699 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header 1700 * @retval None 1701 */ 1702 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__)) 1703 1704 /** 1705 * @brief Enables the DMA Tx Desc CRC. 1706 * @param __HANDLE__ ETH Handle 1707 * @retval None 1708 */ 1709 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC) 1710 1711 /** 1712 * @brief Disables the DMA Tx Desc CRC. 1713 * @param __HANDLE__ ETH Handle 1714 * @retval None 1715 */ 1716 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC) 1717 1718 /** 1719 * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes. 1720 * @param __HANDLE__ ETH Handle 1721 * @retval None 1722 */ 1723 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP) 1724 1725 /** 1726 * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes. 1727 * @param __HANDLE__ ETH Handle 1728 * @retval None 1729 */ 1730 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP) 1731 1732 /** 1733 * @brief Enables the specified Ethernet MAC interrupts. 1734 * @param __HANDLE__ ETH Handle 1735 * @param __INTERRUPT__ specifies the Ethernet MAC interrupt sources to be 1736 * enabled or disabled. 1737 * This parameter can be any combination of the following values: 1738 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt 1739 * @arg ETH_MAC_IT_PMT : PMT interrupt 1740 * @retval None 1741 */ 1742 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__)) 1743 1744 /** 1745 * @brief Disables the specified Ethernet MAC interrupts. 1746 * @param __HANDLE__ ETH Handle 1747 * @param __INTERRUPT__ specifies the Ethernet MAC interrupt sources to be 1748 * enabled or disabled. 1749 * This parameter can be any combination of the following values: 1750 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt 1751 * @arg ETH_MAC_IT_PMT : PMT interrupt 1752 * @retval None 1753 */ 1754 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__)) 1755 1756 /** 1757 * @brief Initiate a Pause Control Frame (Full-duplex only). 1758 * @param __HANDLE__ ETH Handle 1759 * @retval None 1760 */ 1761 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) 1762 1763 /** 1764 * @brief Checks whether the Ethernet flow control busy bit is set or not. 1765 * @param __HANDLE__ ETH Handle 1766 * @retval The new state of flow control busy status bit (SET or RESET). 1767 */ 1768 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA) 1769 1770 /** 1771 * @brief Enables the MAC Back Pressure operation activation (Half-duplex only). 1772 * @param __HANDLE__ ETH Handle 1773 * @retval None 1774 */ 1775 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) 1776 1777 /** 1778 * @brief Disables the MAC BackPressure operation activation (Half-duplex only). 1779 * @param __HANDLE__ ETH Handle 1780 * @retval None 1781 */ 1782 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA) 1783 1784 /** 1785 * @brief Checks whether the specified Ethernet MAC flag is set or not. 1786 * @param __HANDLE__ ETH Handle 1787 * @param __FLAG__ specifies the flag to check. 1788 * This parameter can be one of the following values: 1789 * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag 1790 * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag 1791 * @arg ETH_MAC_FLAG_MMCR : MMC receive flag 1792 * @arg ETH_MAC_FLAG_MMC : MMC flag 1793 * @arg ETH_MAC_FLAG_PMT : PMT flag 1794 * @retval The state of Ethernet MAC flag. 1795 */ 1796 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__)) 1797 1798 /** 1799 * @brief Enables the specified Ethernet DMA interrupts. 1800 * @param __HANDLE__ ETH Handle 1801 * @param __INTERRUPT__ specifies the Ethernet DMA interrupt sources to be 1802 * enabled @ref ETH_DMA_Interrupts 1803 * @retval None 1804 */ 1805 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__)) 1806 1807 /** 1808 * @brief Disables the specified Ethernet DMA interrupts. 1809 * @param __HANDLE__ ETH Handle 1810 * @param __INTERRUPT__ specifies the Ethernet DMA interrupt sources to be 1811 * disabled. @ref ETH_DMA_Interrupts 1812 * @retval None 1813 */ 1814 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__)) 1815 1816 /** 1817 * @brief Clears the Ethernet DMA IT pending bit. 1818 * @param __HANDLE__ ETH Handle 1819 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts 1820 * @retval None 1821 */ 1822 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__)) 1823 1824 /** 1825 * @brief Checks whether the specified Ethernet DMA flag is set or not. 1826 * @param __HANDLE__ ETH Handle 1827 * @param __FLAG__ specifies the flag to check. @ref ETH_DMA_Flags 1828 * @retval The new state of ETH_DMA_FLAG (SET or RESET). 1829 */ 1830 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__)) 1831 1832 /** 1833 * @brief Checks whether the specified Ethernet DMA flag is set or not. 1834 * @param __HANDLE__ ETH Handle 1835 * @param __FLAG__ specifies the flag to clear. @ref ETH_DMA_Flags 1836 * @retval The new state of ETH_DMA_FLAG (SET or RESET). 1837 */ 1838 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__)) 1839 1840 /** 1841 * @brief Checks whether the specified Ethernet DMA overflow flag is set or not. 1842 * @param __HANDLE__ ETH Handle 1843 * @param __OVERFLOW__ specifies the DMA overflow flag to check. 1844 * This parameter can be one of the following values: 1845 * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter 1846 * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter 1847 * @retval The state of Ethernet DMA overflow Flag (SET or RESET). 1848 */ 1849 #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__)) 1850 1851 /** 1852 * @brief Set the DMA Receive status watchdog timer register value 1853 * @param __HANDLE__ ETH Handle 1854 * @param __VALUE__ DMA Receive status watchdog timer register value 1855 * @retval None 1856 */ 1857 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__)) 1858 1859 /** 1860 * @brief Enables any unicast packet filtered by the MAC address 1861 * recognition to be a wake-up frame. 1862 * @param __HANDLE__ ETH Handle. 1863 * @retval None 1864 */ 1865 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU) 1866 1867 /** 1868 * @brief Disables any unicast packet filtered by the MAC address 1869 * recognition to be a wake-up frame. 1870 * @param __HANDLE__ ETH Handle. 1871 * @retval None 1872 */ 1873 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU) 1874 1875 /** 1876 * @brief Enables the MAC Wake-Up Frame Detection. 1877 * @param __HANDLE__ ETH Handle. 1878 * @retval None 1879 */ 1880 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE) 1881 1882 /** 1883 * @brief Disables the MAC Wake-Up Frame Detection. 1884 * @param __HANDLE__ ETH Handle. 1885 * @retval None 1886 */ 1887 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) 1888 1889 /** 1890 * @brief Enables the MAC Magic Packet Detection. 1891 * @param __HANDLE__ ETH Handle. 1892 * @retval None 1893 */ 1894 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE) 1895 1896 /** 1897 * @brief Disables the MAC Magic Packet Detection. 1898 * @param __HANDLE__ ETH Handle. 1899 * @retval None 1900 */ 1901 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) 1902 1903 /** 1904 * @brief Enables the MAC Power Down. 1905 * @param __HANDLE__ ETH Handle 1906 * @retval None 1907 */ 1908 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD) 1909 1910 /** 1911 * @brief Disables the MAC Power Down. 1912 * @param __HANDLE__ ETH Handle 1913 * @retval None 1914 */ 1915 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD) 1916 1917 /** 1918 * @brief Checks whether the specified Ethernet PMT flag is set or not. 1919 * @param __HANDLE__ ETH Handle. 1920 * @param __FLAG__ specifies the flag to check. 1921 * This parameter can be one of the following values: 1922 * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset 1923 * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received 1924 * @arg ETH_PMT_FLAG_MPR : Magic Packet Received 1925 * @retval The new state of Ethernet PMT Flag (SET or RESET). 1926 */ 1927 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__)) 1928 1929 /** 1930 * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16) 1931 * @param __HANDLE__ ETH Handle. 1932 * @retval None 1933 */ 1934 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP)) 1935 1936 /** 1937 * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16) 1938 * @param __HANDLE__ ETH Handle. 1939 * @retval None 1940 */ 1941 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\ 1942 (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0) 1943 1944 /** 1945 * @brief Enables the MMC Counter Freeze. 1946 * @param __HANDLE__ ETH Handle. 1947 * @retval None 1948 */ 1949 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF) 1950 1951 /** 1952 * @brief Disables the MMC Counter Freeze. 1953 * @param __HANDLE__ ETH Handle. 1954 * @retval None 1955 */ 1956 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF) 1957 1958 /** 1959 * @brief Enables the MMC Reset On Read. 1960 * @param __HANDLE__ ETH Handle. 1961 * @retval None 1962 */ 1963 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR) 1964 1965 /** 1966 * @brief Disables the MMC Reset On Read. 1967 * @param __HANDLE__ ETH Handle. 1968 * @retval None 1969 */ 1970 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR) 1971 1972 /** 1973 * @brief Enables the MMC Counter Stop Rollover. 1974 * @param __HANDLE__ ETH Handle. 1975 * @retval None 1976 */ 1977 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR) 1978 1979 /** 1980 * @brief Disables the MMC Counter Stop Rollover. 1981 * @param __HANDLE__ ETH Handle. 1982 * @retval None 1983 */ 1984 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR) 1985 1986 /** 1987 * @brief Resets the MMC Counters. 1988 * @param __HANDLE__ ETH Handle. 1989 * @retval None 1990 */ 1991 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR) 1992 1993 /** 1994 * @brief Enables the specified Ethernet MMC Rx interrupts. 1995 * @param __HANDLE__ ETH Handle. 1996 * @param __INTERRUPT__ specifies the Ethernet MMC interrupt sources to be enabled or disabled. 1997 * This parameter can be one of the following values: 1998 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value 1999 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value 2000 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value 2001 * @retval None 2002 */ 2003 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF) 2004 /** 2005 * @brief Disables the specified Ethernet MMC Rx interrupts. 2006 * @param __HANDLE__ ETH Handle. 2007 * @param __INTERRUPT__ specifies the Ethernet MMC interrupt sources to be enabled or disabled. 2008 * This parameter can be one of the following values: 2009 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value 2010 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value 2011 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value 2012 * @retval None 2013 */ 2014 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF) 2015 /** 2016 * @brief Enables the specified Ethernet MMC Tx interrupts. 2017 * @param __HANDLE__ ETH Handle. 2018 * @param __INTERRUPT__ specifies the Ethernet MMC interrupt sources to be enabled or disabled. 2019 * This parameter can be one of the following values: 2020 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value 2021 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value 2022 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value 2023 * @retval None 2024 */ 2025 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__)) 2026 2027 /** 2028 * @brief Disables the specified Ethernet MMC Tx interrupts. 2029 * @param __HANDLE__ ETH Handle. 2030 * @param __INTERRUPT__ specifies the Ethernet MMC interrupt sources to be enabled or disabled. 2031 * This parameter can be one of the following values: 2032 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value 2033 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value 2034 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value 2035 * @retval None 2036 */ 2037 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__)) 2038 2039 /** 2040 * @brief Enables the ETH External interrupt line. 2041 * @retval None 2042 */ 2043 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP) 2044 2045 /** 2046 * @brief Disables the ETH External interrupt line. 2047 * @retval None 2048 */ 2049 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP) 2050 2051 /** 2052 * @brief Enable event on ETH External event line. 2053 * @retval None. 2054 */ 2055 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP) 2056 2057 /** 2058 * @brief Disable event on ETH External event line 2059 * @retval None. 2060 */ 2061 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP) 2062 2063 /** 2064 * @brief Get flag of the ETH External interrupt line. 2065 * @retval None 2066 */ 2067 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP) 2068 2069 /** 2070 * @brief Clear flag of the ETH External interrupt line. 2071 * @retval None 2072 */ 2073 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP) 2074 2075 /** 2076 * @brief Enables rising edge trigger to the ETH External interrupt line. 2077 * @retval None 2078 */ 2079 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP 2080 2081 /** 2082 * @brief Disables the rising edge trigger to the ETH External interrupt line. 2083 * @retval None 2084 */ 2085 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP) 2086 2087 /** 2088 * @brief Enables falling edge trigger to the ETH External interrupt line. 2089 * @retval None 2090 */ 2091 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP) 2092 2093 /** 2094 * @brief Disables falling edge trigger to the ETH External interrupt line. 2095 * @retval None 2096 */ 2097 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP) 2098 2099 /** 2100 * @brief Enables rising/falling edge trigger to the ETH External interrupt line. 2101 * @retval None 2102 */ 2103 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\ 2104 EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\ 2105 }while(0) 2106 2107 /** 2108 * @brief Disables rising/falling edge trigger to the ETH External interrupt line. 2109 * @retval None 2110 */ 2111 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ 2112 EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ 2113 }while(0) 2114 2115 /** 2116 * @brief Generate a Software interrupt on selected EXTI line. 2117 * @retval None. 2118 */ 2119 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP 2120 2121 /** 2122 * @} 2123 */ 2124 /* Exported functions --------------------------------------------------------*/ 2125 2126 /** @addtogroup ETH_Exported_Functions 2127 * @{ 2128 */ 2129 2130 /* Initialization and de-initialization functions ****************************/ 2131 2132 /** @addtogroup ETH_Exported_Functions_Group1 2133 * @{ 2134 */ 2135 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); 2136 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); 2137 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); 2138 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); 2139 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount); 2140 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); 2141 /* Callbacks Register/UnRegister functions ***********************************/ 2142 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 2143 HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback); 2144 HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID); 2145 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 2146 2147 /** 2148 * @} 2149 */ 2150 /* IO operation functions ****************************************************/ 2151 2152 /** @addtogroup ETH_Exported_Functions_Group2 2153 * @{ 2154 */ 2155 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength); 2156 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth); 2157 /* Communication with PHY functions*/ 2158 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue); 2159 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue); 2160 /* Non-Blocking mode: Interrupt */ 2161 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth); 2162 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); 2163 /* Callback in non blocking modes (Interrupt) */ 2164 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); 2165 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); 2166 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); 2167 /** 2168 * @} 2169 */ 2170 2171 /* Peripheral Control functions **********************************************/ 2172 2173 /** @addtogroup ETH_Exported_Functions_Group3 2174 * @{ 2175 */ 2176 2177 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); 2178 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); 2179 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf); 2180 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf); 2181 /** 2182 * @} 2183 */ 2184 2185 /* Peripheral State functions ************************************************/ 2186 2187 /** @addtogroup ETH_Exported_Functions_Group4 2188 * @{ 2189 */ 2190 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); 2191 /** 2192 * @} 2193 */ 2194 2195 /** 2196 * @} 2197 */ 2198 2199 /** 2200 * @} 2201 */ 2202 2203 /** 2204 * @} 2205 */ 2206 #endif /* ETH */ 2207 2208 #ifdef __cplusplus 2209 } 2210 #endif 2211 2212 #endif /* __STM32F7xx_HAL_ETH_LEGACY_H */ 2213
