1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_utils.c
4 * @author MCD Application Team
5 * @brief UTILS LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 /* Includes ------------------------------------------------------------------*/
19 #include "stm32f4xx_ll_utils.h"
20 #include "stm32f4xx_ll_rcc.h"
21 #include "stm32f4xx_ll_system.h"
22 #include "stm32f4xx_ll_pwr.h"
23 #ifdef USE_FULL_ASSERT
24 #include "stm32_assert.h"
25 #else
26 #define assert_param(expr) ((void)0U)
27 #endif /* USE_FULL_ASSERT */
28
29 /** @addtogroup STM32F4xx_LL_Driver
30 * @{
31 */
32
33 /** @addtogroup UTILS_LL
34 * @{
35 */
36
37 /* Private types -------------------------------------------------------------*/
38 /* Private variables ---------------------------------------------------------*/
39 /* Private constants ---------------------------------------------------------*/
40 /** @addtogroup UTILS_LL_Private_Constants
41 * @{
42 */
43 #if defined(RCC_MAX_FREQUENCY_SCALE1)
44 #define UTILS_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
45 #endif /*RCC_MAX_FREQUENCY_SCALE1 */
46 #define UTILS_MAX_FREQUENCY_SCALE2 RCC_MAX_FREQUENCY_SCALE2 /*!< Maximum frequency for system clock at power scale2, in Hz */
47 #if defined(RCC_MAX_FREQUENCY_SCALE3)
48 #define UTILS_MAX_FREQUENCY_SCALE3 RCC_MAX_FREQUENCY_SCALE3 /*!< Maximum frequency for system clock at power scale3, in Hz */
49 #endif /* MAX_FREQUENCY_SCALE3 */
50
51 /* Defines used for PLL range */
52 #define UTILS_PLLVCO_INPUT_MIN RCC_PLLVCO_INPUT_MIN /*!< Frequency min for PLLVCO input, in Hz */
53 #define UTILS_PLLVCO_INPUT_MAX RCC_PLLVCO_INPUT_MAX /*!< Frequency max for PLLVCO input, in Hz */
54 #define UTILS_PLLVCO_OUTPUT_MIN RCC_PLLVCO_OUTPUT_MIN /*!< Frequency min for PLLVCO output, in Hz */
55 #define UTILS_PLLVCO_OUTPUT_MAX RCC_PLLVCO_OUTPUT_MAX /*!< Frequency max for PLLVCO output, in Hz */
56
57 /* Defines used for HSE range */
58 #define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
59 #define UTILS_HSE_FREQUENCY_MAX 26000000U /*!< Frequency max for HSE frequency, in Hz */
60
61 /* Defines used for FLASH latency according to HCLK Frequency */
62 #if defined(FLASH_SCALE1_LATENCY1_FREQ)
63 #define UTILS_SCALE1_LATENCY1_FREQ FLASH_SCALE1_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
64 #endif
65 #if defined(FLASH_SCALE1_LATENCY2_FREQ)
66 #define UTILS_SCALE1_LATENCY2_FREQ FLASH_SCALE1_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
67 #endif
68 #if defined(FLASH_SCALE1_LATENCY3_FREQ)
69 #define UTILS_SCALE1_LATENCY3_FREQ FLASH_SCALE1_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
70 #endif
71 #if defined(FLASH_SCALE1_LATENCY4_FREQ)
72 #define UTILS_SCALE1_LATENCY4_FREQ FLASH_SCALE1_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
73 #endif
74 #if defined(FLASH_SCALE1_LATENCY5_FREQ)
75 #define UTILS_SCALE1_LATENCY5_FREQ FLASH_SCALE1_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
76 #endif
77 #define UTILS_SCALE2_LATENCY1_FREQ FLASH_SCALE2_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
78 #define UTILS_SCALE2_LATENCY2_FREQ FLASH_SCALE2_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
79 #if defined(FLASH_SCALE2_LATENCY3_FREQ)
80 #define UTILS_SCALE2_LATENCY3_FREQ FLASH_SCALE2_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
81 #endif
82 #if defined(FLASH_SCALE2_LATENCY4_FREQ)
83 #define UTILS_SCALE2_LATENCY4_FREQ FLASH_SCALE2_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
84 #endif
85 #if defined(FLASH_SCALE2_LATENCY5_FREQ)
86 #define UTILS_SCALE2_LATENCY5_FREQ FLASH_SCALE2_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
87 #endif
88 #if defined(FLASH_SCALE3_LATENCY1_FREQ)
89 #define UTILS_SCALE3_LATENCY1_FREQ FLASH_SCALE3_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
90 #endif
91 #if defined(FLASH_SCALE3_LATENCY2_FREQ)
92 #define UTILS_SCALE3_LATENCY2_FREQ FLASH_SCALE3_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
93 #endif
94 #if defined(FLASH_SCALE3_LATENCY3_FREQ)
95 #define UTILS_SCALE3_LATENCY3_FREQ FLASH_SCALE3_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
96 #endif
97 #if defined(FLASH_SCALE3_LATENCY4_FREQ)
98 #define UTILS_SCALE3_LATENCY4_FREQ FLASH_SCALE3_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 3 */
99 #endif
100 #if defined(FLASH_SCALE3_LATENCY5_FREQ)
101 #define UTILS_SCALE3_LATENCY5_FREQ FLASH_SCALE3_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 3 */
102 #endif
103 /**
104 * @}
105 */
106
107 /* Private macros ------------------------------------------------------------*/
108 /** @addtogroup UTILS_LL_Private_Macros
109 * @{
110 */
111 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
112 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
113 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
114 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
115 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
116 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
117 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
118 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
119 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
120
121 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
122 || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
123 || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
124 || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
125 || ((__VALUE__) == LL_RCC_APB1_DIV_16))
126
127 #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
128 || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
129 || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
130 || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
131 || ((__VALUE__) == LL_RCC_APB2_DIV_16))
132
133 #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_2) \
134 || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
135 || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
136 || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
137 || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
138 || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
139 || ((__VALUE__) == LL_RCC_PLLM_DIV_8) \
140 || ((__VALUE__) == LL_RCC_PLLM_DIV_9) \
141 || ((__VALUE__) == LL_RCC_PLLM_DIV_10) \
142 || ((__VALUE__) == LL_RCC_PLLM_DIV_11) \
143 || ((__VALUE__) == LL_RCC_PLLM_DIV_12) \
144 || ((__VALUE__) == LL_RCC_PLLM_DIV_13) \
145 || ((__VALUE__) == LL_RCC_PLLM_DIV_14) \
146 || ((__VALUE__) == LL_RCC_PLLM_DIV_15) \
147 || ((__VALUE__) == LL_RCC_PLLM_DIV_16) \
148 || ((__VALUE__) == LL_RCC_PLLM_DIV_17) \
149 || ((__VALUE__) == LL_RCC_PLLM_DIV_18) \
150 || ((__VALUE__) == LL_RCC_PLLM_DIV_19) \
151 || ((__VALUE__) == LL_RCC_PLLM_DIV_20) \
152 || ((__VALUE__) == LL_RCC_PLLM_DIV_21) \
153 || ((__VALUE__) == LL_RCC_PLLM_DIV_22) \
154 || ((__VALUE__) == LL_RCC_PLLM_DIV_23) \
155 || ((__VALUE__) == LL_RCC_PLLM_DIV_24) \
156 || ((__VALUE__) == LL_RCC_PLLM_DIV_25) \
157 || ((__VALUE__) == LL_RCC_PLLM_DIV_26) \
158 || ((__VALUE__) == LL_RCC_PLLM_DIV_27) \
159 || ((__VALUE__) == LL_RCC_PLLM_DIV_28) \
160 || ((__VALUE__) == LL_RCC_PLLM_DIV_29) \
161 || ((__VALUE__) == LL_RCC_PLLM_DIV_30) \
162 || ((__VALUE__) == LL_RCC_PLLM_DIV_31) \
163 || ((__VALUE__) == LL_RCC_PLLM_DIV_32) \
164 || ((__VALUE__) == LL_RCC_PLLM_DIV_33) \
165 || ((__VALUE__) == LL_RCC_PLLM_DIV_34) \
166 || ((__VALUE__) == LL_RCC_PLLM_DIV_35) \
167 || ((__VALUE__) == LL_RCC_PLLM_DIV_36) \
168 || ((__VALUE__) == LL_RCC_PLLM_DIV_37) \
169 || ((__VALUE__) == LL_RCC_PLLM_DIV_38) \
170 || ((__VALUE__) == LL_RCC_PLLM_DIV_39) \
171 || ((__VALUE__) == LL_RCC_PLLM_DIV_40) \
172 || ((__VALUE__) == LL_RCC_PLLM_DIV_41) \
173 || ((__VALUE__) == LL_RCC_PLLM_DIV_42) \
174 || ((__VALUE__) == LL_RCC_PLLM_DIV_43) \
175 || ((__VALUE__) == LL_RCC_PLLM_DIV_44) \
176 || ((__VALUE__) == LL_RCC_PLLM_DIV_45) \
177 || ((__VALUE__) == LL_RCC_PLLM_DIV_46) \
178 || ((__VALUE__) == LL_RCC_PLLM_DIV_47) \
179 || ((__VALUE__) == LL_RCC_PLLM_DIV_48) \
180 || ((__VALUE__) == LL_RCC_PLLM_DIV_49) \
181 || ((__VALUE__) == LL_RCC_PLLM_DIV_50) \
182 || ((__VALUE__) == LL_RCC_PLLM_DIV_51) \
183 || ((__VALUE__) == LL_RCC_PLLM_DIV_52) \
184 || ((__VALUE__) == LL_RCC_PLLM_DIV_53) \
185 || ((__VALUE__) == LL_RCC_PLLM_DIV_54) \
186 || ((__VALUE__) == LL_RCC_PLLM_DIV_55) \
187 || ((__VALUE__) == LL_RCC_PLLM_DIV_56) \
188 || ((__VALUE__) == LL_RCC_PLLM_DIV_57) \
189 || ((__VALUE__) == LL_RCC_PLLM_DIV_58) \
190 || ((__VALUE__) == LL_RCC_PLLM_DIV_59) \
191 || ((__VALUE__) == LL_RCC_PLLM_DIV_60) \
192 || ((__VALUE__) == LL_RCC_PLLM_DIV_61) \
193 || ((__VALUE__) == LL_RCC_PLLM_DIV_62) \
194 || ((__VALUE__) == LL_RCC_PLLM_DIV_63))
195
196 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((RCC_PLLN_MIN_VALUE <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLN_MAX_VALUE))
197
198 #define IS_LL_UTILS_PLLP_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLP_DIV_2) \
199 || ((__VALUE__) == LL_RCC_PLLP_DIV_4) \
200 || ((__VALUE__) == LL_RCC_PLLP_DIV_6) \
201 || ((__VALUE__) == LL_RCC_PLLP_DIV_8))
202
203 #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
204
205 #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
206
207 #if !defined(RCC_MAX_FREQUENCY_SCALE1)
208 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
209 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
210
211 #elif defined(RCC_MAX_FREQUENCY_SCALE3)
212 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
213 (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
214 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
215
216 #else
217 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
218 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2))
219
220 #endif /* RCC_MAX_FREQUENCY_SCALE1*/
221 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
222 || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
223
224 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
225 /**
226 * @}
227 */
228 /* Private function prototypes -----------------------------------------------*/
229 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
230 * @{
231 */
232 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
233 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
234 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
235 static ErrorStatus UTILS_PLL_IsBusy(void);
236 /**
237 * @}
238 */
239
240 /* Exported functions --------------------------------------------------------*/
241 /** @addtogroup UTILS_LL_Exported_Functions
242 * @{
243 */
244
245 /** @addtogroup UTILS_LL_EF_DELAY
246 * @{
247 */
248
249 /**
250 * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
251 * @note When a RTOS is used, it is recommended to avoid changing the Systick
252 * configuration by calling this function, for a delay use rather osDelay RTOS service.
253 * @param HCLKFrequency HCLK frequency in Hz
254 * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
255 * @retval None
256 */
LL_Init1msTick(uint32_t HCLKFrequency)257 void LL_Init1msTick(uint32_t HCLKFrequency)
258 {
259 /* Use frequency provided in argument */
260 LL_InitTick(HCLKFrequency, 1000U);
261 }
262
263 /**
264 * @brief This function provides accurate delay (in milliseconds) based
265 * on SysTick counter flag
266 * @note When a RTOS is used, it is recommended to avoid using blocking delay
267 * and use rather osDelay service.
268 * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
269 * will configure Systick to 1ms
270 * @param Delay specifies the delay time length, in milliseconds.
271 * @retval None
272 */
LL_mDelay(uint32_t Delay)273 void LL_mDelay(uint32_t Delay)
274 {
275 __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
276 /* Add this code to indicate that local variable is not used */
277 ((void)tmp);
278
279 /* Add a period to guaranty minimum wait */
280 if(Delay < LL_MAX_DELAY)
281 {
282 Delay++;
283 }
284
285 while (Delay)
286 {
287 if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
288 {
289 Delay--;
290 }
291 }
292 }
293
294 /**
295 * @}
296 */
297
298 /** @addtogroup UTILS_EF_SYSTEM
299 * @brief System Configuration functions
300 *
301 @verbatim
302 ===============================================================================
303 ##### System Configuration functions #####
304 ===============================================================================
305 [..]
306 System, AHB and APB buses clocks configuration
307
308 (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 180000000 Hz.
309 @endverbatim
310 @internal
311 Depending on the device voltage range, the maximum frequency should be
312 adapted accordingly to the Refenece manual.
313 @endinternal
314 * @{
315 */
316
317 /**
318 * @brief This function sets directly SystemCoreClock CMSIS variable.
319 * @note Variable can be calculated also through SystemCoreClockUpdate function.
320 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
321 * @retval None
322 */
LL_SetSystemCoreClock(uint32_t HCLKFrequency)323 void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
324 {
325 /* HCLK clock frequency */
326 SystemCoreClock = HCLKFrequency;
327 }
328
329 /**
330 * @brief Update number of Flash wait states in line with new frequency and current
331 voltage range.
332 * @note This Function support ONLY devices with supply voltage (voltage range) between 2.7V and 3.6V
333 * @param HCLK_Frequency HCLK frequency
334 * @retval An ErrorStatus enumeration value:
335 * - SUCCESS: Latency has been modified
336 * - ERROR: Latency cannot be modified
337 */
LL_SetFlashLatency(uint32_t HCLK_Frequency)338 ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency)
339 {
340 uint32_t timeout;
341 uint32_t getlatency;
342 uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
343 ErrorStatus status = SUCCESS;
344
345
346 /* Frequency cannot be equal to 0 */
347 if(HCLK_Frequency == 0U)
348 {
349 status = ERROR;
350 }
351 else
352 {
353 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
354 {
355 #if defined (UTILS_SCALE1_LATENCY5_FREQ)
356 if((HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0))
357 {
358 latency = LL_FLASH_LATENCY_5;
359 }
360 #endif /*UTILS_SCALE1_LATENCY5_FREQ */
361 #if defined (UTILS_SCALE1_LATENCY4_FREQ)
362 if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0))
363 {
364 latency = LL_FLASH_LATENCY_4;
365 }
366 #endif /* UTILS_SCALE1_LATENCY4_FREQ */
367 #if defined (UTILS_SCALE1_LATENCY3_FREQ)
368 if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
369 {
370 latency = LL_FLASH_LATENCY_3;
371 }
372 #endif /* UTILS_SCALE1_LATENCY3_FREQ */
373 #if defined (UTILS_SCALE1_LATENCY2_FREQ)
374 if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
375 {
376 latency = LL_FLASH_LATENCY_2;
377 }
378 else
379 {
380 if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
381 {
382 latency = LL_FLASH_LATENCY_1;
383 }
384 }
385 #endif /* UTILS_SCALE1_LATENCY2_FREQ */
386 }
387 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
388 {
389 #if defined (UTILS_SCALE2_LATENCY5_FREQ)
390 if((HCLK_Frequency > UTILS_SCALE2_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0))
391 {
392 latency = LL_FLASH_LATENCY_5;
393 }
394 #endif /*UTILS_SCALE1_LATENCY5_FREQ */
395 #if defined (UTILS_SCALE2_LATENCY4_FREQ)
396 if((HCLK_Frequency > UTILS_SCALE2_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0))
397 {
398 latency = LL_FLASH_LATENCY_4;
399 }
400 #endif /*UTILS_SCALE1_LATENCY4_FREQ */
401 #if defined (UTILS_SCALE2_LATENCY3_FREQ)
402 if((HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
403 {
404 latency = LL_FLASH_LATENCY_3;
405 }
406 #endif /*UTILS_SCALE1_LATENCY3_FREQ */
407 if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
408 {
409 latency = LL_FLASH_LATENCY_2;
410 }
411 else
412 {
413 if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
414 {
415 latency = LL_FLASH_LATENCY_1;
416 }
417 }
418 }
419 #if defined (LL_PWR_REGU_VOLTAGE_SCALE3)
420 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE3)
421 {
422 #if defined (UTILS_SCALE3_LATENCY3_FREQ)
423 if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
424 {
425 latency = LL_FLASH_LATENCY_3;
426 }
427 #endif /*UTILS_SCALE1_LATENCY3_FREQ */
428 #if defined (UTILS_SCALE3_LATENCY2_FREQ)
429 if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
430 {
431 latency = LL_FLASH_LATENCY_2;
432 }
433 else
434 {
435 if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
436 {
437 latency = LL_FLASH_LATENCY_1;
438 }
439 }
440 }
441 #endif /*UTILS_SCALE1_LATENCY2_FREQ */
442 #endif /* LL_PWR_REGU_VOLTAGE_SCALE3 */
443
444 LL_FLASH_SetLatency(latency);
445 /* Check that the new number of wait states is taken into account to access the Flash
446 memory by reading the FLASH_ACR register */
447 timeout = 2;
448 do
449 {
450 /* Wait for Flash latency to be updated */
451 getlatency = LL_FLASH_GetLatency();
452 timeout--;
453 } while ((getlatency != latency) && (timeout > 0));
454
455 if(getlatency != latency)
456 {
457 status = ERROR;
458 }
459 else
460 {
461 status = SUCCESS;
462 }
463 }
464 return status;
465 }
466
467 /**
468 * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL
469 * @note The application need to ensure that PLL is disabled.
470 * @note Function is based on the following formula:
471 * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
472 * - PLLM: ensure that the VCO input frequency ranges from @ref RCC_PLLVCO_INPUT_MIN to @ref RCC_PLLVCO_INPUT_MAX (PLLVCO_input = HSI frequency / PLLM)
473 * - PLLN: ensure that the VCO output frequency is between @ref RCC_PLLVCO_OUTPUT_MIN and @ref RCC_PLLVCO_OUTPUT_MAX (PLLVCO_output = PLLVCO_input * PLLN)
474 * - PLLP: ensure that max frequency at 180000000 Hz is reach (PLLVCO_output / PLLP)
475 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
476 * the configuration information for the PLL.
477 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
478 * the configuration information for the BUS prescalers.
479 * @retval An ErrorStatus enumeration value:
480 * - SUCCESS: Max frequency configuration done
481 * - ERROR: Max frequency configuration not done
482 */
LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct,LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct)483 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
484 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
485 {
486 ErrorStatus status = SUCCESS;
487 uint32_t pllfreq = 0U;
488
489 /* Check if one of the PLL is enabled */
490 if(UTILS_PLL_IsBusy() == SUCCESS)
491 {
492 /* Calculate the new PLL output frequency */
493 pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
494
495 /* Enable HSI if not enabled */
496 if(LL_RCC_HSI_IsReady() != 1U)
497 {
498 LL_RCC_HSI_Enable();
499 while (LL_RCC_HSI_IsReady() != 1U)
500 {
501 /* Wait for HSI ready */
502 }
503 }
504
505 /* Configure PLL */
506 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
507 UTILS_PLLInitStruct->PLLP);
508
509 /* Enable PLL and switch system clock to PLL */
510 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
511 }
512 else
513 {
514 /* Current PLL configuration cannot be modified */
515 status = ERROR;
516 }
517
518 return status;
519 }
520
521 /**
522 * @brief This function configures system clock with HSE as clock source of the PLL
523 * @note The application need to ensure that PLL is disabled.
524 * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
525 * - PLLM: ensure that the VCO input frequency ranges from @ref RCC_PLLVCO_INPUT_MIN to @ref RCC_PLLVCO_INPUT_MAX (PLLVCO_input = HSI frequency / PLLM)
526 * - PLLN: ensure that the VCO output frequency is between @ref RCC_PLLVCO_OUTPUT_MIN and @ref RCC_PLLVCO_OUTPUT_MAX (PLLVCO_output = PLLVCO_input * PLLN)
527 * - PLLP: ensure that max frequency at 180000000 Hz is reach (PLLVCO_output / PLLP)
528 * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 26000000
529 * @param HSEBypass This parameter can be one of the following values:
530 * @arg @ref LL_UTILS_HSEBYPASS_ON
531 * @arg @ref LL_UTILS_HSEBYPASS_OFF
532 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
533 * the configuration information for the PLL.
534 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
535 * the configuration information for the BUS prescalers.
536 * @retval An ErrorStatus enumeration value:
537 * - SUCCESS: Max frequency configuration done
538 * - ERROR: Max frequency configuration not done
539 */
LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency,uint32_t HSEBypass,LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct,LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct)540 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
541 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
542 {
543 ErrorStatus status = SUCCESS;
544 uint32_t pllfreq = 0U;
545
546 /* Check the parameters */
547 assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
548 assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
549
550 /* Check if one of the PLL is enabled */
551 if(UTILS_PLL_IsBusy() == SUCCESS)
552 {
553 /* Calculate the new PLL output frequency */
554 pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
555
556 /* Enable HSE if not enabled */
557 if(LL_RCC_HSE_IsReady() != 1U)
558 {
559 /* Check if need to enable HSE bypass feature or not */
560 if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
561 {
562 LL_RCC_HSE_EnableBypass();
563 }
564 else
565 {
566 LL_RCC_HSE_DisableBypass();
567 }
568
569 /* Enable HSE */
570 LL_RCC_HSE_Enable();
571 while (LL_RCC_HSE_IsReady() != 1U)
572 {
573 /* Wait for HSE ready */
574 }
575 }
576
577 /* Configure PLL */
578 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
579 UTILS_PLLInitStruct->PLLP);
580
581 /* Enable PLL and switch system clock to PLL */
582 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
583 }
584 else
585 {
586 /* Current PLL configuration cannot be modified */
587 status = ERROR;
588 }
589
590 return status;
591 }
592
593 /**
594 * @}
595 */
596
597 /**
598 * @}
599 */
600
601 /** @addtogroup UTILS_LL_Private_Functions
602 * @{
603 */
604 /**
605 * @brief Function to check that PLL can be modified
606 * @param PLL_InputFrequency PLL input frequency (in Hz)
607 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
608 * the configuration information for the PLL.
609 * @retval PLL output frequency (in Hz)
610 */
UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct)611 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
612 {
613 uint32_t pllfreq = 0U;
614
615 /* Check the parameters */
616 assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
617 assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
618 assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
619
620 /* Check different PLL parameters according to RM */
621 /* - PLLM: ensure that the VCO input frequency ranges from @ref UTILS_PLLVCO_INPUT_MIN to @ref UTILS_PLLVCO_INPUT_MAX MHz. */
622 pllfreq = PLL_InputFrequency / (UTILS_PLLInitStruct->PLLM & (RCC_PLLCFGR_PLLM >> RCC_PLLCFGR_PLLM_Pos));
623 assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
624
625 /* - PLLN: ensure that the VCO output frequency is between @ref UTILS_PLLVCO_OUTPUT_MIN and @ref UTILS_PLLVCO_OUTPUT_MAX .*/
626 pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
627 assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
628
629 /* - PLLP: ensure that max frequency at @ref RCC_MAX_FREQUENCY Hz is reached */
630 pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLP >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
631 assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
632
633 return pllfreq;
634 }
635
636 /**
637 * @brief Function to check that PLL can be modified
638 * @retval An ErrorStatus enumeration value:
639 * - SUCCESS: PLL modification can be done
640 * - ERROR: PLL is busy
641 */
UTILS_PLL_IsBusy(void)642 static ErrorStatus UTILS_PLL_IsBusy(void)
643 {
644 ErrorStatus status = SUCCESS;
645
646 /* Check if PLL is busy*/
647 if(LL_RCC_PLL_IsReady() != 0U)
648 {
649 /* PLL configuration cannot be modified */
650 status = ERROR;
651 }
652
653 #if defined(RCC_PLLSAI_SUPPORT)
654 /* Check if PLLSAI is busy*/
655 if(LL_RCC_PLLSAI_IsReady() != 0U)
656 {
657 /* PLLSAI1 configuration cannot be modified */
658 status = ERROR;
659 }
660 #endif /*RCC_PLLSAI_SUPPORT*/
661 #if defined(RCC_PLLI2S_SUPPORT)
662 /* Check if PLLI2S is busy*/
663 if(LL_RCC_PLLI2S_IsReady() != 0U)
664 {
665 /* PLLI2S configuration cannot be modified */
666 status = ERROR;
667 }
668 #endif /*RCC_PLLI2S_SUPPORT*/
669 return status;
670 }
671
672 /**
673 * @brief Function to enable PLL and switch system clock to PLL
674 * @param SYSCLK_Frequency SYSCLK frequency
675 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
676 * the configuration information for the BUS prescalers.
677 * @retval An ErrorStatus enumeration value:
678 * - SUCCESS: No problem to switch system to PLL
679 * - ERROR: Problem to switch system to PLL
680 */
UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency,LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct)681 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
682 {
683 ErrorStatus status = SUCCESS;
684 uint32_t hclk_frequency = 0U;
685
686 assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
687 assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
688 assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
689
690 /* Calculate HCLK frequency */
691 hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
692
693 /* Increasing the number of wait states because of higher CPU frequency */
694 if(SystemCoreClock < hclk_frequency)
695 {
696 /* Set FLASH latency to highest latency */
697 status = LL_SetFlashLatency(hclk_frequency);
698 }
699
700 /* Update system clock configuration */
701 if(status == SUCCESS)
702 {
703 /* Enable PLL */
704 LL_RCC_PLL_Enable();
705 while (LL_RCC_PLL_IsReady() != 1U)
706 {
707 /* Wait for PLL ready */
708 }
709
710 /* Sysclk activation on the main PLL */
711 LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
712 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
713 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
714 {
715 /* Wait for system clock switch to PLL */
716 }
717
718 /* Set APB1 & APB2 prescaler*/
719 LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
720 LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
721 }
722
723 /* Decreasing the number of wait states because of lower CPU frequency */
724 if(SystemCoreClock > hclk_frequency)
725 {
726 /* Set FLASH latency to lowest latency */
727 status = LL_SetFlashLatency(hclk_frequency);
728 }
729
730 /* Update SystemCoreClock variable */
731 if(status == SUCCESS)
732 {
733 LL_SetSystemCoreClock(hclk_frequency);
734 }
735
736 return status;
737 }
738
739 /**
740 * @}
741 */
742
743 /**
744 * @}
745 */
746
747 /**
748 * @}
749 */
750
