1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_spi.c
4 * @author MCD Application Team
5 * @brief SPI LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32f4xx_ll_spi.h"
22 #include "stm32f4xx_ll_bus.h"
23 #include "stm32f4xx_ll_rcc.h"
24
25 #ifdef USE_FULL_ASSERT
26 #include "stm32_assert.h"
27 #else
28 #define assert_param(expr) ((void)0U)
29 #endif /* USE_FULL_ASSERT */
30
31 /** @addtogroup STM32F4xx_LL_Driver
32 * @{
33 */
34
35 #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6)
36
37 /** @addtogroup SPI_LL
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup SPI_LL_Private_Constants SPI Private Constants
46 * @{
47 */
48 /* SPI registers Masks */
49 #define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
50 SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
51 SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_DFF | \
52 SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
53 SPI_CR1_BIDIMODE)
54 /**
55 * @}
56 */
57
58 /* Private macros ------------------------------------------------------------*/
59 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
60 * @{
61 */
62 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
63 || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
64 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
65 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
66
67 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
68 || ((__VALUE__) == LL_SPI_MODE_SLAVE))
69
70 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
71 || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
72
73 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
74 || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
75
76 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
77 || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
78
79 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
80 || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
81 || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
82
83 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
84 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
85 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
86 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
87 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
88 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
89 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
90 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
91
92 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
93 || ((__VALUE__) == LL_SPI_MSB_FIRST))
94
95 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
96 || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
97
98 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
99
100 /**
101 * @}
102 */
103
104 /* Private function prototypes -----------------------------------------------*/
105
106 /* Exported functions --------------------------------------------------------*/
107 /** @addtogroup SPI_LL_Exported_Functions
108 * @{
109 */
110
111 /** @addtogroup SPI_LL_EF_Init
112 * @{
113 */
114
115 /**
116 * @brief De-initialize the SPI registers to their default reset values.
117 * @param SPIx SPI Instance
118 * @retval An ErrorStatus enumeration value:
119 * - SUCCESS: SPI registers are de-initialized
120 * - ERROR: SPI registers are not de-initialized
121 */
LL_SPI_DeInit(SPI_TypeDef * SPIx)122 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
123 {
124 ErrorStatus status = ERROR;
125
126 /* Check the parameters */
127 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
128
129 #if defined(SPI1)
130 if (SPIx == SPI1)
131 {
132 /* Force reset of SPI clock */
133 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
134
135 /* Release reset of SPI clock */
136 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
137
138 status = SUCCESS;
139 }
140 #endif /* SPI1 */
141 #if defined(SPI2)
142 if (SPIx == SPI2)
143 {
144 /* Force reset of SPI clock */
145 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
146
147 /* Release reset of SPI clock */
148 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
149
150 status = SUCCESS;
151 }
152 #endif /* SPI2 */
153 #if defined(SPI3)
154 if (SPIx == SPI3)
155 {
156 /* Force reset of SPI clock */
157 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
158
159 /* Release reset of SPI clock */
160 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
161
162 status = SUCCESS;
163 }
164 #endif /* SPI3 */
165 #if defined(SPI4)
166 if (SPIx == SPI4)
167 {
168 /* Force reset of SPI clock */
169 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
170
171 /* Release reset of SPI clock */
172 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
173
174 status = SUCCESS;
175 }
176 #endif /* SPI4 */
177 #if defined(SPI5)
178 if (SPIx == SPI5)
179 {
180 /* Force reset of SPI clock */
181 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5);
182
183 /* Release reset of SPI clock */
184 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5);
185
186 status = SUCCESS;
187 }
188 #endif /* SPI5 */
189 #if defined(SPI6)
190 if (SPIx == SPI6)
191 {
192 /* Force reset of SPI clock */
193 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI6);
194
195 /* Release reset of SPI clock */
196 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI6);
197
198 status = SUCCESS;
199 }
200 #endif /* SPI6 */
201
202 return status;
203 }
204
205 /**
206 * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
207 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
208 * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
209 * @param SPIx SPI Instance
210 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
211 * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
212 */
LL_SPI_Init(SPI_TypeDef * SPIx,LL_SPI_InitTypeDef * SPI_InitStruct)213 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
214 {
215 ErrorStatus status = ERROR;
216
217 /* Check the SPI Instance SPIx*/
218 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
219
220 /* Check the SPI parameters from SPI_InitStruct*/
221 assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
222 assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
223 assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
224 assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
225 assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
226 assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
227 assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
228 assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
229 assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
230
231 if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
232 {
233 /*---------------------------- SPIx CR1 Configuration ------------------------
234 * Configure SPIx CR1 with parameters:
235 * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
236 * - Master/Slave Mode: SPI_CR1_MSTR bit
237 * - DataWidth: SPI_CR1_DFF bit
238 * - ClockPolarity: SPI_CR1_CPOL bit
239 * - ClockPhase: SPI_CR1_CPHA bit
240 * - NSS management: SPI_CR1_SSM bit
241 * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
242 * - BitOrder: SPI_CR1_LSBFIRST bit
243 * - CRCCalculation: SPI_CR1_CRCEN bit
244 */
245 MODIFY_REG(SPIx->CR1,
246 SPI_CR1_CLEAR_MASK,
247 SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode | SPI_InitStruct->DataWidth |
248 SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
249 SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
250 SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
251
252 /*---------------------------- SPIx CR2 Configuration ------------------------
253 * Configure SPIx CR2 with parameters:
254 * - NSS management: SSOE bit
255 */
256 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, (SPI_InitStruct->NSS >> 16U));
257
258 /*---------------------------- SPIx CRCPR Configuration ----------------------
259 * Configure SPIx CRCPR with parameters:
260 * - CRCPoly: CRCPOLY[15:0] bits
261 */
262 if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
263 {
264 assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
265 LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
266 }
267 status = SUCCESS;
268 }
269
270 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
271 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
272 return status;
273 }
274
275 /**
276 * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
277 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
278 * whose fields will be set to default values.
279 * @retval None
280 */
LL_SPI_StructInit(LL_SPI_InitTypeDef * SPI_InitStruct)281 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
282 {
283 /* Set SPI_InitStruct fields to default values */
284 SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
285 SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
286 SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
287 SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
288 SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
289 SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
290 SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
291 SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
292 SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
293 SPI_InitStruct->CRCPoly = 7U;
294 }
295
296 /**
297 * @}
298 */
299
300 /**
301 * @}
302 */
303
304 /**
305 * @}
306 */
307
308 /** @addtogroup I2S_LL
309 * @{
310 */
311
312 /* Private types -------------------------------------------------------------*/
313 /* Private variables ---------------------------------------------------------*/
314 /* Private constants ---------------------------------------------------------*/
315 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
316 * @{
317 */
318 /* I2S registers Masks */
319 #define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
320 SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
321 SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
322
323 #define I2S_I2SPR_CLEAR_MASK 0x0002U
324 /**
325 * @}
326 */
327 /* Private macros ------------------------------------------------------------*/
328 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
329 * @{
330 */
331
332 #define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
333 || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
334 || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
335 || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
336
337 #define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
338 || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
339
340 #define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
341 || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
342 || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
343 || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
344 || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
345
346 #define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
347 || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
348 || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
349 || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
350
351 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
352 || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
353
354 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
355 && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
356 || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
357
358 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
359
360 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
361 || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
362 /**
363 * @}
364 */
365
366 /* Private function prototypes -----------------------------------------------*/
367
368 /* Exported functions --------------------------------------------------------*/
369 /** @addtogroup I2S_LL_Exported_Functions
370 * @{
371 */
372
373 /** @addtogroup I2S_LL_EF_Init
374 * @{
375 */
376
377 /**
378 * @brief De-initialize the SPI/I2S registers to their default reset values.
379 * @param SPIx SPI Instance
380 * @retval An ErrorStatus enumeration value:
381 * - SUCCESS: SPI registers are de-initialized
382 * - ERROR: SPI registers are not de-initialized
383 */
LL_I2S_DeInit(SPI_TypeDef * SPIx)384 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
385 {
386 return LL_SPI_DeInit(SPIx);
387 }
388
389 /**
390 * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
391 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
392 * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
393 * @param SPIx SPI Instance
394 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
395 * @retval An ErrorStatus enumeration value:
396 * - SUCCESS: SPI registers are Initialized
397 * - ERROR: SPI registers are not Initialized
398 */
LL_I2S_Init(SPI_TypeDef * SPIx,LL_I2S_InitTypeDef * I2S_InitStruct)399 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
400 {
401 uint32_t i2sdiv = 2U;
402 uint32_t i2sodd = 0U;
403 uint32_t packetlength = 1U;
404 uint32_t tmp;
405 uint32_t sourceclock;
406 ErrorStatus status = ERROR;
407
408 /* Check the I2S parameters */
409 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
410 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
411 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
412 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
413 assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
414 assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
415 assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
416
417 if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
418 {
419 /*---------------------------- SPIx I2SCFGR Configuration --------------------
420 * Configure SPIx I2SCFGR with parameters:
421 * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
422 * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
423 * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
424 * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
425 */
426
427 /* Write to SPIx I2SCFGR */
428 MODIFY_REG(SPIx->I2SCFGR,
429 I2S_I2SCFGR_CLEAR_MASK,
430 I2S_InitStruct->Mode | I2S_InitStruct->Standard |
431 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
432 SPI_I2SCFGR_I2SMOD);
433
434 /*---------------------------- SPIx I2SPR Configuration ----------------------
435 * Configure SPIx I2SPR with parameters:
436 * - MCLKOutput: SPI_I2SPR_MCKOE bit
437 * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
438 */
439
440 /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
441 * else, default values are used: i2sodd = 0U, i2sdiv = 2U.
442 */
443 if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
444 {
445 /* Check the frame length (For the Prescaler computing)
446 * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
447 */
448 if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
449 {
450 /* Packet length is 32 bits */
451 packetlength = 2U;
452 }
453
454 /* If an external I2S clock has to be used, the specific define should be set
455 in the project configuration or in the stm32f4xx_ll_rcc.h file */
456 /* Get the I2S source clock value */
457 sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
458
459 /* Compute the Real divider depending on the MCLK output state with a floating point */
460 if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
461 {
462 /* MCLK output is enabled */
463 tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
464 }
465 else
466 {
467 /* MCLK output is disabled */
468 tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
469 }
470
471 /* Remove the floating point */
472 tmp = tmp / 10U;
473
474 /* Check the parity of the divider */
475 i2sodd = (tmp & (uint16_t)0x0001U);
476
477 /* Compute the i2sdiv prescaler */
478 i2sdiv = ((tmp - i2sodd) / 2U);
479
480 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
481 i2sodd = (i2sodd << 8U);
482 }
483
484 /* Test if the divider is 1 or 0 or greater than 0xFF */
485 if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
486 {
487 /* Set the default values */
488 i2sdiv = 2U;
489 i2sodd = 0U;
490 }
491
492 /* Write to SPIx I2SPR register the computed value */
493 WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
494
495 status = SUCCESS;
496 }
497 return status;
498 }
499
500 /**
501 * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
502 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
503 * whose fields will be set to default values.
504 * @retval None
505 */
LL_I2S_StructInit(LL_I2S_InitTypeDef * I2S_InitStruct)506 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
507 {
508 /*--------------- Reset I2S init structure parameters values -----------------*/
509 I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
510 I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
511 I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
512 I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
513 I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
514 I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
515 }
516
517 /**
518 * @brief Set linear and parity prescaler.
519 * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
520 * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
521 * @param SPIx SPI Instance
522 * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
523 * @param PrescalerParity This parameter can be one of the following values:
524 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
525 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
526 * @retval None
527 */
LL_I2S_ConfigPrescaler(SPI_TypeDef * SPIx,uint32_t PrescalerLinear,uint32_t PrescalerParity)528 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
529 {
530 /* Check the I2S parameters */
531 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
532 assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
533 assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
534
535 /* Write to SPIx I2SPR */
536 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
537 }
538
539 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
540 /**
541 * @brief Configures the full duplex mode for the I2Sx peripheral using its extension
542 * I2Sxext according to the specified parameters in the I2S_InitStruct.
543 * @note The structure pointed by I2S_InitStruct parameter should be the same
544 * used for the master I2S peripheral. In this case, if the master is
545 * configured as transmitter, the slave will be receiver and vice versa.
546 * Or you can force a different mode by modifying the field I2S_Mode to the
547 * value I2S_SlaveRx or I2S_SlaveTx independently of the master configuration.
548 * @param I2Sxext SPI Instance
549 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
550 * @retval An ErrorStatus enumeration value:
551 * - SUCCESS: I2Sxext registers are Initialized
552 * - ERROR: I2Sxext registers are not Initialized
553 */
LL_I2S_InitFullDuplex(SPI_TypeDef * I2Sxext,LL_I2S_InitTypeDef * I2S_InitStruct)554 ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_InitStruct)
555 {
556 uint32_t mode = 0U;
557 ErrorStatus status = ERROR;
558
559 /* Check the I2S parameters */
560 assert_param(IS_I2S_EXT_ALL_INSTANCE(I2Sxext));
561 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
562 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
563 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
564 assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
565
566 if (LL_I2S_IsEnabled(I2Sxext) == 0x00000000U)
567 {
568 /*---------------------------- SPIx I2SCFGR Configuration --------------------
569 * Configure SPIx I2SCFGR with parameters:
570 * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
571 * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
572 * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
573 * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
574 */
575
576 /* Reset I2SPR registers */
577 WRITE_REG(I2Sxext->I2SPR, I2S_I2SPR_CLEAR_MASK);
578
579 /* Get the mode to be configured for the extended I2S */
580 if ((I2S_InitStruct->Mode == LL_I2S_MODE_MASTER_TX) || (I2S_InitStruct->Mode == LL_I2S_MODE_SLAVE_TX))
581 {
582 mode = LL_I2S_MODE_SLAVE_RX;
583 }
584 else
585 {
586 if ((I2S_InitStruct->Mode == LL_I2S_MODE_MASTER_RX) || (I2S_InitStruct->Mode == LL_I2S_MODE_SLAVE_RX))
587 {
588 mode = LL_I2S_MODE_SLAVE_TX;
589 }
590 }
591
592 /* Write to SPIx I2SCFGR */
593 MODIFY_REG(I2Sxext->I2SCFGR,
594 I2S_I2SCFGR_CLEAR_MASK,
595 I2S_InitStruct->Standard |
596 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
597 SPI_I2SCFGR_I2SMOD | mode);
598
599 status = SUCCESS;
600 }
601 return status;
602 }
603 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
604
605 /**
606 * @}
607 */
608
609 /**
610 * @}
611 */
612
613 /**
614 * @}
615 */
616
617 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) */
618
619 /**
620 * @}
621 */
622
623 #endif /* USE_FULL_LL_DRIVER */
624
625
