1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_sdram.c
4 * @author MCD Application Team
5 * @brief SDRAM HAL module driver.
6 * This file provides a generic firmware to drive SDRAM memories mounted
7 * as external device.
8 *
9 ******************************************************************************
10 * @attention
11 *
12 * Copyright (c) 2016 STMicroelectronics.
13 * All rights reserved.
14 *
15 * This software is licensed under terms that can be found in the LICENSE file
16 * in the root directory of this software component.
17 * If no LICENSE file comes with this software, it is provided AS-IS.
18 *
19 ******************************************************************************
20 @verbatim
21 ==============================================================================
22 ##### How to use this driver #####
23 ==============================================================================
24 [..]
25 This driver is a generic layered driver which contains a set of APIs used to
26 control SDRAM memories. It uses the FMC layer functions to interface
27 with SDRAM devices.
28 The following sequence should be followed to configure the FMC to interface
29 with SDRAM memories:
30
31 (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
32 SDRAM_HandleTypeDef hsdram
33
34 (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
35 values of the structure member.
36
37 (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
38 base register instance for NOR or SDRAM device
39
40 (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
41 FMC_SDRAM_TimingTypeDef Timing;
42 and fill its fields with the allowed values of the structure member.
43
44 (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
45 performs the following sequence:
46
47 (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
48 (##) Control register configuration using the FMC SDRAM interface function
49 FMC_SDRAM_Init()
50 (##) Timing register configuration using the FMC SDRAM interface function
51 FMC_SDRAM_Timing_Init()
52 (##) Program the SDRAM external device by applying its initialization sequence
53 according to the device plugged in your hardware. This step is mandatory
54 for accessing the SDRAM device.
55
56 (#) At this stage you can perform read/write accesses from/to the memory connected
57 to the SDRAM Bank. You can perform either polling or DMA transfer using the
58 following APIs:
59 (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
60 (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
61
62 (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
63 HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
64 the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
65 device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
66 structure.
67
68 (#) You can continuously monitor the SDRAM device HAL state by calling the function
69 HAL_SDRAM_GetState()
70
71 *** Callback registration ***
72 =============================================
73 [..]
74 The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS when set to 1
75 allows the user to configure dynamically the driver callbacks.
76
77 Use Functions HAL_SDRAM_RegisterCallback() to register a user callback,
78 it allows to register following callbacks:
79 (+) MspInitCallback : SDRAM MspInit.
80 (+) MspDeInitCallback : SDRAM MspDeInit.
81 This function takes as parameters the HAL peripheral handle, the Callback ID
82 and a pointer to the user callback function.
83
84 Use function HAL_SDRAM_UnRegisterCallback() to reset a callback to the default
85 weak (surcharged) function. It allows to reset following callbacks:
86 (+) MspInitCallback : SDRAM MspInit.
87 (+) MspDeInitCallback : SDRAM MspDeInit.
88 This function) takes as parameters the HAL peripheral handle and the Callback ID.
89
90 By default, after the HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET
91 all callbacks are reset to the corresponding legacy weak (surcharged) functions.
92 Exception done for MspInit and MspDeInit callbacks that are respectively
93 reset to the legacy weak (surcharged) functions in the HAL_SDRAM_Init
94 and HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand).
95 If not, MspInit or MspDeInit are not null, the HAL_SDRAM_Init and HAL_SDRAM_DeInit
96 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
97
98 Callbacks can be registered/unregistered in READY state only.
99 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
100 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
101 during the Init/DeInit.
102 In that case first register the MspInit/MspDeInit user callbacks
103 using HAL_SDRAM_RegisterCallback before calling HAL_SDRAM_DeInit
104 or HAL_SDRAM_Init function.
105
106 When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or
107 not defined, the callback registering feature is not available
108 and weak (surcharged) callbacks are used.
109
110 @endverbatim
111 ******************************************************************************
112 */
113
114 /* Includes ------------------------------------------------------------------*/
115 #include "stm32f4xx_hal.h"
116
117 #if defined(FMC_Bank5_6)
118
119 /** @addtogroup STM32F4xx_HAL_Driver
120 * @{
121 */
122
123 #ifdef HAL_SDRAM_MODULE_ENABLED
124
125 /** @defgroup SDRAM SDRAM
126 * @brief SDRAM driver modules
127 * @{
128 */
129
130 /* Private typedef -----------------------------------------------------------*/
131 /* Private define ------------------------------------------------------------*/
132 /* Private macro -------------------------------------------------------------*/
133 /* Private variables ---------------------------------------------------------*/
134 /* Private function prototypes -----------------------------------------------*/
135 static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma);
136 static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
137 static void SDRAM_DMAError(DMA_HandleTypeDef *hdma);
138
139 /* Exported functions --------------------------------------------------------*/
140 /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
141 * @{
142 */
143
144 /** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions
145 * @brief Initialization and Configuration functions
146 *
147 @verbatim
148 ==============================================================================
149 ##### SDRAM Initialization and de_initialization functions #####
150 ==============================================================================
151 [..]
152 This section provides functions allowing to initialize/de-initialize
153 the SDRAM memory
154
155 @endverbatim
156 * @{
157 */
158
159 /**
160 * @brief Performs the SDRAM device initialization sequence.
161 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
162 * the configuration information for SDRAM module.
163 * @param Timing Pointer to SDRAM control timing structure
164 * @retval HAL status
165 */
HAL_SDRAM_Init(SDRAM_HandleTypeDef * hsdram,FMC_SDRAM_TimingTypeDef * Timing)166 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
167 {
168 /* Check the SDRAM handle parameter */
169 if (hsdram == NULL)
170 {
171 return HAL_ERROR;
172 }
173
174 if (hsdram->State == HAL_SDRAM_STATE_RESET)
175 {
176 /* Allocate lock resource and initialize it */
177 hsdram->Lock = HAL_UNLOCKED;
178 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
179 if (hsdram->MspInitCallback == NULL)
180 {
181 hsdram->MspInitCallback = HAL_SDRAM_MspInit;
182 }
183 hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
184 hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
185 hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
186
187 /* Init the low level hardware */
188 hsdram->MspInitCallback(hsdram);
189 #else
190 /* Initialize the low level hardware (MSP) */
191 HAL_SDRAM_MspInit(hsdram);
192 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
193 }
194
195 /* Initialize the SDRAM controller state */
196 hsdram->State = HAL_SDRAM_STATE_BUSY;
197
198 /* Initialize SDRAM control Interface */
199 (void)FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
200
201 /* Initialize SDRAM timing Interface */
202 (void)FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
203 /* Update the SDRAM controller state */
204 hsdram->State = HAL_SDRAM_STATE_READY;
205
206 return HAL_OK;
207 }
208
209 /**
210 * @brief Perform the SDRAM device initialization sequence.
211 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
212 * the configuration information for SDRAM module.
213 * @retval HAL status
214 */
HAL_SDRAM_DeInit(SDRAM_HandleTypeDef * hsdram)215 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
216 {
217 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
218 if (hsdram->MspDeInitCallback == NULL)
219 {
220 hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
221 }
222
223 /* DeInit the low level hardware */
224 hsdram->MspDeInitCallback(hsdram);
225 #else
226 /* Initialize the low level hardware (MSP) */
227 HAL_SDRAM_MspDeInit(hsdram);
228 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
229
230 /* Configure the SDRAM registers with their reset values */
231 (void)FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
232
233 /* Reset the SDRAM controller state */
234 hsdram->State = HAL_SDRAM_STATE_RESET;
235
236 /* Release Lock */
237 __HAL_UNLOCK(hsdram);
238
239 return HAL_OK;
240 }
241
242 /**
243 * @brief SDRAM MSP Init.
244 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
245 * the configuration information for SDRAM module.
246 * @retval None
247 */
HAL_SDRAM_MspInit(SDRAM_HandleTypeDef * hsdram)248 __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
249 {
250 /* Prevent unused argument(s) compilation warning */
251 UNUSED(hsdram);
252
253 /* NOTE: This function Should not be modified, when the callback is needed,
254 the HAL_SDRAM_MspInit could be implemented in the user file
255 */
256 }
257
258 /**
259 * @brief SDRAM MSP DeInit.
260 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
261 * the configuration information for SDRAM module.
262 * @retval None
263 */
HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef * hsdram)264 __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
265 {
266 /* Prevent unused argument(s) compilation warning */
267 UNUSED(hsdram);
268
269 /* NOTE: This function Should not be modified, when the callback is needed,
270 the HAL_SDRAM_MspDeInit could be implemented in the user file
271 */
272 }
273
274 /**
275 * @brief This function handles SDRAM refresh error interrupt request.
276 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
277 * the configuration information for SDRAM module.
278 * @retval HAL status
279 */
HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef * hsdram)280 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
281 {
282 /* Check SDRAM interrupt Rising edge flag */
283 if (__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
284 {
285 /* SDRAM refresh error interrupt callback */
286 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
287 hsdram->RefreshErrorCallback(hsdram);
288 #else
289 HAL_SDRAM_RefreshErrorCallback(hsdram);
290 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
291
292 /* Clear SDRAM refresh error interrupt pending bit */
293 __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
294 }
295 }
296
297 /**
298 * @brief SDRAM Refresh error callback.
299 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
300 * the configuration information for SDRAM module.
301 * @retval None
302 */
HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef * hsdram)303 __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
304 {
305 /* Prevent unused argument(s) compilation warning */
306 UNUSED(hsdram);
307
308 /* NOTE: This function Should not be modified, when the callback is needed,
309 the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
310 */
311 }
312
313 /**
314 * @brief DMA transfer complete callback.
315 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
316 * the configuration information for the specified DMA module.
317 * @retval None
318 */
HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef * hdma)319 __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
320 {
321 /* Prevent unused argument(s) compilation warning */
322 UNUSED(hdma);
323
324 /* NOTE: This function Should not be modified, when the callback is needed,
325 the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
326 */
327 }
328
329 /**
330 * @brief DMA transfer complete error callback.
331 * @param hdma DMA handle
332 * @retval None
333 */
HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef * hdma)334 __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
335 {
336 /* Prevent unused argument(s) compilation warning */
337 UNUSED(hdma);
338
339 /* NOTE: This function Should not be modified, when the callback is needed,
340 the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
341 */
342 }
343
344 /**
345 * @}
346 */
347
348 /** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions
349 * @brief Input Output and memory control functions
350 *
351 @verbatim
352 ==============================================================================
353 ##### SDRAM Input and Output functions #####
354 ==============================================================================
355 [..]
356 This section provides functions allowing to use and control the SDRAM memory
357
358 @endverbatim
359 * @{
360 */
361
362 /**
363 * @brief Reads 8-bit data buffer from the SDRAM memory.
364 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
365 * the configuration information for SDRAM module.
366 * @param pAddress Pointer to read start address
367 * @param pDstBuffer Pointer to destination buffer
368 * @param BufferSize Size of the buffer to read from memory
369 * @retval HAL status
370 */
HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint8_t * pDstBuffer,uint32_t BufferSize)371 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer,
372 uint32_t BufferSize)
373 {
374 uint32_t size;
375 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
376 uint8_t *pdestbuff = pDstBuffer;
377 HAL_SDRAM_StateTypeDef state = hsdram->State;
378
379 /* Check the SDRAM controller state */
380 if (state == HAL_SDRAM_STATE_BUSY)
381 {
382 return HAL_BUSY;
383 }
384 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
385 {
386 /* Process Locked */
387 __HAL_LOCK(hsdram);
388
389 /* Update the SDRAM controller state */
390 hsdram->State = HAL_SDRAM_STATE_BUSY;
391
392 /* Read data from source */
393 for (size = BufferSize; size != 0U; size--)
394 {
395 *pdestbuff = *(__IO uint8_t *)pSdramAddress;
396 pdestbuff++;
397 pSdramAddress++;
398 }
399
400 /* Update the SDRAM controller state */
401 hsdram->State = state;
402
403 /* Process Unlocked */
404 __HAL_UNLOCK(hsdram);
405 }
406 else
407 {
408 return HAL_ERROR;
409 }
410
411 return HAL_OK;
412 }
413
414 /**
415 * @brief Writes 8-bit data buffer to SDRAM memory.
416 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
417 * the configuration information for SDRAM module.
418 * @param pAddress Pointer to write start address
419 * @param pSrcBuffer Pointer to source buffer to write
420 * @param BufferSize Size of the buffer to write to memory
421 * @retval HAL status
422 */
HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint8_t * pSrcBuffer,uint32_t BufferSize)423 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer,
424 uint32_t BufferSize)
425 {
426 uint32_t size;
427 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
428 uint8_t *psrcbuff = pSrcBuffer;
429
430 /* Check the SDRAM controller state */
431 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
432 {
433 return HAL_BUSY;
434 }
435 else if (hsdram->State == HAL_SDRAM_STATE_READY)
436 {
437 /* Process Locked */
438 __HAL_LOCK(hsdram);
439
440 /* Update the SDRAM controller state */
441 hsdram->State = HAL_SDRAM_STATE_BUSY;
442
443 /* Write data to memory */
444 for (size = BufferSize; size != 0U; size--)
445 {
446 *(__IO uint8_t *)pSdramAddress = *psrcbuff;
447 psrcbuff++;
448 pSdramAddress++;
449 }
450
451 /* Update the SDRAM controller state */
452 hsdram->State = HAL_SDRAM_STATE_READY;
453
454 /* Process Unlocked */
455 __HAL_UNLOCK(hsdram);
456 }
457 else
458 {
459 return HAL_ERROR;
460 }
461
462 return HAL_OK;
463 }
464
465 /**
466 * @brief Reads 16-bit data buffer from the SDRAM memory.
467 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
468 * the configuration information for SDRAM module.
469 * @param pAddress Pointer to read start address
470 * @param pDstBuffer Pointer to destination buffer
471 * @param BufferSize Size of the buffer to read from memory
472 * @retval HAL status
473 */
HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint16_t * pDstBuffer,uint32_t BufferSize)474 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer,
475 uint32_t BufferSize)
476 {
477 uint32_t size;
478 __IO uint32_t *pSdramAddress = pAddress;
479 uint16_t *pdestbuff = pDstBuffer;
480 HAL_SDRAM_StateTypeDef state = hsdram->State;
481
482 /* Check the SDRAM controller state */
483 if (state == HAL_SDRAM_STATE_BUSY)
484 {
485 return HAL_BUSY;
486 }
487 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
488 {
489 /* Process Locked */
490 __HAL_LOCK(hsdram);
491
492 /* Update the SDRAM controller state */
493 hsdram->State = HAL_SDRAM_STATE_BUSY;
494
495 /* Read data from memory */
496 for (size = BufferSize; size >= 2U ; size -= 2U)
497 {
498 *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU);
499 pdestbuff++;
500 *pdestbuff = (uint16_t)(((*pSdramAddress) & 0xFFFF0000U) >> 16U);
501 pdestbuff++;
502 pSdramAddress++;
503 }
504
505 /* Read last 16-bits if size is not 32-bits multiple */
506 if ((BufferSize % 2U) != 0U)
507 {
508 *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU);
509 }
510
511 /* Update the SDRAM controller state */
512 hsdram->State = state;
513
514 /* Process Unlocked */
515 __HAL_UNLOCK(hsdram);
516 }
517 else
518 {
519 return HAL_ERROR;
520 }
521
522 return HAL_OK;
523 }
524
525 /**
526 * @brief Writes 16-bit data buffer to SDRAM memory.
527 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
528 * the configuration information for SDRAM module.
529 * @param pAddress Pointer to write start address
530 * @param pSrcBuffer Pointer to source buffer to write
531 * @param BufferSize Size of the buffer to write to memory
532 * @retval HAL status
533 */
HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint16_t * pSrcBuffer,uint32_t BufferSize)534 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer,
535 uint32_t BufferSize)
536 {
537 uint32_t size;
538 __IO uint32_t *psdramaddress = pAddress;
539 uint16_t *psrcbuff = pSrcBuffer;
540
541 /* Check the SDRAM controller state */
542 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
543 {
544 return HAL_BUSY;
545 }
546 else if (hsdram->State == HAL_SDRAM_STATE_READY)
547 {
548 /* Process Locked */
549 __HAL_LOCK(hsdram);
550
551 /* Update the SDRAM controller state */
552 hsdram->State = HAL_SDRAM_STATE_BUSY;
553
554 /* Write data to memory */
555 for (size = BufferSize; size >= 2U ; size -= 2U)
556 {
557 *psdramaddress = (uint32_t)(*psrcbuff);
558 psrcbuff++;
559 *psdramaddress |= ((uint32_t)(*psrcbuff) << 16U);
560 psrcbuff++;
561 psdramaddress++;
562 }
563
564 /* Write last 16-bits if size is not 32-bits multiple */
565 if ((BufferSize % 2U) != 0U)
566 {
567 *psdramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psdramaddress) & 0xFFFF0000U);
568 }
569
570 /* Update the SDRAM controller state */
571 hsdram->State = HAL_SDRAM_STATE_READY;
572
573 /* Process Unlocked */
574 __HAL_UNLOCK(hsdram);
575 }
576 else
577 {
578 return HAL_ERROR;
579 }
580
581 return HAL_OK;
582 }
583
584 /**
585 * @brief Reads 32-bit data buffer from the SDRAM memory.
586 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
587 * the configuration information for SDRAM module.
588 * @param pAddress Pointer to read start address
589 * @param pDstBuffer Pointer to destination buffer
590 * @param BufferSize Size of the buffer to read from memory
591 * @retval HAL status
592 */
HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)593 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
594 uint32_t BufferSize)
595 {
596 uint32_t size;
597 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
598 uint32_t *pdestbuff = pDstBuffer;
599 HAL_SDRAM_StateTypeDef state = hsdram->State;
600
601 /* Check the SDRAM controller state */
602 if (state == HAL_SDRAM_STATE_BUSY)
603 {
604 return HAL_BUSY;
605 }
606 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
607 {
608 /* Process Locked */
609 __HAL_LOCK(hsdram);
610
611 /* Update the SDRAM controller state */
612 hsdram->State = HAL_SDRAM_STATE_BUSY;
613
614 /* Read data from source */
615 for (size = BufferSize; size != 0U; size--)
616 {
617 *pdestbuff = *(__IO uint32_t *)pSdramAddress;
618 pdestbuff++;
619 pSdramAddress++;
620 }
621
622 /* Update the SDRAM controller state */
623 hsdram->State = state;
624
625 /* Process Unlocked */
626 __HAL_UNLOCK(hsdram);
627 }
628 else
629 {
630 return HAL_ERROR;
631 }
632
633 return HAL_OK;
634 }
635
636 /**
637 * @brief Writes 32-bit data buffer to SDRAM memory.
638 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
639 * the configuration information for SDRAM module.
640 * @param pAddress Pointer to write start address
641 * @param pSrcBuffer Pointer to source buffer to write
642 * @param BufferSize Size of the buffer to write to memory
643 * @retval HAL status
644 */
HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)645 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
646 uint32_t BufferSize)
647 {
648 uint32_t size;
649 __IO uint32_t *pSdramAddress = pAddress;
650 uint32_t *psrcbuff = pSrcBuffer;
651
652 /* Check the SDRAM controller state */
653 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
654 {
655 return HAL_BUSY;
656 }
657 else if (hsdram->State == HAL_SDRAM_STATE_READY)
658 {
659 /* Process Locked */
660 __HAL_LOCK(hsdram);
661
662 /* Update the SDRAM controller state */
663 hsdram->State = HAL_SDRAM_STATE_BUSY;
664
665 /* Write data to memory */
666 for (size = BufferSize; size != 0U; size--)
667 {
668 *pSdramAddress = *psrcbuff;
669 psrcbuff++;
670 pSdramAddress++;
671 }
672
673 /* Update the SDRAM controller state */
674 hsdram->State = HAL_SDRAM_STATE_READY;
675
676 /* Process Unlocked */
677 __HAL_UNLOCK(hsdram);
678 }
679 else
680 {
681 return HAL_ERROR;
682 }
683
684 return HAL_OK;
685 }
686
687 /**
688 * @brief Reads a Words data from the SDRAM memory using DMA transfer.
689 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
690 * the configuration information for SDRAM module.
691 * @param pAddress Pointer to read start address
692 * @param pDstBuffer Pointer to destination buffer
693 * @param BufferSize Size of the buffer to read from memory
694 * @retval HAL status
695 */
HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)696 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
697 uint32_t BufferSize)
698 {
699 HAL_StatusTypeDef status;
700 HAL_SDRAM_StateTypeDef state = hsdram->State;
701
702 /* Check the SDRAM controller state */
703 if (state == HAL_SDRAM_STATE_BUSY)
704 {
705 status = HAL_BUSY;
706 }
707 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
708 {
709 /* Process Locked */
710 __HAL_LOCK(hsdram);
711
712 /* Update the SDRAM controller state */
713 hsdram->State = HAL_SDRAM_STATE_BUSY;
714
715 /* Configure DMA user callbacks */
716 if (state == HAL_SDRAM_STATE_READY)
717 {
718 hsdram->hdma->XferCpltCallback = SDRAM_DMACplt;
719 }
720 else
721 {
722 hsdram->hdma->XferCpltCallback = SDRAM_DMACpltProt;
723 }
724 hsdram->hdma->XferErrorCallback = SDRAM_DMAError;
725
726 /* Enable the DMA Stream */
727 status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
728
729 /* Process Unlocked */
730 __HAL_UNLOCK(hsdram);
731 }
732 else
733 {
734 status = HAL_ERROR;
735 }
736
737 return status;
738 }
739
740 /**
741 * @brief Writes a Words data buffer to SDRAM memory using DMA transfer.
742 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
743 * the configuration information for SDRAM module.
744 * @param pAddress Pointer to write start address
745 * @param pSrcBuffer Pointer to source buffer to write
746 * @param BufferSize Size of the buffer to write to memory
747 * @retval HAL status
748 */
HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)749 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
750 uint32_t BufferSize)
751 {
752 HAL_StatusTypeDef status;
753
754 /* Check the SDRAM controller state */
755 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
756 {
757 status = HAL_BUSY;
758 }
759 else if (hsdram->State == HAL_SDRAM_STATE_READY)
760 {
761 /* Process Locked */
762 __HAL_LOCK(hsdram);
763
764 /* Update the SDRAM controller state */
765 hsdram->State = HAL_SDRAM_STATE_BUSY;
766
767 /* Configure DMA user callbacks */
768 hsdram->hdma->XferCpltCallback = SDRAM_DMACplt;
769 hsdram->hdma->XferErrorCallback = SDRAM_DMAError;
770
771 /* Enable the DMA Stream */
772 status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
773
774 /* Process Unlocked */
775 __HAL_UNLOCK(hsdram);
776 }
777 else
778 {
779 status = HAL_ERROR;
780 }
781
782 return status;
783 }
784
785 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
786 /**
787 * @brief Register a User SDRAM Callback
788 * To be used instead of the weak (surcharged) predefined callback
789 * @param hsdram : SDRAM handle
790 * @param CallbackId : ID of the callback to be registered
791 * This parameter can be one of the following values:
792 * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID
793 * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID
794 * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID
795 * @param pCallback : pointer to the Callback function
796 * @retval status
797 */
HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef * hsdram,HAL_SDRAM_CallbackIDTypeDef CallbackId,pSDRAM_CallbackTypeDef pCallback)798 HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
799 pSDRAM_CallbackTypeDef pCallback)
800 {
801 HAL_StatusTypeDef status = HAL_OK;
802 HAL_SDRAM_StateTypeDef state;
803
804 if (pCallback == NULL)
805 {
806 return HAL_ERROR;
807 }
808
809 /* Process locked */
810 __HAL_LOCK(hsdram);
811
812 state = hsdram->State;
813 if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
814 {
815 switch (CallbackId)
816 {
817 case HAL_SDRAM_MSP_INIT_CB_ID :
818 hsdram->MspInitCallback = pCallback;
819 break;
820 case HAL_SDRAM_MSP_DEINIT_CB_ID :
821 hsdram->MspDeInitCallback = pCallback;
822 break;
823 case HAL_SDRAM_REFRESH_ERR_CB_ID :
824 hsdram->RefreshErrorCallback = pCallback;
825 break;
826 default :
827 /* update return status */
828 status = HAL_ERROR;
829 break;
830 }
831 }
832 else if (hsdram->State == HAL_SDRAM_STATE_RESET)
833 {
834 switch (CallbackId)
835 {
836 case HAL_SDRAM_MSP_INIT_CB_ID :
837 hsdram->MspInitCallback = pCallback;
838 break;
839 case HAL_SDRAM_MSP_DEINIT_CB_ID :
840 hsdram->MspDeInitCallback = pCallback;
841 break;
842 default :
843 /* update return status */
844 status = HAL_ERROR;
845 break;
846 }
847 }
848 else
849 {
850 /* update return status */
851 status = HAL_ERROR;
852 }
853
854 /* Release Lock */
855 __HAL_UNLOCK(hsdram);
856 return status;
857 }
858
859 /**
860 * @brief Unregister a User SDRAM Callback
861 * SDRAM Callback is redirected to the weak (surcharged) predefined callback
862 * @param hsdram : SDRAM handle
863 * @param CallbackId : ID of the callback to be unregistered
864 * This parameter can be one of the following values:
865 * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID
866 * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID
867 * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID
868 * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID
869 * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID
870 * @retval status
871 */
HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef * hsdram,HAL_SDRAM_CallbackIDTypeDef CallbackId)872 HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId)
873 {
874 HAL_StatusTypeDef status = HAL_OK;
875 HAL_SDRAM_StateTypeDef state;
876
877 /* Process locked */
878 __HAL_LOCK(hsdram);
879
880 state = hsdram->State;
881 if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
882 {
883 switch (CallbackId)
884 {
885 case HAL_SDRAM_MSP_INIT_CB_ID :
886 hsdram->MspInitCallback = HAL_SDRAM_MspInit;
887 break;
888 case HAL_SDRAM_MSP_DEINIT_CB_ID :
889 hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
890 break;
891 case HAL_SDRAM_REFRESH_ERR_CB_ID :
892 hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
893 break;
894 case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
895 hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
896 break;
897 case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
898 hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
899 break;
900 default :
901 /* update return status */
902 status = HAL_ERROR;
903 break;
904 }
905 }
906 else if (hsdram->State == HAL_SDRAM_STATE_RESET)
907 {
908 switch (CallbackId)
909 {
910 case HAL_SDRAM_MSP_INIT_CB_ID :
911 hsdram->MspInitCallback = HAL_SDRAM_MspInit;
912 break;
913 case HAL_SDRAM_MSP_DEINIT_CB_ID :
914 hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
915 break;
916 default :
917 /* update return status */
918 status = HAL_ERROR;
919 break;
920 }
921 }
922 else
923 {
924 /* update return status */
925 status = HAL_ERROR;
926 }
927
928 /* Release Lock */
929 __HAL_UNLOCK(hsdram);
930 return status;
931 }
932
933 /**
934 * @brief Register a User SDRAM Callback for DMA transfers
935 * To be used instead of the weak (surcharged) predefined callback
936 * @param hsdram : SDRAM handle
937 * @param CallbackId : ID of the callback to be registered
938 * This parameter can be one of the following values:
939 * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID
940 * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID
941 * @param pCallback : pointer to the Callback function
942 * @retval status
943 */
HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef * hsdram,HAL_SDRAM_CallbackIDTypeDef CallbackId,pSDRAM_DmaCallbackTypeDef pCallback)944 HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
945 pSDRAM_DmaCallbackTypeDef pCallback)
946 {
947 HAL_StatusTypeDef status = HAL_OK;
948 HAL_SDRAM_StateTypeDef state;
949
950 if (pCallback == NULL)
951 {
952 return HAL_ERROR;
953 }
954
955 /* Process locked */
956 __HAL_LOCK(hsdram);
957
958 state = hsdram->State;
959 if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
960 {
961 switch (CallbackId)
962 {
963 case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
964 hsdram->DmaXferCpltCallback = pCallback;
965 break;
966 case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
967 hsdram->DmaXferErrorCallback = pCallback;
968 break;
969 default :
970 /* update return status */
971 status = HAL_ERROR;
972 break;
973 }
974 }
975 else
976 {
977 /* update return status */
978 status = HAL_ERROR;
979 }
980
981 /* Release Lock */
982 __HAL_UNLOCK(hsdram);
983 return status;
984 }
985 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
986
987 /**
988 * @}
989 */
990
991 /** @defgroup SDRAM_Exported_Functions_Group3 Control functions
992 * @brief management functions
993 *
994 @verbatim
995 ==============================================================================
996 ##### SDRAM Control functions #####
997 ==============================================================================
998 [..]
999 This subsection provides a set of functions allowing to control dynamically
1000 the SDRAM interface.
1001
1002 @endverbatim
1003 * @{
1004 */
1005
1006 /**
1007 * @brief Enables dynamically SDRAM write protection.
1008 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1009 * the configuration information for SDRAM module.
1010 * @retval HAL status
1011 */
HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef * hsdram)1012 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
1013 {
1014 /* Check the SDRAM controller state */
1015 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
1016 {
1017 return HAL_BUSY;
1018 }
1019 else if (hsdram->State == HAL_SDRAM_STATE_READY)
1020 {
1021 /* Update the SDRAM state */
1022 hsdram->State = HAL_SDRAM_STATE_BUSY;
1023
1024 /* Enable write protection */
1025 (void)FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
1026
1027 /* Update the SDRAM state */
1028 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
1029 }
1030 else
1031 {
1032 return HAL_ERROR;
1033 }
1034
1035 return HAL_OK;
1036 }
1037
1038 /**
1039 * @brief Disables dynamically SDRAM write protection.
1040 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1041 * the configuration information for SDRAM module.
1042 * @retval HAL status
1043 */
HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef * hsdram)1044 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
1045 {
1046 HAL_SDRAM_StateTypeDef state = hsdram->State;
1047
1048 /* Check the SDRAM controller state */
1049 if (state == HAL_SDRAM_STATE_BUSY)
1050 {
1051 return HAL_BUSY;
1052 }
1053 else if (state == HAL_SDRAM_STATE_WRITE_PROTECTED)
1054 {
1055 /* Update the SDRAM state */
1056 hsdram->State = HAL_SDRAM_STATE_BUSY;
1057
1058 /* Disable write protection */
1059 (void)FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
1060
1061 /* Update the SDRAM state */
1062 hsdram->State = HAL_SDRAM_STATE_READY;
1063 }
1064 else
1065 {
1066 return HAL_ERROR;
1067 }
1068
1069 return HAL_OK;
1070 }
1071
1072 /**
1073 * @brief Sends Command to the SDRAM bank.
1074 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1075 * the configuration information for SDRAM module.
1076 * @param Command SDRAM command structure
1077 * @param Timeout Timeout duration
1078 * @retval HAL status
1079 */
HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef * hsdram,FMC_SDRAM_CommandTypeDef * Command,uint32_t Timeout)1080 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command,
1081 uint32_t Timeout)
1082 {
1083 HAL_SDRAM_StateTypeDef state = hsdram->State;
1084
1085 /* Check the SDRAM controller state */
1086 if (state == HAL_SDRAM_STATE_BUSY)
1087 {
1088 return HAL_BUSY;
1089 }
1090 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_PRECHARGED))
1091 {
1092 /* Update the SDRAM state */
1093 hsdram->State = HAL_SDRAM_STATE_BUSY;
1094
1095 /* Send SDRAM command */
1096 (void)FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
1097
1098 /* Update the SDRAM controller state state */
1099 if (Command->CommandMode == FMC_SDRAM_CMD_PALL)
1100 {
1101 hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
1102 }
1103 else
1104 {
1105 hsdram->State = HAL_SDRAM_STATE_READY;
1106 }
1107 }
1108 else
1109 {
1110 return HAL_ERROR;
1111 }
1112
1113 return HAL_OK;
1114 }
1115
1116 /**
1117 * @brief Programs the SDRAM Memory Refresh rate.
1118 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1119 * the configuration information for SDRAM module.
1120 * @param RefreshRate The SDRAM refresh rate value
1121 * @retval HAL status
1122 */
HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef * hsdram,uint32_t RefreshRate)1123 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
1124 {
1125 /* Check the SDRAM controller state */
1126 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
1127 {
1128 return HAL_BUSY;
1129 }
1130 else if (hsdram->State == HAL_SDRAM_STATE_READY)
1131 {
1132 /* Update the SDRAM state */
1133 hsdram->State = HAL_SDRAM_STATE_BUSY;
1134
1135 /* Program the refresh rate */
1136 (void)FMC_SDRAM_ProgramRefreshRate(hsdram->Instance, RefreshRate);
1137
1138 /* Update the SDRAM state */
1139 hsdram->State = HAL_SDRAM_STATE_READY;
1140 }
1141 else
1142 {
1143 return HAL_ERROR;
1144 }
1145
1146 return HAL_OK;
1147 }
1148
1149 /**
1150 * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
1151 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1152 * the configuration information for SDRAM module.
1153 * @param AutoRefreshNumber The SDRAM auto Refresh number
1154 * @retval HAL status
1155 */
HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef * hsdram,uint32_t AutoRefreshNumber)1156 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
1157 {
1158 /* Check the SDRAM controller state */
1159 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
1160 {
1161 return HAL_BUSY;
1162 }
1163 else if (hsdram->State == HAL_SDRAM_STATE_READY)
1164 {
1165 /* Update the SDRAM state */
1166 hsdram->State = HAL_SDRAM_STATE_BUSY;
1167
1168 /* Set the Auto-Refresh number */
1169 (void)FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance, AutoRefreshNumber);
1170
1171 /* Update the SDRAM state */
1172 hsdram->State = HAL_SDRAM_STATE_READY;
1173 }
1174 else
1175 {
1176 return HAL_ERROR;
1177 }
1178
1179 return HAL_OK;
1180 }
1181
1182 /**
1183 * @brief Returns the SDRAM memory current mode.
1184 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1185 * the configuration information for SDRAM module.
1186 * @retval The SDRAM memory mode.
1187 */
HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef * hsdram)1188 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
1189 {
1190 /* Return the SDRAM memory current mode */
1191 return (FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
1192 }
1193
1194 /**
1195 * @}
1196 */
1197
1198 /** @defgroup SDRAM_Exported_Functions_Group4 State functions
1199 * @brief Peripheral State functions
1200 *
1201 @verbatim
1202 ==============================================================================
1203 ##### SDRAM State functions #####
1204 ==============================================================================
1205 [..]
1206 This subsection permits to get in run-time the status of the SDRAM controller
1207 and the data flow.
1208
1209 @endverbatim
1210 * @{
1211 */
1212
1213 /**
1214 * @brief Returns the SDRAM state.
1215 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1216 * the configuration information for SDRAM module.
1217 * @retval HAL state
1218 */
HAL_SDRAM_GetState(SDRAM_HandleTypeDef * hsdram)1219 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
1220 {
1221 return hsdram->State;
1222 }
1223
1224 /**
1225 * @}
1226 */
1227
1228 /**
1229 * @}
1230 */
1231
1232 /**
1233 * @brief DMA SDRAM process complete callback.
1234 * @param hdma : DMA handle
1235 * @retval None
1236 */
SDRAM_DMACplt(DMA_HandleTypeDef * hdma)1237 static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma)
1238 {
1239 SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
1240
1241 /* Disable the DMA channel */
1242 __HAL_DMA_DISABLE(hdma);
1243
1244 /* Update the SDRAM controller state */
1245 hsdram->State = HAL_SDRAM_STATE_READY;
1246
1247 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
1248 hsdram->DmaXferCpltCallback(hdma);
1249 #else
1250 HAL_SDRAM_DMA_XferCpltCallback(hdma);
1251 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
1252 }
1253
1254 /**
1255 * @brief DMA SRAM process complete callback.
1256 * @param hdma : DMA handle
1257 * @retval None
1258 */
SDRAM_DMACpltProt(DMA_HandleTypeDef * hdma)1259 static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
1260 {
1261 SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
1262
1263 /* Disable the DMA channel */
1264 __HAL_DMA_DISABLE(hdma);
1265
1266 /* Update the SDRAM controller state */
1267 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
1268
1269 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
1270 hsdram->DmaXferCpltCallback(hdma);
1271 #else
1272 HAL_SDRAM_DMA_XferCpltCallback(hdma);
1273 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
1274 }
1275
1276 /**
1277 * @brief DMA SDRAM error callback.
1278 * @param hdma : DMA handle
1279 * @retval None
1280 */
SDRAM_DMAError(DMA_HandleTypeDef * hdma)1281 static void SDRAM_DMAError(DMA_HandleTypeDef *hdma)
1282 {
1283 SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
1284
1285 /* Disable the DMA channel */
1286 __HAL_DMA_DISABLE(hdma);
1287
1288 /* Update the SDRAM controller state */
1289 hsdram->State = HAL_SDRAM_STATE_ERROR;
1290
1291 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
1292 hsdram->DmaXferErrorCallback(hdma);
1293 #else
1294 HAL_SDRAM_DMA_XferErrorCallback(hdma);
1295 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
1296 }
1297
1298 /**
1299 * @}
1300 */
1301
1302 #endif /* HAL_SDRAM_MODULE_ENABLED */
1303
1304 /**
1305 * @}
1306 */
1307
1308 #endif /* FMC_Bank5_6 */
1309
