1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_pwr.c
4 * @author MCD Application Team
5 * @brief PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller (PWR) peripheral:
8 * + Initialization and de-initialization functions
9 * + Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2017 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software is licensed under terms that can be found in the LICENSE file in
18 * the root directory of this software component.
19 * If no LICENSE file comes with this software, it is provided AS-IS.
20 ******************************************************************************
21 */
22
23 /* Includes ------------------------------------------------------------------*/
24 #include "stm32f4xx_hal.h"
25
26 /** @addtogroup STM32F4xx_HAL_Driver
27 * @{
28 */
29
30 /** @defgroup PWR PWR
31 * @brief PWR HAL module driver
32 * @{
33 */
34
35 #ifdef HAL_PWR_MODULE_ENABLED
36
37 /* Private typedef -----------------------------------------------------------*/
38 /* Private define ------------------------------------------------------------*/
39 /** @addtogroup PWR_Private_Constants
40 * @{
41 */
42
43 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
44 * @{
45 */
46 #define PVD_MODE_IT 0x00010000U
47 #define PVD_MODE_EVT 0x00020000U
48 #define PVD_RISING_EDGE 0x00000001U
49 #define PVD_FALLING_EDGE 0x00000002U
50 /**
51 * @}
52 */
53
54 /**
55 * @}
56 */
57 /* Private macro -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59 /* Private function prototypes -----------------------------------------------*/
60 /* Private functions ---------------------------------------------------------*/
61
62 /** @defgroup PWR_Exported_Functions PWR Exported Functions
63 * @{
64 */
65
66 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
67 * @brief Initialization and de-initialization functions
68 *
69 @verbatim
70 ===============================================================================
71 ##### Initialization and de-initialization functions #####
72 ===============================================================================
73 [..]
74 After reset, the backup domain (RTC registers, RTC backup data
75 registers and backup SRAM) is protected against possible unwanted
76 write accesses.
77 To enable access to the RTC Domain and RTC registers, proceed as follows:
78 (+) Enable the Power Controller (PWR) APB1 interface clock using the
79 __HAL_RCC_PWR_CLK_ENABLE() macro.
80 (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
81
82 @endverbatim
83 * @{
84 */
85
86 /**
87 * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
88 * @retval None
89 */
HAL_PWR_DeInit(void)90 void HAL_PWR_DeInit(void)
91 {
92 __HAL_RCC_PWR_FORCE_RESET();
93 __HAL_RCC_PWR_RELEASE_RESET();
94 }
95
96 /**
97 * @brief Enables access to the backup domain (RTC registers, RTC
98 * backup data registers and backup SRAM).
99 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
100 * Backup Domain Access should be kept enabled.
101 * @note The following sequence is required to bypass the delay between
102 * DBP bit programming and the effective enabling of the backup domain.
103 * Please check the Errata Sheet for more details under "Possible delay
104 * in backup domain protection disabling/enabling after programming the
105 * DBP bit" section.
106 * @retval None
107 */
HAL_PWR_EnableBkUpAccess(void)108 void HAL_PWR_EnableBkUpAccess(void)
109 {
110 __IO uint32_t dummyread;
111 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
112 dummyread = PWR->CR;
113 UNUSED(dummyread);
114 }
115
116 /**
117 * @brief Disables access to the backup domain (RTC registers, RTC
118 * backup data registers and backup SRAM).
119 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
120 * Backup Domain Access should be kept enabled.
121 * @note The following sequence is required to bypass the delay between
122 * DBP bit programming and the effective disabling of the backup domain.
123 * Please check the Errata Sheet for more details under "Possible delay
124 * in backup domain protection disabling/enabling after programming the
125 * DBP bit" section.
126 * @retval None
127 */
HAL_PWR_DisableBkUpAccess(void)128 void HAL_PWR_DisableBkUpAccess(void)
129 {
130 __IO uint32_t dummyread;
131 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
132 dummyread = PWR->CR;
133 UNUSED(dummyread);
134 }
135
136 /**
137 * @}
138 */
139
140 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
141 * @brief Low Power modes configuration functions
142 *
143 @verbatim
144
145 ===============================================================================
146 ##### Peripheral Control functions #####
147 ===============================================================================
148
149 *** PVD configuration ***
150 =========================
151 [..]
152 (+) The PVD is used to monitor the VDD power supply by comparing it to a
153 threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
154 (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
155 than the PVD threshold. This event is internally connected to the EXTI
156 line16 and can generate an interrupt if enabled. This is done through
157 __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
158 (+) The PVD is stopped in Standby mode.
159
160 *** Wake-up pin configuration ***
161 ================================
162 [..]
163 (+) Wake-up pin is used to wake up the system from Standby mode. This pin is
164 forced in input pull-down configuration and is active on rising edges.
165 (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00.
166 (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13
167 (++) For STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01
168
169 *** Low Power modes configuration ***
170 =====================================
171 [..]
172 The devices feature 3 low-power modes:
173 (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
174 (+) Stop mode: all clocks are stopped, regulator running, regulator
175 in low power mode
176 (+) Standby mode: 1.2V domain powered off.
177
178 *** Sleep mode ***
179 ==================
180 [..]
181 (+) Entry:
182 The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)
183 functions with
184 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
185 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
186
187 -@@- The Regulator parameter is not used for the STM32F4 family
188 and is kept as parameter just to maintain compatibility with the
189 lower power families (STM32L).
190 (+) Exit:
191 Any peripheral interrupt acknowledged by the nested vectored interrupt
192 controller (NVIC) can wake up the device from Sleep mode.
193
194 *** Stop mode ***
195 =================
196 [..]
197 In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
198 and the HSE RC oscillators are disabled. Internal SRAM and register contents
199 are preserved.
200 The voltage regulator can be configured either in normal or low-power mode.
201 To minimize the consumption In Stop mode, FLASH can be powered off before
202 entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
203 It can be switched on again by software after exiting the Stop mode using
204 the HAL_PWREx_DisableFlashPowerDown() function.
205
206 (+) Entry:
207 The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON)
208 function with:
209 (++) Main regulator ON.
210 (++) Low Power regulator ON.
211 (+) Exit:
212 Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
213
214 *** Standby mode ***
215 ====================
216 [..]
217 (+)
218 The Standby mode allows to achieve the lowest power consumption. It is based
219 on the Cortex-M4 deep sleep mode, with the voltage regulator disabled.
220 The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
221 the HSE oscillator are also switched off. SRAM and register contents are lost
222 except for the RTC registers, RTC backup registers, backup SRAM and Standby
223 circuitry.
224
225 The voltage regulator is OFF.
226
227 (++) Entry:
228 (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
229 (++) Exit:
230 (+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up,
231 tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
232
233 *** Auto-wake-up (AWU) from low-power mode ***
234 =============================================
235 [..]
236
237 (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
238 Wake-up event, a tamper event or a time-stamp event, without depending on
239 an external interrupt (Auto-wake-up mode).
240
241 (+) RTC auto-wake-up (AWU) from the Stop and Standby modes
242
243 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
244 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
245
246 (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
247 is necessary to configure the RTC to detect the tamper or time stamp event using the
248 HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
249
250 (++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to
251 configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
252
253 @endverbatim
254 * @{
255 */
256
257 /**
258 * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
259 * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
260 * information for the PVD.
261 * @note Refer to the electrical characteristics of your device datasheet for
262 * more details about the voltage threshold corresponding to each
263 * detection level.
264 * @retval None
265 */
HAL_PWR_ConfigPVD(PWR_PVDTypeDef * sConfigPVD)266 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
267 {
268 /* Check the parameters */
269 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
270 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
271
272 /* Set PLS[7:5] bits according to PVDLevel value */
273 MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
274
275 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
276 __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
277 __HAL_PWR_PVD_EXTI_DISABLE_IT();
278 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
279 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
280
281 /* Configure interrupt mode */
282 if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
283 {
284 __HAL_PWR_PVD_EXTI_ENABLE_IT();
285 }
286
287 /* Configure event mode */
288 if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
289 {
290 __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
291 }
292
293 /* Configure the edge */
294 if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
295 {
296 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
297 }
298
299 if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
300 {
301 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
302 }
303 }
304
305 /**
306 * @brief Enables the Power Voltage Detector(PVD).
307 * @retval None
308 */
HAL_PWR_EnablePVD(void)309 void HAL_PWR_EnablePVD(void)
310 {
311 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
312 }
313
314 /**
315 * @brief Disables the Power Voltage Detector(PVD).
316 * @retval None
317 */
HAL_PWR_DisablePVD(void)318 void HAL_PWR_DisablePVD(void)
319 {
320 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
321 }
322
323 /**
324 * @brief Enables the Wake-up PINx functionality.
325 * @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
326 * This parameter can be one of the following values:
327 * @arg PWR_WAKEUP_PIN1
328 * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices
329 * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices
330 * @retval None
331 */
HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)332 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
333 {
334 /* Check the parameter */
335 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
336
337 /* Enable the wake up pin */
338 SET_BIT(PWR->CSR, WakeUpPinx);
339 }
340
341 /**
342 * @brief Disables the Wake-up PINx functionality.
343 * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
344 * This parameter can be one of the following values:
345 * @arg PWR_WAKEUP_PIN1
346 * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices
347 * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices
348 * @retval None
349 */
HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)350 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
351 {
352 /* Check the parameter */
353 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
354
355 /* Disable the wake up pin */
356 CLEAR_BIT(PWR->CSR, WakeUpPinx);
357 }
358
359 /**
360 * @brief Enters Sleep mode.
361 *
362 * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
363 *
364 * @note In Sleep mode, the systick is stopped to avoid exit from this mode with
365 * systick interrupt when used as time base for Timeout
366 *
367 * @param Regulator Specifies the regulator state in SLEEP mode.
368 * This parameter can be one of the following values:
369 * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
370 * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
371 * @note This parameter is not used for the STM32F4 family and is kept as parameter
372 * just to maintain compatibility with the lower power families.
373 * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction.
374 * This parameter can be one of the following values:
375 * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
376 * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
377 * @retval None
378 */
HAL_PWR_EnterSLEEPMode(uint32_t Regulator,uint8_t SLEEPEntry)379 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
380 {
381 /* Check the parameters */
382 assert_param(IS_PWR_REGULATOR(Regulator));
383 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
384
385 /* Clear SLEEPDEEP bit of Cortex System Control Register */
386 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
387
388 /* Select SLEEP mode entry -------------------------------------------------*/
389 if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
390 {
391 /* Request Wait For Interrupt */
392 __WFI();
393 }
394 else
395 {
396 /* Request Wait For Event */
397 __SEV();
398 __WFE();
399 __WFE();
400 }
401 }
402
403 /**
404 * @brief Enters Stop mode.
405 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
406 * @note When exiting Stop mode by issuing an interrupt or a wake-up event,
407 * the HSI RC oscillator is selected as system clock.
408 * @note When the voltage regulator operates in low power mode, an additional
409 * startup delay is incurred when waking up from Stop mode.
410 * By keeping the internal regulator ON during Stop mode, the consumption
411 * is higher although the startup time is reduced.
412 * @param Regulator Specifies the regulator state in Stop mode.
413 * This parameter can be one of the following values:
414 * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
415 * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
416 * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction.
417 * This parameter can be one of the following values:
418 * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
419 * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
420 * @retval None
421 */
HAL_PWR_EnterSTOPMode(uint32_t Regulator,uint8_t STOPEntry)422 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
423 {
424 /* Check the parameters */
425 assert_param(IS_PWR_REGULATOR(Regulator));
426 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
427
428 /* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator value */
429 MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator);
430
431 /* Set SLEEPDEEP bit of Cortex System Control Register */
432 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
433
434 /* Select Stop mode entry --------------------------------------------------*/
435 if(STOPEntry == PWR_STOPENTRY_WFI)
436 {
437 /* Request Wait For Interrupt */
438 __WFI();
439 }
440 else
441 {
442 /* Request Wait For Event */
443 __SEV();
444 __WFE();
445 __WFE();
446 }
447 /* Reset SLEEPDEEP bit of Cortex System Control Register */
448 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
449 }
450
451 /**
452 * @brief Enters Standby mode.
453 * @note In Standby mode, all I/O pins are high impedance except for:
454 * - Reset pad (still available)
455 * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
456 * Alarm out, or RTC clock calibration out.
457 * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
458 * - WKUP pin 1 (PA0) if enabled.
459 * @retval None
460 */
HAL_PWR_EnterSTANDBYMode(void)461 void HAL_PWR_EnterSTANDBYMode(void)
462 {
463 /* Select Standby mode */
464 SET_BIT(PWR->CR, PWR_CR_PDDS);
465
466 /* Set SLEEPDEEP bit of Cortex System Control Register */
467 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
468
469 /* This option is used to ensure that store operations are completed */
470 #if defined ( __CC_ARM)
471 __force_stores();
472 #endif
473 /* Request Wait For Interrupt */
474 __WFI();
475 }
476
477 /**
478 * @brief This function handles the PWR PVD interrupt request.
479 * @note This API should be called under the PVD_IRQHandler().
480 * @retval None
481 */
HAL_PWR_PVD_IRQHandler(void)482 void HAL_PWR_PVD_IRQHandler(void)
483 {
484 /* Check PWR Exti flag */
485 if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
486 {
487 /* PWR PVD interrupt user callback */
488 HAL_PWR_PVDCallback();
489
490 /* Clear PWR Exti pending bit */
491 __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
492 }
493 }
494
495 /**
496 * @brief PWR PVD interrupt callback
497 * @retval None
498 */
HAL_PWR_PVDCallback(void)499 __weak void HAL_PWR_PVDCallback(void)
500 {
501 /* NOTE : This function Should not be modified, when the callback is needed,
502 the HAL_PWR_PVDCallback could be implemented in the user file
503 */
504 }
505
506 /**
507 * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
508 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
509 * re-enters SLEEP mode when an interruption handling is over.
510 * Setting this bit is useful when the processor is expected to run only on
511 * interruptions handling.
512 * @retval None
513 */
HAL_PWR_EnableSleepOnExit(void)514 void HAL_PWR_EnableSleepOnExit(void)
515 {
516 /* Set SLEEPONEXIT bit of Cortex System Control Register */
517 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
518 }
519
520 /**
521 * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
522 * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
523 * re-enters SLEEP mode when an interruption handling is over.
524 * @retval None
525 */
HAL_PWR_DisableSleepOnExit(void)526 void HAL_PWR_DisableSleepOnExit(void)
527 {
528 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
529 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
530 }
531
532 /**
533 * @brief Enables CORTEX M4 SEVONPEND bit.
534 * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
535 * WFE to wake up when an interrupt moves from inactive to pended.
536 * @retval None
537 */
HAL_PWR_EnableSEVOnPend(void)538 void HAL_PWR_EnableSEVOnPend(void)
539 {
540 /* Set SEVONPEND bit of Cortex System Control Register */
541 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
542 }
543
544 /**
545 * @brief Disables CORTEX M4 SEVONPEND bit.
546 * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
547 * WFE to wake up when an interrupt moves from inactive to pended.
548 * @retval None
549 */
HAL_PWR_DisableSEVOnPend(void)550 void HAL_PWR_DisableSEVOnPend(void)
551 {
552 /* Clear SEVONPEND bit of Cortex System Control Register */
553 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
554 }
555
556 /**
557 * @}
558 */
559
560 /**
561 * @}
562 */
563
564 #endif /* HAL_PWR_MODULE_ENABLED */
565 /**
566 * @}
567 */
568
569 /**
570 * @}
571 */
572
