1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_i2c.c
4 * @author MCD Application Team
5 * @brief I2C HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Inter Integrated Circuit (I2C) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral State, Mode and Error functions
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2016 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 @verbatim
24 ==============================================================================
25 ##### How to use this driver #####
26 ==============================================================================
27 [..]
28 The I2C HAL driver can be used as follows:
29
30 (#) Declare a I2C_HandleTypeDef handle structure, for example:
31 I2C_HandleTypeDef hi2c;
32
33 (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
34 (##) Enable the I2Cx interface clock
35 (##) I2C pins configuration
36 (+++) Enable the clock for the I2C GPIOs
37 (+++) Configure I2C pins as alternate function open-drain
38 (##) NVIC configuration if you need to use interrupt process
39 (+++) Configure the I2Cx interrupt priority
40 (+++) Enable the NVIC I2C IRQ Channel
41 (##) DMA Configuration if you need to use DMA process
42 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
43 (+++) Enable the DMAx interface clock using
44 (+++) Configure the DMA handle parameters
45 (+++) Configure the DMA Tx or Rx stream
46 (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
47 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
48 the DMA Tx or Rx stream
49
50 (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
51 Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.
52
53 (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
54 (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit() API.
55
56 (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
57
58 (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
59
60 *** Polling mode IO operation ***
61 =================================
62 [..]
63 (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
64 (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
65 (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
66 (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
67
68 *** Polling mode IO MEM operation ***
69 =====================================
70 [..]
71 (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
72 (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
73
74
75 *** Interrupt mode IO operation ***
76 ===================================
77 [..]
78 (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
79 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
80 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
81 (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
82 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
83 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
84 (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
85 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
86 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
87 (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
88 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
89 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
90 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
91 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
92 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
93 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
94 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
95
96 *** Interrupt mode or DMA mode IO sequential operation ***
97 ==========================================================
98 [..]
99 (@) These interfaces allow to manage a sequential transfer with a repeated start condition
100 when a direction change during transfer
101 [..]
102 (+) A specific option field manage the different steps of a sequential transfer
103 (+) Option field values are defined through I2C_XferOptions_definition and are listed below:
104 (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode
105 (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
106 and data to transfer without a final stop condition
107 (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
108 and data to transfer without a final stop condition, an then permit a call the same master sequential interface
109 several times (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
110 or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
111 (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
112 and with new data to transfer if the direction change or manage only the new data to transfer
113 if no direction change and without a final stop condition in both cases
114 (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
115 and with new data to transfer if the direction change or manage only the new data to transfer
116 if no direction change and with a final stop condition in both cases
117 (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential
118 interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).
119 Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
120 or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
121 or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
122 or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
123 Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit
124 without stopping the communication and so generate a restart condition.
125 (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
126 interface.
127 Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
128 or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
129 or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
130 or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
131 Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
132
133 (+) Different sequential I2C interfaces are listed below:
134 (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Seq_Transmit_IT()
135 or using HAL_I2C_Master_Seq_Transmit_DMA()
136 (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
137 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
138 (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Seq_Receive_IT()
139 or using HAL_I2C_Master_Seq_Receive_DMA()
140 (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
141 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
142 (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
143 (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
144 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
145 (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
146 (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
147 add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
148 (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
149 add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
150 (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Seq_Transmit_IT()
151 or using HAL_I2C_Slave_Seq_Transmit_DMA()
152 (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
153 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
154 (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Seq_Receive_IT()
155 or using HAL_I2C_Slave_Seq_Receive_DMA()
156 (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
157 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
158 (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
159 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
160
161 *** Interrupt mode IO MEM operation ***
162 =======================================
163 [..]
164 (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
165 HAL_I2C_Mem_Write_IT()
166 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
167 add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
168 (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
169 HAL_I2C_Mem_Read_IT()
170 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
171 add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
172 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
173 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
174
175 *** DMA mode IO operation ***
176 ==============================
177 [..]
178 (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
179 HAL_I2C_Master_Transmit_DMA()
180 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
181 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
182 (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
183 HAL_I2C_Master_Receive_DMA()
184 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
185 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
186 (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
187 HAL_I2C_Slave_Transmit_DMA()
188 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
189 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
190 (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
191 HAL_I2C_Slave_Receive_DMA()
192 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
193 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
194 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
195 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
196 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
197 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
198 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
199
200 *** DMA mode IO MEM operation ***
201 =================================
202 [..]
203 (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
204 HAL_I2C_Mem_Write_DMA()
205 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
206 add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
207 (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
208 HAL_I2C_Mem_Read_DMA()
209 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
210 add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
211 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
212 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
213
214
215 *** I2C HAL driver macros list ***
216 ==================================
217 [..]
218 Below the list of most used macros in I2C HAL driver.
219
220 (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
221 (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
222 (+) __HAL_I2C_GET_FLAG: Checks whether the specified I2C flag is set or not
223 (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
224 (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
225 (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
226
227 *** Callback registration ***
228 =============================================
229 [..]
230 The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
231 allows the user to configure dynamically the driver callbacks.
232 Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
233 to register an interrupt callback.
234 [..]
235 Function HAL_I2C_RegisterCallback() allows to register following callbacks:
236 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
237 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
238 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
239 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
240 (+) ListenCpltCallback : callback for end of listen mode.
241 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
242 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
243 (+) ErrorCallback : callback for error detection.
244 (+) AbortCpltCallback : callback for abort completion process.
245 (+) MspInitCallback : callback for Msp Init.
246 (+) MspDeInitCallback : callback for Msp DeInit.
247 This function takes as parameters the HAL peripheral handle, the Callback ID
248 and a pointer to the user callback function.
249 [..]
250 For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
251 [..]
252 Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
253 weak function.
254 HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
255 and the Callback ID.
256 This function allows to reset following callbacks:
257 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
258 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
259 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
260 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
261 (+) ListenCpltCallback : callback for end of listen mode.
262 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
263 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
264 (+) ErrorCallback : callback for error detection.
265 (+) AbortCpltCallback : callback for abort completion process.
266 (+) MspInitCallback : callback for Msp Init.
267 (+) MspDeInitCallback : callback for Msp DeInit.
268 [..]
269 For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
270 [..]
271 By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
272 all callbacks are set to the corresponding weak functions:
273 examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
274 Exception done for MspInit and MspDeInit functions that are
275 reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
276 these callbacks are null (not registered beforehand).
277 If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
278 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
279 [..]
280 Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
281 Exception done MspInit/MspDeInit functions that can be registered/unregistered
282 in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
283 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
284 Then, the user first registers the MspInit/MspDeInit user callbacks
285 using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
286 or HAL_I2C_Init() function.
287 [..]
288 When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
289 not defined, the callback registration feature is not available and all callbacks
290 are set to the corresponding weak functions.
291
292
293
294 [..]
295 (@) You can refer to the I2C HAL driver header file for more useful macros
296
297 @endverbatim
298 */
299
300 /* Includes ------------------------------------------------------------------*/
301 #include "stm32f4xx_hal.h"
302
303 /** @addtogroup STM32F4xx_HAL_Driver
304 * @{
305 */
306
307 /** @defgroup I2C I2C
308 * @brief I2C HAL module driver
309 * @{
310 */
311
312 #ifdef HAL_I2C_MODULE_ENABLED
313
314 /* Private typedef -----------------------------------------------------------*/
315 /* Private define ------------------------------------------------------------*/
316 /** @addtogroup I2C_Private_Define
317 * @{
318 */
319 #define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */
320 #define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */
321 #define I2C_TIMEOUT_STOP_FLAG 5U /*!< Timeout 5 ms */
322 #define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */
323
324 /* Private define for @ref PreviousState usage */
325 #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */
326 #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */
327 #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
328 #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
329 #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
330 #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
331
332 /**
333 * @}
334 */
335
336 /* Private macro -------------------------------------------------------------*/
337 /* Private variables ---------------------------------------------------------*/
338 /* Private function prototypes -----------------------------------------------*/
339
340 /** @defgroup I2C_Private_Functions I2C Private Functions
341 * @{
342 */
343 /* Private functions to handle DMA transfer */
344 static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma);
345 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
346 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
347
348 static void I2C_ITError(I2C_HandleTypeDef *hi2c);
349
350 static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
351 static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
352 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
353 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
354
355 /* Private functions to handle flags during polling transfer */
356 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
357 static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart);
358 static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
359 static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
360 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
361 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
362 static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c);
363 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c);
364
365 /* Private functions for I2C transfer IRQ handler */
366 static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
367 static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
368 static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
369 static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
370 static void I2C_Master_SB(I2C_HandleTypeDef *hi2c);
371 static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c);
372 static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c);
373
374 static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);
375 static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);
376 static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c);
377 static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c);
378 static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags);
379 static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
380 static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
381
382 static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c);
383
384 /* Private function to Convert Specific options */
385 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
386 /**
387 * @}
388 */
389
390 /* Exported functions --------------------------------------------------------*/
391
392 /** @defgroup I2C_Exported_Functions I2C Exported Functions
393 * @{
394 */
395
396 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
397 * @brief Initialization and Configuration functions
398 *
399 @verbatim
400 ===============================================================================
401 ##### Initialization and de-initialization functions #####
402 ===============================================================================
403 [..] This subsection provides a set of functions allowing to initialize and
404 deinitialize the I2Cx peripheral:
405
406 (+) User must Implement HAL_I2C_MspInit() function in which he configures
407 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).
408
409 (+) Call the function HAL_I2C_Init() to configure the selected device with
410 the selected configuration:
411 (++) Communication Speed
412 (++) Duty cycle
413 (++) Addressing mode
414 (++) Own Address 1
415 (++) Dual Addressing mode
416 (++) Own Address 2
417 (++) General call mode
418 (++) Nostretch mode
419
420 (+) Call the function HAL_I2C_DeInit() to restore the default configuration
421 of the selected I2Cx peripheral.
422
423 @endverbatim
424 * @{
425 */
426
427 /**
428 * @brief Initializes the I2C according to the specified parameters
429 * in the I2C_InitTypeDef and initialize the associated handle.
430 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
431 * the configuration information for the specified I2C.
432 * @retval HAL status
433 */
HAL_I2C_Init(I2C_HandleTypeDef * hi2c)434 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
435 {
436 uint32_t freqrange;
437 uint32_t pclk1;
438
439 /* Check the I2C handle allocation */
440 if (hi2c == NULL)
441 {
442 return HAL_ERROR;
443 }
444
445 /* Check the parameters */
446 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
447 assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed));
448 assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle));
449 assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
450 assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
451 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
452 assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
453 assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
454 assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
455
456 if (hi2c->State == HAL_I2C_STATE_RESET)
457 {
458 /* Allocate lock resource and initialize it */
459 hi2c->Lock = HAL_UNLOCKED;
460
461 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
462 /* Init the I2C Callback settings */
463 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
464 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
465 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
466 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
467 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
468 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
469 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
470 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
471 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
472 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
473
474 if (hi2c->MspInitCallback == NULL)
475 {
476 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
477 }
478
479 /* Init the low level hardware : GPIO, CLOCK, NVIC */
480 hi2c->MspInitCallback(hi2c);
481 #else
482 /* Init the low level hardware : GPIO, CLOCK, NVIC */
483 HAL_I2C_MspInit(hi2c);
484 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
485 }
486
487 hi2c->State = HAL_I2C_STATE_BUSY;
488
489 /* Disable the selected I2C peripheral */
490 __HAL_I2C_DISABLE(hi2c);
491
492 /*Reset I2C*/
493 hi2c->Instance->CR1 |= I2C_CR1_SWRST;
494 hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;
495
496 /* Get PCLK1 frequency */
497 pclk1 = HAL_RCC_GetPCLK1Freq();
498
499 /* Check the minimum allowed PCLK1 frequency */
500 if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
501 {
502 return HAL_ERROR;
503 }
504
505 /* Calculate frequency range */
506 freqrange = I2C_FREQRANGE(pclk1);
507
508 /*---------------------------- I2Cx CR2 Configuration ----------------------*/
509 /* Configure I2Cx: Frequency range */
510 MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
511
512 /*---------------------------- I2Cx TRISE Configuration --------------------*/
513 /* Configure I2Cx: Rise Time */
514 MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
515
516 /*---------------------------- I2Cx CCR Configuration ----------------------*/
517 /* Configure I2Cx: Speed */
518 MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
519
520 /*---------------------------- I2Cx CR1 Configuration ----------------------*/
521 /* Configure I2Cx: Generalcall and NoStretch mode */
522 MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
523
524 /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
525 /* Configure I2Cx: Own Address1 and addressing mode */
526 MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
527
528 /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
529 /* Configure I2Cx: Dual mode and Own Address2 */
530 MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
531
532 /* Enable the selected I2C peripheral */
533 __HAL_I2C_ENABLE(hi2c);
534
535 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
536 hi2c->State = HAL_I2C_STATE_READY;
537 hi2c->PreviousState = I2C_STATE_NONE;
538 hi2c->Mode = HAL_I2C_MODE_NONE;
539
540 return HAL_OK;
541 }
542
543 /**
544 * @brief DeInitialize the I2C peripheral.
545 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
546 * the configuration information for the specified I2C.
547 * @retval HAL status
548 */
HAL_I2C_DeInit(I2C_HandleTypeDef * hi2c)549 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
550 {
551 /* Check the I2C handle allocation */
552 if (hi2c == NULL)
553 {
554 return HAL_ERROR;
555 }
556
557 /* Check the parameters */
558 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
559
560 hi2c->State = HAL_I2C_STATE_BUSY;
561
562 /* Disable the I2C Peripheral Clock */
563 __HAL_I2C_DISABLE(hi2c);
564
565 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
566 if (hi2c->MspDeInitCallback == NULL)
567 {
568 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
569 }
570
571 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
572 hi2c->MspDeInitCallback(hi2c);
573 #else
574 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
575 HAL_I2C_MspDeInit(hi2c);
576 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
577
578 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
579 hi2c->State = HAL_I2C_STATE_RESET;
580 hi2c->PreviousState = I2C_STATE_NONE;
581 hi2c->Mode = HAL_I2C_MODE_NONE;
582
583 /* Release Lock */
584 __HAL_UNLOCK(hi2c);
585
586 return HAL_OK;
587 }
588
589 /**
590 * @brief Initialize the I2C MSP.
591 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
592 * the configuration information for the specified I2C.
593 * @retval None
594 */
HAL_I2C_MspInit(I2C_HandleTypeDef * hi2c)595 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
596 {
597 /* Prevent unused argument(s) compilation warning */
598 UNUSED(hi2c);
599
600 /* NOTE : This function should not be modified, when the callback is needed,
601 the HAL_I2C_MspInit could be implemented in the user file
602 */
603 }
604
605 /**
606 * @brief DeInitialize the I2C MSP.
607 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
608 * the configuration information for the specified I2C.
609 * @retval None
610 */
HAL_I2C_MspDeInit(I2C_HandleTypeDef * hi2c)611 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
612 {
613 /* Prevent unused argument(s) compilation warning */
614 UNUSED(hi2c);
615
616 /* NOTE : This function should not be modified, when the callback is needed,
617 the HAL_I2C_MspDeInit could be implemented in the user file
618 */
619 }
620
621 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
622 /**
623 * @brief Register a User I2C Callback
624 * To be used instead of the weak predefined callback
625 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
626 * the configuration information for the specified I2C.
627 * @param CallbackID ID of the callback to be registered
628 * This parameter can be one of the following values:
629 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
630 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
631 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
632 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
633 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
634 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
635 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
636 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
637 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
638 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
639 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
640 * @param pCallback pointer to the Callback function
641 * @retval HAL status
642 */
HAL_I2C_RegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID,pI2C_CallbackTypeDef pCallback)643 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
644 {
645 HAL_StatusTypeDef status = HAL_OK;
646
647 if (pCallback == NULL)
648 {
649 /* Update the error code */
650 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
651
652 return HAL_ERROR;
653 }
654 /* Process locked */
655 __HAL_LOCK(hi2c);
656
657 if (HAL_I2C_STATE_READY == hi2c->State)
658 {
659 switch (CallbackID)
660 {
661 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
662 hi2c->MasterTxCpltCallback = pCallback;
663 break;
664
665 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
666 hi2c->MasterRxCpltCallback = pCallback;
667 break;
668
669 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
670 hi2c->SlaveTxCpltCallback = pCallback;
671 break;
672
673 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
674 hi2c->SlaveRxCpltCallback = pCallback;
675 break;
676
677 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
678 hi2c->ListenCpltCallback = pCallback;
679 break;
680
681 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
682 hi2c->MemTxCpltCallback = pCallback;
683 break;
684
685 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
686 hi2c->MemRxCpltCallback = pCallback;
687 break;
688
689 case HAL_I2C_ERROR_CB_ID :
690 hi2c->ErrorCallback = pCallback;
691 break;
692
693 case HAL_I2C_ABORT_CB_ID :
694 hi2c->AbortCpltCallback = pCallback;
695 break;
696
697 case HAL_I2C_MSPINIT_CB_ID :
698 hi2c->MspInitCallback = pCallback;
699 break;
700
701 case HAL_I2C_MSPDEINIT_CB_ID :
702 hi2c->MspDeInitCallback = pCallback;
703 break;
704
705 default :
706 /* Update the error code */
707 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
708
709 /* Return error status */
710 status = HAL_ERROR;
711 break;
712 }
713 }
714 else if (HAL_I2C_STATE_RESET == hi2c->State)
715 {
716 switch (CallbackID)
717 {
718 case HAL_I2C_MSPINIT_CB_ID :
719 hi2c->MspInitCallback = pCallback;
720 break;
721
722 case HAL_I2C_MSPDEINIT_CB_ID :
723 hi2c->MspDeInitCallback = pCallback;
724 break;
725
726 default :
727 /* Update the error code */
728 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
729
730 /* Return error status */
731 status = HAL_ERROR;
732 break;
733 }
734 }
735 else
736 {
737 /* Update the error code */
738 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
739
740 /* Return error status */
741 status = HAL_ERROR;
742 }
743
744 /* Release Lock */
745 __HAL_UNLOCK(hi2c);
746 return status;
747 }
748
749 /**
750 * @brief Unregister an I2C Callback
751 * I2C callback is redirected to the weak predefined callback
752 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
753 * the configuration information for the specified I2C.
754 * @param CallbackID ID of the callback to be unregistered
755 * This parameter can be one of the following values:
756 * This parameter can be one of the following values:
757 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
758 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
759 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
760 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
761 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
762 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
763 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
764 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
765 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
766 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
767 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
768 * @retval HAL status
769 */
HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID)770 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
771 {
772 HAL_StatusTypeDef status = HAL_OK;
773
774 /* Process locked */
775 __HAL_LOCK(hi2c);
776
777 if (HAL_I2C_STATE_READY == hi2c->State)
778 {
779 switch (CallbackID)
780 {
781 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
782 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
783 break;
784
785 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
786 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
787 break;
788
789 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
790 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
791 break;
792
793 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
794 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
795 break;
796
797 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
798 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
799 break;
800
801 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
802 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
803 break;
804
805 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
806 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
807 break;
808
809 case HAL_I2C_ERROR_CB_ID :
810 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
811 break;
812
813 case HAL_I2C_ABORT_CB_ID :
814 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
815 break;
816
817 case HAL_I2C_MSPINIT_CB_ID :
818 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
819 break;
820
821 case HAL_I2C_MSPDEINIT_CB_ID :
822 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
823 break;
824
825 default :
826 /* Update the error code */
827 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
828
829 /* Return error status */
830 status = HAL_ERROR;
831 break;
832 }
833 }
834 else if (HAL_I2C_STATE_RESET == hi2c->State)
835 {
836 switch (CallbackID)
837 {
838 case HAL_I2C_MSPINIT_CB_ID :
839 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
840 break;
841
842 case HAL_I2C_MSPDEINIT_CB_ID :
843 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
844 break;
845
846 default :
847 /* Update the error code */
848 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
849
850 /* Return error status */
851 status = HAL_ERROR;
852 break;
853 }
854 }
855 else
856 {
857 /* Update the error code */
858 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
859
860 /* Return error status */
861 status = HAL_ERROR;
862 }
863
864 /* Release Lock */
865 __HAL_UNLOCK(hi2c);
866 return status;
867 }
868
869 /**
870 * @brief Register the Slave Address Match I2C Callback
871 * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
872 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
873 * the configuration information for the specified I2C.
874 * @param pCallback pointer to the Address Match Callback function
875 * @retval HAL status
876 */
HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef * hi2c,pI2C_AddrCallbackTypeDef pCallback)877 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
878 {
879 HAL_StatusTypeDef status = HAL_OK;
880
881 if (pCallback == NULL)
882 {
883 /* Update the error code */
884 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
885
886 return HAL_ERROR;
887 }
888 /* Process locked */
889 __HAL_LOCK(hi2c);
890
891 if (HAL_I2C_STATE_READY == hi2c->State)
892 {
893 hi2c->AddrCallback = pCallback;
894 }
895 else
896 {
897 /* Update the error code */
898 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
899
900 /* Return error status */
901 status = HAL_ERROR;
902 }
903
904 /* Release Lock */
905 __HAL_UNLOCK(hi2c);
906 return status;
907 }
908
909 /**
910 * @brief UnRegister the Slave Address Match I2C Callback
911 * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
912 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
913 * the configuration information for the specified I2C.
914 * @retval HAL status
915 */
HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef * hi2c)916 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
917 {
918 HAL_StatusTypeDef status = HAL_OK;
919
920 /* Process locked */
921 __HAL_LOCK(hi2c);
922
923 if (HAL_I2C_STATE_READY == hi2c->State)
924 {
925 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
926 }
927 else
928 {
929 /* Update the error code */
930 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
931
932 /* Return error status */
933 status = HAL_ERROR;
934 }
935
936 /* Release Lock */
937 __HAL_UNLOCK(hi2c);
938 return status;
939 }
940
941 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
942
943 /**
944 * @}
945 */
946
947 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
948 * @brief Data transfers functions
949 *
950 @verbatim
951 ===============================================================================
952 ##### IO operation functions #####
953 ===============================================================================
954 [..]
955 This subsection provides a set of functions allowing to manage the I2C data
956 transfers.
957
958 (#) There are two modes of transfer:
959 (++) Blocking mode : The communication is performed in the polling mode.
960 The status of all data processing is returned by the same function
961 after finishing transfer.
962 (++) No-Blocking mode : The communication is performed using Interrupts
963 or DMA. These functions return the status of the transfer startup.
964 The end of the data processing will be indicated through the
965 dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
966 using DMA mode.
967
968 (#) Blocking mode functions are :
969 (++) HAL_I2C_Master_Transmit()
970 (++) HAL_I2C_Master_Receive()
971 (++) HAL_I2C_Slave_Transmit()
972 (++) HAL_I2C_Slave_Receive()
973 (++) HAL_I2C_Mem_Write()
974 (++) HAL_I2C_Mem_Read()
975 (++) HAL_I2C_IsDeviceReady()
976
977 (#) No-Blocking mode functions with Interrupt are :
978 (++) HAL_I2C_Master_Transmit_IT()
979 (++) HAL_I2C_Master_Receive_IT()
980 (++) HAL_I2C_Slave_Transmit_IT()
981 (++) HAL_I2C_Slave_Receive_IT()
982 (++) HAL_I2C_Mem_Write_IT()
983 (++) HAL_I2C_Mem_Read_IT()
984 (++) HAL_I2C_Master_Seq_Transmit_IT()
985 (++) HAL_I2C_Master_Seq_Receive_IT()
986 (++) HAL_I2C_Slave_Seq_Transmit_IT()
987 (++) HAL_I2C_Slave_Seq_Receive_IT()
988 (++) HAL_I2C_EnableListen_IT()
989 (++) HAL_I2C_DisableListen_IT()
990 (++) HAL_I2C_Master_Abort_IT()
991
992 (#) No-Blocking mode functions with DMA are :
993 (++) HAL_I2C_Master_Transmit_DMA()
994 (++) HAL_I2C_Master_Receive_DMA()
995 (++) HAL_I2C_Slave_Transmit_DMA()
996 (++) HAL_I2C_Slave_Receive_DMA()
997 (++) HAL_I2C_Mem_Write_DMA()
998 (++) HAL_I2C_Mem_Read_DMA()
999 (++) HAL_I2C_Master_Seq_Transmit_DMA()
1000 (++) HAL_I2C_Master_Seq_Receive_DMA()
1001 (++) HAL_I2C_Slave_Seq_Transmit_DMA()
1002 (++) HAL_I2C_Slave_Seq_Receive_DMA()
1003
1004 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
1005 (++) HAL_I2C_MasterTxCpltCallback()
1006 (++) HAL_I2C_MasterRxCpltCallback()
1007 (++) HAL_I2C_SlaveTxCpltCallback()
1008 (++) HAL_I2C_SlaveRxCpltCallback()
1009 (++) HAL_I2C_MemTxCpltCallback()
1010 (++) HAL_I2C_MemRxCpltCallback()
1011 (++) HAL_I2C_AddrCallback()
1012 (++) HAL_I2C_ListenCpltCallback()
1013 (++) HAL_I2C_ErrorCallback()
1014 (++) HAL_I2C_AbortCpltCallback()
1015
1016 @endverbatim
1017 * @{
1018 */
1019
1020 /**
1021 * @brief Transmits in master mode an amount of data in blocking mode.
1022 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1023 * the configuration information for the specified I2C.
1024 * @param DevAddress Target device address: The device 7 bits address value
1025 * in datasheet must be shifted to the left before calling the interface
1026 * @param pData Pointer to data buffer
1027 * @param Size Amount of data to be sent
1028 * @param Timeout Timeout duration
1029 * @retval HAL status
1030 */
HAL_I2C_Master_Transmit(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1031 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1032 {
1033 /* Init tickstart for timeout management*/
1034 uint32_t tickstart = HAL_GetTick();
1035
1036 if (hi2c->State == HAL_I2C_STATE_READY)
1037 {
1038 /* Wait until BUSY flag is reset */
1039 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
1040 {
1041 return HAL_BUSY;
1042 }
1043
1044 /* Process Locked */
1045 __HAL_LOCK(hi2c);
1046
1047 /* Check if the I2C is already enabled */
1048 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1049 {
1050 /* Enable I2C peripheral */
1051 __HAL_I2C_ENABLE(hi2c);
1052 }
1053
1054 /* Disable Pos */
1055 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1056
1057 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1058 hi2c->Mode = HAL_I2C_MODE_MASTER;
1059 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1060
1061 /* Prepare transfer parameters */
1062 hi2c->pBuffPtr = pData;
1063 hi2c->XferCount = Size;
1064 hi2c->XferSize = hi2c->XferCount;
1065 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1066
1067 /* Send Slave Address */
1068 if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
1069 {
1070 return HAL_ERROR;
1071 }
1072
1073 /* Clear ADDR flag */
1074 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1075
1076 while (hi2c->XferSize > 0U)
1077 {
1078 /* Wait until TXE flag is set */
1079 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1080 {
1081 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1082 {
1083 /* Generate Stop */
1084 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1085 }
1086 return HAL_ERROR;
1087 }
1088
1089 /* Write data to DR */
1090 hi2c->Instance->DR = *hi2c->pBuffPtr;
1091
1092 /* Increment Buffer pointer */
1093 hi2c->pBuffPtr++;
1094
1095 /* Update counter */
1096 hi2c->XferCount--;
1097 hi2c->XferSize--;
1098
1099 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
1100 {
1101 /* Write data to DR */
1102 hi2c->Instance->DR = *hi2c->pBuffPtr;
1103
1104 /* Increment Buffer pointer */
1105 hi2c->pBuffPtr++;
1106
1107 /* Update counter */
1108 hi2c->XferCount--;
1109 hi2c->XferSize--;
1110 }
1111
1112 /* Wait until BTF flag is set */
1113 if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1114 {
1115 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1116 {
1117 /* Generate Stop */
1118 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1119 }
1120 return HAL_ERROR;
1121 }
1122 }
1123
1124 /* Generate Stop */
1125 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1126
1127 hi2c->State = HAL_I2C_STATE_READY;
1128 hi2c->Mode = HAL_I2C_MODE_NONE;
1129
1130 /* Process Unlocked */
1131 __HAL_UNLOCK(hi2c);
1132
1133 return HAL_OK;
1134 }
1135 else
1136 {
1137 return HAL_BUSY;
1138 }
1139 }
1140
1141 /**
1142 * @brief Receives in master mode an amount of data in blocking mode.
1143 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1144 * the configuration information for the specified I2C.
1145 * @param DevAddress Target device address: The device 7 bits address value
1146 * in datasheet must be shifted to the left before calling the interface
1147 * @param pData Pointer to data buffer
1148 * @param Size Amount of data to be sent
1149 * @param Timeout Timeout duration
1150 * @retval HAL status
1151 */
HAL_I2C_Master_Receive(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1152 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1153 {
1154 /* Init tickstart for timeout management*/
1155 uint32_t tickstart = HAL_GetTick();
1156
1157 if (hi2c->State == HAL_I2C_STATE_READY)
1158 {
1159 /* Wait until BUSY flag is reset */
1160 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
1161 {
1162 return HAL_BUSY;
1163 }
1164
1165 /* Process Locked */
1166 __HAL_LOCK(hi2c);
1167
1168 /* Check if the I2C is already enabled */
1169 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1170 {
1171 /* Enable I2C peripheral */
1172 __HAL_I2C_ENABLE(hi2c);
1173 }
1174
1175 /* Disable Pos */
1176 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1177
1178 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1179 hi2c->Mode = HAL_I2C_MODE_MASTER;
1180 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1181
1182 /* Prepare transfer parameters */
1183 hi2c->pBuffPtr = pData;
1184 hi2c->XferCount = Size;
1185 hi2c->XferSize = hi2c->XferCount;
1186 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1187
1188 /* Send Slave Address */
1189 if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
1190 {
1191 return HAL_ERROR;
1192 }
1193
1194 if (hi2c->XferSize == 0U)
1195 {
1196 /* Clear ADDR flag */
1197 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1198
1199 /* Generate Stop */
1200 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1201 }
1202 else if (hi2c->XferSize == 1U)
1203 {
1204 /* Disable Acknowledge */
1205 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1206
1207 /* Clear ADDR flag */
1208 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1209
1210 /* Generate Stop */
1211 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1212 }
1213 else if (hi2c->XferSize == 2U)
1214 {
1215 /* Disable Acknowledge */
1216 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1217
1218 /* Enable Pos */
1219 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1220
1221 /* Clear ADDR flag */
1222 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1223 }
1224 else
1225 {
1226 /* Enable Acknowledge */
1227 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1228
1229 /* Clear ADDR flag */
1230 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1231 }
1232
1233 while (hi2c->XferSize > 0U)
1234 {
1235 if (hi2c->XferSize <= 3U)
1236 {
1237 /* One byte */
1238 if (hi2c->XferSize == 1U)
1239 {
1240 /* Wait until RXNE flag is set */
1241 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1242 {
1243 return HAL_ERROR;
1244 }
1245
1246 /* Read data from DR */
1247 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1248
1249 /* Increment Buffer pointer */
1250 hi2c->pBuffPtr++;
1251
1252 /* Update counter */
1253 hi2c->XferSize--;
1254 hi2c->XferCount--;
1255 }
1256 /* Two bytes */
1257 else if (hi2c->XferSize == 2U)
1258 {
1259 /* Wait until BTF flag is set */
1260 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
1261 {
1262 return HAL_ERROR;
1263 }
1264
1265 /* Generate Stop */
1266 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1267
1268 /* Read data from DR */
1269 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1270
1271 /* Increment Buffer pointer */
1272 hi2c->pBuffPtr++;
1273
1274 /* Update counter */
1275 hi2c->XferSize--;
1276 hi2c->XferCount--;
1277
1278 /* Read data from DR */
1279 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1280
1281 /* Increment Buffer pointer */
1282 hi2c->pBuffPtr++;
1283
1284 /* Update counter */
1285 hi2c->XferSize--;
1286 hi2c->XferCount--;
1287 }
1288 /* 3 Last bytes */
1289 else
1290 {
1291 /* Wait until BTF flag is set */
1292 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
1293 {
1294 return HAL_ERROR;
1295 }
1296
1297 /* Disable Acknowledge */
1298 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1299
1300 /* Read data from DR */
1301 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1302
1303 /* Increment Buffer pointer */
1304 hi2c->pBuffPtr++;
1305
1306 /* Update counter */
1307 hi2c->XferSize--;
1308 hi2c->XferCount--;
1309
1310 /* Wait until BTF flag is set */
1311 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
1312 {
1313 return HAL_ERROR;
1314 }
1315
1316 /* Generate Stop */
1317 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1318
1319 /* Read data from DR */
1320 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1321
1322 /* Increment Buffer pointer */
1323 hi2c->pBuffPtr++;
1324
1325 /* Update counter */
1326 hi2c->XferSize--;
1327 hi2c->XferCount--;
1328
1329 /* Read data from DR */
1330 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1331
1332 /* Increment Buffer pointer */
1333 hi2c->pBuffPtr++;
1334
1335 /* Update counter */
1336 hi2c->XferSize--;
1337 hi2c->XferCount--;
1338 }
1339 }
1340 else
1341 {
1342 /* Wait until RXNE flag is set */
1343 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1344 {
1345 return HAL_ERROR;
1346 }
1347
1348 /* Read data from DR */
1349 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1350
1351 /* Increment Buffer pointer */
1352 hi2c->pBuffPtr++;
1353
1354 /* Update counter */
1355 hi2c->XferSize--;
1356 hi2c->XferCount--;
1357
1358 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
1359 {
1360 /* Read data from DR */
1361 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1362
1363 /* Increment Buffer pointer */
1364 hi2c->pBuffPtr++;
1365
1366 /* Update counter */
1367 hi2c->XferSize--;
1368 hi2c->XferCount--;
1369 }
1370 }
1371 }
1372
1373 hi2c->State = HAL_I2C_STATE_READY;
1374 hi2c->Mode = HAL_I2C_MODE_NONE;
1375
1376 /* Process Unlocked */
1377 __HAL_UNLOCK(hi2c);
1378
1379 return HAL_OK;
1380 }
1381 else
1382 {
1383 return HAL_BUSY;
1384 }
1385 }
1386
1387 /**
1388 * @brief Transmits in slave mode an amount of data in blocking mode.
1389 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1390 * the configuration information for the specified I2C.
1391 * @param pData Pointer to data buffer
1392 * @param Size Amount of data to be sent
1393 * @param Timeout Timeout duration
1394 * @retval HAL status
1395 */
HAL_I2C_Slave_Transmit(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1396 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1397 {
1398 /* Init tickstart for timeout management*/
1399 uint32_t tickstart = HAL_GetTick();
1400
1401 if (hi2c->State == HAL_I2C_STATE_READY)
1402 {
1403 if ((pData == NULL) || (Size == 0U))
1404 {
1405 return HAL_ERROR;
1406 }
1407
1408 /* Process Locked */
1409 __HAL_LOCK(hi2c);
1410
1411 /* Check if the I2C is already enabled */
1412 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1413 {
1414 /* Enable I2C peripheral */
1415 __HAL_I2C_ENABLE(hi2c);
1416 }
1417
1418 /* Disable Pos */
1419 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1420
1421 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1422 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1423 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1424
1425 /* Prepare transfer parameters */
1426 hi2c->pBuffPtr = pData;
1427 hi2c->XferCount = Size;
1428 hi2c->XferSize = hi2c->XferCount;
1429 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1430
1431 /* Enable Address Acknowledge */
1432 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1433
1434 /* Wait until ADDR flag is set */
1435 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1436 {
1437 return HAL_ERROR;
1438 }
1439
1440 /* Clear ADDR flag */
1441 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1442
1443 /* If 10bit addressing mode is selected */
1444 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
1445 {
1446 /* Wait until ADDR flag is set */
1447 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1448 {
1449 return HAL_ERROR;
1450 }
1451
1452 /* Clear ADDR flag */
1453 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1454 }
1455
1456 while (hi2c->XferSize > 0U)
1457 {
1458 /* Wait until TXE flag is set */
1459 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1460 {
1461 /* Disable Address Acknowledge */
1462 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1463
1464 return HAL_ERROR;
1465 }
1466
1467 /* Write data to DR */
1468 hi2c->Instance->DR = *hi2c->pBuffPtr;
1469
1470 /* Increment Buffer pointer */
1471 hi2c->pBuffPtr++;
1472
1473 /* Update counter */
1474 hi2c->XferCount--;
1475 hi2c->XferSize--;
1476
1477 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
1478 {
1479 /* Write data to DR */
1480 hi2c->Instance->DR = *hi2c->pBuffPtr;
1481
1482 /* Increment Buffer pointer */
1483 hi2c->pBuffPtr++;
1484
1485 /* Update counter */
1486 hi2c->XferCount--;
1487 hi2c->XferSize--;
1488 }
1489 }
1490
1491 /* Wait until AF flag is set */
1492 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
1493 {
1494 return HAL_ERROR;
1495 }
1496
1497 /* Clear AF flag */
1498 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
1499
1500 /* Disable Address Acknowledge */
1501 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1502
1503 hi2c->State = HAL_I2C_STATE_READY;
1504 hi2c->Mode = HAL_I2C_MODE_NONE;
1505
1506 /* Process Unlocked */
1507 __HAL_UNLOCK(hi2c);
1508
1509 return HAL_OK;
1510 }
1511 else
1512 {
1513 return HAL_BUSY;
1514 }
1515 }
1516
1517 /**
1518 * @brief Receive in slave mode an amount of data in blocking mode
1519 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1520 * the configuration information for the specified I2C.
1521 * @param pData Pointer to data buffer
1522 * @param Size Amount of data to be sent
1523 * @param Timeout Timeout duration
1524 * @retval HAL status
1525 */
HAL_I2C_Slave_Receive(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1526 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1527 {
1528 /* Init tickstart for timeout management*/
1529 uint32_t tickstart = HAL_GetTick();
1530
1531 if (hi2c->State == HAL_I2C_STATE_READY)
1532 {
1533 if ((pData == NULL) || (Size == (uint16_t)0))
1534 {
1535 return HAL_ERROR;
1536 }
1537
1538 /* Process Locked */
1539 __HAL_LOCK(hi2c);
1540
1541 /* Check if the I2C is already enabled */
1542 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1543 {
1544 /* Enable I2C peripheral */
1545 __HAL_I2C_ENABLE(hi2c);
1546 }
1547
1548 /* Disable Pos */
1549 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1550
1551 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1552 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1553 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1554
1555 /* Prepare transfer parameters */
1556 hi2c->pBuffPtr = pData;
1557 hi2c->XferCount = Size;
1558 hi2c->XferSize = hi2c->XferCount;
1559 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1560
1561 /* Enable Address Acknowledge */
1562 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1563
1564 /* Wait until ADDR flag is set */
1565 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1566 {
1567 return HAL_ERROR;
1568 }
1569
1570 /* Clear ADDR flag */
1571 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1572
1573 while (hi2c->XferSize > 0U)
1574 {
1575 /* Wait until RXNE flag is set */
1576 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1577 {
1578 /* Disable Address Acknowledge */
1579 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1580
1581 return HAL_ERROR;
1582 }
1583
1584 /* Read data from DR */
1585 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1586
1587 /* Increment Buffer pointer */
1588 hi2c->pBuffPtr++;
1589
1590 /* Update counter */
1591 hi2c->XferSize--;
1592 hi2c->XferCount--;
1593
1594 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
1595 {
1596 /* Read data from DR */
1597 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1598
1599 /* Increment Buffer pointer */
1600 hi2c->pBuffPtr++;
1601
1602 /* Update counter */
1603 hi2c->XferSize--;
1604 hi2c->XferCount--;
1605 }
1606 }
1607
1608 /* Wait until STOP flag is set */
1609 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1610 {
1611 /* Disable Address Acknowledge */
1612 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1613
1614 return HAL_ERROR;
1615 }
1616
1617 /* Clear STOP flag */
1618 __HAL_I2C_CLEAR_STOPFLAG(hi2c);
1619
1620 /* Disable Address Acknowledge */
1621 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1622
1623 hi2c->State = HAL_I2C_STATE_READY;
1624 hi2c->Mode = HAL_I2C_MODE_NONE;
1625
1626 /* Process Unlocked */
1627 __HAL_UNLOCK(hi2c);
1628
1629 return HAL_OK;
1630 }
1631 else
1632 {
1633 return HAL_BUSY;
1634 }
1635 }
1636
1637 /**
1638 * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
1639 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1640 * the configuration information for the specified I2C.
1641 * @param DevAddress Target device address: The device 7 bits address value
1642 * in datasheet must be shifted to the left before calling the interface
1643 * @param pData Pointer to data buffer
1644 * @param Size Amount of data to be sent
1645 * @retval HAL status
1646 */
HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1647 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1648 {
1649 __IO uint32_t count = 0U;
1650
1651 if (hi2c->State == HAL_I2C_STATE_READY)
1652 {
1653 /* Wait until BUSY flag is reset */
1654 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
1655 do
1656 {
1657 count--;
1658 if (count == 0U)
1659 {
1660 hi2c->PreviousState = I2C_STATE_NONE;
1661 hi2c->State = HAL_I2C_STATE_READY;
1662 hi2c->Mode = HAL_I2C_MODE_NONE;
1663 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
1664
1665 /* Process Unlocked */
1666 __HAL_UNLOCK(hi2c);
1667
1668 return HAL_ERROR;
1669 }
1670 }
1671 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1672
1673 /* Process Locked */
1674 __HAL_LOCK(hi2c);
1675
1676 /* Check if the I2C is already enabled */
1677 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1678 {
1679 /* Enable I2C peripheral */
1680 __HAL_I2C_ENABLE(hi2c);
1681 }
1682
1683 /* Disable Pos */
1684 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1685
1686 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1687 hi2c->Mode = HAL_I2C_MODE_MASTER;
1688 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1689
1690 /* Prepare transfer parameters */
1691 hi2c->pBuffPtr = pData;
1692 hi2c->XferCount = Size;
1693 hi2c->XferSize = hi2c->XferCount;
1694 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1695 hi2c->Devaddress = DevAddress;
1696
1697 /* Process Unlocked */
1698 __HAL_UNLOCK(hi2c);
1699
1700 /* Note : The I2C interrupts must be enabled after unlocking current process
1701 to avoid the risk of I2C interrupt handle execution before current
1702 process unlock */
1703 /* Enable EVT, BUF and ERR interrupt */
1704 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1705
1706 /* Generate Start */
1707 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
1708
1709 return HAL_OK;
1710 }
1711 else
1712 {
1713 return HAL_BUSY;
1714 }
1715 }
1716
1717 /**
1718 * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
1719 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1720 * the configuration information for the specified I2C.
1721 * @param DevAddress Target device address: The device 7 bits address value
1722 * in datasheet must be shifted to the left before calling the interface
1723 * @param pData Pointer to data buffer
1724 * @param Size Amount of data to be sent
1725 * @retval HAL status
1726 */
HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1727 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1728 {
1729 __IO uint32_t count = 0U;
1730
1731 if (hi2c->State == HAL_I2C_STATE_READY)
1732 {
1733 /* Wait until BUSY flag is reset */
1734 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
1735 do
1736 {
1737 count--;
1738 if (count == 0U)
1739 {
1740 hi2c->PreviousState = I2C_STATE_NONE;
1741 hi2c->State = HAL_I2C_STATE_READY;
1742 hi2c->Mode = HAL_I2C_MODE_NONE;
1743 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
1744
1745 /* Process Unlocked */
1746 __HAL_UNLOCK(hi2c);
1747
1748 return HAL_ERROR;
1749 }
1750 }
1751 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1752
1753 /* Process Locked */
1754 __HAL_LOCK(hi2c);
1755
1756 /* Check if the I2C is already enabled */
1757 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1758 {
1759 /* Enable I2C peripheral */
1760 __HAL_I2C_ENABLE(hi2c);
1761 }
1762
1763 /* Disable Pos */
1764 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1765
1766 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1767 hi2c->Mode = HAL_I2C_MODE_MASTER;
1768 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1769
1770 /* Prepare transfer parameters */
1771 hi2c->pBuffPtr = pData;
1772 hi2c->XferCount = Size;
1773 hi2c->XferSize = hi2c->XferCount;
1774 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1775 hi2c->Devaddress = DevAddress;
1776
1777
1778 /* Process Unlocked */
1779 __HAL_UNLOCK(hi2c);
1780
1781 /* Note : The I2C interrupts must be enabled after unlocking current process
1782 to avoid the risk of I2C interrupt handle execution before current
1783 process unlock */
1784
1785 /* Enable EVT, BUF and ERR interrupt */
1786 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1787
1788 /* Enable Acknowledge */
1789 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1790
1791 /* Generate Start */
1792 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
1793
1794 return HAL_OK;
1795 }
1796 else
1797 {
1798 return HAL_BUSY;
1799 }
1800 }
1801
1802 /**
1803 * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
1804 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1805 * the configuration information for the specified I2C.
1806 * @param pData Pointer to data buffer
1807 * @param Size Amount of data to be sent
1808 * @retval HAL status
1809 */
HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1810 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1811 {
1812
1813 if (hi2c->State == HAL_I2C_STATE_READY)
1814 {
1815 if ((pData == NULL) || (Size == 0U))
1816 {
1817 return HAL_ERROR;
1818 }
1819
1820 /* Process Locked */
1821 __HAL_LOCK(hi2c);
1822
1823 /* Check if the I2C is already enabled */
1824 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1825 {
1826 /* Enable I2C peripheral */
1827 __HAL_I2C_ENABLE(hi2c);
1828 }
1829
1830 /* Disable Pos */
1831 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1832
1833 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1834 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1835 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1836
1837 /* Prepare transfer parameters */
1838 hi2c->pBuffPtr = pData;
1839 hi2c->XferCount = Size;
1840 hi2c->XferSize = hi2c->XferCount;
1841 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1842
1843 /* Enable Address Acknowledge */
1844 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1845
1846 /* Process Unlocked */
1847 __HAL_UNLOCK(hi2c);
1848
1849 /* Note : The I2C interrupts must be enabled after unlocking current process
1850 to avoid the risk of I2C interrupt handle execution before current
1851 process unlock */
1852
1853 /* Enable EVT, BUF and ERR interrupt */
1854 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1855
1856 return HAL_OK;
1857 }
1858 else
1859 {
1860 return HAL_BUSY;
1861 }
1862 }
1863
1864 /**
1865 * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
1866 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1867 * the configuration information for the specified I2C.
1868 * @param pData Pointer to data buffer
1869 * @param Size Amount of data to be sent
1870 * @retval HAL status
1871 */
HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1872 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1873 {
1874
1875 if (hi2c->State == HAL_I2C_STATE_READY)
1876 {
1877 if ((pData == NULL) || (Size == 0U))
1878 {
1879 return HAL_ERROR;
1880 }
1881
1882 /* Process Locked */
1883 __HAL_LOCK(hi2c);
1884
1885 /* Check if the I2C is already enabled */
1886 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1887 {
1888 /* Enable I2C peripheral */
1889 __HAL_I2C_ENABLE(hi2c);
1890 }
1891
1892 /* Disable Pos */
1893 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1894
1895 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1896 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1897 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1898
1899 /* Prepare transfer parameters */
1900 hi2c->pBuffPtr = pData;
1901 hi2c->XferCount = Size;
1902 hi2c->XferSize = hi2c->XferCount;
1903 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1904
1905 /* Enable Address Acknowledge */
1906 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1907
1908 /* Process Unlocked */
1909 __HAL_UNLOCK(hi2c);
1910
1911 /* Note : The I2C interrupts must be enabled after unlocking current process
1912 to avoid the risk of I2C interrupt handle execution before current
1913 process unlock */
1914
1915 /* Enable EVT, BUF and ERR interrupt */
1916 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1917
1918 return HAL_OK;
1919 }
1920 else
1921 {
1922 return HAL_BUSY;
1923 }
1924 }
1925
1926 /**
1927 * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
1928 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1929 * the configuration information for the specified I2C.
1930 * @param DevAddress Target device address: The device 7 bits address value
1931 * in datasheet must be shifted to the left before calling the interface
1932 * @param pData Pointer to data buffer
1933 * @param Size Amount of data to be sent
1934 * @retval HAL status
1935 */
HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1936 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1937 {
1938 __IO uint32_t count = 0U;
1939 HAL_StatusTypeDef dmaxferstatus;
1940
1941 if (hi2c->State == HAL_I2C_STATE_READY)
1942 {
1943 /* Wait until BUSY flag is reset */
1944 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
1945 do
1946 {
1947 count--;
1948 if (count == 0U)
1949 {
1950 hi2c->PreviousState = I2C_STATE_NONE;
1951 hi2c->State = HAL_I2C_STATE_READY;
1952 hi2c->Mode = HAL_I2C_MODE_NONE;
1953 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
1954
1955 /* Process Unlocked */
1956 __HAL_UNLOCK(hi2c);
1957
1958 return HAL_ERROR;
1959 }
1960 }
1961 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1962
1963 /* Process Locked */
1964 __HAL_LOCK(hi2c);
1965
1966 /* Check if the I2C is already enabled */
1967 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1968 {
1969 /* Enable I2C peripheral */
1970 __HAL_I2C_ENABLE(hi2c);
1971 }
1972
1973 /* Disable Pos */
1974 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1975
1976 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1977 hi2c->Mode = HAL_I2C_MODE_MASTER;
1978 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1979
1980 /* Prepare transfer parameters */
1981 hi2c->pBuffPtr = pData;
1982 hi2c->XferCount = Size;
1983 hi2c->XferSize = hi2c->XferCount;
1984 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1985 hi2c->Devaddress = DevAddress;
1986
1987 if (hi2c->XferSize > 0U)
1988 {
1989 if (hi2c->hdmatx != NULL)
1990 {
1991 /* Set the I2C DMA transfer complete callback */
1992 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
1993
1994 /* Set the DMA error callback */
1995 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
1996
1997 /* Set the unused DMA callbacks to NULL */
1998 hi2c->hdmatx->XferHalfCpltCallback = NULL;
1999 hi2c->hdmatx->XferM1CpltCallback = NULL;
2000 hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
2001 hi2c->hdmatx->XferAbortCallback = NULL;
2002
2003 /* Enable the DMA stream */
2004 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
2005 }
2006 else
2007 {
2008 /* Update I2C state */
2009 hi2c->State = HAL_I2C_STATE_READY;
2010 hi2c->Mode = HAL_I2C_MODE_NONE;
2011
2012 /* Update I2C error code */
2013 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2014
2015 /* Process Unlocked */
2016 __HAL_UNLOCK(hi2c);
2017
2018 return HAL_ERROR;
2019 }
2020
2021 if (dmaxferstatus == HAL_OK)
2022 {
2023 /* Process Unlocked */
2024 __HAL_UNLOCK(hi2c);
2025
2026 /* Note : The I2C interrupts must be enabled after unlocking current process
2027 to avoid the risk of I2C interrupt handle execution before current
2028 process unlock */
2029
2030 /* Enable EVT and ERR interrupt */
2031 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2032
2033 /* Enable DMA Request */
2034 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
2035
2036 /* Enable Acknowledge */
2037 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2038
2039 /* Generate Start */
2040 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2041 }
2042 else
2043 {
2044 /* Update I2C state */
2045 hi2c->State = HAL_I2C_STATE_READY;
2046 hi2c->Mode = HAL_I2C_MODE_NONE;
2047
2048 /* Update I2C error code */
2049 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2050
2051 /* Process Unlocked */
2052 __HAL_UNLOCK(hi2c);
2053
2054 return HAL_ERROR;
2055 }
2056 }
2057 else
2058 {
2059 /* Enable Acknowledge */
2060 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2061
2062 /* Generate Start */
2063 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2064
2065 /* Process Unlocked */
2066 __HAL_UNLOCK(hi2c);
2067
2068 /* Note : The I2C interrupts must be enabled after unlocking current process
2069 to avoid the risk of I2C interrupt handle execution before current
2070 process unlock */
2071
2072 /* Enable EVT, BUF and ERR interrupt */
2073 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2074 }
2075
2076 return HAL_OK;
2077 }
2078 else
2079 {
2080 return HAL_BUSY;
2081 }
2082 }
2083
2084 /**
2085 * @brief Receive in master mode an amount of data in non-blocking mode with DMA
2086 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2087 * the configuration information for the specified I2C.
2088 * @param DevAddress Target device address: The device 7 bits address value
2089 * in datasheet must be shifted to the left before calling the interface
2090 * @param pData Pointer to data buffer
2091 * @param Size Amount of data to be sent
2092 * @retval HAL status
2093 */
HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)2094 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
2095 {
2096 __IO uint32_t count = 0U;
2097 HAL_StatusTypeDef dmaxferstatus;
2098
2099 if (hi2c->State == HAL_I2C_STATE_READY)
2100 {
2101 /* Wait until BUSY flag is reset */
2102 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
2103 do
2104 {
2105 count--;
2106 if (count == 0U)
2107 {
2108 hi2c->PreviousState = I2C_STATE_NONE;
2109 hi2c->State = HAL_I2C_STATE_READY;
2110 hi2c->Mode = HAL_I2C_MODE_NONE;
2111 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
2112
2113 /* Process Unlocked */
2114 __HAL_UNLOCK(hi2c);
2115
2116 return HAL_ERROR;
2117 }
2118 }
2119 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2120
2121 /* Process Locked */
2122 __HAL_LOCK(hi2c);
2123
2124 /* Check if the I2C is already enabled */
2125 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2126 {
2127 /* Enable I2C peripheral */
2128 __HAL_I2C_ENABLE(hi2c);
2129 }
2130
2131 /* Disable Pos */
2132 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2133
2134 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2135 hi2c->Mode = HAL_I2C_MODE_MASTER;
2136 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2137
2138 /* Prepare transfer parameters */
2139 hi2c->pBuffPtr = pData;
2140 hi2c->XferCount = Size;
2141 hi2c->XferSize = hi2c->XferCount;
2142 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2143 hi2c->Devaddress = DevAddress;
2144
2145 if (hi2c->XferSize > 0U)
2146 {
2147 if (hi2c->hdmarx != NULL)
2148 {
2149 /* Set the I2C DMA transfer complete callback */
2150 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
2151
2152 /* Set the DMA error callback */
2153 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2154
2155 /* Set the unused DMA callbacks to NULL */
2156 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2157 hi2c->hdmarx->XferM1CpltCallback = NULL;
2158 hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
2159 hi2c->hdmarx->XferAbortCallback = NULL;
2160
2161 /* Enable the DMA stream */
2162 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
2163 }
2164 else
2165 {
2166 /* Update I2C state */
2167 hi2c->State = HAL_I2C_STATE_READY;
2168 hi2c->Mode = HAL_I2C_MODE_NONE;
2169
2170 /* Update I2C error code */
2171 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2172
2173 /* Process Unlocked */
2174 __HAL_UNLOCK(hi2c);
2175
2176 return HAL_ERROR;
2177 }
2178
2179 if (dmaxferstatus == HAL_OK)
2180 {
2181 /* Enable Acknowledge */
2182 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2183
2184 /* Generate Start */
2185 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2186
2187 /* Process Unlocked */
2188 __HAL_UNLOCK(hi2c);
2189
2190 /* Note : The I2C interrupts must be enabled after unlocking current process
2191 to avoid the risk of I2C interrupt handle execution before current
2192 process unlock */
2193
2194 /* Enable EVT and ERR interrupt */
2195 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2196
2197 /* Enable DMA Request */
2198 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
2199 }
2200 else
2201 {
2202 /* Update I2C state */
2203 hi2c->State = HAL_I2C_STATE_READY;
2204 hi2c->Mode = HAL_I2C_MODE_NONE;
2205
2206 /* Update I2C error code */
2207 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2208
2209 /* Process Unlocked */
2210 __HAL_UNLOCK(hi2c);
2211
2212 return HAL_ERROR;
2213 }
2214 }
2215 else
2216 {
2217 /* Process Unlocked */
2218 __HAL_UNLOCK(hi2c);
2219
2220 /* Note : The I2C interrupts must be enabled after unlocking current process
2221 to avoid the risk of I2C interrupt handle execution before current
2222 process unlock */
2223
2224 /* Enable EVT, BUF and ERR interrupt */
2225 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2226
2227 /* Enable Acknowledge */
2228 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2229
2230 /* Generate Start */
2231 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2232 }
2233
2234 return HAL_OK;
2235 }
2236 else
2237 {
2238 return HAL_BUSY;
2239 }
2240 }
2241
2242 /**
2243 * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
2244 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2245 * the configuration information for the specified I2C.
2246 * @param pData Pointer to data buffer
2247 * @param Size Amount of data to be sent
2248 * @retval HAL status
2249 */
HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2250 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2251 {
2252 HAL_StatusTypeDef dmaxferstatus;
2253
2254 if (hi2c->State == HAL_I2C_STATE_READY)
2255 {
2256 if ((pData == NULL) || (Size == 0U))
2257 {
2258 return HAL_ERROR;
2259 }
2260
2261 /* Process Locked */
2262 __HAL_LOCK(hi2c);
2263
2264 /* Check if the I2C is already enabled */
2265 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2266 {
2267 /* Enable I2C peripheral */
2268 __HAL_I2C_ENABLE(hi2c);
2269 }
2270
2271 /* Disable Pos */
2272 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2273
2274 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2275 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2276 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2277
2278 /* Prepare transfer parameters */
2279 hi2c->pBuffPtr = pData;
2280 hi2c->XferCount = Size;
2281 hi2c->XferSize = hi2c->XferCount;
2282 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2283
2284 if (hi2c->hdmatx != NULL)
2285 {
2286 /* Set the I2C DMA transfer complete callback */
2287 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
2288
2289 /* Set the DMA error callback */
2290 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2291
2292 /* Set the unused DMA callbacks to NULL */
2293 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2294 hi2c->hdmatx->XferM1CpltCallback = NULL;
2295 hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
2296 hi2c->hdmatx->XferAbortCallback = NULL;
2297
2298 /* Enable the DMA stream */
2299 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
2300 }
2301 else
2302 {
2303 /* Update I2C state */
2304 hi2c->State = HAL_I2C_STATE_LISTEN;
2305 hi2c->Mode = HAL_I2C_MODE_NONE;
2306
2307 /* Update I2C error code */
2308 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2309
2310 /* Process Unlocked */
2311 __HAL_UNLOCK(hi2c);
2312
2313 return HAL_ERROR;
2314 }
2315
2316 if (dmaxferstatus == HAL_OK)
2317 {
2318 /* Enable Address Acknowledge */
2319 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2320
2321 /* Process Unlocked */
2322 __HAL_UNLOCK(hi2c);
2323
2324 /* Note : The I2C interrupts must be enabled after unlocking current process
2325 to avoid the risk of I2C interrupt handle execution before current
2326 process unlock */
2327 /* Enable EVT and ERR interrupt */
2328 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2329
2330 /* Enable DMA Request */
2331 hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
2332
2333 return HAL_OK;
2334 }
2335 else
2336 {
2337 /* Update I2C state */
2338 hi2c->State = HAL_I2C_STATE_READY;
2339 hi2c->Mode = HAL_I2C_MODE_NONE;
2340
2341 /* Update I2C error code */
2342 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2343
2344 /* Process Unlocked */
2345 __HAL_UNLOCK(hi2c);
2346
2347 return HAL_ERROR;
2348 }
2349 }
2350 else
2351 {
2352 return HAL_BUSY;
2353 }
2354 }
2355
2356 /**
2357 * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
2358 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2359 * the configuration information for the specified I2C.
2360 * @param pData Pointer to data buffer
2361 * @param Size Amount of data to be sent
2362 * @retval HAL status
2363 */
HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2364 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2365 {
2366 HAL_StatusTypeDef dmaxferstatus;
2367
2368 if (hi2c->State == HAL_I2C_STATE_READY)
2369 {
2370 if ((pData == NULL) || (Size == 0U))
2371 {
2372 return HAL_ERROR;
2373 }
2374
2375 /* Process Locked */
2376 __HAL_LOCK(hi2c);
2377
2378 /* Check if the I2C is already enabled */
2379 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2380 {
2381 /* Enable I2C peripheral */
2382 __HAL_I2C_ENABLE(hi2c);
2383 }
2384
2385 /* Disable Pos */
2386 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2387
2388 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2389 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2390 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2391
2392 /* Prepare transfer parameters */
2393 hi2c->pBuffPtr = pData;
2394 hi2c->XferCount = Size;
2395 hi2c->XferSize = hi2c->XferCount;
2396 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2397
2398 if (hi2c->hdmarx != NULL)
2399 {
2400 /* Set the I2C DMA transfer complete callback */
2401 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
2402
2403 /* Set the DMA error callback */
2404 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2405
2406 /* Set the unused DMA callbacks to NULL */
2407 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2408 hi2c->hdmarx->XferM1CpltCallback = NULL;
2409 hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
2410 hi2c->hdmarx->XferAbortCallback = NULL;
2411
2412 /* Enable the DMA stream */
2413 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
2414 }
2415 else
2416 {
2417 /* Update I2C state */
2418 hi2c->State = HAL_I2C_STATE_LISTEN;
2419 hi2c->Mode = HAL_I2C_MODE_NONE;
2420
2421 /* Update I2C error code */
2422 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2423
2424 /* Process Unlocked */
2425 __HAL_UNLOCK(hi2c);
2426
2427 return HAL_ERROR;
2428 }
2429
2430 if (dmaxferstatus == HAL_OK)
2431 {
2432 /* Enable Address Acknowledge */
2433 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2434
2435 /* Process Unlocked */
2436 __HAL_UNLOCK(hi2c);
2437
2438 /* Note : The I2C interrupts must be enabled after unlocking current process
2439 to avoid the risk of I2C interrupt handle execution before current
2440 process unlock */
2441 /* Enable EVT and ERR interrupt */
2442 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2443
2444 /* Enable DMA Request */
2445 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
2446
2447 return HAL_OK;
2448 }
2449 else
2450 {
2451 /* Update I2C state */
2452 hi2c->State = HAL_I2C_STATE_READY;
2453 hi2c->Mode = HAL_I2C_MODE_NONE;
2454
2455 /* Update I2C error code */
2456 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2457
2458 /* Process Unlocked */
2459 __HAL_UNLOCK(hi2c);
2460
2461 return HAL_ERROR;
2462 }
2463 }
2464 else
2465 {
2466 return HAL_BUSY;
2467 }
2468 }
2469
2470 /**
2471 * @brief Write an amount of data in blocking mode to a specific memory address
2472 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2473 * the configuration information for the specified I2C.
2474 * @param DevAddress Target device address: The device 7 bits address value
2475 * in datasheet must be shifted to the left before calling the interface
2476 * @param MemAddress Internal memory address
2477 * @param MemAddSize Size of internal memory address
2478 * @param pData Pointer to data buffer
2479 * @param Size Amount of data to be sent
2480 * @param Timeout Timeout duration
2481 * @retval HAL status
2482 */
HAL_I2C_Mem_Write(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2483 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2484 {
2485 /* Init tickstart for timeout management*/
2486 uint32_t tickstart = HAL_GetTick();
2487
2488 /* Check the parameters */
2489 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2490
2491 if (hi2c->State == HAL_I2C_STATE_READY)
2492 {
2493 /* Wait until BUSY flag is reset */
2494 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
2495 {
2496 return HAL_BUSY;
2497 }
2498
2499 /* Process Locked */
2500 __HAL_LOCK(hi2c);
2501
2502 /* Check if the I2C is already enabled */
2503 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2504 {
2505 /* Enable I2C peripheral */
2506 __HAL_I2C_ENABLE(hi2c);
2507 }
2508
2509 /* Disable Pos */
2510 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2511
2512 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2513 hi2c->Mode = HAL_I2C_MODE_MEM;
2514 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2515
2516 /* Prepare transfer parameters */
2517 hi2c->pBuffPtr = pData;
2518 hi2c->XferCount = Size;
2519 hi2c->XferSize = hi2c->XferCount;
2520 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2521
2522 /* Send Slave Address and Memory Address */
2523 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2524 {
2525 return HAL_ERROR;
2526 }
2527
2528 while (hi2c->XferSize > 0U)
2529 {
2530 /* Wait until TXE flag is set */
2531 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2532 {
2533 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2534 {
2535 /* Generate Stop */
2536 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2537 }
2538 return HAL_ERROR;
2539 }
2540
2541 /* Write data to DR */
2542 hi2c->Instance->DR = *hi2c->pBuffPtr;
2543
2544 /* Increment Buffer pointer */
2545 hi2c->pBuffPtr++;
2546
2547 /* Update counter */
2548 hi2c->XferSize--;
2549 hi2c->XferCount--;
2550
2551 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
2552 {
2553 /* Write data to DR */
2554 hi2c->Instance->DR = *hi2c->pBuffPtr;
2555
2556 /* Increment Buffer pointer */
2557 hi2c->pBuffPtr++;
2558
2559 /* Update counter */
2560 hi2c->XferSize--;
2561 hi2c->XferCount--;
2562 }
2563 }
2564
2565 /* Wait until BTF flag is set */
2566 if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2567 {
2568 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2569 {
2570 /* Generate Stop */
2571 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2572 }
2573 return HAL_ERROR;
2574 }
2575
2576 /* Generate Stop */
2577 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2578
2579 hi2c->State = HAL_I2C_STATE_READY;
2580 hi2c->Mode = HAL_I2C_MODE_NONE;
2581
2582 /* Process Unlocked */
2583 __HAL_UNLOCK(hi2c);
2584
2585 return HAL_OK;
2586 }
2587 else
2588 {
2589 return HAL_BUSY;
2590 }
2591 }
2592
2593 /**
2594 * @brief Read an amount of data in blocking mode from a specific memory address
2595 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2596 * the configuration information for the specified I2C.
2597 * @param DevAddress Target device address: The device 7 bits address value
2598 * in datasheet must be shifted to the left before calling the interface
2599 * @param MemAddress Internal memory address
2600 * @param MemAddSize Size of internal memory address
2601 * @param pData Pointer to data buffer
2602 * @param Size Amount of data to be sent
2603 * @param Timeout Timeout duration
2604 * @retval HAL status
2605 */
HAL_I2C_Mem_Read(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2606 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2607 {
2608 /* Init tickstart for timeout management*/
2609 uint32_t tickstart = HAL_GetTick();
2610
2611 /* Check the parameters */
2612 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2613
2614 if (hi2c->State == HAL_I2C_STATE_READY)
2615 {
2616 /* Wait until BUSY flag is reset */
2617 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
2618 {
2619 return HAL_BUSY;
2620 }
2621
2622 /* Process Locked */
2623 __HAL_LOCK(hi2c);
2624
2625 /* Check if the I2C is already enabled */
2626 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2627 {
2628 /* Enable I2C peripheral */
2629 __HAL_I2C_ENABLE(hi2c);
2630 }
2631
2632 /* Disable Pos */
2633 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2634
2635 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2636 hi2c->Mode = HAL_I2C_MODE_MEM;
2637 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2638
2639 /* Prepare transfer parameters */
2640 hi2c->pBuffPtr = pData;
2641 hi2c->XferCount = Size;
2642 hi2c->XferSize = hi2c->XferCount;
2643 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2644
2645 /* Send Slave Address and Memory Address */
2646 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2647 {
2648 return HAL_ERROR;
2649 }
2650
2651 if (hi2c->XferSize == 0U)
2652 {
2653 /* Clear ADDR flag */
2654 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2655
2656 /* Generate Stop */
2657 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2658 }
2659 else if (hi2c->XferSize == 1U)
2660 {
2661 /* Disable Acknowledge */
2662 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2663
2664 /* Clear ADDR flag */
2665 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2666
2667 /* Generate Stop */
2668 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2669 }
2670 else if (hi2c->XferSize == 2U)
2671 {
2672 /* Disable Acknowledge */
2673 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2674
2675 /* Enable Pos */
2676 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2677
2678 /* Clear ADDR flag */
2679 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2680 }
2681 else
2682 {
2683 /* Clear ADDR flag */
2684 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2685 }
2686
2687 while (hi2c->XferSize > 0U)
2688 {
2689 if (hi2c->XferSize <= 3U)
2690 {
2691 /* One byte */
2692 if (hi2c->XferSize == 1U)
2693 {
2694 /* Wait until RXNE flag is set */
2695 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2696 {
2697 return HAL_ERROR;
2698 }
2699
2700 /* Read data from DR */
2701 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2702
2703 /* Increment Buffer pointer */
2704 hi2c->pBuffPtr++;
2705
2706 /* Update counter */
2707 hi2c->XferSize--;
2708 hi2c->XferCount--;
2709 }
2710 /* Two bytes */
2711 else if (hi2c->XferSize == 2U)
2712 {
2713 /* Wait until BTF flag is set */
2714 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
2715 {
2716 return HAL_ERROR;
2717 }
2718
2719 /* Generate Stop */
2720 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2721
2722 /* Read data from DR */
2723 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2724
2725 /* Increment Buffer pointer */
2726 hi2c->pBuffPtr++;
2727
2728 /* Update counter */
2729 hi2c->XferSize--;
2730 hi2c->XferCount--;
2731
2732 /* Read data from DR */
2733 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2734
2735 /* Increment Buffer pointer */
2736 hi2c->pBuffPtr++;
2737
2738 /* Update counter */
2739 hi2c->XferSize--;
2740 hi2c->XferCount--;
2741 }
2742 /* 3 Last bytes */
2743 else
2744 {
2745 /* Wait until BTF flag is set */
2746 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
2747 {
2748 return HAL_ERROR;
2749 }
2750
2751 /* Disable Acknowledge */
2752 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2753
2754 /* Read data from DR */
2755 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2756
2757 /* Increment Buffer pointer */
2758 hi2c->pBuffPtr++;
2759
2760 /* Update counter */
2761 hi2c->XferSize--;
2762 hi2c->XferCount--;
2763
2764 /* Wait until BTF flag is set */
2765 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
2766 {
2767 return HAL_ERROR;
2768 }
2769
2770 /* Generate Stop */
2771 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2772
2773 /* Read data from DR */
2774 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2775
2776 /* Increment Buffer pointer */
2777 hi2c->pBuffPtr++;
2778
2779 /* Update counter */
2780 hi2c->XferSize--;
2781 hi2c->XferCount--;
2782
2783 /* Read data from DR */
2784 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2785
2786 /* Increment Buffer pointer */
2787 hi2c->pBuffPtr++;
2788
2789 /* Update counter */
2790 hi2c->XferSize--;
2791 hi2c->XferCount--;
2792 }
2793 }
2794 else
2795 {
2796 /* Wait until RXNE flag is set */
2797 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2798 {
2799 return HAL_ERROR;
2800 }
2801
2802 /* Read data from DR */
2803 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2804
2805 /* Increment Buffer pointer */
2806 hi2c->pBuffPtr++;
2807
2808 /* Update counter */
2809 hi2c->XferSize--;
2810 hi2c->XferCount--;
2811
2812 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
2813 {
2814 /* Read data from DR */
2815 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2816
2817 /* Increment Buffer pointer */
2818 hi2c->pBuffPtr++;
2819
2820 /* Update counter */
2821 hi2c->XferSize--;
2822 hi2c->XferCount--;
2823 }
2824 }
2825 }
2826
2827 hi2c->State = HAL_I2C_STATE_READY;
2828 hi2c->Mode = HAL_I2C_MODE_NONE;
2829
2830 /* Process Unlocked */
2831 __HAL_UNLOCK(hi2c);
2832
2833 return HAL_OK;
2834 }
2835 else
2836 {
2837 return HAL_BUSY;
2838 }
2839 }
2840
2841 /**
2842 * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
2843 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2844 * the configuration information for the specified I2C.
2845 * @param DevAddress Target device address: The device 7 bits address value
2846 * in datasheet must be shifted to the left before calling the interface
2847 * @param MemAddress Internal memory address
2848 * @param MemAddSize Size of internal memory address
2849 * @param pData Pointer to data buffer
2850 * @param Size Amount of data to be sent
2851 * @retval HAL status
2852 */
HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2853 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2854 {
2855 __IO uint32_t count = 0U;
2856
2857 /* Check the parameters */
2858 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2859
2860 if (hi2c->State == HAL_I2C_STATE_READY)
2861 {
2862 /* Wait until BUSY flag is reset */
2863 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
2864 do
2865 {
2866 count--;
2867 if (count == 0U)
2868 {
2869 hi2c->PreviousState = I2C_STATE_NONE;
2870 hi2c->State = HAL_I2C_STATE_READY;
2871 hi2c->Mode = HAL_I2C_MODE_NONE;
2872 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
2873
2874 /* Process Unlocked */
2875 __HAL_UNLOCK(hi2c);
2876
2877 return HAL_ERROR;
2878 }
2879 }
2880 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2881
2882 /* Process Locked */
2883 __HAL_LOCK(hi2c);
2884
2885 /* Check if the I2C is already enabled */
2886 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2887 {
2888 /* Enable I2C peripheral */
2889 __HAL_I2C_ENABLE(hi2c);
2890 }
2891
2892 /* Disable Pos */
2893 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2894
2895 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2896 hi2c->Mode = HAL_I2C_MODE_MEM;
2897 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2898
2899 /* Prepare transfer parameters */
2900 hi2c->pBuffPtr = pData;
2901 hi2c->XferCount = Size;
2902 hi2c->XferSize = hi2c->XferCount;
2903 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2904 hi2c->Devaddress = DevAddress;
2905 hi2c->Memaddress = MemAddress;
2906 hi2c->MemaddSize = MemAddSize;
2907 hi2c->EventCount = 0U;
2908
2909 /* Generate Start */
2910 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2911
2912 /* Process Unlocked */
2913 __HAL_UNLOCK(hi2c);
2914
2915 /* Note : The I2C interrupts must be enabled after unlocking current process
2916 to avoid the risk of I2C interrupt handle execution before current
2917 process unlock */
2918
2919 /* Enable EVT, BUF and ERR interrupt */
2920 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2921
2922 return HAL_OK;
2923 }
2924 else
2925 {
2926 return HAL_BUSY;
2927 }
2928 }
2929
2930 /**
2931 * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
2932 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2933 * the configuration information for the specified I2C.
2934 * @param DevAddress Target device address
2935 * @param MemAddress Internal memory address
2936 * @param MemAddSize Size of internal memory address
2937 * @param pData Pointer to data buffer
2938 * @param Size Amount of data to be sent
2939 * @retval HAL status
2940 */
HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2941 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2942 {
2943 __IO uint32_t count = 0U;
2944
2945 /* Check the parameters */
2946 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2947
2948 if (hi2c->State == HAL_I2C_STATE_READY)
2949 {
2950 /* Wait until BUSY flag is reset */
2951 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
2952 do
2953 {
2954 count--;
2955 if (count == 0U)
2956 {
2957 hi2c->PreviousState = I2C_STATE_NONE;
2958 hi2c->State = HAL_I2C_STATE_READY;
2959 hi2c->Mode = HAL_I2C_MODE_NONE;
2960 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
2961
2962 /* Process Unlocked */
2963 __HAL_UNLOCK(hi2c);
2964
2965 return HAL_ERROR;
2966 }
2967 }
2968 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2969
2970 /* Process Locked */
2971 __HAL_LOCK(hi2c);
2972
2973 /* Check if the I2C is already enabled */
2974 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2975 {
2976 /* Enable I2C peripheral */
2977 __HAL_I2C_ENABLE(hi2c);
2978 }
2979
2980 /* Disable Pos */
2981 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2982
2983 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2984 hi2c->Mode = HAL_I2C_MODE_MEM;
2985 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2986
2987 /* Prepare transfer parameters */
2988 hi2c->pBuffPtr = pData;
2989 hi2c->XferCount = Size;
2990 hi2c->XferSize = hi2c->XferCount;
2991 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2992 hi2c->Devaddress = DevAddress;
2993 hi2c->Memaddress = MemAddress;
2994 hi2c->MemaddSize = MemAddSize;
2995 hi2c->EventCount = 0U;
2996
2997 /* Enable Acknowledge */
2998 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2999
3000 /* Generate Start */
3001 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3002
3003 /* Process Unlocked */
3004 __HAL_UNLOCK(hi2c);
3005
3006 if (hi2c->XferSize > 0U)
3007 {
3008 /* Note : The I2C interrupts must be enabled after unlocking current process
3009 to avoid the risk of I2C interrupt handle execution before current
3010 process unlock */
3011
3012 /* Enable EVT, BUF and ERR interrupt */
3013 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3014 }
3015 return HAL_OK;
3016 }
3017 else
3018 {
3019 return HAL_BUSY;
3020 }
3021 }
3022
3023 /**
3024 * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
3025 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3026 * the configuration information for the specified I2C.
3027 * @param DevAddress Target device address: The device 7 bits address value
3028 * in datasheet must be shifted to the left before calling the interface
3029 * @param MemAddress Internal memory address
3030 * @param MemAddSize Size of internal memory address
3031 * @param pData Pointer to data buffer
3032 * @param Size Amount of data to be sent
3033 * @retval HAL status
3034 */
HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)3035 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3036 {
3037 __IO uint32_t count = 0U;
3038 HAL_StatusTypeDef dmaxferstatus;
3039
3040 /* Init tickstart for timeout management*/
3041 uint32_t tickstart = HAL_GetTick();
3042
3043 /* Check the parameters */
3044 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3045
3046 if (hi2c->State == HAL_I2C_STATE_READY)
3047 {
3048 /* Wait until BUSY flag is reset */
3049 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3050 do
3051 {
3052 count--;
3053 if (count == 0U)
3054 {
3055 hi2c->PreviousState = I2C_STATE_NONE;
3056 hi2c->State = HAL_I2C_STATE_READY;
3057 hi2c->Mode = HAL_I2C_MODE_NONE;
3058 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3059
3060 /* Process Unlocked */
3061 __HAL_UNLOCK(hi2c);
3062
3063 return HAL_ERROR;
3064 }
3065 }
3066 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3067
3068 /* Process Locked */
3069 __HAL_LOCK(hi2c);
3070
3071 /* Check if the I2C is already enabled */
3072 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3073 {
3074 /* Enable I2C peripheral */
3075 __HAL_I2C_ENABLE(hi2c);
3076 }
3077
3078 /* Disable Pos */
3079 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3080
3081 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3082 hi2c->Mode = HAL_I2C_MODE_MEM;
3083 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3084
3085 /* Prepare transfer parameters */
3086 hi2c->pBuffPtr = pData;
3087 hi2c->XferCount = Size;
3088 hi2c->XferSize = hi2c->XferCount;
3089 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3090 hi2c->Devaddress = DevAddress;
3091 hi2c->Memaddress = MemAddress;
3092 hi2c->MemaddSize = MemAddSize;
3093 hi2c->EventCount = 0U;
3094
3095 if (hi2c->XferSize > 0U)
3096 {
3097 if (hi2c->hdmatx != NULL)
3098 {
3099 /* Set the I2C DMA transfer complete callback */
3100 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
3101
3102 /* Set the DMA error callback */
3103 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3104
3105 /* Set the unused DMA callbacks to NULL */
3106 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3107 hi2c->hdmatx->XferM1CpltCallback = NULL;
3108 hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
3109 hi2c->hdmatx->XferAbortCallback = NULL;
3110
3111 /* Enable the DMA stream */
3112 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
3113 }
3114 else
3115 {
3116 /* Update I2C state */
3117 hi2c->State = HAL_I2C_STATE_READY;
3118 hi2c->Mode = HAL_I2C_MODE_NONE;
3119
3120 /* Update I2C error code */
3121 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3122
3123 /* Process Unlocked */
3124 __HAL_UNLOCK(hi2c);
3125
3126 return HAL_ERROR;
3127 }
3128
3129 if (dmaxferstatus == HAL_OK)
3130 {
3131 /* Send Slave Address and Memory Address */
3132 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
3133 {
3134 /* Abort the ongoing DMA */
3135 dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmatx);
3136
3137 /* Prevent unused argument(s) compilation and MISRA warning */
3138 UNUSED(dmaxferstatus);
3139
3140 /* Set the unused I2C DMA transfer complete callback to NULL */
3141 hi2c->hdmatx->XferCpltCallback = NULL;
3142
3143 /* Disable Acknowledge */
3144 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3145
3146 hi2c->XferSize = 0U;
3147 hi2c->XferCount = 0U;
3148
3149 /* Disable I2C peripheral to prevent dummy data in buffer */
3150 __HAL_I2C_DISABLE(hi2c);
3151
3152 return HAL_ERROR;
3153 }
3154
3155 /* Clear ADDR flag */
3156 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3157
3158 /* Process Unlocked */
3159 __HAL_UNLOCK(hi2c);
3160
3161 /* Note : The I2C interrupts must be enabled after unlocking current process
3162 to avoid the risk of I2C interrupt handle execution before current
3163 process unlock */
3164 /* Enable ERR interrupt */
3165 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
3166
3167 /* Enable DMA Request */
3168 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
3169
3170 return HAL_OK;
3171 }
3172 else
3173 {
3174 /* Update I2C state */
3175 hi2c->State = HAL_I2C_STATE_READY;
3176 hi2c->Mode = HAL_I2C_MODE_NONE;
3177
3178 /* Update I2C error code */
3179 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3180
3181 /* Process Unlocked */
3182 __HAL_UNLOCK(hi2c);
3183
3184 return HAL_ERROR;
3185 }
3186 }
3187 else
3188 {
3189 /* Update I2C state */
3190 hi2c->State = HAL_I2C_STATE_READY;
3191 hi2c->Mode = HAL_I2C_MODE_NONE;
3192
3193 /* Update I2C error code */
3194 hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;
3195
3196 /* Process Unlocked */
3197 __HAL_UNLOCK(hi2c);
3198
3199 return HAL_ERROR;
3200 }
3201 }
3202 else
3203 {
3204 return HAL_BUSY;
3205 }
3206 }
3207
3208 /**
3209 * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
3210 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3211 * the configuration information for the specified I2C.
3212 * @param DevAddress Target device address: The device 7 bits address value
3213 * in datasheet must be shifted to the left before calling the interface
3214 * @param MemAddress Internal memory address
3215 * @param MemAddSize Size of internal memory address
3216 * @param pData Pointer to data buffer
3217 * @param Size Amount of data to be read
3218 * @retval HAL status
3219 */
HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)3220 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3221 {
3222 /* Init tickstart for timeout management*/
3223 uint32_t tickstart = HAL_GetTick();
3224 __IO uint32_t count = 0U;
3225 HAL_StatusTypeDef dmaxferstatus;
3226
3227 /* Check the parameters */
3228 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3229
3230 if (hi2c->State == HAL_I2C_STATE_READY)
3231 {
3232 /* Wait until BUSY flag is reset */
3233 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3234 do
3235 {
3236 count--;
3237 if (count == 0U)
3238 {
3239 hi2c->PreviousState = I2C_STATE_NONE;
3240 hi2c->State = HAL_I2C_STATE_READY;
3241 hi2c->Mode = HAL_I2C_MODE_NONE;
3242 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3243
3244 /* Process Unlocked */
3245 __HAL_UNLOCK(hi2c);
3246
3247 return HAL_ERROR;
3248 }
3249 }
3250 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3251
3252 /* Process Locked */
3253 __HAL_LOCK(hi2c);
3254
3255 /* Check if the I2C is already enabled */
3256 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3257 {
3258 /* Enable I2C peripheral */
3259 __HAL_I2C_ENABLE(hi2c);
3260 }
3261
3262 /* Disable Pos */
3263 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3264
3265 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3266 hi2c->Mode = HAL_I2C_MODE_MEM;
3267 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3268
3269 /* Prepare transfer parameters */
3270 hi2c->pBuffPtr = pData;
3271 hi2c->XferCount = Size;
3272 hi2c->XferSize = hi2c->XferCount;
3273 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3274 hi2c->Devaddress = DevAddress;
3275 hi2c->Memaddress = MemAddress;
3276 hi2c->MemaddSize = MemAddSize;
3277 hi2c->EventCount = 0U;
3278
3279 if (hi2c->XferSize > 0U)
3280 {
3281 if (hi2c->hdmarx != NULL)
3282 {
3283 /* Set the I2C DMA transfer complete callback */
3284 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
3285
3286 /* Set the DMA error callback */
3287 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3288
3289 /* Set the unused DMA callbacks to NULL */
3290 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3291 hi2c->hdmarx->XferM1CpltCallback = NULL;
3292 hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
3293 hi2c->hdmarx->XferAbortCallback = NULL;
3294
3295 /* Enable the DMA stream */
3296 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
3297 }
3298 else
3299 {
3300 /* Update I2C state */
3301 hi2c->State = HAL_I2C_STATE_READY;
3302 hi2c->Mode = HAL_I2C_MODE_NONE;
3303
3304 /* Update I2C error code */
3305 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3306
3307 /* Process Unlocked */
3308 __HAL_UNLOCK(hi2c);
3309
3310 return HAL_ERROR;
3311 }
3312
3313 if (dmaxferstatus == HAL_OK)
3314 {
3315 /* Send Slave Address and Memory Address */
3316 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
3317 {
3318 /* Abort the ongoing DMA */
3319 dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmarx);
3320
3321 /* Prevent unused argument(s) compilation and MISRA warning */
3322 UNUSED(dmaxferstatus);
3323
3324 /* Set the unused I2C DMA transfer complete callback to NULL */
3325 hi2c->hdmarx->XferCpltCallback = NULL;
3326
3327 /* Disable Acknowledge */
3328 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3329
3330 hi2c->XferSize = 0U;
3331 hi2c->XferCount = 0U;
3332
3333 /* Disable I2C peripheral to prevent dummy data in buffer */
3334 __HAL_I2C_DISABLE(hi2c);
3335
3336 return HAL_ERROR;
3337 }
3338
3339 if (hi2c->XferSize == 1U)
3340 {
3341 /* Disable Acknowledge */
3342 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3343 }
3344 else
3345 {
3346 /* Enable Last DMA bit */
3347 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
3348 }
3349
3350 /* Clear ADDR flag */
3351 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3352
3353 /* Process Unlocked */
3354 __HAL_UNLOCK(hi2c);
3355
3356 /* Note : The I2C interrupts must be enabled after unlocking current process
3357 to avoid the risk of I2C interrupt handle execution before current
3358 process unlock */
3359 /* Enable ERR interrupt */
3360 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
3361
3362 /* Enable DMA Request */
3363 hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
3364 }
3365 else
3366 {
3367 /* Update I2C state */
3368 hi2c->State = HAL_I2C_STATE_READY;
3369 hi2c->Mode = HAL_I2C_MODE_NONE;
3370
3371 /* Update I2C error code */
3372 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3373
3374 /* Process Unlocked */
3375 __HAL_UNLOCK(hi2c);
3376
3377 return HAL_ERROR;
3378 }
3379 }
3380 else
3381 {
3382 /* Send Slave Address and Memory Address */
3383 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
3384 {
3385 return HAL_ERROR;
3386 }
3387
3388 /* Clear ADDR flag */
3389 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3390
3391 /* Generate Stop */
3392 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
3393
3394 hi2c->State = HAL_I2C_STATE_READY;
3395
3396 /* Process Unlocked */
3397 __HAL_UNLOCK(hi2c);
3398 }
3399
3400 return HAL_OK;
3401 }
3402 else
3403 {
3404 return HAL_BUSY;
3405 }
3406 }
3407
3408 /**
3409 * @brief Checks if target device is ready for communication.
3410 * @note This function is used with Memory devices
3411 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3412 * the configuration information for the specified I2C.
3413 * @param DevAddress Target device address: The device 7 bits address value
3414 * in datasheet must be shifted to the left before calling the interface
3415 * @param Trials Number of trials
3416 * @param Timeout Timeout duration
3417 * @retval HAL status
3418 */
HAL_I2C_IsDeviceReady(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Trials,uint32_t Timeout)3419 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
3420 {
3421 /* Get tick */
3422 uint32_t tickstart = HAL_GetTick();
3423 uint32_t I2C_Trials = 0U;
3424 FlagStatus tmp1;
3425 FlagStatus tmp2;
3426
3427 if (hi2c->State == HAL_I2C_STATE_READY)
3428 {
3429 /* Wait until BUSY flag is reset */
3430 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3431 {
3432 return HAL_BUSY;
3433 }
3434
3435 /* Process Locked */
3436 __HAL_LOCK(hi2c);
3437
3438 /* Check if the I2C is already enabled */
3439 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3440 {
3441 /* Enable I2C peripheral */
3442 __HAL_I2C_ENABLE(hi2c);
3443 }
3444
3445 /* Disable Pos */
3446 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3447
3448 hi2c->State = HAL_I2C_STATE_BUSY;
3449 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3450 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3451
3452 do
3453 {
3454 /* Generate Start */
3455 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3456
3457 /* Wait until SB flag is set */
3458 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)
3459 {
3460 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
3461 {
3462 hi2c->ErrorCode = HAL_I2C_WRONG_START;
3463 }
3464 return HAL_TIMEOUT;
3465 }
3466
3467 /* Send slave address */
3468 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
3469
3470 /* Wait until ADDR or AF flag are set */
3471 /* Get tick */
3472 tickstart = HAL_GetTick();
3473
3474 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
3475 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3476 while ((hi2c->State != HAL_I2C_STATE_TIMEOUT) && (tmp1 == RESET) && (tmp2 == RESET))
3477 {
3478 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3479 {
3480 hi2c->State = HAL_I2C_STATE_TIMEOUT;
3481 }
3482 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
3483 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3484 }
3485
3486 hi2c->State = HAL_I2C_STATE_READY;
3487
3488 /* Check if the ADDR flag has been set */
3489 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
3490 {
3491 /* Generate Stop */
3492 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
3493
3494 /* Clear ADDR Flag */
3495 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3496
3497 /* Wait until BUSY flag is reset */
3498 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3499 {
3500 return HAL_ERROR;
3501 }
3502
3503 hi2c->State = HAL_I2C_STATE_READY;
3504
3505 /* Process Unlocked */
3506 __HAL_UNLOCK(hi2c);
3507
3508 return HAL_OK;
3509 }
3510 else
3511 {
3512 /* Generate Stop */
3513 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
3514
3515 /* Clear AF Flag */
3516 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3517
3518 /* Wait until BUSY flag is reset */
3519 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3520 {
3521 return HAL_ERROR;
3522 }
3523 }
3524
3525 /* Increment Trials */
3526 I2C_Trials++;
3527 }
3528 while (I2C_Trials < Trials);
3529
3530 hi2c->State = HAL_I2C_STATE_READY;
3531
3532 /* Process Unlocked */
3533 __HAL_UNLOCK(hi2c);
3534
3535 return HAL_ERROR;
3536 }
3537 else
3538 {
3539 return HAL_BUSY;
3540 }
3541 }
3542
3543 /**
3544 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
3545 * @note This interface allow to manage repeated start condition when a direction change during transfer
3546 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3547 * the configuration information for the specified I2C.
3548 * @param DevAddress Target device address: The device 7 bits address value
3549 * in datasheet must be shifted to the left before calling the interface
3550 * @param pData Pointer to data buffer
3551 * @param Size Amount of data to be sent
3552 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
3553 * @retval HAL status
3554 */
HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3555 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3556 {
3557 __IO uint32_t Prev_State = 0x00U;
3558 __IO uint32_t count = 0x00U;
3559
3560 /* Check the parameters */
3561 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3562
3563 if (hi2c->State == HAL_I2C_STATE_READY)
3564 {
3565 /* Check Busy Flag only if FIRST call of Master interface */
3566 if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3567 {
3568 /* Wait until BUSY flag is reset */
3569 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3570 do
3571 {
3572 count--;
3573 if (count == 0U)
3574 {
3575 hi2c->PreviousState = I2C_STATE_NONE;
3576 hi2c->State = HAL_I2C_STATE_READY;
3577 hi2c->Mode = HAL_I2C_MODE_NONE;
3578 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3579
3580 /* Process Unlocked */
3581 __HAL_UNLOCK(hi2c);
3582
3583 return HAL_ERROR;
3584 }
3585 }
3586 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3587 }
3588
3589 /* Process Locked */
3590 __HAL_LOCK(hi2c);
3591
3592 /* Check if the I2C is already enabled */
3593 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3594 {
3595 /* Enable I2C peripheral */
3596 __HAL_I2C_ENABLE(hi2c);
3597 }
3598
3599 /* Disable Pos */
3600 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3601
3602 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3603 hi2c->Mode = HAL_I2C_MODE_MASTER;
3604 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3605
3606 /* Prepare transfer parameters */
3607 hi2c->pBuffPtr = pData;
3608 hi2c->XferCount = Size;
3609 hi2c->XferSize = hi2c->XferCount;
3610 hi2c->XferOptions = XferOptions;
3611 hi2c->Devaddress = DevAddress;
3612
3613 Prev_State = hi2c->PreviousState;
3614
3615 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3616 /* Mean Previous state is same as current state */
3617 if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3618 {
3619 /* Generate Start */
3620 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3621 }
3622
3623 /* Process Unlocked */
3624 __HAL_UNLOCK(hi2c);
3625
3626 /* Note : The I2C interrupts must be enabled after unlocking current process
3627 to avoid the risk of I2C interrupt handle execution before current
3628 process unlock */
3629
3630 /* Enable EVT, BUF and ERR interrupt */
3631 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3632
3633 return HAL_OK;
3634 }
3635 else
3636 {
3637 return HAL_BUSY;
3638 }
3639 }
3640
3641 /**
3642 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
3643 * @note This interface allow to manage repeated start condition when a direction change during transfer
3644 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3645 * the configuration information for the specified I2C.
3646 * @param DevAddress Target device address: The device 7 bits address value
3647 * in datasheet must be shifted to the left before calling the interface
3648 * @param pData Pointer to data buffer
3649 * @param Size Amount of data to be sent
3650 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
3651 * @retval HAL status
3652 */
HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3653 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3654 {
3655 __IO uint32_t Prev_State = 0x00U;
3656 __IO uint32_t count = 0x00U;
3657 HAL_StatusTypeDef dmaxferstatus;
3658
3659 /* Check the parameters */
3660 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3661
3662 if (hi2c->State == HAL_I2C_STATE_READY)
3663 {
3664 /* Check Busy Flag only if FIRST call of Master interface */
3665 if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3666 {
3667 /* Wait until BUSY flag is reset */
3668 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3669 do
3670 {
3671 count--;
3672 if (count == 0U)
3673 {
3674 hi2c->PreviousState = I2C_STATE_NONE;
3675 hi2c->State = HAL_I2C_STATE_READY;
3676 hi2c->Mode = HAL_I2C_MODE_NONE;
3677 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3678
3679 /* Process Unlocked */
3680 __HAL_UNLOCK(hi2c);
3681
3682 return HAL_ERROR;
3683 }
3684 }
3685 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3686 }
3687
3688 /* Process Locked */
3689 __HAL_LOCK(hi2c);
3690
3691 /* Check if the I2C is already enabled */
3692 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3693 {
3694 /* Enable I2C peripheral */
3695 __HAL_I2C_ENABLE(hi2c);
3696 }
3697
3698 /* Disable Pos */
3699 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3700
3701 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3702 hi2c->Mode = HAL_I2C_MODE_MASTER;
3703 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3704
3705 /* Prepare transfer parameters */
3706 hi2c->pBuffPtr = pData;
3707 hi2c->XferCount = Size;
3708 hi2c->XferSize = hi2c->XferCount;
3709 hi2c->XferOptions = XferOptions;
3710 hi2c->Devaddress = DevAddress;
3711
3712 Prev_State = hi2c->PreviousState;
3713
3714 if (hi2c->XferSize > 0U)
3715 {
3716 if (hi2c->hdmatx != NULL)
3717 {
3718 /* Set the I2C DMA transfer complete callback */
3719 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
3720
3721 /* Set the DMA error callback */
3722 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3723
3724 /* Set the unused DMA callbacks to NULL */
3725 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3726 hi2c->hdmatx->XferAbortCallback = NULL;
3727
3728 /* Enable the DMA stream */
3729 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
3730 }
3731 else
3732 {
3733 /* Update I2C state */
3734 hi2c->State = HAL_I2C_STATE_READY;
3735 hi2c->Mode = HAL_I2C_MODE_NONE;
3736
3737 /* Update I2C error code */
3738 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3739
3740 /* Process Unlocked */
3741 __HAL_UNLOCK(hi2c);
3742
3743 return HAL_ERROR;
3744 }
3745
3746 if (dmaxferstatus == HAL_OK)
3747 {
3748 /* Enable Acknowledge */
3749 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3750
3751 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3752 /* Mean Previous state is same as current state */
3753 if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3754 {
3755 /* Generate Start */
3756 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3757 }
3758
3759 /* Process Unlocked */
3760 __HAL_UNLOCK(hi2c);
3761
3762 /* Note : The I2C interrupts must be enabled after unlocking current process
3763 to avoid the risk of I2C interrupt handle execution before current
3764 process unlock */
3765
3766 /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */
3767 /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */
3768 if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
3769 {
3770 /* Enable DMA Request */
3771 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
3772 }
3773
3774 /* Enable EVT and ERR interrupt */
3775 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
3776 }
3777 else
3778 {
3779 /* Update I2C state */
3780 hi2c->State = HAL_I2C_STATE_READY;
3781 hi2c->Mode = HAL_I2C_MODE_NONE;
3782
3783 /* Update I2C error code */
3784 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3785
3786 /* Process Unlocked */
3787 __HAL_UNLOCK(hi2c);
3788
3789 return HAL_ERROR;
3790 }
3791 }
3792 else
3793 {
3794 /* Enable Acknowledge */
3795 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3796
3797 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3798 /* Mean Previous state is same as current state */
3799 if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3800 {
3801 /* Generate Start */
3802 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3803 }
3804
3805 /* Process Unlocked */
3806 __HAL_UNLOCK(hi2c);
3807
3808 /* Note : The I2C interrupts must be enabled after unlocking current process
3809 to avoid the risk of I2C interrupt handle execution before current
3810 process unlock */
3811
3812 /* Enable EVT, BUF and ERR interrupt */
3813 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3814 }
3815
3816 return HAL_OK;
3817 }
3818 else
3819 {
3820 return HAL_BUSY;
3821 }
3822 }
3823
3824 /**
3825 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
3826 * @note This interface allow to manage repeated start condition when a direction change during transfer
3827 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3828 * the configuration information for the specified I2C.
3829 * @param DevAddress Target device address: The device 7 bits address value
3830 * in datasheet must be shifted to the left before calling the interface
3831 * @param pData Pointer to data buffer
3832 * @param Size Amount of data to be sent
3833 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
3834 * @retval HAL status
3835 */
HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3836 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3837 {
3838 __IO uint32_t Prev_State = 0x00U;
3839 __IO uint32_t count = 0U;
3840 uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3841
3842 /* Check the parameters */
3843 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3844
3845 if (hi2c->State == HAL_I2C_STATE_READY)
3846 {
3847 /* Check Busy Flag only if FIRST call of Master interface */
3848 if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3849 {
3850 /* Wait until BUSY flag is reset */
3851 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3852 do
3853 {
3854 count--;
3855 if (count == 0U)
3856 {
3857 hi2c->PreviousState = I2C_STATE_NONE;
3858 hi2c->State = HAL_I2C_STATE_READY;
3859 hi2c->Mode = HAL_I2C_MODE_NONE;
3860 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3861
3862 /* Process Unlocked */
3863 __HAL_UNLOCK(hi2c);
3864
3865 return HAL_ERROR;
3866 }
3867 }
3868 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3869 }
3870
3871 /* Process Locked */
3872 __HAL_LOCK(hi2c);
3873
3874 /* Check if the I2C is already enabled */
3875 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3876 {
3877 /* Enable I2C peripheral */
3878 __HAL_I2C_ENABLE(hi2c);
3879 }
3880
3881 /* Disable Pos */
3882 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3883
3884 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3885 hi2c->Mode = HAL_I2C_MODE_MASTER;
3886 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3887
3888 /* Prepare transfer parameters */
3889 hi2c->pBuffPtr = pData;
3890 hi2c->XferCount = Size;
3891 hi2c->XferSize = hi2c->XferCount;
3892 hi2c->XferOptions = XferOptions;
3893 hi2c->Devaddress = DevAddress;
3894
3895 Prev_State = hi2c->PreviousState;
3896
3897 if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)))
3898 {
3899 if (Prev_State == I2C_STATE_MASTER_BUSY_RX)
3900 {
3901 /* Disable Acknowledge */
3902 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3903
3904 /* Enable Pos */
3905 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3906
3907 /* Remove Enabling of IT_BUF, mean RXNE treatment, treat the 2 bytes through BTF */
3908 enableIT &= ~I2C_IT_BUF;
3909 }
3910 else
3911 {
3912 /* Enable Acknowledge */
3913 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3914 }
3915 }
3916 else
3917 {
3918 /* Enable Acknowledge */
3919 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3920 }
3921
3922 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3923 /* Mean Previous state is same as current state */
3924 if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3925 {
3926 /* Generate Start */
3927 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3928 }
3929
3930 /* Process Unlocked */
3931 __HAL_UNLOCK(hi2c);
3932
3933 /* Note : The I2C interrupts must be enabled after unlocking current process
3934 to avoid the risk of I2C interrupt handle execution before current
3935 process unlock */
3936
3937 /* Enable interrupts */
3938 __HAL_I2C_ENABLE_IT(hi2c, enableIT);
3939
3940 return HAL_OK;
3941 }
3942 else
3943 {
3944 return HAL_BUSY;
3945 }
3946 }
3947
3948 /**
3949 * @brief Sequential receive in master mode an amount of data in non-blocking mode with DMA
3950 * @note This interface allow to manage repeated start condition when a direction change during transfer
3951 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3952 * the configuration information for the specified I2C.
3953 * @param DevAddress Target device address: The device 7 bits address value
3954 * in datasheet must be shifted to the left before calling the interface
3955 * @param pData Pointer to data buffer
3956 * @param Size Amount of data to be sent
3957 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
3958 * @retval HAL status
3959 */
HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3960 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3961 {
3962 __IO uint32_t Prev_State = 0x00U;
3963 __IO uint32_t count = 0U;
3964 uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3965 HAL_StatusTypeDef dmaxferstatus;
3966
3967 /* Check the parameters */
3968 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3969
3970 if (hi2c->State == HAL_I2C_STATE_READY)
3971 {
3972 /* Check Busy Flag only if FIRST call of Master interface */
3973 if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3974 {
3975 /* Wait until BUSY flag is reset */
3976 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3977 do
3978 {
3979 count--;
3980 if (count == 0U)
3981 {
3982 hi2c->PreviousState = I2C_STATE_NONE;
3983 hi2c->State = HAL_I2C_STATE_READY;
3984 hi2c->Mode = HAL_I2C_MODE_NONE;
3985 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3986
3987 /* Process Unlocked */
3988 __HAL_UNLOCK(hi2c);
3989
3990 return HAL_ERROR;
3991 }
3992 }
3993 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3994 }
3995
3996 /* Process Locked */
3997 __HAL_LOCK(hi2c);
3998
3999 /* Check if the I2C is already enabled */
4000 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4001 {
4002 /* Enable I2C peripheral */
4003 __HAL_I2C_ENABLE(hi2c);
4004 }
4005
4006 /* Disable Pos */
4007 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4008
4009 /* Clear Last DMA bit */
4010 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
4011
4012 hi2c->State = HAL_I2C_STATE_BUSY_RX;
4013 hi2c->Mode = HAL_I2C_MODE_MASTER;
4014 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4015
4016 /* Prepare transfer parameters */
4017 hi2c->pBuffPtr = pData;
4018 hi2c->XferCount = Size;
4019 hi2c->XferSize = hi2c->XferCount;
4020 hi2c->XferOptions = XferOptions;
4021 hi2c->Devaddress = DevAddress;
4022
4023 Prev_State = hi2c->PreviousState;
4024
4025 if (hi2c->XferSize > 0U)
4026 {
4027 if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)))
4028 {
4029 if (Prev_State == I2C_STATE_MASTER_BUSY_RX)
4030 {
4031 /* Disable Acknowledge */
4032 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4033
4034 /* Enable Pos */
4035 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4036
4037 /* Enable Last DMA bit */
4038 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
4039 }
4040 else
4041 {
4042 /* Enable Acknowledge */
4043 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4044 }
4045 }
4046 else
4047 {
4048 /* Enable Acknowledge */
4049 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4050
4051 if ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_OTHER_AND_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
4052 {
4053 /* Enable Last DMA bit */
4054 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
4055 }
4056 }
4057 if (hi2c->hdmarx != NULL)
4058 {
4059 /* Set the I2C DMA transfer complete callback */
4060 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
4061
4062 /* Set the DMA error callback */
4063 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4064
4065 /* Set the unused DMA callbacks to NULL */
4066 hi2c->hdmarx->XferHalfCpltCallback = NULL;
4067 hi2c->hdmarx->XferAbortCallback = NULL;
4068
4069 /* Enable the DMA stream */
4070 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
4071 }
4072 else
4073 {
4074 /* Update I2C state */
4075 hi2c->State = HAL_I2C_STATE_READY;
4076 hi2c->Mode = HAL_I2C_MODE_NONE;
4077
4078 /* Update I2C error code */
4079 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4080
4081 /* Process Unlocked */
4082 __HAL_UNLOCK(hi2c);
4083
4084 return HAL_ERROR;
4085 }
4086 if (dmaxferstatus == HAL_OK)
4087 {
4088 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
4089 /* Mean Previous state is same as current state */
4090 if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
4091 {
4092 /* Generate Start */
4093 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
4094
4095 /* Update interrupt for only EVT and ERR */
4096 enableIT = (I2C_IT_EVT | I2C_IT_ERR);
4097 }
4098 else
4099 {
4100 /* Update interrupt for only ERR */
4101 enableIT = I2C_IT_ERR;
4102 }
4103
4104 /* Process Unlocked */
4105 __HAL_UNLOCK(hi2c);
4106
4107 /* Note : The I2C interrupts must be enabled after unlocking current process
4108 to avoid the risk of I2C interrupt handle execution before current
4109 process unlock */
4110
4111 /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */
4112 /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */
4113 if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
4114 {
4115 /* Enable DMA Request */
4116 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4117 }
4118
4119 /* Enable EVT and ERR interrupt */
4120 __HAL_I2C_ENABLE_IT(hi2c, enableIT);
4121 }
4122 else
4123 {
4124 /* Update I2C state */
4125 hi2c->State = HAL_I2C_STATE_READY;
4126 hi2c->Mode = HAL_I2C_MODE_NONE;
4127
4128 /* Update I2C error code */
4129 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4130
4131 /* Process Unlocked */
4132 __HAL_UNLOCK(hi2c);
4133
4134 return HAL_ERROR;
4135 }
4136 }
4137 else
4138 {
4139 /* Enable Acknowledge */
4140 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4141
4142 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
4143 /* Mean Previous state is same as current state */
4144 if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
4145 {
4146 /* Generate Start */
4147 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
4148 }
4149
4150 /* Process Unlocked */
4151 __HAL_UNLOCK(hi2c);
4152
4153 /* Note : The I2C interrupts must be enabled after unlocking current process
4154 to avoid the risk of I2C interrupt handle execution before current
4155 process unlock */
4156
4157 /* Enable interrupts */
4158 __HAL_I2C_ENABLE_IT(hi2c, enableIT);
4159 }
4160 return HAL_OK;
4161 }
4162 else
4163 {
4164 return HAL_BUSY;
4165 }
4166 }
4167
4168 /**
4169 * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with Interrupt
4170 * @note This interface allow to manage repeated start condition when a direction change during transfer
4171 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4172 * the configuration information for the specified I2C.
4173 * @param pData Pointer to data buffer
4174 * @param Size Amount of data to be sent
4175 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
4176 * @retval HAL status
4177 */
HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4178 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4179 {
4180 /* Check the parameters */
4181 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4182
4183 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4184 {
4185 if ((pData == NULL) || (Size == 0U))
4186 {
4187 return HAL_ERROR;
4188 }
4189
4190 /* Process Locked */
4191 __HAL_LOCK(hi2c);
4192
4193 /* Check if the I2C is already enabled */
4194 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4195 {
4196 /* Enable I2C peripheral */
4197 __HAL_I2C_ENABLE(hi2c);
4198 }
4199
4200 /* Disable Pos */
4201 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4202
4203 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
4204 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4205 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4206
4207 /* Prepare transfer parameters */
4208 hi2c->pBuffPtr = pData;
4209 hi2c->XferCount = Size;
4210 hi2c->XferSize = hi2c->XferCount;
4211 hi2c->XferOptions = XferOptions;
4212
4213 /* Clear ADDR flag */
4214 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4215
4216 /* Process Unlocked */
4217 __HAL_UNLOCK(hi2c);
4218
4219 /* Note : The I2C interrupts must be enabled after unlocking current process
4220 to avoid the risk of I2C interrupt handle execution before current
4221 process unlock */
4222
4223 /* Enable EVT, BUF and ERR interrupt */
4224 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4225
4226 return HAL_OK;
4227 }
4228 else
4229 {
4230 return HAL_BUSY;
4231 }
4232 }
4233
4234 /**
4235 * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with DMA
4236 * @note This interface allow to manage repeated start condition when a direction change during transfer
4237 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4238 * the configuration information for the specified I2C.
4239 * @param pData Pointer to data buffer
4240 * @param Size Amount of data to be sent
4241 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
4242 * @retval HAL status
4243 */
HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4244 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4245 {
4246 HAL_StatusTypeDef dmaxferstatus;
4247
4248 /* Check the parameters */
4249 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4250
4251 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4252 {
4253 if ((pData == NULL) || (Size == 0U))
4254 {
4255 return HAL_ERROR;
4256 }
4257
4258 /* Process Locked */
4259 __HAL_LOCK(hi2c);
4260
4261 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4262 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4263
4264 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4265 /* and then toggle the HAL slave RX state to TX state */
4266 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4267 {
4268 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4269 {
4270 /* Abort DMA Xfer if any */
4271 if (hi2c->hdmarx != NULL)
4272 {
4273 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4274
4275 /* Set the I2C DMA Abort callback :
4276 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4277 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4278
4279 /* Abort DMA RX */
4280 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4281 {
4282 /* Call Directly XferAbortCallback function in case of error */
4283 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4284 }
4285 }
4286 }
4287 }
4288 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4289 {
4290 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4291 {
4292 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4293
4294 /* Abort DMA Xfer if any */
4295 if (hi2c->hdmatx != NULL)
4296 {
4297 /* Set the I2C DMA Abort callback :
4298 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4299 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4300
4301 /* Abort DMA TX */
4302 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4303 {
4304 /* Call Directly XferAbortCallback function in case of error */
4305 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4306 }
4307 }
4308 }
4309 }
4310 else
4311 {
4312 /* Nothing to do */
4313 }
4314
4315 /* Check if the I2C is already enabled */
4316 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4317 {
4318 /* Enable I2C peripheral */
4319 __HAL_I2C_ENABLE(hi2c);
4320 }
4321
4322 /* Disable Pos */
4323 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4324
4325 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
4326 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4327 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4328
4329 /* Prepare transfer parameters */
4330 hi2c->pBuffPtr = pData;
4331 hi2c->XferCount = Size;
4332 hi2c->XferSize = hi2c->XferCount;
4333 hi2c->XferOptions = XferOptions;
4334
4335 if (hi2c->hdmatx != NULL)
4336 {
4337 /* Set the I2C DMA transfer complete callback */
4338 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
4339
4340 /* Set the DMA error callback */
4341 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
4342
4343 /* Set the unused DMA callbacks to NULL */
4344 hi2c->hdmatx->XferHalfCpltCallback = NULL;
4345 hi2c->hdmatx->XferAbortCallback = NULL;
4346
4347 /* Enable the DMA stream */
4348 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
4349 }
4350 else
4351 {
4352 /* Update I2C state */
4353 hi2c->State = HAL_I2C_STATE_LISTEN;
4354 hi2c->Mode = HAL_I2C_MODE_NONE;
4355
4356 /* Update I2C error code */
4357 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4358
4359 /* Process Unlocked */
4360 __HAL_UNLOCK(hi2c);
4361
4362 return HAL_ERROR;
4363 }
4364
4365 if (dmaxferstatus == HAL_OK)
4366 {
4367 /* Enable Address Acknowledge */
4368 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4369
4370 /* Clear ADDR flag */
4371 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4372
4373 /* Process Unlocked */
4374 __HAL_UNLOCK(hi2c);
4375
4376 /* Note : The I2C interrupts must be enabled after unlocking current process
4377 to avoid the risk of I2C interrupt handle execution before current
4378 process unlock */
4379 /* Enable EVT and ERR interrupt */
4380 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4381
4382 /* Enable DMA Request */
4383 hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
4384
4385 return HAL_OK;
4386 }
4387 else
4388 {
4389 /* Update I2C state */
4390 hi2c->State = HAL_I2C_STATE_READY;
4391 hi2c->Mode = HAL_I2C_MODE_NONE;
4392
4393 /* Update I2C error code */
4394 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4395
4396 /* Process Unlocked */
4397 __HAL_UNLOCK(hi2c);
4398
4399 return HAL_ERROR;
4400 }
4401 }
4402 else
4403 {
4404 return HAL_BUSY;
4405 }
4406 }
4407
4408 /**
4409 * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt
4410 * @note This interface allow to manage repeated start condition when a direction change during transfer
4411 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4412 * the configuration information for the specified I2C.
4413 * @param pData Pointer to data buffer
4414 * @param Size Amount of data to be sent
4415 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
4416 * @retval HAL status
4417 */
HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4418 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4419 {
4420 /* Check the parameters */
4421 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4422
4423 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4424 {
4425 if ((pData == NULL) || (Size == 0U))
4426 {
4427 return HAL_ERROR;
4428 }
4429
4430 /* Process Locked */
4431 __HAL_LOCK(hi2c);
4432
4433 /* Check if the I2C is already enabled */
4434 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4435 {
4436 /* Enable I2C peripheral */
4437 __HAL_I2C_ENABLE(hi2c);
4438 }
4439
4440 /* Disable Pos */
4441 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4442
4443 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4444 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4445 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4446
4447 /* Prepare transfer parameters */
4448 hi2c->pBuffPtr = pData;
4449 hi2c->XferCount = Size;
4450 hi2c->XferSize = hi2c->XferCount;
4451 hi2c->XferOptions = XferOptions;
4452
4453 /* Clear ADDR flag */
4454 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4455
4456 /* Process Unlocked */
4457 __HAL_UNLOCK(hi2c);
4458
4459 /* Note : The I2C interrupts must be enabled after unlocking current process
4460 to avoid the risk of I2C interrupt handle execution before current
4461 process unlock */
4462
4463 /* Enable EVT, BUF and ERR interrupt */
4464 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4465
4466 return HAL_OK;
4467 }
4468 else
4469 {
4470 return HAL_BUSY;
4471 }
4472 }
4473
4474 /**
4475 * @brief Sequential receive in slave mode an amount of data in non-blocking mode with DMA
4476 * @note This interface allow to manage repeated start condition when a direction change during transfer
4477 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4478 * the configuration information for the specified I2C.
4479 * @param pData Pointer to data buffer
4480 * @param Size Amount of data to be sent
4481 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
4482 * @retval HAL status
4483 */
HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4484 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4485 {
4486 HAL_StatusTypeDef dmaxferstatus;
4487
4488 /* Check the parameters */
4489 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4490
4491 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4492 {
4493 if ((pData == NULL) || (Size == 0U))
4494 {
4495 return HAL_ERROR;
4496 }
4497
4498 /* Process Locked */
4499 __HAL_LOCK(hi2c);
4500
4501 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4502 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4503
4504 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4505 /* and then toggle the HAL slave RX state to TX state */
4506 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4507 {
4508 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4509 {
4510 /* Abort DMA Xfer if any */
4511 if (hi2c->hdmarx != NULL)
4512 {
4513 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4514
4515 /* Set the I2C DMA Abort callback :
4516 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4517 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4518
4519 /* Abort DMA RX */
4520 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4521 {
4522 /* Call Directly XferAbortCallback function in case of error */
4523 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4524 }
4525 }
4526 }
4527 }
4528 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4529 {
4530 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4531 {
4532 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4533
4534 /* Abort DMA Xfer if any */
4535 if (hi2c->hdmatx != NULL)
4536 {
4537 /* Set the I2C DMA Abort callback :
4538 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4539 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4540
4541 /* Abort DMA TX */
4542 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4543 {
4544 /* Call Directly XferAbortCallback function in case of error */
4545 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4546 }
4547 }
4548 }
4549 }
4550 else
4551 {
4552 /* Nothing to do */
4553 }
4554
4555 /* Check if the I2C is already enabled */
4556 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4557 {
4558 /* Enable I2C peripheral */
4559 __HAL_I2C_ENABLE(hi2c);
4560 }
4561
4562 /* Disable Pos */
4563 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4564
4565 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4566 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4567 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4568
4569 /* Prepare transfer parameters */
4570 hi2c->pBuffPtr = pData;
4571 hi2c->XferCount = Size;
4572 hi2c->XferSize = hi2c->XferCount;
4573 hi2c->XferOptions = XferOptions;
4574
4575 if (hi2c->hdmarx != NULL)
4576 {
4577 /* Set the I2C DMA transfer complete callback */
4578 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
4579
4580 /* Set the DMA error callback */
4581 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4582
4583 /* Set the unused DMA callbacks to NULL */
4584 hi2c->hdmarx->XferHalfCpltCallback = NULL;
4585 hi2c->hdmarx->XferAbortCallback = NULL;
4586
4587 /* Enable the DMA stream */
4588 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
4589 }
4590 else
4591 {
4592 /* Update I2C state */
4593 hi2c->State = HAL_I2C_STATE_LISTEN;
4594 hi2c->Mode = HAL_I2C_MODE_NONE;
4595
4596 /* Update I2C error code */
4597 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4598
4599 /* Process Unlocked */
4600 __HAL_UNLOCK(hi2c);
4601
4602 return HAL_ERROR;
4603 }
4604
4605 if (dmaxferstatus == HAL_OK)
4606 {
4607 /* Enable Address Acknowledge */
4608 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4609
4610 /* Clear ADDR flag */
4611 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4612
4613 /* Process Unlocked */
4614 __HAL_UNLOCK(hi2c);
4615
4616 /* Enable DMA Request */
4617 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4618
4619 /* Note : The I2C interrupts must be enabled after unlocking current process
4620 to avoid the risk of I2C interrupt handle execution before current
4621 process unlock */
4622 /* Enable EVT and ERR interrupt */
4623 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4624
4625 return HAL_OK;
4626 }
4627 else
4628 {
4629 /* Update I2C state */
4630 hi2c->State = HAL_I2C_STATE_READY;
4631 hi2c->Mode = HAL_I2C_MODE_NONE;
4632
4633 /* Update I2C error code */
4634 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4635
4636 /* Process Unlocked */
4637 __HAL_UNLOCK(hi2c);
4638
4639 return HAL_ERROR;
4640 }
4641 }
4642 else
4643 {
4644 return HAL_BUSY;
4645 }
4646 }
4647
4648 /**
4649 * @brief Enable the Address listen mode with Interrupt.
4650 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4651 * the configuration information for the specified I2C.
4652 * @retval HAL status
4653 */
HAL_I2C_EnableListen_IT(I2C_HandleTypeDef * hi2c)4654 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
4655 {
4656 if (hi2c->State == HAL_I2C_STATE_READY)
4657 {
4658 hi2c->State = HAL_I2C_STATE_LISTEN;
4659
4660 /* Check if the I2C is already enabled */
4661 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4662 {
4663 /* Enable I2C peripheral */
4664 __HAL_I2C_ENABLE(hi2c);
4665 }
4666
4667 /* Enable Address Acknowledge */
4668 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4669
4670 /* Enable EVT and ERR interrupt */
4671 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4672
4673 return HAL_OK;
4674 }
4675 else
4676 {
4677 return HAL_BUSY;
4678 }
4679 }
4680
4681 /**
4682 * @brief Disable the Address listen mode with Interrupt.
4683 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4684 * the configuration information for the specified I2C.
4685 * @retval HAL status
4686 */
HAL_I2C_DisableListen_IT(I2C_HandleTypeDef * hi2c)4687 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
4688 {
4689 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4690 uint32_t tmp;
4691
4692 /* Disable Address listen mode only if a transfer is not ongoing */
4693 if (hi2c->State == HAL_I2C_STATE_LISTEN)
4694 {
4695 tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
4696 hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
4697 hi2c->State = HAL_I2C_STATE_READY;
4698 hi2c->Mode = HAL_I2C_MODE_NONE;
4699
4700 /* Disable Address Acknowledge */
4701 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4702
4703 /* Disable EVT and ERR interrupt */
4704 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4705
4706 return HAL_OK;
4707 }
4708 else
4709 {
4710 return HAL_BUSY;
4711 }
4712 }
4713
4714 /**
4715 * @brief Abort a master I2C IT or DMA process communication with Interrupt.
4716 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4717 * the configuration information for the specified I2C.
4718 * @param DevAddress Target device address: The device 7 bits address value
4719 * in datasheet must be shifted to the left before calling the interface
4720 * @retval HAL status
4721 */
HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress)4722 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
4723 {
4724 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
4725 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
4726
4727 /* Prevent unused argument(s) compilation warning */
4728 UNUSED(DevAddress);
4729
4730 /* Abort Master transfer during Receive or Transmit process */
4731 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && (CurrentMode == HAL_I2C_MODE_MASTER))
4732 {
4733 /* Process Locked */
4734 __HAL_LOCK(hi2c);
4735
4736 hi2c->PreviousState = I2C_STATE_NONE;
4737 hi2c->State = HAL_I2C_STATE_ABORT;
4738
4739 /* Disable Acknowledge */
4740 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4741
4742 /* Generate Stop */
4743 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
4744
4745 hi2c->XferCount = 0U;
4746
4747 /* Disable EVT, BUF and ERR interrupt */
4748 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4749
4750 /* Process Unlocked */
4751 __HAL_UNLOCK(hi2c);
4752
4753 /* Call the corresponding callback to inform upper layer of End of Transfer */
4754 I2C_ITError(hi2c);
4755
4756 return HAL_OK;
4757 }
4758 else
4759 {
4760 /* Wrong usage of abort function */
4761 /* This function should be used only in case of abort monitored by master device */
4762 /* Or periphal is not in busy state, mean there is no active sequence to be abort */
4763 return HAL_ERROR;
4764 }
4765 }
4766
4767 /**
4768 * @}
4769 */
4770
4771 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
4772 * @{
4773 */
4774
4775 /**
4776 * @brief This function handles I2C event interrupt request.
4777 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4778 * the configuration information for the specified I2C.
4779 * @retval None
4780 */
HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef * hi2c)4781 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
4782 {
4783 uint32_t sr1itflags;
4784 uint32_t sr2itflags = 0U;
4785 uint32_t itsources = READ_REG(hi2c->Instance->CR2);
4786 uint32_t CurrentXferOptions = hi2c->XferOptions;
4787 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
4788 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
4789
4790 /* Master or Memory mode selected */
4791 if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
4792 {
4793 sr2itflags = READ_REG(hi2c->Instance->SR2);
4794 sr1itflags = READ_REG(hi2c->Instance->SR1);
4795
4796 /* Exit IRQ event until Start Bit detected in case of Other frame requested */
4797 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) == RESET) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(CurrentXferOptions) == 1U))
4798 {
4799 return;
4800 }
4801
4802 /* SB Set ----------------------------------------------------------------*/
4803 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4804 {
4805 /* Convert OTHER_xxx XferOptions if any */
4806 I2C_ConvertOtherXferOptions(hi2c);
4807
4808 I2C_Master_SB(hi2c);
4809 }
4810 /* ADD10 Set -------------------------------------------------------------*/
4811 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADD10) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4812 {
4813 I2C_Master_ADD10(hi2c);
4814 }
4815 /* ADDR Set --------------------------------------------------------------*/
4816 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4817 {
4818 I2C_Master_ADDR(hi2c);
4819 }
4820 /* I2C in mode Transmitter -----------------------------------------------*/
4821 else if (I2C_CHECK_FLAG(sr2itflags, I2C_FLAG_TRA) != RESET)
4822 {
4823 /* Do not check buffer and BTF flag if a Xfer DMA is on going */
4824 if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN)
4825 {
4826 /* TXE set and BTF reset -----------------------------------------------*/
4827 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
4828 {
4829 I2C_MasterTransmit_TXE(hi2c);
4830 }
4831 /* BTF set -------------------------------------------------------------*/
4832 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4833 {
4834 if (CurrentState == HAL_I2C_STATE_BUSY_TX)
4835 {
4836 I2C_MasterTransmit_BTF(hi2c);
4837 }
4838 else /* HAL_I2C_MODE_MEM */
4839 {
4840 if (CurrentMode == HAL_I2C_MODE_MEM)
4841 {
4842 I2C_MemoryTransmit_TXE_BTF(hi2c);
4843 }
4844 }
4845 }
4846 else
4847 {
4848 /* Do nothing */
4849 }
4850 }
4851 }
4852 /* I2C in mode Receiver --------------------------------------------------*/
4853 else
4854 {
4855 /* Do not check buffer and BTF flag if a Xfer DMA is on going */
4856 if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN)
4857 {
4858 /* RXNE set and BTF reset -----------------------------------------------*/
4859 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
4860 {
4861 I2C_MasterReceive_RXNE(hi2c);
4862 }
4863 /* BTF set -------------------------------------------------------------*/
4864 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4865 {
4866 I2C_MasterReceive_BTF(hi2c);
4867 }
4868 else
4869 {
4870 /* Do nothing */
4871 }
4872 }
4873 }
4874 }
4875 /* Slave mode selected */
4876 else
4877 {
4878 /* If an error is detected, read only SR1 register to prevent */
4879 /* a clear of ADDR flags by reading SR2 after reading SR1 in Error treatment */
4880 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
4881 {
4882 sr1itflags = READ_REG(hi2c->Instance->SR1);
4883 }
4884 else
4885 {
4886 sr2itflags = READ_REG(hi2c->Instance->SR2);
4887 sr1itflags = READ_REG(hi2c->Instance->SR1);
4888 }
4889
4890 /* ADDR set --------------------------------------------------------------*/
4891 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4892 {
4893 /* Now time to read SR2, this will clear ADDR flag automatically */
4894 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
4895 {
4896 sr2itflags = READ_REG(hi2c->Instance->SR2);
4897 }
4898 I2C_Slave_ADDR(hi2c, sr2itflags);
4899 }
4900 /* STOPF set --------------------------------------------------------------*/
4901 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4902 {
4903 I2C_Slave_STOPF(hi2c);
4904 }
4905 /* I2C in mode Transmitter -----------------------------------------------*/
4906 else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
4907 {
4908 /* TXE set and BTF reset -----------------------------------------------*/
4909 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
4910 {
4911 I2C_SlaveTransmit_TXE(hi2c);
4912 }
4913 /* BTF set -------------------------------------------------------------*/
4914 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4915 {
4916 I2C_SlaveTransmit_BTF(hi2c);
4917 }
4918 else
4919 {
4920 /* Do nothing */
4921 }
4922 }
4923 /* I2C in mode Receiver --------------------------------------------------*/
4924 else
4925 {
4926 /* RXNE set and BTF reset ----------------------------------------------*/
4927 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
4928 {
4929 I2C_SlaveReceive_RXNE(hi2c);
4930 }
4931 /* BTF set -------------------------------------------------------------*/
4932 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4933 {
4934 I2C_SlaveReceive_BTF(hi2c);
4935 }
4936 else
4937 {
4938 /* Do nothing */
4939 }
4940 }
4941 }
4942 }
4943
4944 /**
4945 * @brief This function handles I2C error interrupt request.
4946 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4947 * the configuration information for the specified I2C.
4948 * @retval None
4949 */
HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef * hi2c)4950 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
4951 {
4952 HAL_I2C_ModeTypeDef tmp1;
4953 uint32_t tmp2;
4954 HAL_I2C_StateTypeDef tmp3;
4955 uint32_t tmp4;
4956 uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
4957 uint32_t itsources = READ_REG(hi2c->Instance->CR2);
4958 uint32_t error = HAL_I2C_ERROR_NONE;
4959 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
4960
4961 /* I2C Bus error interrupt occurred ----------------------------------------*/
4962 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
4963 {
4964 error |= HAL_I2C_ERROR_BERR;
4965
4966 /* Clear BERR flag */
4967 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
4968 }
4969
4970 /* I2C Arbitration Lost error interrupt occurred ---------------------------*/
4971 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
4972 {
4973 error |= HAL_I2C_ERROR_ARLO;
4974
4975 /* Clear ARLO flag */
4976 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
4977 }
4978
4979 /* I2C Acknowledge failure error interrupt occurred ------------------------*/
4980 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
4981 {
4982 tmp1 = CurrentMode;
4983 tmp2 = hi2c->XferCount;
4984 tmp3 = hi2c->State;
4985 tmp4 = hi2c->PreviousState;
4986 if ((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \
4987 ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \
4988 ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX))))
4989 {
4990 I2C_Slave_AF(hi2c);
4991 }
4992 else
4993 {
4994 /* Clear AF flag */
4995 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4996
4997 error |= HAL_I2C_ERROR_AF;
4998
4999 /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */
5000 if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
5001 {
5002 /* Generate Stop */
5003 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5004 }
5005 }
5006 }
5007
5008 /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/
5009 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
5010 {
5011 error |= HAL_I2C_ERROR_OVR;
5012 /* Clear OVR flag */
5013 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
5014 }
5015
5016 /* Call the Error Callback in case of Error detected -----------------------*/
5017 if (error != HAL_I2C_ERROR_NONE)
5018 {
5019 hi2c->ErrorCode |= error;
5020 I2C_ITError(hi2c);
5021 }
5022 }
5023
5024 /**
5025 * @brief Master Tx Transfer completed callback.
5026 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5027 * the configuration information for the specified I2C.
5028 * @retval None
5029 */
HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef * hi2c)5030 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
5031 {
5032 /* Prevent unused argument(s) compilation warning */
5033 UNUSED(hi2c);
5034
5035 /* NOTE : This function should not be modified, when the callback is needed,
5036 the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
5037 */
5038 }
5039
5040 /**
5041 * @brief Master Rx Transfer completed callback.
5042 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5043 * the configuration information for the specified I2C.
5044 * @retval None
5045 */
HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef * hi2c)5046 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
5047 {
5048 /* Prevent unused argument(s) compilation warning */
5049 UNUSED(hi2c);
5050
5051 /* NOTE : This function should not be modified, when the callback is needed,
5052 the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
5053 */
5054 }
5055
5056 /** @brief Slave Tx Transfer completed callback.
5057 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5058 * the configuration information for the specified I2C.
5059 * @retval None
5060 */
HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef * hi2c)5061 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
5062 {
5063 /* Prevent unused argument(s) compilation warning */
5064 UNUSED(hi2c);
5065
5066 /* NOTE : This function should not be modified, when the callback is needed,
5067 the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
5068 */
5069 }
5070
5071 /**
5072 * @brief Slave Rx Transfer completed callback.
5073 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5074 * the configuration information for the specified I2C.
5075 * @retval None
5076 */
HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef * hi2c)5077 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
5078 {
5079 /* Prevent unused argument(s) compilation warning */
5080 UNUSED(hi2c);
5081
5082 /* NOTE : This function should not be modified, when the callback is needed,
5083 the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
5084 */
5085 }
5086
5087 /**
5088 * @brief Slave Address Match callback.
5089 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5090 * the configuration information for the specified I2C.
5091 * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferDirection_definition
5092 * @param AddrMatchCode Address Match Code
5093 * @retval None
5094 */
HAL_I2C_AddrCallback(I2C_HandleTypeDef * hi2c,uint8_t TransferDirection,uint16_t AddrMatchCode)5095 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
5096 {
5097 /* Prevent unused argument(s) compilation warning */
5098 UNUSED(hi2c);
5099 UNUSED(TransferDirection);
5100 UNUSED(AddrMatchCode);
5101
5102 /* NOTE : This function should not be modified, when the callback is needed,
5103 the HAL_I2C_AddrCallback() could be implemented in the user file
5104 */
5105 }
5106
5107 /**
5108 * @brief Listen Complete callback.
5109 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5110 * the configuration information for the specified I2C.
5111 * @retval None
5112 */
HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef * hi2c)5113 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
5114 {
5115 /* Prevent unused argument(s) compilation warning */
5116 UNUSED(hi2c);
5117
5118 /* NOTE : This function should not be modified, when the callback is needed,
5119 the HAL_I2C_ListenCpltCallback() could be implemented in the user file
5120 */
5121 }
5122
5123 /**
5124 * @brief Memory Tx Transfer completed callback.
5125 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5126 * the configuration information for the specified I2C.
5127 * @retval None
5128 */
HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef * hi2c)5129 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
5130 {
5131 /* Prevent unused argument(s) compilation warning */
5132 UNUSED(hi2c);
5133
5134 /* NOTE : This function should not be modified, when the callback is needed,
5135 the HAL_I2C_MemTxCpltCallback could be implemented in the user file
5136 */
5137 }
5138
5139 /**
5140 * @brief Memory Rx Transfer completed callback.
5141 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5142 * the configuration information for the specified I2C.
5143 * @retval None
5144 */
HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef * hi2c)5145 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
5146 {
5147 /* Prevent unused argument(s) compilation warning */
5148 UNUSED(hi2c);
5149
5150 /* NOTE : This function should not be modified, when the callback is needed,
5151 the HAL_I2C_MemRxCpltCallback could be implemented in the user file
5152 */
5153 }
5154
5155 /**
5156 * @brief I2C error callback.
5157 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5158 * the configuration information for the specified I2C.
5159 * @retval None
5160 */
HAL_I2C_ErrorCallback(I2C_HandleTypeDef * hi2c)5161 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
5162 {
5163 /* Prevent unused argument(s) compilation warning */
5164 UNUSED(hi2c);
5165
5166 /* NOTE : This function should not be modified, when the callback is needed,
5167 the HAL_I2C_ErrorCallback could be implemented in the user file
5168 */
5169 }
5170
5171 /**
5172 * @brief I2C abort callback.
5173 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5174 * the configuration information for the specified I2C.
5175 * @retval None
5176 */
HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef * hi2c)5177 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
5178 {
5179 /* Prevent unused argument(s) compilation warning */
5180 UNUSED(hi2c);
5181
5182 /* NOTE : This function should not be modified, when the callback is needed,
5183 the HAL_I2C_AbortCpltCallback could be implemented in the user file
5184 */
5185 }
5186
5187 /**
5188 * @}
5189 */
5190
5191 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
5192 * @brief Peripheral State, Mode and Error functions
5193 *
5194 @verbatim
5195 ===============================================================================
5196 ##### Peripheral State, Mode and Error functions #####
5197 ===============================================================================
5198 [..]
5199 This subsection permit to get in run-time the status of the peripheral
5200 and the data flow.
5201
5202 @endverbatim
5203 * @{
5204 */
5205
5206 /**
5207 * @brief Return the I2C handle state.
5208 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5209 * the configuration information for the specified I2C.
5210 * @retval HAL state
5211 */
HAL_I2C_GetState(I2C_HandleTypeDef * hi2c)5212 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
5213 {
5214 /* Return I2C handle state */
5215 return hi2c->State;
5216 }
5217
5218 /**
5219 * @brief Returns the I2C Master, Slave, Memory or no mode.
5220 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5221 * the configuration information for I2C module
5222 * @retval HAL mode
5223 */
HAL_I2C_GetMode(I2C_HandleTypeDef * hi2c)5224 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
5225 {
5226 return hi2c->Mode;
5227 }
5228
5229 /**
5230 * @brief Return the I2C error code.
5231 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5232 * the configuration information for the specified I2C.
5233 * @retval I2C Error Code
5234 */
HAL_I2C_GetError(I2C_HandleTypeDef * hi2c)5235 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
5236 {
5237 return hi2c->ErrorCode;
5238 }
5239
5240 /**
5241 * @}
5242 */
5243
5244 /**
5245 * @}
5246 */
5247
5248 /** @addtogroup I2C_Private_Functions
5249 * @{
5250 */
5251
5252 /**
5253 * @brief Handle TXE flag for Master
5254 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5255 * the configuration information for I2C module
5256 * @retval None
5257 */
I2C_MasterTransmit_TXE(I2C_HandleTypeDef * hi2c)5258 static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
5259 {
5260 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5261 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
5262 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
5263 uint32_t CurrentXferOptions = hi2c->XferOptions;
5264
5265 if ((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
5266 {
5267 /* Call TxCpltCallback() directly if no stop mode is set */
5268 if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
5269 {
5270 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5271
5272 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
5273 hi2c->Mode = HAL_I2C_MODE_NONE;
5274 hi2c->State = HAL_I2C_STATE_READY;
5275
5276 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5277 hi2c->MasterTxCpltCallback(hi2c);
5278 #else
5279 HAL_I2C_MasterTxCpltCallback(hi2c);
5280 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5281 }
5282 else /* Generate Stop condition then Call TxCpltCallback() */
5283 {
5284 /* Disable EVT, BUF and ERR interrupt */
5285 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5286
5287 /* Generate Stop */
5288 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5289
5290 hi2c->PreviousState = I2C_STATE_NONE;
5291 hi2c->State = HAL_I2C_STATE_READY;
5292
5293 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5294 {
5295 hi2c->Mode = HAL_I2C_MODE_NONE;
5296 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5297 hi2c->MemTxCpltCallback(hi2c);
5298 #else
5299 HAL_I2C_MemTxCpltCallback(hi2c);
5300 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5301 }
5302 else
5303 {
5304 hi2c->Mode = HAL_I2C_MODE_NONE;
5305 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5306 hi2c->MasterTxCpltCallback(hi2c);
5307 #else
5308 HAL_I2C_MasterTxCpltCallback(hi2c);
5309 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5310 }
5311 }
5312 }
5313 else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || \
5314 ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX)))
5315 {
5316 if (hi2c->XferCount == 0U)
5317 {
5318 /* Disable BUF interrupt */
5319 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5320 }
5321 else
5322 {
5323 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5324 {
5325 I2C_MemoryTransmit_TXE_BTF(hi2c);
5326 }
5327 else
5328 {
5329 /* Write data to DR */
5330 hi2c->Instance->DR = *hi2c->pBuffPtr;
5331
5332 /* Increment Buffer pointer */
5333 hi2c->pBuffPtr++;
5334
5335 /* Update counter */
5336 hi2c->XferCount--;
5337 }
5338 }
5339 }
5340 else
5341 {
5342 /* Do nothing */
5343 }
5344 }
5345
5346 /**
5347 * @brief Handle BTF flag for Master transmitter
5348 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5349 * the configuration information for I2C module
5350 * @retval None
5351 */
I2C_MasterTransmit_BTF(I2C_HandleTypeDef * hi2c)5352 static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
5353 {
5354 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5355 uint32_t CurrentXferOptions = hi2c->XferOptions;
5356
5357 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5358 {
5359 if (hi2c->XferCount != 0U)
5360 {
5361 /* Write data to DR */
5362 hi2c->Instance->DR = *hi2c->pBuffPtr;
5363
5364 /* Increment Buffer pointer */
5365 hi2c->pBuffPtr++;
5366
5367 /* Update counter */
5368 hi2c->XferCount--;
5369 }
5370 else
5371 {
5372 /* Call TxCpltCallback() directly if no stop mode is set */
5373 if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
5374 {
5375 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5376
5377 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
5378 hi2c->Mode = HAL_I2C_MODE_NONE;
5379 hi2c->State = HAL_I2C_STATE_READY;
5380
5381 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5382 hi2c->MasterTxCpltCallback(hi2c);
5383 #else
5384 HAL_I2C_MasterTxCpltCallback(hi2c);
5385 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5386 }
5387 else /* Generate Stop condition then Call TxCpltCallback() */
5388 {
5389 /* Disable EVT, BUF and ERR interrupt */
5390 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5391
5392 /* Generate Stop */
5393 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5394
5395 hi2c->PreviousState = I2C_STATE_NONE;
5396 hi2c->State = HAL_I2C_STATE_READY;
5397 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5398 {
5399 hi2c->Mode = HAL_I2C_MODE_NONE;
5400 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5401 hi2c->MemTxCpltCallback(hi2c);
5402 #else
5403 HAL_I2C_MemTxCpltCallback(hi2c);
5404 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5405 }
5406 else
5407 {
5408 hi2c->Mode = HAL_I2C_MODE_NONE;
5409
5410 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5411 hi2c->MasterTxCpltCallback(hi2c);
5412 #else
5413 HAL_I2C_MasterTxCpltCallback(hi2c);
5414 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5415 }
5416 }
5417 }
5418 }
5419 else
5420 {
5421 /* Do nothing */
5422 }
5423 }
5424
5425 /**
5426 * @brief Handle TXE and BTF flag for Memory transmitter
5427 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5428 * the configuration information for I2C module
5429 * @retval None
5430 */
I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef * hi2c)5431 static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c)
5432 {
5433 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5434 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
5435
5436 if (hi2c->EventCount == 0U)
5437 {
5438 /* If Memory address size is 8Bit */
5439 if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
5440 {
5441 /* Send Memory Address */
5442 hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
5443
5444 hi2c->EventCount += 2U;
5445 }
5446 /* If Memory address size is 16Bit */
5447 else
5448 {
5449 /* Send MSB of Memory Address */
5450 hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress);
5451
5452 hi2c->EventCount++;
5453 }
5454 }
5455 else if (hi2c->EventCount == 1U)
5456 {
5457 /* Send LSB of Memory Address */
5458 hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
5459
5460 hi2c->EventCount++;
5461 }
5462 else if (hi2c->EventCount == 2U)
5463 {
5464 if (CurrentState == HAL_I2C_STATE_BUSY_RX)
5465 {
5466 /* Generate Restart */
5467 hi2c->Instance->CR1 |= I2C_CR1_START;
5468
5469 hi2c->EventCount++;
5470 }
5471 else if ((hi2c->XferCount > 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
5472 {
5473 /* Write data to DR */
5474 hi2c->Instance->DR = *hi2c->pBuffPtr;
5475
5476 /* Increment Buffer pointer */
5477 hi2c->pBuffPtr++;
5478
5479 /* Update counter */
5480 hi2c->XferCount--;
5481 }
5482 else if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
5483 {
5484 /* Generate Stop condition then Call TxCpltCallback() */
5485 /* Disable EVT, BUF and ERR interrupt */
5486 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5487
5488 /* Generate Stop */
5489 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5490
5491 hi2c->PreviousState = I2C_STATE_NONE;
5492 hi2c->State = HAL_I2C_STATE_READY;
5493 hi2c->Mode = HAL_I2C_MODE_NONE;
5494 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5495 hi2c->MemTxCpltCallback(hi2c);
5496 #else
5497 HAL_I2C_MemTxCpltCallback(hi2c);
5498 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5499 }
5500 else
5501 {
5502 /* Do nothing */
5503 }
5504 }
5505 else
5506 {
5507 /* Do nothing */
5508 }
5509 }
5510
5511 /**
5512 * @brief Handle RXNE flag for Master
5513 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5514 * the configuration information for I2C module
5515 * @retval None
5516 */
I2C_MasterReceive_RXNE(I2C_HandleTypeDef * hi2c)5517 static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
5518 {
5519 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5520 {
5521 uint32_t tmp;
5522
5523 tmp = hi2c->XferCount;
5524 if (tmp > 3U)
5525 {
5526 /* Read data from DR */
5527 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5528
5529 /* Increment Buffer pointer */
5530 hi2c->pBuffPtr++;
5531
5532 /* Update counter */
5533 hi2c->XferCount--;
5534
5535 if (hi2c->XferCount == (uint16_t)3)
5536 {
5537 /* Disable BUF interrupt, this help to treat correctly the last 4 bytes
5538 on BTF subroutine */
5539 /* Disable BUF interrupt */
5540 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5541 }
5542 }
5543 else if ((hi2c->XferOptions != I2C_FIRST_AND_NEXT_FRAME) && ((tmp == 1U) || (tmp == 0U)))
5544 {
5545 if (I2C_WaitOnSTOPRequestThroughIT(hi2c) == HAL_OK)
5546 {
5547 /* Disable Acknowledge */
5548 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5549
5550 /* Disable EVT, BUF and ERR interrupt */
5551 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5552
5553 /* Read data from DR */
5554 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5555
5556 /* Increment Buffer pointer */
5557 hi2c->pBuffPtr++;
5558
5559 /* Update counter */
5560 hi2c->XferCount--;
5561
5562 hi2c->State = HAL_I2C_STATE_READY;
5563
5564 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5565 {
5566 hi2c->Mode = HAL_I2C_MODE_NONE;
5567 hi2c->PreviousState = I2C_STATE_NONE;
5568
5569 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5570 hi2c->MemRxCpltCallback(hi2c);
5571 #else
5572 HAL_I2C_MemRxCpltCallback(hi2c);
5573 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5574 }
5575 else
5576 {
5577 hi2c->Mode = HAL_I2C_MODE_NONE;
5578 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
5579
5580 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5581 hi2c->MasterRxCpltCallback(hi2c);
5582 #else
5583 HAL_I2C_MasterRxCpltCallback(hi2c);
5584 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5585 }
5586 }
5587 else
5588 {
5589 /* Disable EVT, BUF and ERR interrupt */
5590 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5591
5592 /* Read data from DR */
5593 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5594
5595 /* Increment Buffer pointer */
5596 hi2c->pBuffPtr++;
5597
5598 /* Update counter */
5599 hi2c->XferCount--;
5600
5601 hi2c->State = HAL_I2C_STATE_READY;
5602 hi2c->Mode = HAL_I2C_MODE_NONE;
5603
5604 /* Call user error callback */
5605 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5606 hi2c->ErrorCallback(hi2c);
5607 #else
5608 HAL_I2C_ErrorCallback(hi2c);
5609 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5610 }
5611 }
5612 else
5613 {
5614 /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
5615 on BTF subroutine if there is a reception delay between N-1 and N byte */
5616 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5617 }
5618 }
5619 }
5620
5621 /**
5622 * @brief Handle BTF flag for Master receiver
5623 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5624 * the configuration information for I2C module
5625 * @retval None
5626 */
I2C_MasterReceive_BTF(I2C_HandleTypeDef * hi2c)5627 static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
5628 {
5629 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5630 uint32_t CurrentXferOptions = hi2c->XferOptions;
5631
5632 if (hi2c->XferCount == 4U)
5633 {
5634 /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
5635 on BTF subroutine if there is a reception delay between N-1 and N byte */
5636 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5637
5638 /* Read data from DR */
5639 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5640
5641 /* Increment Buffer pointer */
5642 hi2c->pBuffPtr++;
5643
5644 /* Update counter */
5645 hi2c->XferCount--;
5646 }
5647 else if (hi2c->XferCount == 3U)
5648 {
5649 /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
5650 on BTF subroutine if there is a reception delay between N-1 and N byte */
5651 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5652
5653 if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME))
5654 {
5655 /* Disable Acknowledge */
5656 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5657 }
5658
5659 /* Read data from DR */
5660 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5661
5662 /* Increment Buffer pointer */
5663 hi2c->pBuffPtr++;
5664
5665 /* Update counter */
5666 hi2c->XferCount--;
5667 }
5668 else if (hi2c->XferCount == 2U)
5669 {
5670 /* Prepare next transfer or stop current transfer */
5671 if ((CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP))
5672 {
5673 /* Disable Acknowledge */
5674 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5675 }
5676 else if ((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_NEXT_FRAME))
5677 {
5678 /* Enable Acknowledge */
5679 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5680 }
5681 else if (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)
5682 {
5683 /* Generate Stop */
5684 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5685 }
5686 else
5687 {
5688 /* Do nothing */
5689 }
5690
5691 /* Read data from DR */
5692 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5693
5694 /* Increment Buffer pointer */
5695 hi2c->pBuffPtr++;
5696
5697 /* Update counter */
5698 hi2c->XferCount--;
5699
5700 /* Read data from DR */
5701 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5702
5703 /* Increment Buffer pointer */
5704 hi2c->pBuffPtr++;
5705
5706 /* Update counter */
5707 hi2c->XferCount--;
5708
5709 /* Disable EVT and ERR interrupt */
5710 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
5711
5712 hi2c->State = HAL_I2C_STATE_READY;
5713 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5714 {
5715 hi2c->Mode = HAL_I2C_MODE_NONE;
5716 hi2c->PreviousState = I2C_STATE_NONE;
5717 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5718 hi2c->MemRxCpltCallback(hi2c);
5719 #else
5720 HAL_I2C_MemRxCpltCallback(hi2c);
5721 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5722 }
5723 else
5724 {
5725 hi2c->Mode = HAL_I2C_MODE_NONE;
5726 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
5727 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5728 hi2c->MasterRxCpltCallback(hi2c);
5729 #else
5730 HAL_I2C_MasterRxCpltCallback(hi2c);
5731 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5732 }
5733 }
5734 else
5735 {
5736 /* Read data from DR */
5737 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5738
5739 /* Increment Buffer pointer */
5740 hi2c->pBuffPtr++;
5741
5742 /* Update counter */
5743 hi2c->XferCount--;
5744 }
5745 }
5746
5747 /**
5748 * @brief Handle SB flag for Master
5749 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5750 * the configuration information for I2C module
5751 * @retval None
5752 */
I2C_Master_SB(I2C_HandleTypeDef * hi2c)5753 static void I2C_Master_SB(I2C_HandleTypeDef *hi2c)
5754 {
5755 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5756 {
5757 if (hi2c->EventCount == 0U)
5758 {
5759 /* Send slave address */
5760 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
5761 }
5762 else
5763 {
5764 hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
5765 }
5766 }
5767 else
5768 {
5769 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
5770 {
5771 /* Send slave 7 Bits address */
5772 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5773 {
5774 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
5775 }
5776 else
5777 {
5778 hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
5779 }
5780
5781 if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL))
5782 || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL)))
5783 {
5784 /* Enable DMA Request */
5785 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
5786 }
5787 }
5788 else
5789 {
5790 if (hi2c->EventCount == 0U)
5791 {
5792 /* Send header of slave address */
5793 hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress);
5794 }
5795 else if (hi2c->EventCount == 1U)
5796 {
5797 /* Send header of slave address */
5798 hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress);
5799 }
5800 else
5801 {
5802 /* Do nothing */
5803 }
5804 }
5805 }
5806 }
5807
5808 /**
5809 * @brief Handle ADD10 flag for Master
5810 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5811 * the configuration information for I2C module
5812 * @retval None
5813 */
I2C_Master_ADD10(I2C_HandleTypeDef * hi2c)5814 static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c)
5815 {
5816 /* Send slave address */
5817 hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress);
5818
5819 if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL))
5820 || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL)))
5821 {
5822 /* Enable DMA Request */
5823 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
5824 }
5825 }
5826
5827 /**
5828 * @brief Handle ADDR flag for Master
5829 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5830 * the configuration information for I2C module
5831 * @retval None
5832 */
I2C_Master_ADDR(I2C_HandleTypeDef * hi2c)5833 static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c)
5834 {
5835 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
5836 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
5837 uint32_t CurrentXferOptions = hi2c->XferOptions;
5838 uint32_t Prev_State = hi2c->PreviousState;
5839
5840 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5841 {
5842 if ((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM))
5843 {
5844 /* Clear ADDR flag */
5845 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5846 }
5847 else if ((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT))
5848 {
5849 /* Clear ADDR flag */
5850 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5851
5852 /* Generate Restart */
5853 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
5854
5855 hi2c->EventCount++;
5856 }
5857 else
5858 {
5859 if (hi2c->XferCount == 0U)
5860 {
5861 /* Clear ADDR flag */
5862 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5863
5864 /* Generate Stop */
5865 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5866 }
5867 else if (hi2c->XferCount == 1U)
5868 {
5869 if (CurrentXferOptions == I2C_NO_OPTION_FRAME)
5870 {
5871 /* Disable Acknowledge */
5872 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5873
5874 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
5875 {
5876 /* Disable Acknowledge */
5877 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5878
5879 /* Clear ADDR flag */
5880 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5881 }
5882 else
5883 {
5884 /* Clear ADDR flag */
5885 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5886
5887 /* Generate Stop */
5888 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5889 }
5890 }
5891 /* Prepare next transfer or stop current transfer */
5892 else if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \
5893 && ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (CurrentXferOptions == I2C_FIRST_FRAME)))
5894 {
5895 if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP))
5896 {
5897 /* Disable Acknowledge */
5898 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5899 }
5900 else
5901 {
5902 /* Enable Acknowledge */
5903 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5904 }
5905
5906 /* Clear ADDR flag */
5907 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5908 }
5909 else
5910 {
5911 /* Disable Acknowledge */
5912 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5913
5914 /* Clear ADDR flag */
5915 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5916
5917 /* Generate Stop */
5918 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5919 }
5920 }
5921 else if (hi2c->XferCount == 2U)
5922 {
5923 if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP))
5924 {
5925 /* Disable Acknowledge */
5926 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5927
5928 /* Enable Pos */
5929 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
5930 }
5931 else
5932 {
5933 /* Enable Acknowledge */
5934 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5935 }
5936
5937 if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME)))
5938 {
5939 /* Enable Last DMA bit */
5940 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
5941 }
5942
5943 /* Clear ADDR flag */
5944 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5945 }
5946 else
5947 {
5948 /* Enable Acknowledge */
5949 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5950
5951 if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME)))
5952 {
5953 /* Enable Last DMA bit */
5954 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
5955 }
5956
5957 /* Clear ADDR flag */
5958 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5959 }
5960
5961 /* Reset Event counter */
5962 hi2c->EventCount = 0U;
5963 }
5964 }
5965 else
5966 {
5967 /* Clear ADDR flag */
5968 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5969 }
5970 }
5971
5972 /**
5973 * @brief Handle TXE flag for Slave
5974 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5975 * the configuration information for I2C module
5976 * @retval None
5977 */
I2C_SlaveTransmit_TXE(I2C_HandleTypeDef * hi2c)5978 static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
5979 {
5980 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5981 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
5982
5983 if (hi2c->XferCount != 0U)
5984 {
5985 /* Write data to DR */
5986 hi2c->Instance->DR = *hi2c->pBuffPtr;
5987
5988 /* Increment Buffer pointer */
5989 hi2c->pBuffPtr++;
5990
5991 /* Update counter */
5992 hi2c->XferCount--;
5993
5994 if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
5995 {
5996 /* Last Byte is received, disable Interrupt */
5997 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5998
5999 /* Set state at HAL_I2C_STATE_LISTEN */
6000 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6001 hi2c->State = HAL_I2C_STATE_LISTEN;
6002
6003 /* Call the corresponding callback to inform upper layer of End of Transfer */
6004 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6005 hi2c->SlaveTxCpltCallback(hi2c);
6006 #else
6007 HAL_I2C_SlaveTxCpltCallback(hi2c);
6008 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6009 }
6010 }
6011 }
6012
6013 /**
6014 * @brief Handle BTF flag for Slave transmitter
6015 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6016 * the configuration information for I2C module
6017 * @retval None
6018 */
I2C_SlaveTransmit_BTF(I2C_HandleTypeDef * hi2c)6019 static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
6020 {
6021 if (hi2c->XferCount != 0U)
6022 {
6023 /* Write data to DR */
6024 hi2c->Instance->DR = *hi2c->pBuffPtr;
6025
6026 /* Increment Buffer pointer */
6027 hi2c->pBuffPtr++;
6028
6029 /* Update counter */
6030 hi2c->XferCount--;
6031 }
6032 }
6033
6034 /**
6035 * @brief Handle RXNE flag for Slave
6036 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6037 * the configuration information for I2C module
6038 * @retval None
6039 */
I2C_SlaveReceive_RXNE(I2C_HandleTypeDef * hi2c)6040 static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
6041 {
6042 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
6043 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6044
6045 if (hi2c->XferCount != 0U)
6046 {
6047 /* Read data from DR */
6048 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6049
6050 /* Increment Buffer pointer */
6051 hi2c->pBuffPtr++;
6052
6053 /* Update counter */
6054 hi2c->XferCount--;
6055
6056 if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
6057 {
6058 /* Last Byte is received, disable Interrupt */
6059 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
6060
6061 /* Set state at HAL_I2C_STATE_LISTEN */
6062 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6063 hi2c->State = HAL_I2C_STATE_LISTEN;
6064
6065 /* Call the corresponding callback to inform upper layer of End of Transfer */
6066 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6067 hi2c->SlaveRxCpltCallback(hi2c);
6068 #else
6069 HAL_I2C_SlaveRxCpltCallback(hi2c);
6070 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6071 }
6072 }
6073 }
6074
6075 /**
6076 * @brief Handle BTF flag for Slave receiver
6077 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6078 * the configuration information for I2C module
6079 * @retval None
6080 */
I2C_SlaveReceive_BTF(I2C_HandleTypeDef * hi2c)6081 static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
6082 {
6083 if (hi2c->XferCount != 0U)
6084 {
6085 /* Read data from DR */
6086 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6087
6088 /* Increment Buffer pointer */
6089 hi2c->pBuffPtr++;
6090
6091 /* Update counter */
6092 hi2c->XferCount--;
6093 }
6094 }
6095
6096 /**
6097 * @brief Handle ADD flag for Slave
6098 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6099 * the configuration information for I2C module
6100 * @param IT2Flags Interrupt2 flags to handle.
6101 * @retval None
6102 */
I2C_Slave_ADDR(I2C_HandleTypeDef * hi2c,uint32_t IT2Flags)6103 static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags)
6104 {
6105 uint8_t TransferDirection = I2C_DIRECTION_RECEIVE;
6106 uint16_t SlaveAddrCode;
6107
6108 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
6109 {
6110 /* Disable BUF interrupt, BUF enabling is manage through slave specific interface */
6111 __HAL_I2C_DISABLE_IT(hi2c, (I2C_IT_BUF));
6112
6113 /* Transfer Direction requested by Master */
6114 if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_TRA) == RESET)
6115 {
6116 TransferDirection = I2C_DIRECTION_TRANSMIT;
6117 }
6118
6119 if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_DUALF) == RESET)
6120 {
6121 SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress1;
6122 }
6123 else
6124 {
6125 SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress2;
6126 }
6127
6128 /* Process Unlocked */
6129 __HAL_UNLOCK(hi2c);
6130
6131 /* Call Slave Addr callback */
6132 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6133 hi2c->AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
6134 #else
6135 HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
6136 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6137 }
6138 else
6139 {
6140 /* Clear ADDR flag */
6141 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6142
6143 /* Process Unlocked */
6144 __HAL_UNLOCK(hi2c);
6145 }
6146 }
6147
6148 /**
6149 * @brief Handle STOPF flag for Slave
6150 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6151 * the configuration information for I2C module
6152 * @retval None
6153 */
I2C_Slave_STOPF(I2C_HandleTypeDef * hi2c)6154 static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
6155 {
6156 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6157 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6158
6159 /* Disable EVT, BUF and ERR interrupt */
6160 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
6161
6162 /* Clear STOPF flag */
6163 __HAL_I2C_CLEAR_STOPFLAG(hi2c);
6164
6165 /* Disable Acknowledge */
6166 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6167
6168 /* If a DMA is ongoing, Update handle size context */
6169 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
6170 {
6171 if ((CurrentState == HAL_I2C_STATE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
6172 {
6173 hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmarx));
6174
6175 if (hi2c->XferCount != 0U)
6176 {
6177 /* Set ErrorCode corresponding to a Non-Acknowledge */
6178 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6179 }
6180
6181 /* Disable, stop the current DMA */
6182 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
6183
6184 /* Abort DMA Xfer if any */
6185 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
6186 {
6187 /* Set the I2C DMA Abort callback :
6188 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6189 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
6190
6191 /* Abort DMA RX */
6192 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
6193 {
6194 /* Call Directly XferAbortCallback function in case of error */
6195 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
6196 }
6197 }
6198 }
6199 else
6200 {
6201 hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmatx));
6202
6203 if (hi2c->XferCount != 0U)
6204 {
6205 /* Set ErrorCode corresponding to a Non-Acknowledge */
6206 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6207 }
6208
6209 /* Disable, stop the current DMA */
6210 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
6211
6212 /* Abort DMA Xfer if any */
6213 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
6214 {
6215 /* Set the I2C DMA Abort callback :
6216 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6217 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
6218
6219 /* Abort DMA TX */
6220 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
6221 {
6222 /* Call Directly XferAbortCallback function in case of error */
6223 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
6224 }
6225 }
6226 }
6227 }
6228
6229 /* All data are not transferred, so set error code accordingly */
6230 if (hi2c->XferCount != 0U)
6231 {
6232 /* Store Last receive data if any */
6233 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
6234 {
6235 /* Read data from DR */
6236 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6237
6238 /* Increment Buffer pointer */
6239 hi2c->pBuffPtr++;
6240
6241 /* Update counter */
6242 hi2c->XferCount--;
6243 }
6244
6245 /* Store Last receive data if any */
6246 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6247 {
6248 /* Read data from DR */
6249 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6250
6251 /* Increment Buffer pointer */
6252 hi2c->pBuffPtr++;
6253
6254 /* Update counter */
6255 hi2c->XferCount--;
6256 }
6257
6258 if (hi2c->XferCount != 0U)
6259 {
6260 /* Set ErrorCode corresponding to a Non-Acknowledge */
6261 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6262 }
6263 }
6264
6265 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
6266 {
6267 /* Call the corresponding callback to inform upper layer of End of Transfer */
6268 I2C_ITError(hi2c);
6269 }
6270 else
6271 {
6272 if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)
6273 {
6274 /* Set state at HAL_I2C_STATE_LISTEN */
6275 hi2c->PreviousState = I2C_STATE_NONE;
6276 hi2c->State = HAL_I2C_STATE_LISTEN;
6277
6278 /* Call the corresponding callback to inform upper layer of End of Transfer */
6279 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6280 hi2c->SlaveRxCpltCallback(hi2c);
6281 #else
6282 HAL_I2C_SlaveRxCpltCallback(hi2c);
6283 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6284 }
6285
6286 if (hi2c->State == HAL_I2C_STATE_LISTEN)
6287 {
6288 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6289 hi2c->PreviousState = I2C_STATE_NONE;
6290 hi2c->State = HAL_I2C_STATE_READY;
6291 hi2c->Mode = HAL_I2C_MODE_NONE;
6292
6293 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6294 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6295 hi2c->ListenCpltCallback(hi2c);
6296 #else
6297 HAL_I2C_ListenCpltCallback(hi2c);
6298 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6299 }
6300 else
6301 {
6302 if ((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX))
6303 {
6304 hi2c->PreviousState = I2C_STATE_NONE;
6305 hi2c->State = HAL_I2C_STATE_READY;
6306 hi2c->Mode = HAL_I2C_MODE_NONE;
6307
6308 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6309 hi2c->SlaveRxCpltCallback(hi2c);
6310 #else
6311 HAL_I2C_SlaveRxCpltCallback(hi2c);
6312 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6313 }
6314 }
6315 }
6316 }
6317
6318 /**
6319 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6320 * the configuration information for I2C module
6321 * @retval None
6322 */
I2C_Slave_AF(I2C_HandleTypeDef * hi2c)6323 static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
6324 {
6325 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
6326 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6327 uint32_t CurrentXferOptions = hi2c->XferOptions;
6328
6329 if (((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \
6330 (CurrentState == HAL_I2C_STATE_LISTEN))
6331 {
6332 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6333
6334 /* Disable EVT, BUF and ERR interrupt */
6335 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
6336
6337 /* Clear AF flag */
6338 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6339
6340 /* Disable Acknowledge */
6341 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6342
6343 hi2c->PreviousState = I2C_STATE_NONE;
6344 hi2c->State = HAL_I2C_STATE_READY;
6345 hi2c->Mode = HAL_I2C_MODE_NONE;
6346
6347 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6348 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6349 hi2c->ListenCpltCallback(hi2c);
6350 #else
6351 HAL_I2C_ListenCpltCallback(hi2c);
6352 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6353 }
6354 else if (CurrentState == HAL_I2C_STATE_BUSY_TX)
6355 {
6356 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6357 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6358 hi2c->State = HAL_I2C_STATE_READY;
6359 hi2c->Mode = HAL_I2C_MODE_NONE;
6360
6361 /* Disable EVT, BUF and ERR interrupt */
6362 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
6363
6364 /* Clear AF flag */
6365 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6366
6367 /* Disable Acknowledge */
6368 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6369
6370 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6371 hi2c->SlaveTxCpltCallback(hi2c);
6372 #else
6373 HAL_I2C_SlaveTxCpltCallback(hi2c);
6374 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6375 }
6376 else
6377 {
6378 /* Clear AF flag only */
6379 /* State Listen, but XferOptions == FIRST or NEXT */
6380 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6381 }
6382 }
6383
6384 /**
6385 * @brief I2C interrupts error process
6386 * @param hi2c I2C handle.
6387 * @retval None
6388 */
I2C_ITError(I2C_HandleTypeDef * hi2c)6389 static void I2C_ITError(I2C_HandleTypeDef *hi2c)
6390 {
6391 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6392 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6393 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
6394 uint32_t CurrentError;
6395
6396 if (((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) && (CurrentState == HAL_I2C_STATE_BUSY_RX))
6397 {
6398 /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
6399 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
6400 }
6401
6402 if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
6403 {
6404 /* keep HAL_I2C_STATE_LISTEN */
6405 hi2c->PreviousState = I2C_STATE_NONE;
6406 hi2c->State = HAL_I2C_STATE_LISTEN;
6407 }
6408 else
6409 {
6410 /* If state is an abort treatment on going, don't change state */
6411 /* This change will be do later */
6412 if ((READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) && (CurrentState != HAL_I2C_STATE_ABORT))
6413 {
6414 hi2c->State = HAL_I2C_STATE_READY;
6415 hi2c->Mode = HAL_I2C_MODE_NONE;
6416 }
6417 hi2c->PreviousState = I2C_STATE_NONE;
6418 }
6419
6420 /* Abort DMA transfer */
6421 if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
6422 {
6423 hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
6424
6425 if (hi2c->hdmatx->State != HAL_DMA_STATE_READY)
6426 {
6427 /* Set the DMA Abort callback :
6428 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6429 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
6430
6431 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
6432 {
6433 /* Disable I2C peripheral to prevent dummy data in buffer */
6434 __HAL_I2C_DISABLE(hi2c);
6435
6436 hi2c->State = HAL_I2C_STATE_READY;
6437
6438 /* Call Directly XferAbortCallback function in case of error */
6439 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
6440 }
6441 }
6442 else
6443 {
6444 /* Set the DMA Abort callback :
6445 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6446 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
6447
6448 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
6449 {
6450 /* Store Last receive data if any */
6451 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6452 {
6453 /* Read data from DR */
6454 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6455
6456 /* Increment Buffer pointer */
6457 hi2c->pBuffPtr++;
6458 }
6459
6460 /* Disable I2C peripheral to prevent dummy data in buffer */
6461 __HAL_I2C_DISABLE(hi2c);
6462
6463 hi2c->State = HAL_I2C_STATE_READY;
6464
6465 /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
6466 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
6467 }
6468 }
6469 }
6470 else if (hi2c->State == HAL_I2C_STATE_ABORT)
6471 {
6472 hi2c->State = HAL_I2C_STATE_READY;
6473 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
6474
6475 /* Store Last receive data if any */
6476 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6477 {
6478 /* Read data from DR */
6479 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6480
6481 /* Increment Buffer pointer */
6482 hi2c->pBuffPtr++;
6483 }
6484
6485 /* Disable I2C peripheral to prevent dummy data in buffer */
6486 __HAL_I2C_DISABLE(hi2c);
6487
6488 /* Call the corresponding callback to inform upper layer of End of Transfer */
6489 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6490 hi2c->AbortCpltCallback(hi2c);
6491 #else
6492 HAL_I2C_AbortCpltCallback(hi2c);
6493 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6494 }
6495 else
6496 {
6497 /* Store Last receive data if any */
6498 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6499 {
6500 /* Read data from DR */
6501 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6502
6503 /* Increment Buffer pointer */
6504 hi2c->pBuffPtr++;
6505 }
6506
6507 /* Call user error callback */
6508 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6509 hi2c->ErrorCallback(hi2c);
6510 #else
6511 HAL_I2C_ErrorCallback(hi2c);
6512 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6513 }
6514
6515 /* STOP Flag is not set after a NACK reception, BusError, ArbitrationLost, OverRun */
6516 CurrentError = hi2c->ErrorCode;
6517
6518 if (((CurrentError & HAL_I2C_ERROR_BERR) == HAL_I2C_ERROR_BERR) || \
6519 ((CurrentError & HAL_I2C_ERROR_ARLO) == HAL_I2C_ERROR_ARLO) || \
6520 ((CurrentError & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) || \
6521 ((CurrentError & HAL_I2C_ERROR_OVR) == HAL_I2C_ERROR_OVR))
6522 {
6523 /* Disable EVT, BUF and ERR interrupt */
6524 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
6525 }
6526
6527 /* So may inform upper layer that listen phase is stopped */
6528 /* during NACK error treatment */
6529 CurrentState = hi2c->State;
6530 if (((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) && (CurrentState == HAL_I2C_STATE_LISTEN))
6531 {
6532 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6533 hi2c->PreviousState = I2C_STATE_NONE;
6534 hi2c->State = HAL_I2C_STATE_READY;
6535 hi2c->Mode = HAL_I2C_MODE_NONE;
6536
6537 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6538 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6539 hi2c->ListenCpltCallback(hi2c);
6540 #else
6541 HAL_I2C_ListenCpltCallback(hi2c);
6542 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6543 }
6544 }
6545
6546 /**
6547 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6548 * the configuration information for I2C module
6549 * @param DevAddress Target device address: The device 7 bits address value
6550 * in datasheet must be shifted to the left before calling the interface
6551 * @param Timeout Timeout duration
6552 * @param Tickstart Tick start value
6553 * @retval HAL status
6554 */
I2C_MasterRequestWrite(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Timeout,uint32_t Tickstart)6555 static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
6556 {
6557 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6558 uint32_t CurrentXferOptions = hi2c->XferOptions;
6559
6560 /* Generate Start condition if first transfer */
6561 if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
6562 {
6563 /* Generate Start */
6564 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6565 }
6566 else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
6567 {
6568 /* Generate ReStart */
6569 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6570 }
6571 else
6572 {
6573 /* Do nothing */
6574 }
6575
6576 /* Wait until SB flag is set */
6577 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6578 {
6579 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6580 {
6581 hi2c->ErrorCode = HAL_I2C_WRONG_START;
6582 }
6583 return HAL_TIMEOUT;
6584 }
6585
6586 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
6587 {
6588 /* Send slave address */
6589 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
6590 }
6591 else
6592 {
6593 /* Send header of slave address */
6594 hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
6595
6596 /* Wait until ADD10 flag is set */
6597 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
6598 {
6599 return HAL_ERROR;
6600 }
6601
6602 /* Send slave address */
6603 hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
6604 }
6605
6606 /* Wait until ADDR flag is set */
6607 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6608 {
6609 return HAL_ERROR;
6610 }
6611
6612 return HAL_OK;
6613 }
6614
6615 /**
6616 * @brief Master sends target device address for read request.
6617 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6618 * the configuration information for I2C module
6619 * @param DevAddress Target device address: The device 7 bits address value
6620 * in datasheet must be shifted to the left before calling the interface
6621 * @param Timeout Timeout duration
6622 * @param Tickstart Tick start value
6623 * @retval HAL status
6624 */
I2C_MasterRequestRead(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Timeout,uint32_t Tickstart)6625 static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
6626 {
6627 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6628 uint32_t CurrentXferOptions = hi2c->XferOptions;
6629
6630 /* Enable Acknowledge */
6631 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6632
6633 /* Generate Start condition if first transfer */
6634 if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
6635 {
6636 /* Generate Start */
6637 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6638 }
6639 else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
6640 {
6641 /* Generate ReStart */
6642 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6643 }
6644 else
6645 {
6646 /* Do nothing */
6647 }
6648
6649 /* Wait until SB flag is set */
6650 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6651 {
6652 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6653 {
6654 hi2c->ErrorCode = HAL_I2C_WRONG_START;
6655 }
6656 return HAL_TIMEOUT;
6657 }
6658
6659 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
6660 {
6661 /* Send slave address */
6662 hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
6663 }
6664 else
6665 {
6666 /* Send header of slave address */
6667 hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
6668
6669 /* Wait until ADD10 flag is set */
6670 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
6671 {
6672 return HAL_ERROR;
6673 }
6674
6675 /* Send slave address */
6676 hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
6677
6678 /* Wait until ADDR flag is set */
6679 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6680 {
6681 return HAL_ERROR;
6682 }
6683
6684 /* Clear ADDR flag */
6685 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6686
6687 /* Generate Restart */
6688 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6689
6690 /* Wait until SB flag is set */
6691 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6692 {
6693 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6694 {
6695 hi2c->ErrorCode = HAL_I2C_WRONG_START;
6696 }
6697 return HAL_TIMEOUT;
6698 }
6699
6700 /* Send header of slave address */
6701 hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
6702 }
6703
6704 /* Wait until ADDR flag is set */
6705 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6706 {
6707 return HAL_ERROR;
6708 }
6709
6710 return HAL_OK;
6711 }
6712
6713 /**
6714 * @brief Master sends target device address followed by internal memory address for write request.
6715 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6716 * the configuration information for I2C module
6717 * @param DevAddress Target device address: The device 7 bits address value
6718 * in datasheet must be shifted to the left before calling the interface
6719 * @param MemAddress Internal memory address
6720 * @param MemAddSize Size of internal memory address
6721 * @param Timeout Timeout duration
6722 * @param Tickstart Tick start value
6723 * @retval HAL status
6724 */
I2C_RequestMemoryWrite(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)6725 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
6726 {
6727 /* Generate Start */
6728 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6729
6730 /* Wait until SB flag is set */
6731 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6732 {
6733 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6734 {
6735 hi2c->ErrorCode = HAL_I2C_WRONG_START;
6736 }
6737 return HAL_TIMEOUT;
6738 }
6739
6740 /* Send slave address */
6741 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
6742
6743 /* Wait until ADDR flag is set */
6744 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6745 {
6746 return HAL_ERROR;
6747 }
6748
6749 /* Clear ADDR flag */
6750 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6751
6752 /* Wait until TXE flag is set */
6753 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6754 {
6755 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6756 {
6757 /* Generate Stop */
6758 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6759 }
6760 return HAL_ERROR;
6761 }
6762
6763 /* If Memory address size is 8Bit */
6764 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
6765 {
6766 /* Send Memory Address */
6767 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6768 }
6769 /* If Memory address size is 16Bit */
6770 else
6771 {
6772 /* Send MSB of Memory Address */
6773 hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
6774
6775 /* Wait until TXE flag is set */
6776 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6777 {
6778 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6779 {
6780 /* Generate Stop */
6781 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6782 }
6783 return HAL_ERROR;
6784 }
6785
6786 /* Send LSB of Memory Address */
6787 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6788 }
6789
6790 return HAL_OK;
6791 }
6792
6793 /**
6794 * @brief Master sends target device address followed by internal memory address for read request.
6795 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6796 * the configuration information for I2C module
6797 * @param DevAddress Target device address: The device 7 bits address value
6798 * in datasheet must be shifted to the left before calling the interface
6799 * @param MemAddress Internal memory address
6800 * @param MemAddSize Size of internal memory address
6801 * @param Timeout Timeout duration
6802 * @param Tickstart Tick start value
6803 * @retval HAL status
6804 */
I2C_RequestMemoryRead(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)6805 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
6806 {
6807 /* Enable Acknowledge */
6808 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6809
6810 /* Generate Start */
6811 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6812
6813 /* Wait until SB flag is set */
6814 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6815 {
6816 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6817 {
6818 hi2c->ErrorCode = HAL_I2C_WRONG_START;
6819 }
6820 return HAL_TIMEOUT;
6821 }
6822
6823 /* Send slave address */
6824 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
6825
6826 /* Wait until ADDR flag is set */
6827 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6828 {
6829 return HAL_ERROR;
6830 }
6831
6832 /* Clear ADDR flag */
6833 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6834
6835 /* Wait until TXE flag is set */
6836 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6837 {
6838 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6839 {
6840 /* Generate Stop */
6841 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6842 }
6843 return HAL_ERROR;
6844 }
6845
6846 /* If Memory address size is 8Bit */
6847 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
6848 {
6849 /* Send Memory Address */
6850 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6851 }
6852 /* If Memory address size is 16Bit */
6853 else
6854 {
6855 /* Send MSB of Memory Address */
6856 hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
6857
6858 /* Wait until TXE flag is set */
6859 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6860 {
6861 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6862 {
6863 /* Generate Stop */
6864 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6865 }
6866 return HAL_ERROR;
6867 }
6868
6869 /* Send LSB of Memory Address */
6870 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6871 }
6872
6873 /* Wait until TXE flag is set */
6874 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6875 {
6876 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6877 {
6878 /* Generate Stop */
6879 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6880 }
6881 return HAL_ERROR;
6882 }
6883
6884 /* Generate Restart */
6885 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6886
6887 /* Wait until SB flag is set */
6888 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6889 {
6890 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6891 {
6892 hi2c->ErrorCode = HAL_I2C_WRONG_START;
6893 }
6894 return HAL_TIMEOUT;
6895 }
6896
6897 /* Send slave address */
6898 hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
6899
6900 /* Wait until ADDR flag is set */
6901 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6902 {
6903 return HAL_ERROR;
6904 }
6905
6906 return HAL_OK;
6907 }
6908
6909 /**
6910 * @brief DMA I2C process complete callback.
6911 * @param hdma DMA handle
6912 * @retval None
6913 */
I2C_DMAXferCplt(DMA_HandleTypeDef * hdma)6914 static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
6915 {
6916 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
6917
6918 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6919 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6920 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
6921 uint32_t CurrentXferOptions = hi2c->XferOptions;
6922
6923 /* Disable EVT and ERR interrupt */
6924 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
6925
6926 /* Clear Complete callback */
6927 if (hi2c->hdmatx != NULL)
6928 {
6929 hi2c->hdmatx->XferCpltCallback = NULL;
6930 }
6931 if (hi2c->hdmarx != NULL)
6932 {
6933 hi2c->hdmarx->XferCpltCallback = NULL;
6934 }
6935
6936 if ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_TX) == (uint32_t)HAL_I2C_STATE_BUSY_TX) || ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_RX) == (uint32_t)HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE)))
6937 {
6938 /* Disable DMA Request */
6939 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
6940
6941 hi2c->XferCount = 0U;
6942
6943 if (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)
6944 {
6945 /* Set state at HAL_I2C_STATE_LISTEN */
6946 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6947 hi2c->State = HAL_I2C_STATE_LISTEN;
6948
6949 /* Call the corresponding callback to inform upper layer of End of Transfer */
6950 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6951 hi2c->SlaveTxCpltCallback(hi2c);
6952 #else
6953 HAL_I2C_SlaveTxCpltCallback(hi2c);
6954 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6955 }
6956 else if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)
6957 {
6958 /* Set state at HAL_I2C_STATE_LISTEN */
6959 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6960 hi2c->State = HAL_I2C_STATE_LISTEN;
6961
6962 /* Call the corresponding callback to inform upper layer of End of Transfer */
6963 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6964 hi2c->SlaveRxCpltCallback(hi2c);
6965 #else
6966 HAL_I2C_SlaveRxCpltCallback(hi2c);
6967 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6968 }
6969 else
6970 {
6971 /* Do nothing */
6972 }
6973
6974 /* Enable EVT and ERR interrupt to treat end of transfer in IRQ handler */
6975 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
6976 }
6977 /* Check current Mode, in case of treatment DMA handler have been preempted by a prior interrupt */
6978 else if (hi2c->Mode != HAL_I2C_MODE_NONE)
6979 {
6980 if (hi2c->XferCount == (uint16_t)1)
6981 {
6982 /* Disable Acknowledge */
6983 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6984 }
6985
6986 /* Disable EVT and ERR interrupt */
6987 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
6988
6989 /* Prepare next transfer or stop current transfer */
6990 if ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_OTHER_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME))
6991 {
6992 /* Generate Stop */
6993 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6994 }
6995
6996 /* Disable Last DMA */
6997 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
6998
6999 /* Disable DMA Request */
7000 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
7001
7002 hi2c->XferCount = 0U;
7003
7004 /* Check if Errors has been detected during transfer */
7005 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
7006 {
7007 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7008 hi2c->ErrorCallback(hi2c);
7009 #else
7010 HAL_I2C_ErrorCallback(hi2c);
7011 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7012 }
7013 else
7014 {
7015 hi2c->State = HAL_I2C_STATE_READY;
7016
7017 if (hi2c->Mode == HAL_I2C_MODE_MEM)
7018 {
7019 hi2c->Mode = HAL_I2C_MODE_NONE;
7020 hi2c->PreviousState = I2C_STATE_NONE;
7021
7022 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7023 hi2c->MemRxCpltCallback(hi2c);
7024 #else
7025 HAL_I2C_MemRxCpltCallback(hi2c);
7026 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7027 }
7028 else
7029 {
7030 hi2c->Mode = HAL_I2C_MODE_NONE;
7031 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
7032
7033 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7034 hi2c->MasterRxCpltCallback(hi2c);
7035 #else
7036 HAL_I2C_MasterRxCpltCallback(hi2c);
7037 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7038 }
7039 }
7040 }
7041 else
7042 {
7043 /* Do nothing */
7044 }
7045 }
7046
7047 /**
7048 * @brief DMA I2C communication error callback.
7049 * @param hdma DMA handle
7050 * @retval None
7051 */
I2C_DMAError(DMA_HandleTypeDef * hdma)7052 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
7053 {
7054 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
7055
7056 /* Clear Complete callback */
7057 if (hi2c->hdmatx != NULL)
7058 {
7059 hi2c->hdmatx->XferCpltCallback = NULL;
7060 }
7061 if (hi2c->hdmarx != NULL)
7062 {
7063 hi2c->hdmarx->XferCpltCallback = NULL;
7064 }
7065
7066 /* Ignore DMA FIFO error */
7067 if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
7068 {
7069 /* Disable Acknowledge */
7070 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
7071
7072 hi2c->XferCount = 0U;
7073
7074 hi2c->State = HAL_I2C_STATE_READY;
7075 hi2c->Mode = HAL_I2C_MODE_NONE;
7076
7077 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
7078
7079 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7080 hi2c->ErrorCallback(hi2c);
7081 #else
7082 HAL_I2C_ErrorCallback(hi2c);
7083 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7084 }
7085 }
7086
7087 /**
7088 * @brief DMA I2C communication abort callback
7089 * (To be called at end of DMA Abort procedure).
7090 * @param hdma DMA handle.
7091 * @retval None
7092 */
I2C_DMAAbort(DMA_HandleTypeDef * hdma)7093 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
7094 {
7095 __IO uint32_t count = 0U;
7096 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
7097
7098 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
7099 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
7100
7101 /* During abort treatment, check that there is no pending STOP request */
7102 /* Wait until STOP flag is reset */
7103 count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U);
7104 do
7105 {
7106 if (count == 0U)
7107 {
7108 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7109 break;
7110 }
7111 count--;
7112 }
7113 while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP);
7114
7115 /* Clear Complete callback */
7116 if (hi2c->hdmatx != NULL)
7117 {
7118 hi2c->hdmatx->XferCpltCallback = NULL;
7119 }
7120 if (hi2c->hdmarx != NULL)
7121 {
7122 hi2c->hdmarx->XferCpltCallback = NULL;
7123 }
7124
7125 /* Disable Acknowledge */
7126 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
7127
7128 hi2c->XferCount = 0U;
7129
7130 /* Reset XferAbortCallback */
7131 if (hi2c->hdmatx != NULL)
7132 {
7133 hi2c->hdmatx->XferAbortCallback = NULL;
7134 }
7135 if (hi2c->hdmarx != NULL)
7136 {
7137 hi2c->hdmarx->XferAbortCallback = NULL;
7138 }
7139
7140 /* Disable I2C peripheral to prevent dummy data in buffer */
7141 __HAL_I2C_DISABLE(hi2c);
7142
7143 /* Check if come from abort from user */
7144 if (hi2c->State == HAL_I2C_STATE_ABORT)
7145 {
7146 hi2c->State = HAL_I2C_STATE_READY;
7147 hi2c->Mode = HAL_I2C_MODE_NONE;
7148 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
7149
7150 /* Call the corresponding callback to inform upper layer of End of Transfer */
7151 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7152 hi2c->AbortCpltCallback(hi2c);
7153 #else
7154 HAL_I2C_AbortCpltCallback(hi2c);
7155 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7156 }
7157 else
7158 {
7159 if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
7160 {
7161 /* Renable I2C peripheral */
7162 __HAL_I2C_ENABLE(hi2c);
7163
7164 /* Enable Acknowledge */
7165 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
7166
7167 /* keep HAL_I2C_STATE_LISTEN */
7168 hi2c->PreviousState = I2C_STATE_NONE;
7169 hi2c->State = HAL_I2C_STATE_LISTEN;
7170 }
7171 else
7172 {
7173 hi2c->State = HAL_I2C_STATE_READY;
7174 hi2c->Mode = HAL_I2C_MODE_NONE;
7175 }
7176
7177 /* Call the corresponding callback to inform upper layer of End of Transfer */
7178 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7179 hi2c->ErrorCallback(hi2c);
7180 #else
7181 HAL_I2C_ErrorCallback(hi2c);
7182 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7183 }
7184 }
7185
7186 /**
7187 * @brief This function handles I2C Communication Timeout.
7188 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7189 * the configuration information for I2C module
7190 * @param Flag specifies the I2C flag to check.
7191 * @param Status The new Flag status (SET or RESET).
7192 * @param Timeout Timeout duration
7193 * @param Tickstart Tick start value
7194 * @retval HAL status
7195 */
I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Flag,FlagStatus Status,uint32_t Timeout,uint32_t Tickstart)7196 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
7197 {
7198 /* Wait until flag is set */
7199 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
7200 {
7201 /* Check for the Timeout */
7202 if (Timeout != HAL_MAX_DELAY)
7203 {
7204 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7205 {
7206 hi2c->PreviousState = I2C_STATE_NONE;
7207 hi2c->State = HAL_I2C_STATE_READY;
7208 hi2c->Mode = HAL_I2C_MODE_NONE;
7209 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7210
7211 /* Process Unlocked */
7212 __HAL_UNLOCK(hi2c);
7213
7214 return HAL_ERROR;
7215 }
7216 }
7217 }
7218 return HAL_OK;
7219 }
7220
7221 /**
7222 * @brief This function handles I2C Communication Timeout for Master addressing phase.
7223 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7224 * the configuration information for I2C module
7225 * @param Flag specifies the I2C flag to check.
7226 * @param Timeout Timeout duration
7227 * @param Tickstart Tick start value
7228 * @retval HAL status
7229 */
I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Flag,uint32_t Timeout,uint32_t Tickstart)7230 static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
7231 {
7232 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
7233 {
7234 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
7235 {
7236 /* Generate Stop */
7237 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
7238
7239 /* Clear AF Flag */
7240 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7241
7242 hi2c->PreviousState = I2C_STATE_NONE;
7243 hi2c->State = HAL_I2C_STATE_READY;
7244 hi2c->Mode = HAL_I2C_MODE_NONE;
7245 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
7246
7247 /* Process Unlocked */
7248 __HAL_UNLOCK(hi2c);
7249
7250 return HAL_ERROR;
7251 }
7252
7253 /* Check for the Timeout */
7254 if (Timeout != HAL_MAX_DELAY)
7255 {
7256 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7257 {
7258 hi2c->PreviousState = I2C_STATE_NONE;
7259 hi2c->State = HAL_I2C_STATE_READY;
7260 hi2c->Mode = HAL_I2C_MODE_NONE;
7261 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7262
7263 /* Process Unlocked */
7264 __HAL_UNLOCK(hi2c);
7265
7266 return HAL_ERROR;
7267 }
7268 }
7269 }
7270 return HAL_OK;
7271 }
7272
7273 /**
7274 * @brief This function handles I2C Communication Timeout for specific usage of TXE flag.
7275 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7276 * the configuration information for the specified I2C.
7277 * @param Timeout Timeout duration
7278 * @param Tickstart Tick start value
7279 * @retval HAL status
7280 */
I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7281 static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7282 {
7283 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
7284 {
7285 /* Check if a NACK is detected */
7286 if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
7287 {
7288 return HAL_ERROR;
7289 }
7290
7291 /* Check for the Timeout */
7292 if (Timeout != HAL_MAX_DELAY)
7293 {
7294 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7295 {
7296 hi2c->PreviousState = I2C_STATE_NONE;
7297 hi2c->State = HAL_I2C_STATE_READY;
7298 hi2c->Mode = HAL_I2C_MODE_NONE;
7299 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7300
7301 /* Process Unlocked */
7302 __HAL_UNLOCK(hi2c);
7303
7304 return HAL_ERROR;
7305 }
7306 }
7307 }
7308 return HAL_OK;
7309 }
7310
7311 /**
7312 * @brief This function handles I2C Communication Timeout for specific usage of BTF flag.
7313 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7314 * the configuration information for the specified I2C.
7315 * @param Timeout Timeout duration
7316 * @param Tickstart Tick start value
7317 * @retval HAL status
7318 */
I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7319 static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7320 {
7321 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
7322 {
7323 /* Check if a NACK is detected */
7324 if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
7325 {
7326 return HAL_ERROR;
7327 }
7328
7329 /* Check for the Timeout */
7330 if (Timeout != HAL_MAX_DELAY)
7331 {
7332 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7333 {
7334 hi2c->PreviousState = I2C_STATE_NONE;
7335 hi2c->State = HAL_I2C_STATE_READY;
7336 hi2c->Mode = HAL_I2C_MODE_NONE;
7337 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7338
7339 /* Process Unlocked */
7340 __HAL_UNLOCK(hi2c);
7341
7342 return HAL_ERROR;
7343 }
7344 }
7345 }
7346 return HAL_OK;
7347 }
7348
7349 /**
7350 * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
7351 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7352 * the configuration information for the specified I2C.
7353 * @param Timeout Timeout duration
7354 * @param Tickstart Tick start value
7355 * @retval HAL status
7356 */
I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7357 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7358 {
7359 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
7360 {
7361 /* Check if a NACK is detected */
7362 if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
7363 {
7364 return HAL_ERROR;
7365 }
7366
7367 /* Check for the Timeout */
7368 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7369 {
7370 hi2c->PreviousState = I2C_STATE_NONE;
7371 hi2c->State = HAL_I2C_STATE_READY;
7372 hi2c->Mode = HAL_I2C_MODE_NONE;
7373 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7374
7375 /* Process Unlocked */
7376 __HAL_UNLOCK(hi2c);
7377
7378 return HAL_ERROR;
7379 }
7380 }
7381 return HAL_OK;
7382 }
7383
7384 /**
7385 * @brief This function handles I2C Communication Timeout for specific usage of STOP request through Interrupt.
7386 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7387 * the configuration information for the specified I2C.
7388 * @retval HAL status
7389 */
I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef * hi2c)7390 static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c)
7391 {
7392 __IO uint32_t count = 0U;
7393
7394 /* Wait until STOP flag is reset */
7395 count = I2C_TIMEOUT_STOP_FLAG * (SystemCoreClock / 25U / 1000U);
7396 do
7397 {
7398 count--;
7399 if (count == 0U)
7400 {
7401 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7402
7403 return HAL_ERROR;
7404 }
7405 }
7406 while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP);
7407
7408 return HAL_OK;
7409 }
7410
7411 /**
7412 * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
7413 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7414 * the configuration information for the specified I2C.
7415 * @param Timeout Timeout duration
7416 * @param Tickstart Tick start value
7417 * @retval HAL status
7418 */
I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7419 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7420 {
7421
7422 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
7423 {
7424 /* Check if a STOPF is detected */
7425 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
7426 {
7427 /* Clear STOP Flag */
7428 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
7429
7430 hi2c->PreviousState = I2C_STATE_NONE;
7431 hi2c->State = HAL_I2C_STATE_READY;
7432 hi2c->Mode = HAL_I2C_MODE_NONE;
7433 hi2c->ErrorCode |= HAL_I2C_ERROR_NONE;
7434
7435 /* Process Unlocked */
7436 __HAL_UNLOCK(hi2c);
7437
7438 return HAL_ERROR;
7439 }
7440
7441 /* Check for the Timeout */
7442 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7443 {
7444 hi2c->PreviousState = I2C_STATE_NONE;
7445 hi2c->State = HAL_I2C_STATE_READY;
7446 hi2c->Mode = HAL_I2C_MODE_NONE;
7447 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7448
7449 /* Process Unlocked */
7450 __HAL_UNLOCK(hi2c);
7451
7452 return HAL_ERROR;
7453 }
7454 }
7455 return HAL_OK;
7456 }
7457
7458 /**
7459 * @brief This function handles Acknowledge failed detection during an I2C Communication.
7460 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7461 * the configuration information for the specified I2C.
7462 * @retval HAL status
7463 */
I2C_IsAcknowledgeFailed(I2C_HandleTypeDef * hi2c)7464 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
7465 {
7466 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
7467 {
7468 /* Clear NACKF Flag */
7469 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7470
7471 hi2c->PreviousState = I2C_STATE_NONE;
7472 hi2c->State = HAL_I2C_STATE_READY;
7473 hi2c->Mode = HAL_I2C_MODE_NONE;
7474 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
7475
7476 /* Process Unlocked */
7477 __HAL_UNLOCK(hi2c);
7478
7479 return HAL_ERROR;
7480 }
7481 return HAL_OK;
7482 }
7483
7484 /**
7485 * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
7486 * @param hi2c I2C handle.
7487 * @retval None
7488 */
I2C_ConvertOtherXferOptions(I2C_HandleTypeDef * hi2c)7489 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
7490 {
7491 /* if user set XferOptions to I2C_OTHER_FRAME */
7492 /* it request implicitly to generate a restart condition */
7493 /* set XferOptions to I2C_FIRST_FRAME */
7494 if (hi2c->XferOptions == I2C_OTHER_FRAME)
7495 {
7496 hi2c->XferOptions = I2C_FIRST_FRAME;
7497 }
7498 /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
7499 /* it request implicitly to generate a restart condition */
7500 /* then generate a stop condition at the end of transfer */
7501 /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */
7502 else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
7503 {
7504 hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
7505 }
7506 else
7507 {
7508 /* Nothing to do */
7509 }
7510 }
7511
7512 /**
7513 * @}
7514 */
7515
7516 #endif /* HAL_I2C_MODULE_ENABLED */
7517 /**
7518 * @}
7519 */
7520
7521 /**
7522 * @}
7523 */
7524
7525
