1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_lptim.h
4 * @author MCD Application Team
5 * @brief Header file of LPTIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32F4xx_LL_LPTIM_H
21 #define STM32F4xx_LL_LPTIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f4xx.h"
29
30 /** @addtogroup STM32F4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (LPTIM1)
35
36 /** @defgroup LPTIM_LL LPTIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44
45 /* Private macros ------------------------------------------------------------*/
46 #if defined(USE_FULL_LL_DRIVER)
47 /** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
48 * @{
49 */
50 /**
51 * @}
52 */
53 #endif /*USE_FULL_LL_DRIVER*/
54
55 /* Exported types ------------------------------------------------------------*/
56 #if defined(USE_FULL_LL_DRIVER)
57 /** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
58 * @{
59 */
60
61 /**
62 * @brief LPTIM Init structure definition
63 */
64 typedef struct
65 {
66 uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
67 This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
68
69 This feature can be modified afterwards using unitary
70 function @ref LL_LPTIM_SetClockSource().*/
71
72 uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
73 This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
74
75 This feature can be modified afterwards using using unitary
76 function @ref LL_LPTIM_SetPrescaler().*/
77
78 uint32_t Waveform; /*!< Specifies the waveform shape.
79 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
80
81 This feature can be modified afterwards using unitary
82 function @ref LL_LPTIM_ConfigOutput().*/
83
84 uint32_t Polarity; /*!< Specifies waveform polarity.
85 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY.
86
87 This feature can be modified afterwards using unitary
88 function @ref LL_LPTIM_ConfigOutput().*/
89 } LL_LPTIM_InitTypeDef;
90
91 /**
92 * @}
93 */
94 #endif /* USE_FULL_LL_DRIVER */
95
96 /* Exported constants --------------------------------------------------------*/
97 /** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
98 * @{
99 */
100
101 /** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
102 * @brief Flags defines which can be used with LL_LPTIM_ReadReg function
103 * @{
104 */
105 #define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */
106 #define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */
107 #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
108 #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
109 #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
110 #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
111 #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
112 /**
113 * @}
114 */
115
116 /** @defgroup LPTIM_LL_EC_IT IT Defines
117 * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
118 * @{
119 */
120 #define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match */
121 #define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK */
122 #define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match */
123 #define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger edge event */
124 #define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK */
125 #define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Counter direction change down to up */
126 #define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Counter direction change up to down */
127 /**
128 * @}
129 */
130
131 /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
132 * @{
133 */
134 #define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
135 #define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
136 /**
137 * @}
138 */
139
140 /** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
141 * @{
142 */
143 #define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
144 #define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
145 /**
146 * @}
147 */
148
149 /** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
150 * @{
151 */
152 #define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
153 #define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
154 /**
155 * @}
156 */
157
158 /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
159 * @{
160 */
161 #define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE*/
162 #define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
163 /**
164 * @}
165 */
166
167 /** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
168 * @{
169 */
170 #define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
171 #define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
172 /**
173 * @}
174 */
175
176 /** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
177 * @{
178 */
179 #define LL_LPTIM_PRESCALER_DIV1 0x00000000U /*!<Prescaler division factor is set to 1*/
180 #define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 /*!<Prescaler division factor is set to 2*/
181 #define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 /*!<Prescaler division factor is set to 4*/
182 #define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
183 #define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 /*!<Prescaler division factor is set to 16*/
184 #define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
185 #define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
186 #define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /*!<Prescaler division factor is set to 128*/
187 /**
188 * @}
189 */
190
191 /** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
192 * @{
193 */
194 #define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
195 #define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
196 #define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
197 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
198 #define LL_LPTIM_TRIG_SOURCE_TIM1_TRGO LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to TIM1*/
199 #define LL_LPTIM_TRIG_SOURCE_TIM5_TRGO (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to TIM5*/
200 /**
201 * @}
202 */
203
204 /** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
205 * @{
206 */
207 #define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
208 #define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
209 #define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
210 #define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
211 /**
212 * @}
213 */
214
215 /** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
216 * @{
217 */
218 #define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
219 #define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
220 #define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
221 /**
222 * @}
223 */
224
225 /** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
226 * @{
227 */
228 #define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
229 #define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
230 /**
231 * @}
232 */
233
234 /** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
235 * @{
236 */
237 #define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
238 #define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
239 #define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
240 #define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
241 /**
242 * @}
243 */
244
245 /** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
246 * @{
247 */
248 #define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
249 #define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
250 #define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
251 /**
252 * @}
253 */
254
255 /** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
256 * @{
257 */
258 #define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
259 #define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
260 #define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
261 /**
262 * @}
263 */
264
265 /** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
266 * @{
267 */
268 #define LL_LPTIM_INPUT1_SRC_PAD_AF 0x00000000U
269 #define LL_LPTIM_INPUT1_SRC_PAD_PA4 LPTIM_OR_OR_0
270 #define LL_LPTIM_INPUT1_SRC_PAD_PB9 LPTIM_OR_OR_1
271 #define LL_LPTIM_INPUT1_SRC_TIM_DAC LPTIM_OR_OR
272 /**
273 * @}
274 */
275
276 /**
277 * @}
278 */
279
280 /* Exported macro ------------------------------------------------------------*/
281 /** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
282 * @{
283 */
284
285 /** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
286 * @{
287 */
288
289 /**
290 * @brief Write a value in LPTIM register
291 * @param __INSTANCE__ LPTIM Instance
292 * @param __REG__ Register to be written
293 * @param __VALUE__ Value to be written in the register
294 * @retval None
295 */
296 #define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
297
298 /**
299 * @brief Read a value in LPTIM register
300 * @param __INSTANCE__ LPTIM Instance
301 * @param __REG__ Register to be read
302 * @retval Register value
303 */
304 #define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
305 /**
306 * @}
307 */
308
309 /**
310 * @}
311 */
312
313 /* Exported functions --------------------------------------------------------*/
314 /** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
315 * @{
316 */
317
318 #if defined(USE_FULL_LL_DRIVER)
319 /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
320 * @{
321 */
322
323 ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
324 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
325 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
326 void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx);
327 /**
328 * @}
329 */
330 #endif /* USE_FULL_LL_DRIVER */
331
332 /** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
333 * @{
334 */
335
336 /**
337 * @brief Enable the LPTIM instance
338 * @note After setting the ENABLE bit, a delay of two counter clock is needed
339 * before the LPTIM instance is actually enabled.
340 * @rmtoll CR ENABLE LL_LPTIM_Enable
341 * @param LPTIMx Low-Power Timer instance
342 * @retval None
343 */
LL_LPTIM_Enable(LPTIM_TypeDef * LPTIMx)344 __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
345 {
346 SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
347 }
348
349 /**
350 * @brief Indicates whether the LPTIM instance is enabled.
351 * @rmtoll CR ENABLE LL_LPTIM_IsEnabled
352 * @param LPTIMx Low-Power Timer instance
353 * @retval State of bit (1 or 0).
354 */
LL_LPTIM_IsEnabled(LPTIM_TypeDef * const LPTIMx)355 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *const LPTIMx)
356 {
357 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
358 }
359
360 /**
361 * @brief Starts the LPTIM counter in the desired mode.
362 * @note LPTIM instance must be enabled before starting the counter.
363 * @note It is possible to change on the fly from One Shot mode to
364 * Continuous mode.
365 * @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n
366 * CR SNGSTRT LL_LPTIM_StartCounter
367 * @param LPTIMx Low-Power Timer instance
368 * @param OperatingMode This parameter can be one of the following values:
369 * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
370 * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
371 * @retval None
372 */
LL_LPTIM_StartCounter(LPTIM_TypeDef * LPTIMx,uint32_t OperatingMode)373 __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
374 {
375 MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
376 }
377
378 /**
379 * @brief Set the LPTIM registers update mode (enable/disable register preload)
380 * @note This function must be called when the LPTIM instance is disabled.
381 * @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode
382 * @param LPTIMx Low-Power Timer instance
383 * @param UpdateMode This parameter can be one of the following values:
384 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
385 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
386 * @retval None
387 */
LL_LPTIM_SetUpdateMode(LPTIM_TypeDef * LPTIMx,uint32_t UpdateMode)388 __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
389 {
390 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
391 }
392
393 /**
394 * @brief Get the LPTIM registers update mode
395 * @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode
396 * @param LPTIMx Low-Power Timer instance
397 * @retval Returned value can be one of the following values:
398 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
399 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
400 */
LL_LPTIM_GetUpdateMode(LPTIM_TypeDef * const LPTIMx)401 __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *const LPTIMx)
402 {
403 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
404 }
405
406 /**
407 * @brief Set the auto reload value
408 * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
409 * @note After a write to the LPTIMx_ARR register a new write operation to the
410 * same register can only be performed when the previous write operation
411 * is completed. Any successive write before the ARROK flag is set, will
412 * lead to unpredictable results.
413 * @note autoreload value be strictly greater than the compare value.
414 * @rmtoll ARR ARR LL_LPTIM_SetAutoReload
415 * @param LPTIMx Low-Power Timer instance
416 * @param AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
417 * @retval None
418 */
LL_LPTIM_SetAutoReload(LPTIM_TypeDef * LPTIMx,uint32_t AutoReload)419 __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
420 {
421 MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
422 }
423
424 /**
425 * @brief Get actual auto reload value
426 * @rmtoll ARR ARR LL_LPTIM_GetAutoReload
427 * @param LPTIMx Low-Power Timer instance
428 * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
429 */
LL_LPTIM_GetAutoReload(LPTIM_TypeDef * const LPTIMx)430 __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *const LPTIMx)
431 {
432 return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
433 }
434
435 /**
436 * @brief Set the compare value
437 * @note After a write to the LPTIMx_CMP register a new write operation to the
438 * same register can only be performed when the previous write operation
439 * is completed. Any successive write before the CMPOK flag is set, will
440 * lead to unpredictable results.
441 * @rmtoll CMP CMP LL_LPTIM_SetCompare
442 * @param LPTIMx Low-Power Timer instance
443 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
444 * @retval None
445 */
LL_LPTIM_SetCompare(LPTIM_TypeDef * LPTIMx,uint32_t CompareValue)446 __STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
447 {
448 MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue);
449 }
450
451 /**
452 * @brief Get actual compare value
453 * @rmtoll CMP CMP LL_LPTIM_GetCompare
454 * @param LPTIMx Low-Power Timer instance
455 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
456 */
LL_LPTIM_GetCompare(LPTIM_TypeDef * LPTIMx)457 __STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx)
458 {
459 return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP));
460 }
461
462 /**
463 * @brief Get actual counter value
464 * @note When the LPTIM instance is running with an asynchronous clock, reading
465 * the LPTIMx_CNT register may return unreliable values. So in this case
466 * it is necessary to perform two consecutive read accesses and verify
467 * that the two returned values are identical.
468 * @rmtoll CNT CNT LL_LPTIM_GetCounter
469 * @param LPTIMx Low-Power Timer instance
470 * @retval Counter value
471 */
LL_LPTIM_GetCounter(LPTIM_TypeDef * const LPTIMx)472 __STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *const LPTIMx)
473 {
474 return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
475 }
476
477 /**
478 * @brief Set the counter mode (selection of the LPTIM counter clock source).
479 * @note The counter mode can be set only when the LPTIM instance is disabled.
480 * @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode
481 * @param LPTIMx Low-Power Timer instance
482 * @param CounterMode This parameter can be one of the following values:
483 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
484 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
485 * @retval None
486 */
LL_LPTIM_SetCounterMode(LPTIM_TypeDef * LPTIMx,uint32_t CounterMode)487 __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
488 {
489 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
490 }
491
492 /**
493 * @brief Get the counter mode
494 * @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode
495 * @param LPTIMx Low-Power Timer instance
496 * @retval Returned value can be one of the following values:
497 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
498 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
499 */
LL_LPTIM_GetCounterMode(LPTIM_TypeDef * const LPTIMx)500 __STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *const LPTIMx)
501 {
502 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
503 }
504
505 /**
506 * @brief Configure the LPTIM instance output (LPTIMx_OUT)
507 * @note This function must be called when the LPTIM instance is disabled.
508 * @note Regarding the LPTIM output polarity the change takes effect
509 * immediately, so the output default value will change immediately after
510 * the polarity is re-configured, even before the timer is enabled.
511 * @rmtoll CFGR WAVE LL_LPTIM_ConfigOutput\n
512 * CFGR WAVPOL LL_LPTIM_ConfigOutput
513 * @param LPTIMx Low-Power Timer instance
514 * @param Waveform This parameter can be one of the following values:
515 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
516 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
517 * @param Polarity This parameter can be one of the following values:
518 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
519 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
520 * @retval None
521 */
LL_LPTIM_ConfigOutput(LPTIM_TypeDef * LPTIMx,uint32_t Waveform,uint32_t Polarity)522 __STATIC_INLINE void LL_LPTIM_ConfigOutput(LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
523 {
524 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity);
525 }
526
527 /**
528 * @brief Set waveform shape
529 * @rmtoll CFGR WAVE LL_LPTIM_SetWaveform
530 * @param LPTIMx Low-Power Timer instance
531 * @param Waveform This parameter can be one of the following values:
532 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
533 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
534 * @retval None
535 */
LL_LPTIM_SetWaveform(LPTIM_TypeDef * LPTIMx,uint32_t Waveform)536 __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
537 {
538 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
539 }
540
541 /**
542 * @brief Get actual waveform shape
543 * @rmtoll CFGR WAVE LL_LPTIM_GetWaveform
544 * @param LPTIMx Low-Power Timer instance
545 * @retval Returned value can be one of the following values:
546 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
547 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
548 */
LL_LPTIM_GetWaveform(LPTIM_TypeDef * LPTIMx)549 __STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx)
550 {
551 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
552 }
553
554 /**
555 * @brief Set output polarity
556 * @rmtoll CFGR WAVPOL LL_LPTIM_SetPolarity
557 * @param LPTIMx Low-Power Timer instance
558 * @param Polarity This parameter can be one of the following values:
559 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
560 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
561 * @retval None
562 */
LL_LPTIM_SetPolarity(LPTIM_TypeDef * LPTIMx,uint32_t Polarity)563 __STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
564 {
565 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity);
566 }
567
568 /**
569 * @brief Get actual output polarity
570 * @rmtoll CFGR WAVPOL LL_LPTIM_GetPolarity
571 * @param LPTIMx Low-Power Timer instance
572 * @retval Returned value can be one of the following values:
573 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
574 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
575 */
LL_LPTIM_GetPolarity(LPTIM_TypeDef * LPTIMx)576 __STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(LPTIM_TypeDef *LPTIMx)
577 {
578 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL));
579 }
580
581 /**
582 * @brief Set actual prescaler division ratio.
583 * @note This function must be called when the LPTIM instance is disabled.
584 * @note When the LPTIM is configured to be clocked by an internal clock source
585 * and the LPTIM counter is configured to be updated by active edges
586 * detected on the LPTIM external Input1, the internal clock provided to
587 * the LPTIM must be not be prescaled.
588 * @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler
589 * @param LPTIMx Low-Power Timer instance
590 * @param Prescaler This parameter can be one of the following values:
591 * @arg @ref LL_LPTIM_PRESCALER_DIV1
592 * @arg @ref LL_LPTIM_PRESCALER_DIV2
593 * @arg @ref LL_LPTIM_PRESCALER_DIV4
594 * @arg @ref LL_LPTIM_PRESCALER_DIV8
595 * @arg @ref LL_LPTIM_PRESCALER_DIV16
596 * @arg @ref LL_LPTIM_PRESCALER_DIV32
597 * @arg @ref LL_LPTIM_PRESCALER_DIV64
598 * @arg @ref LL_LPTIM_PRESCALER_DIV128
599 * @retval None
600 */
LL_LPTIM_SetPrescaler(LPTIM_TypeDef * LPTIMx,uint32_t Prescaler)601 __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
602 {
603 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
604 }
605
606 /**
607 * @brief Get actual prescaler division ratio.
608 * @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler
609 * @param LPTIMx Low-Power Timer instance
610 * @retval Returned value can be one of the following values:
611 * @arg @ref LL_LPTIM_PRESCALER_DIV1
612 * @arg @ref LL_LPTIM_PRESCALER_DIV2
613 * @arg @ref LL_LPTIM_PRESCALER_DIV4
614 * @arg @ref LL_LPTIM_PRESCALER_DIV8
615 * @arg @ref LL_LPTIM_PRESCALER_DIV16
616 * @arg @ref LL_LPTIM_PRESCALER_DIV32
617 * @arg @ref LL_LPTIM_PRESCALER_DIV64
618 * @arg @ref LL_LPTIM_PRESCALER_DIV128
619 */
LL_LPTIM_GetPrescaler(LPTIM_TypeDef * LPTIMx)620 __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx)
621 {
622 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
623 }
624
625 /**
626 * @brief Set LPTIM input 1 source (default GPIO).
627 * @rmtoll OR OR LL_LPTIM_SetInput1Src
628 * @param LPTIMx Low-Power Timer instance
629 * @param Src This parameter can be one of the following values:
630 * @arg @ref LL_LPTIM_INPUT1_SRC_PAD_AF
631 * @arg @ref LL_LPTIM_INPUT1_SRC_PAD_PA4
632 * @arg @ref LL_LPTIM_INPUT1_SRC_PAD_PB9
633 * @arg @ref LL_LPTIM_INPUT1_SRC_TIM_DAC
634 * @retval None
635 */
LL_LPTIM_SetInput1Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)636 __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
637 {
638 MODIFY_REG(LPTIMx->OR, LPTIM_OR_OR, Src);
639 }
640
641 /**
642 * @}
643 */
644
645 /** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
646 * @{
647 */
648
649 /**
650 * @brief Enable the timeout function
651 * @note This function must be called when the LPTIM instance is disabled.
652 * @note The first trigger event will start the timer, any successive trigger
653 * event will reset the counter and the timer will restart.
654 * @note The timeout value corresponds to the compare value; if no trigger
655 * occurs within the expected time frame, the MCU is waked-up by the
656 * compare match event.
657 * @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout
658 * @param LPTIMx Low-Power Timer instance
659 * @retval None
660 */
LL_LPTIM_EnableTimeout(LPTIM_TypeDef * LPTIMx)661 __STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
662 {
663 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
664 }
665
666 /**
667 * @brief Disable the timeout function
668 * @note This function must be called when the LPTIM instance is disabled.
669 * @note A trigger event arriving when the timer is already started will be
670 * ignored.
671 * @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout
672 * @param LPTIMx Low-Power Timer instance
673 * @retval None
674 */
LL_LPTIM_DisableTimeout(LPTIM_TypeDef * LPTIMx)675 __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
676 {
677 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
678 }
679
680 /**
681 * @brief Indicate whether the timeout function is enabled.
682 * @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
683 * @param LPTIMx Low-Power Timer instance
684 * @retval State of bit (1 or 0).
685 */
LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef * LPTIMx)686 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
687 {
688 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
689 }
690
691 /**
692 * @brief Start the LPTIM counter
693 * @note This function must be called when the LPTIM instance is disabled.
694 * @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw
695 * @param LPTIMx Low-Power Timer instance
696 * @retval None
697 */
LL_LPTIM_TrigSw(LPTIM_TypeDef * LPTIMx)698 __STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
699 {
700 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
701 }
702
703 /**
704 * @brief Configure the external trigger used as a trigger event for the LPTIM.
705 * @note This function must be called when the LPTIM instance is disabled.
706 * @note An internal clock source must be present when a digital filter is
707 * required for the trigger.
708 * @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n
709 * CFGR TRGFLT LL_LPTIM_ConfigTrigger\n
710 * CFGR TRIGEN LL_LPTIM_ConfigTrigger
711 * @param LPTIMx Low-Power Timer instance
712 * @param Source This parameter can be one of the following values:
713 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
714 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
715 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
716 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
717 * @arg @ref LL_LPTIM_TRIG_SOURCE_TIM1_TRGO
718 * @arg @ref LL_LPTIM_TRIG_SOURCE_TIM5_TRGO
719 * @param Filter This parameter can be one of the following values:
720 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
721 * @arg @ref LL_LPTIM_TRIG_FILTER_2
722 * @arg @ref LL_LPTIM_TRIG_FILTER_4
723 * @arg @ref LL_LPTIM_TRIG_FILTER_8
724 * @param Polarity This parameter can be one of the following values:
725 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
726 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
727 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
728 * @retval None
729 */
LL_LPTIM_ConfigTrigger(LPTIM_TypeDef * LPTIMx,uint32_t Source,uint32_t Filter,uint32_t Polarity)730 __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
731 {
732 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
733 }
734
735 /**
736 * @brief Get actual external trigger source.
737 * @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource
738 * @param LPTIMx Low-Power Timer instance
739 * @retval Returned value can be one of the following values:
740 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
741 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
742 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
743 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
744 * @arg @ref LL_LPTIM_TRIG_SOURCE_TIM1_TRGO
745 * @arg @ref LL_LPTIM_TRIG_SOURCE_TIM5_TRGO
746 */
LL_LPTIM_GetTriggerSource(LPTIM_TypeDef * LPTIMx)747 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx)
748 {
749 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
750 }
751
752 /**
753 * @brief Get actual external trigger filter.
754 * @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter
755 * @param LPTIMx Low-Power Timer instance
756 * @retval Returned value can be one of the following values:
757 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
758 * @arg @ref LL_LPTIM_TRIG_FILTER_2
759 * @arg @ref LL_LPTIM_TRIG_FILTER_4
760 * @arg @ref LL_LPTIM_TRIG_FILTER_8
761 */
LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef * LPTIMx)762 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx)
763 {
764 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
765 }
766
767 /**
768 * @brief Get actual external trigger polarity.
769 * @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
770 * @param LPTIMx Low-Power Timer instance
771 * @retval Returned value can be one of the following values:
772 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
773 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
774 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
775 */
LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef * LPTIMx)776 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx)
777 {
778 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
779 }
780
781 /**
782 * @}
783 */
784
785 /** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
786 * @{
787 */
788
789 /**
790 * @brief Set the source of the clock used by the LPTIM instance.
791 * @note This function must be called when the LPTIM instance is disabled.
792 * @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource
793 * @param LPTIMx Low-Power Timer instance
794 * @param ClockSource This parameter can be one of the following values:
795 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
796 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
797 * @retval None
798 */
LL_LPTIM_SetClockSource(LPTIM_TypeDef * LPTIMx,uint32_t ClockSource)799 __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
800 {
801 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
802 }
803
804 /**
805 * @brief Get actual LPTIM instance clock source.
806 * @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource
807 * @param LPTIMx Low-Power Timer instance
808 * @retval Returned value can be one of the following values:
809 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
810 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
811 */
LL_LPTIM_GetClockSource(LPTIM_TypeDef * LPTIMx)812 __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx)
813 {
814 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
815 }
816
817 /**
818 * @brief Configure the active edge or edges used by the counter when
819 the LPTIM is clocked by an external clock source.
820 * @note This function must be called when the LPTIM instance is disabled.
821 * @note When both external clock signal edges are considered active ones,
822 * the LPTIM must also be clocked by an internal clock source with a
823 * frequency equal to at least four times the external clock frequency.
824 * @note An internal clock source must be present when a digital filter is
825 * required for external clock.
826 * @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n
827 * CFGR CKPOL LL_LPTIM_ConfigClock
828 * @param LPTIMx Low-Power Timer instance
829 * @param ClockFilter This parameter can be one of the following values:
830 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
831 * @arg @ref LL_LPTIM_CLK_FILTER_2
832 * @arg @ref LL_LPTIM_CLK_FILTER_4
833 * @arg @ref LL_LPTIM_CLK_FILTER_8
834 * @param ClockPolarity This parameter can be one of the following values:
835 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
836 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
837 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
838 * @retval None
839 */
LL_LPTIM_ConfigClock(LPTIM_TypeDef * LPTIMx,uint32_t ClockFilter,uint32_t ClockPolarity)840 __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
841 {
842 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
843 }
844
845 /**
846 * @brief Get actual clock polarity
847 * @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity
848 * @param LPTIMx Low-Power Timer instance
849 * @retval Returned value can be one of the following values:
850 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
851 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
852 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
853 */
LL_LPTIM_GetClockPolarity(LPTIM_TypeDef * LPTIMx)854 __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx)
855 {
856 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
857 }
858
859 /**
860 * @brief Get actual clock digital filter
861 * @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter
862 * @param LPTIMx Low-Power Timer instance
863 * @retval Returned value can be one of the following values:
864 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
865 * @arg @ref LL_LPTIM_CLK_FILTER_2
866 * @arg @ref LL_LPTIM_CLK_FILTER_4
867 * @arg @ref LL_LPTIM_CLK_FILTER_8
868 */
LL_LPTIM_GetClockFilter(LPTIM_TypeDef * LPTIMx)869 __STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx)
870 {
871 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
872 }
873
874 /**
875 * @}
876 */
877
878 /** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
879 * @{
880 */
881
882 /**
883 * @brief Configure the encoder mode.
884 * @note This function must be called when the LPTIM instance is disabled.
885 * @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode
886 * @param LPTIMx Low-Power Timer instance
887 * @param EncoderMode This parameter can be one of the following values:
888 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
889 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
890 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
891 * @retval None
892 */
LL_LPTIM_SetEncoderMode(LPTIM_TypeDef * LPTIMx,uint32_t EncoderMode)893 __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
894 {
895 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
896 }
897
898 /**
899 * @brief Get actual encoder mode.
900 * @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode
901 * @param LPTIMx Low-Power Timer instance
902 * @retval Returned value can be one of the following values:
903 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
904 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
905 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
906 */
LL_LPTIM_GetEncoderMode(LPTIM_TypeDef * LPTIMx)907 __STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx)
908 {
909 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
910 }
911
912 /**
913 * @brief Enable the encoder mode
914 * @note This function must be called when the LPTIM instance is disabled.
915 * @note In this mode the LPTIM instance must be clocked by an internal clock
916 * source. Also, the prescaler division ratio must be equal to 1.
917 * @note LPTIM instance must be configured in continuous mode prior enabling
918 * the encoder mode.
919 * @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode
920 * @param LPTIMx Low-Power Timer instance
921 * @retval None
922 */
LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef * LPTIMx)923 __STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
924 {
925 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
926 }
927
928 /**
929 * @brief Disable the encoder mode
930 * @note This function must be called when the LPTIM instance is disabled.
931 * @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode
932 * @param LPTIMx Low-Power Timer instance
933 * @retval None
934 */
LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef * LPTIMx)935 __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
936 {
937 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
938 }
939
940 /**
941 * @brief Indicates whether the LPTIM operates in encoder mode.
942 * @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode
943 * @param LPTIMx Low-Power Timer instance
944 * @retval State of bit (1 or 0).
945 */
LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef * LPTIMx)946 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
947 {
948 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
949 }
950
951 /**
952 * @}
953 */
954
955 /** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
956 * @{
957 */
958
959 /**
960 * @brief Clear the compare match flag (CMPMCF)
961 * @rmtoll ICR CMPMCF LL_LPTIM_ClearFLAG_CMPM
962 * @param LPTIMx Low-Power Timer instance
963 * @retval None
964 */
LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef * LPTIMx)965 __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
966 {
967 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);
968 }
969
970 /**
971 * @brief Inform application whether a compare match interrupt has occurred.
972 * @rmtoll ISR CMPM LL_LPTIM_IsActiveFlag_CMPM
973 * @param LPTIMx Low-Power Timer instance
974 * @retval State of bit (1 or 0).
975 */
LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef * LPTIMx)976 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
977 {
978 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL));
979 }
980
981 /**
982 * @brief Clear the autoreload match flag (ARRMCF)
983 * @rmtoll ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM
984 * @param LPTIMx Low-Power Timer instance
985 * @retval None
986 */
LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef * LPTIMx)987 __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
988 {
989 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
990 }
991
992 /**
993 * @brief Inform application whether a autoreload match interrupt has occurred.
994 * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
995 * @param LPTIMx Low-Power Timer instance
996 * @retval State of bit (1 or 0).
997 */
LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef * LPTIMx)998 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
999 {
1000 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
1001 }
1002
1003 /**
1004 * @brief Clear the external trigger valid edge flag(EXTTRIGCF).
1005 * @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
1006 * @param LPTIMx Low-Power Timer instance
1007 * @retval None
1008 */
LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef * LPTIMx)1009 __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1010 {
1011 SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
1012 }
1013
1014 /**
1015 * @brief Inform application whether a valid edge on the selected external trigger input has occurred.
1016 * @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
1017 * @param LPTIMx Low-Power Timer instance
1018 * @retval State of bit (1 or 0).
1019 */
LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef * LPTIMx)1020 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1021 {
1022 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
1023 }
1024
1025 /**
1026 * @brief Clear the compare register update interrupt flag (CMPOKCF).
1027 * @rmtoll ICR CMPOKCF LL_LPTIM_ClearFlag_CMPOK
1028 * @param LPTIMx Low-Power Timer instance
1029 * @retval None
1030 */
LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef * LPTIMx)1031 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
1032 {
1033 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF);
1034 }
1035
1036 /**
1037 * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully
1038 completed. If so, a new one can be initiated.
1039 * @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK
1040 * @param LPTIMx Low-Power Timer instance
1041 * @retval State of bit (1 or 0).
1042 */
LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef * LPTIMx)1043 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
1044 {
1045 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL));
1046 }
1047
1048 /**
1049 * @brief Clear the autoreload register update interrupt flag (ARROKCF).
1050 * @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
1051 * @param LPTIMx Low-Power Timer instance
1052 * @retval None
1053 */
LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef * LPTIMx)1054 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
1055 {
1056 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
1057 }
1058
1059 /**
1060 * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully
1061 completed. If so, a new one can be initiated.
1062 * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
1063 * @param LPTIMx Low-Power Timer instance
1064 * @retval State of bit (1 or 0).
1065 */
LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef * LPTIMx)1066 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
1067 {
1068 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
1069 }
1070
1071 /**
1072 * @brief Clear the counter direction change to up interrupt flag (UPCF).
1073 * @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP
1074 * @param LPTIMx Low-Power Timer instance
1075 * @retval None
1076 */
LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef * LPTIMx)1077 __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
1078 {
1079 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
1080 }
1081
1082 /**
1083 * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance
1084 operates in encoder mode).
1085 * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
1086 * @param LPTIMx Low-Power Timer instance
1087 * @retval State of bit (1 or 0).
1088 */
LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef * LPTIMx)1089 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
1090 {
1091 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
1092 }
1093
1094 /**
1095 * @brief Clear the counter direction change to down interrupt flag (DOWNCF).
1096 * @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
1097 * @param LPTIMx Low-Power Timer instance
1098 * @retval None
1099 */
LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef * LPTIMx)1100 __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
1101 {
1102 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
1103 }
1104
1105 /**
1106 * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance
1107 operates in encoder mode).
1108 * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
1109 * @param LPTIMx Low-Power Timer instance
1110 * @retval State of bit (1 or 0).
1111 */
LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef * LPTIMx)1112 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
1113 {
1114 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
1115 }
1116
1117 /**
1118 * @}
1119 */
1120
1121 /** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
1122 * @{
1123 */
1124
1125 /**
1126 * @brief Enable compare match interrupt (CMPMIE).
1127 * @rmtoll IER CMPMIE LL_LPTIM_EnableIT_CMPM
1128 * @param LPTIMx Low-Power Timer instance
1129 * @retval None
1130 */
LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef * LPTIMx)1131 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef *LPTIMx)
1132 {
1133 SET_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
1134 }
1135
1136 /**
1137 * @brief Disable compare match interrupt (CMPMIE).
1138 * @rmtoll IER CMPMIE LL_LPTIM_DisableIT_CMPM
1139 * @param LPTIMx Low-Power Timer instance
1140 * @retval None
1141 */
LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef * LPTIMx)1142 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
1143 {
1144 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
1145 }
1146
1147 /**
1148 * @brief Indicates whether the compare match interrupt (CMPMIE) is enabled.
1149 * @rmtoll IER CMPMIE LL_LPTIM_IsEnabledIT_CMPM
1150 * @param LPTIMx Low-Power Timer instance
1151 * @retval State of bit (1 or 0).
1152 */
LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef * LPTIMx)1153 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
1154 {
1155 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL));
1156 }
1157
1158 /**
1159 * @brief Enable autoreload match interrupt (ARRMIE).
1160 * @rmtoll IER ARRMIE LL_LPTIM_EnableIT_ARRM
1161 * @param LPTIMx Low-Power Timer instance
1162 * @retval None
1163 */
LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef * LPTIMx)1164 __STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
1165 {
1166 SET_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
1167 }
1168
1169 /**
1170 * @brief Disable autoreload match interrupt (ARRMIE).
1171 * @rmtoll IER ARRMIE LL_LPTIM_DisableIT_ARRM
1172 * @param LPTIMx Low-Power Timer instance
1173 * @retval None
1174 */
LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef * LPTIMx)1175 __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
1176 {
1177 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
1178 }
1179
1180 /**
1181 * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
1182 * @rmtoll IER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
1183 * @param LPTIMx Low-Power Timer instance
1184 * @retval State of bit (1 or 0).
1185 */
LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef * LPTIMx)1186 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
1187 {
1188 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL));
1189 }
1190
1191 /**
1192 * @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
1193 * @rmtoll IER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
1194 * @param LPTIMx Low-Power Timer instance
1195 * @retval None
1196 */
LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)1197 __STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1198 {
1199 SET_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
1200 }
1201
1202 /**
1203 * @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
1204 * @rmtoll IER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
1205 * @param LPTIMx Low-Power Timer instance
1206 * @retval None
1207 */
LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)1208 __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1209 {
1210 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
1211 }
1212
1213 /**
1214 * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
1215 * @rmtoll IER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
1216 * @param LPTIMx Low-Power Timer instance
1217 * @retval State of bit (1 or 0).
1218 */
LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)1219 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1220 {
1221 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL));
1222 }
1223
1224 /**
1225 * @brief Enable compare register write completed interrupt (CMPOKIE).
1226 * @rmtoll IER CMPOKIE LL_LPTIM_EnableIT_CMPOK
1227 * @param LPTIMx Low-Power Timer instance
1228 * @retval None
1229 */
LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef * LPTIMx)1230 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1231 {
1232 SET_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
1233 }
1234
1235 /**
1236 * @brief Disable compare register write completed interrupt (CMPOKIE).
1237 * @rmtoll IER CMPOKIE LL_LPTIM_DisableIT_CMPOK
1238 * @param LPTIMx Low-Power Timer instance
1239 * @retval None
1240 */
LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef * LPTIMx)1241 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1242 {
1243 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
1244 }
1245
1246 /**
1247 * @brief Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
1248 * @rmtoll IER CMPOKIE LL_LPTIM_IsEnabledIT_CMPOK
1249 * @param LPTIMx Low-Power Timer instance
1250 * @retval State of bit (1 or 0).
1251 */
LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef * LPTIMx)1252 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1253 {
1254 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL));
1255 }
1256
1257 /**
1258 * @brief Enable autoreload register write completed interrupt (ARROKIE).
1259 * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK
1260 * @param LPTIMx Low-Power Timer instance
1261 * @retval None
1262 */
LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef * LPTIMx)1263 __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
1264 {
1265 SET_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
1266 }
1267
1268 /**
1269 * @brief Disable autoreload register write completed interrupt (ARROKIE).
1270 * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK
1271 * @param LPTIMx Low-Power Timer instance
1272 * @retval None
1273 */
LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef * LPTIMx)1274 __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
1275 {
1276 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
1277 }
1278
1279 /**
1280 * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
1281 * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
1282 * @param LPTIMx Low-Power Timer instance
1283 * @retval State of bit(1 or 0).
1284 */
LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef * LPTIMx)1285 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
1286 {
1287 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL));
1288 }
1289
1290 /**
1291 * @brief Enable direction change to up interrupt (UPIE).
1292 * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP
1293 * @param LPTIMx Low-Power Timer instance
1294 * @retval None
1295 */
LL_LPTIM_EnableIT_UP(LPTIM_TypeDef * LPTIMx)1296 __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
1297 {
1298 SET_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
1299 }
1300
1301 /**
1302 * @brief Disable direction change to up interrupt (UPIE).
1303 * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP
1304 * @param LPTIMx Low-Power Timer instance
1305 * @retval None
1306 */
LL_LPTIM_DisableIT_UP(LPTIM_TypeDef * LPTIMx)1307 __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
1308 {
1309 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
1310 }
1311
1312 /**
1313 * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
1314 * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
1315 * @param LPTIMx Low-Power Timer instance
1316 * @retval State of bit(1 or 0).
1317 */
LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef * LPTIMx)1318 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
1319 {
1320 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL));
1321 }
1322
1323 /**
1324 * @brief Enable direction change to down interrupt (DOWNIE).
1325 * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN
1326 * @param LPTIMx Low-Power Timer instance
1327 * @retval None
1328 */
LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef * LPTIMx)1329 __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
1330 {
1331 SET_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
1332 }
1333
1334 /**
1335 * @brief Disable direction change to down interrupt (DOWNIE).
1336 * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN
1337 * @param LPTIMx Low-Power Timer instance
1338 * @retval None
1339 */
LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef * LPTIMx)1340 __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
1341 {
1342 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
1343 }
1344
1345 /**
1346 * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
1347 * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
1348 * @param LPTIMx Low-Power Timer instance
1349 * @retval State of bit(1 or 0).
1350 */
LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef * LPTIMx)1351 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
1352 {
1353 return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL);
1354 }
1355
1356 /**
1357 * @}
1358 */
1359
1360 /**
1361 * @}
1362 */
1363
1364 /**
1365 * @}
1366 */
1367
1368 #endif /* LPTIM1 */
1369
1370 /**
1371 * @}
1372 */
1373
1374 #ifdef __cplusplus
1375 }
1376 #endif
1377
1378 #endif /* STM32F4xx_LL_LPTIM_H */
1379
