1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_i2c.h
4 * @author MCD Application Team
5 * @brief Header file of I2C LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32F4xx_LL_I2C_H
21 #define __STM32F4xx_LL_I2C_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f4xx.h"
29
30 /** @addtogroup STM32F4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (I2C1) || defined (I2C2) || defined (I2C3)
35
36 /** @defgroup I2C_LL I2C
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup I2C_LL_Private_Constants I2C Private Constants
45 * @{
46 */
47
48 /* Defines used to perform compute and check in the macros */
49 #define LL_I2C_MAX_SPEED_STANDARD 100000U
50 #define LL_I2C_MAX_SPEED_FAST 400000U
51 /**
52 * @}
53 */
54
55 /* Private macros ------------------------------------------------------------*/
56 #if defined(USE_FULL_LL_DRIVER)
57 /** @defgroup I2C_LL_Private_Macros I2C Private Macros
58 * @{
59 */
60 /**
61 * @}
62 */
63 #endif /*USE_FULL_LL_DRIVER*/
64
65 /* Exported types ------------------------------------------------------------*/
66 #if defined(USE_FULL_LL_DRIVER)
67 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
68 * @{
69 */
70 typedef struct
71 {
72 uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
73 This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
74
75 This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
76
77 uint32_t ClockSpeed; /*!< Specifies the clock frequency.
78 This parameter must be set to a value lower than 400kHz (in Hz)
79
80 This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod()
81 or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */
82
83 uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
84 This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE
85
86 This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */
87
88 #if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
89 uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
90 This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
91
92 This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
93
94 uint32_t DigitalFilter; /*!< Configures the digital noise filter.
95 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
96
97 This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
98
99 #endif
100 uint32_t OwnAddress1; /*!< Specifies the device own address 1.
101 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
102
103 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
104
105 uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
106 This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
107
108 This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
109
110 uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
111 This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
112
113 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
114 } LL_I2C_InitTypeDef;
115 /**
116 * @}
117 */
118 #endif /*USE_FULL_LL_DRIVER*/
119
120 /* Exported constants --------------------------------------------------------*/
121 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
122 * @{
123 */
124
125 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
126 * @brief Flags defines which can be used with LL_I2C_ReadReg function
127 * @{
128 */
129 #define LL_I2C_SR1_SB I2C_SR1_SB /*!< Start Bit (master mode) */
130 #define LL_I2C_SR1_ADDR I2C_SR1_ADDR /*!< Address sent (master mode) or
131 Address matched flag (slave mode) */
132 #define LL_I2C_SR1_BTF I2C_SR1_BTF /*!< Byte Transfer Finished flag */
133 #define LL_I2C_SR1_ADD10 I2C_SR1_ADD10 /*!< 10-bit header sent (master mode) */
134 #define LL_I2C_SR1_STOPF I2C_SR1_STOPF /*!< Stop detection flag (slave mode) */
135 #define LL_I2C_SR1_RXNE I2C_SR1_RXNE /*!< Data register not empty (receivers) */
136 #define LL_I2C_SR1_TXE I2C_SR1_TXE /*!< Data register empty (transmitters) */
137 #define LL_I2C_SR1_BERR I2C_SR1_BERR /*!< Bus error */
138 #define LL_I2C_SR1_ARLO I2C_SR1_ARLO /*!< Arbitration lost */
139 #define LL_I2C_SR1_AF I2C_SR1_AF /*!< Acknowledge failure flag */
140 #define LL_I2C_SR1_OVR I2C_SR1_OVR /*!< Overrun/Underrun */
141 #define LL_I2C_SR1_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
142 #define LL_I2C_SR1_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
143 #define LL_I2C_SR1_SMALERT I2C_ISR_SMALERT /*!< SMBus alert (SMBus mode) */
144 #define LL_I2C_SR2_MSL I2C_SR2_MSL /*!< Master/Slave flag */
145 #define LL_I2C_SR2_BUSY I2C_SR2_BUSY /*!< Bus busy flag */
146 #define LL_I2C_SR2_TRA I2C_SR2_TRA /*!< Transmitter/receiver direction */
147 #define LL_I2C_SR2_GENCALL I2C_SR2_GENCALL /*!< General call address (Slave mode) */
148 #define LL_I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT /*!< SMBus Device default address (Slave mode) */
149 #define LL_I2C_SR2_SMBHOST I2C_SR2_SMBHOST /*!< SMBus Host address (Slave mode) */
150 #define LL_I2C_SR2_DUALF I2C_SR2_DUALF /*!< Dual flag (Slave mode) */
151 /**
152 * @}
153 */
154
155 /** @defgroup I2C_LL_EC_IT IT Defines
156 * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
157 * @{
158 */
159 #define LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN /*!< Events interrupts enable */
160 #define LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN /*!< Buffer interrupts enable */
161 #define LL_I2C_CR2_ITERREN I2C_CR2_ITERREN /*!< Error interrupts enable */
162 /**
163 * @}
164 */
165
166 #if defined(I2C_FLTR_ANOFF)
167 /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
168 * @{
169 */
170 #define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */
171 #define LL_I2C_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF /*!< Analog filter is disabled.*/
172 /**
173 * @}
174 */
175
176 #endif
177 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
178 * @{
179 */
180 #define LL_I2C_OWNADDRESS1_7BIT 0x00004000U /*!< Own address 1 is a 7-bit address. */
181 #define LL_I2C_OWNADDRESS1_10BIT (uint32_t)(I2C_OAR1_ADDMODE | 0x00004000U) /*!< Own address 1 is a 10-bit address. */
182 /**
183 * @}
184 */
185
186 /** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle
187 * @{
188 */
189 #define LL_I2C_DUTYCYCLE_2 0x00000000U /*!< I2C fast mode Tlow/Thigh = 2 */
190 #define LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY /*!< I2C fast mode Tlow/Thigh = 16/9 */
191 /**
192 * @}
193 */
194
195 /** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode
196 * @{
197 */
198 #define LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U /*!< Master clock speed range is standard mode */
199 #define LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS /*!< Master clock speed range is fast mode */
200 /**
201 * @}
202 */
203
204 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
205 * @{
206 */
207 #define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
208 #define LL_I2C_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP) /*!< SMBus Host address acknowledge */
209 #define LL_I2C_MODE_SMBUS_DEVICE I2C_CR1_SMBUS /*!< SMBus Device default mode (Default address not acknowledge) */
210 #define LL_I2C_MODE_SMBUS_DEVICE_ARP (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_ENARP) /*!< SMBus Device Default address acknowledge */
211 /**
212 * @}
213 */
214
215 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
216 * @{
217 */
218 #define LL_I2C_ACK I2C_CR1_ACK /*!< ACK is sent after current received byte. */
219 #define LL_I2C_NACK 0x00000000U /*!< NACK is sent after current received byte.*/
220 /**
221 * @}
222 */
223
224 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
225 * @{
226 */
227 #define LL_I2C_DIRECTION_WRITE I2C_SR2_TRA /*!< Bus is in write transfer */
228 #define LL_I2C_DIRECTION_READ 0x00000000U /*!< Bus is in read transfer */
229 /**
230 * @}
231 */
232
233 /**
234 * @}
235 */
236
237 /* Exported macro ------------------------------------------------------------*/
238 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
239 * @{
240 */
241
242 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
243 * @{
244 */
245
246 /**
247 * @brief Write a value in I2C register
248 * @param __INSTANCE__ I2C Instance
249 * @param __REG__ Register to be written
250 * @param __VALUE__ Value to be written in the register
251 * @retval None
252 */
253 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
254
255 /**
256 * @brief Read a value in I2C register
257 * @param __INSTANCE__ I2C Instance
258 * @param __REG__ Register to be read
259 * @retval Register value
260 */
261 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
262 /**
263 * @}
264 */
265
266 /** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
267 * @{
268 */
269
270 /**
271 * @brief Convert Peripheral Clock Frequency in Mhz.
272 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
273 * @retval Value of peripheral clock (in Mhz)
274 */
275 #define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U)
276
277 /**
278 * @brief Convert Peripheral Clock Frequency in Hz.
279 * @param __PCLK__ This parameter must be a value of peripheral clock (in Mhz).
280 * @retval Value of peripheral clock (in Hz)
281 */
282 #define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U)
283
284 /**
285 * @brief Compute I2C Clock rising time.
286 * @param __FREQRANGE__ This parameter must be a value of peripheral clock (in Mhz).
287 * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
288 * @retval Value between Min_Data=0x02 and Max_Data=0x3F
289 */
290 #define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
291
292 /**
293 * @brief Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value.
294 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
295 * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
296 * @param __DUTYCYCLE__ This parameter can be one of the following values:
297 * @arg @ref LL_I2C_DUTYCYCLE_2
298 * @arg @ref LL_I2C_DUTYCYCLE_16_9
299 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
300 */
301 #define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \
302 (__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \
303 (__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__))))
304
305 /**
306 * @brief Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value.
307 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
308 * @param __SPEED__ This parameter must be a value lower than 100kHz (in Hz).
309 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF.
310 */
311 #define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
312
313 /**
314 * @brief Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value.
315 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
316 * @param __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz).
317 * @param __DUTYCYCLE__ This parameter can be one of the following values:
318 * @arg @ref LL_I2C_DUTYCYCLE_2
319 * @arg @ref LL_I2C_DUTYCYCLE_16_9
320 * @retval Value between Min_Data=0x001 and Max_Data=0xFFF
321 */
322 #define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \
323 (((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \
324 (((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U))))
325
326 /**
327 * @brief Get the Least significant bits of a 10-Bits address.
328 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
329 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
330 */
331 #define __LL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
332
333 /**
334 * @brief Convert a 10-Bits address to a 10-Bits header with Write direction.
335 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
336 * @retval Value between Min_Data=0xF0 and Max_Data=0xF6
337 */
338 #define __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
339
340 /**
341 * @brief Convert a 10-Bits address to a 10-Bits header with Read direction.
342 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
343 * @retval Value between Min_Data=0xF1 and Max_Data=0xF7
344 */
345 #define __LL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
346
347 /**
348 * @}
349 */
350
351 /**
352 * @}
353 */
354
355 /* Exported functions --------------------------------------------------------*/
356
357 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
358 * @{
359 */
360
361 /** @defgroup I2C_LL_EF_Configuration Configuration
362 * @{
363 */
364
365 /**
366 * @brief Enable I2C peripheral (PE = 1).
367 * @rmtoll CR1 PE LL_I2C_Enable
368 * @param I2Cx I2C Instance.
369 * @retval None
370 */
LL_I2C_Enable(I2C_TypeDef * I2Cx)371 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
372 {
373 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
374 }
375
376 /**
377 * @brief Disable I2C peripheral (PE = 0).
378 * @rmtoll CR1 PE LL_I2C_Disable
379 * @param I2Cx I2C Instance.
380 * @retval None
381 */
LL_I2C_Disable(I2C_TypeDef * I2Cx)382 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
383 {
384 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
385 }
386
387 /**
388 * @brief Check if the I2C peripheral is enabled or disabled.
389 * @rmtoll CR1 PE LL_I2C_IsEnabled
390 * @param I2Cx I2C Instance.
391 * @retval State of bit (1 or 0).
392 */
LL_I2C_IsEnabled(I2C_TypeDef * I2Cx)393 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
394 {
395 return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
396 }
397
398 #if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
399 /**
400 * @brief Configure Noise Filters (Analog and Digital).
401 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
402 * The filters can only be programmed when the I2C is disabled (PE = 0).
403 * @rmtoll FLTR ANOFF LL_I2C_ConfigFilters\n
404 * FLTR DNF LL_I2C_ConfigFilters
405 * @param I2Cx I2C Instance.
406 * @param AnalogFilter This parameter can be one of the following values:
407 * @arg @ref LL_I2C_ANALOGFILTER_ENABLE
408 * @arg @ref LL_I2C_ANALOGFILTER_DISABLE
409 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*TPCLK1)
410 * This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will suppress the spikes with a length of up to DNF[3:0]*TPCLK1.
411 * @retval None
412 */
LL_I2C_ConfigFilters(I2C_TypeDef * I2Cx,uint32_t AnalogFilter,uint32_t DigitalFilter)413 __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
414 {
415 MODIFY_REG(I2Cx->FLTR, I2C_FLTR_ANOFF | I2C_FLTR_DNF, AnalogFilter | DigitalFilter);
416 }
417 #endif
418 #if defined(I2C_FLTR_DNF)
419
420 /**
421 * @brief Configure Digital Noise Filter.
422 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
423 * This filter can only be programmed when the I2C is disabled (PE = 0).
424 * @rmtoll FLTR DNF LL_I2C_SetDigitalFilter
425 * @param I2Cx I2C Instance.
426 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*TPCLK1)
427 * This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will suppress the spikes with a length of up to DNF[3:0]*TPCLK1.
428 * @retval None
429 */
LL_I2C_SetDigitalFilter(I2C_TypeDef * I2Cx,uint32_t DigitalFilter)430 __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
431 {
432 MODIFY_REG(I2Cx->FLTR, I2C_FLTR_DNF, DigitalFilter);
433 }
434
435 /**
436 * @brief Get the current Digital Noise Filter configuration.
437 * @rmtoll FLTR DNF LL_I2C_GetDigitalFilter
438 * @param I2Cx I2C Instance.
439 * @retval Value between Min_Data=0x0 and Max_Data=0xF
440 */
LL_I2C_GetDigitalFilter(I2C_TypeDef * I2Cx)441 __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
442 {
443 return (uint32_t)(READ_BIT(I2Cx->FLTR, I2C_FLTR_DNF));
444 }
445 #endif
446 #if defined(I2C_FLTR_ANOFF)
447
448 /**
449 * @brief Enable Analog Noise Filter.
450 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
451 * @rmtoll FLTR ANOFF LL_I2C_EnableAnalogFilter
452 * @param I2Cx I2C Instance.
453 * @retval None
454 */
LL_I2C_EnableAnalogFilter(I2C_TypeDef * I2Cx)455 __STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
456 {
457 CLEAR_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF);
458 }
459
460 /**
461 * @brief Disable Analog Noise Filter.
462 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
463 * @rmtoll FLTR ANOFF LL_I2C_DisableAnalogFilter
464 * @param I2Cx I2C Instance.
465 * @retval None
466 */
LL_I2C_DisableAnalogFilter(I2C_TypeDef * I2Cx)467 __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
468 {
469 SET_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF);
470 }
471
472 /**
473 * @brief Check if Analog Noise Filter is enabled or disabled.
474 * @rmtoll FLTR ANOFF LL_I2C_IsEnabledAnalogFilter
475 * @param I2Cx I2C Instance.
476 * @retval State of bit (1 or 0).
477 */
LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef * I2Cx)478 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
479 {
480 return (READ_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF) == (I2C_FLTR_ANOFF));
481 }
482 #endif
483
484 /**
485 * @brief Enable DMA transmission requests.
486 * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_TX
487 * @param I2Cx I2C Instance.
488 * @retval None
489 */
LL_I2C_EnableDMAReq_TX(I2C_TypeDef * I2Cx)490 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
491 {
492 SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
493 }
494
495 /**
496 * @brief Disable DMA transmission requests.
497 * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_TX
498 * @param I2Cx I2C Instance.
499 * @retval None
500 */
LL_I2C_DisableDMAReq_TX(I2C_TypeDef * I2Cx)501 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
502 {
503 CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
504 }
505
506 /**
507 * @brief Check if DMA transmission requests are enabled or disabled.
508 * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_TX
509 * @param I2Cx I2C Instance.
510 * @retval State of bit (1 or 0).
511 */
LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef * I2Cx)512 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
513 {
514 return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
515 }
516
517 /**
518 * @brief Enable DMA reception requests.
519 * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_RX
520 * @param I2Cx I2C Instance.
521 * @retval None
522 */
LL_I2C_EnableDMAReq_RX(I2C_TypeDef * I2Cx)523 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
524 {
525 SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
526 }
527
528 /**
529 * @brief Disable DMA reception requests.
530 * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_RX
531 * @param I2Cx I2C Instance.
532 * @retval None
533 */
LL_I2C_DisableDMAReq_RX(I2C_TypeDef * I2Cx)534 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
535 {
536 CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
537 }
538
539 /**
540 * @brief Check if DMA reception requests are enabled or disabled.
541 * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_RX
542 * @param I2Cx I2C Instance.
543 * @retval State of bit (1 or 0).
544 */
LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef * I2Cx)545 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
546 {
547 return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
548 }
549
550 /**
551 * @brief Get the data register address used for DMA transfer.
552 * @rmtoll DR DR LL_I2C_DMA_GetRegAddr
553 * @param I2Cx I2C Instance.
554 * @retval Address of data register
555 */
LL_I2C_DMA_GetRegAddr(I2C_TypeDef * I2Cx)556 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx)
557 {
558 return (uint32_t) & (I2Cx->DR);
559 }
560
561 /**
562 * @brief Enable Clock stretching.
563 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
564 * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
565 * @param I2Cx I2C Instance.
566 * @retval None
567 */
LL_I2C_EnableClockStretching(I2C_TypeDef * I2Cx)568 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
569 {
570 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
571 }
572
573 /**
574 * @brief Disable Clock stretching.
575 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
576 * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
577 * @param I2Cx I2C Instance.
578 * @retval None
579 */
LL_I2C_DisableClockStretching(I2C_TypeDef * I2Cx)580 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
581 {
582 SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
583 }
584
585 /**
586 * @brief Check if Clock stretching is enabled or disabled.
587 * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
588 * @param I2Cx I2C Instance.
589 * @retval State of bit (1 or 0).
590 */
LL_I2C_IsEnabledClockStretching(I2C_TypeDef * I2Cx)591 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
592 {
593 return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
594 }
595
596 /**
597 * @brief Enable General Call.
598 * @note When enabled the Address 0x00 is ACKed.
599 * @rmtoll CR1 ENGC LL_I2C_EnableGeneralCall
600 * @param I2Cx I2C Instance.
601 * @retval None
602 */
LL_I2C_EnableGeneralCall(I2C_TypeDef * I2Cx)603 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
604 {
605 SET_BIT(I2Cx->CR1, I2C_CR1_ENGC);
606 }
607
608 /**
609 * @brief Disable General Call.
610 * @note When disabled the Address 0x00 is NACKed.
611 * @rmtoll CR1 ENGC LL_I2C_DisableGeneralCall
612 * @param I2Cx I2C Instance.
613 * @retval None
614 */
LL_I2C_DisableGeneralCall(I2C_TypeDef * I2Cx)615 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
616 {
617 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC);
618 }
619
620 /**
621 * @brief Check if General Call is enabled or disabled.
622 * @rmtoll CR1 ENGC LL_I2C_IsEnabledGeneralCall
623 * @param I2Cx I2C Instance.
624 * @retval State of bit (1 or 0).
625 */
LL_I2C_IsEnabledGeneralCall(I2C_TypeDef * I2Cx)626 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
627 {
628 return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC));
629 }
630
631 /**
632 * @brief Set the Own Address1.
633 * @rmtoll OAR1 ADD0 LL_I2C_SetOwnAddress1\n
634 * OAR1 ADD1_7 LL_I2C_SetOwnAddress1\n
635 * OAR1 ADD8_9 LL_I2C_SetOwnAddress1\n
636 * OAR1 ADDMODE LL_I2C_SetOwnAddress1
637 * @param I2Cx I2C Instance.
638 * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
639 * @param OwnAddrSize This parameter can be one of the following values:
640 * @arg @ref LL_I2C_OWNADDRESS1_7BIT
641 * @arg @ref LL_I2C_OWNADDRESS1_10BIT
642 * @retval None
643 */
LL_I2C_SetOwnAddress1(I2C_TypeDef * I2Cx,uint32_t OwnAddress1,uint32_t OwnAddrSize)644 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
645 {
646 MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD0 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD8_9 | I2C_OAR1_ADDMODE, OwnAddress1 | OwnAddrSize);
647 }
648
649 /**
650 * @brief Set the 7bits Own Address2.
651 * @note This action has no effect if own address2 is enabled.
652 * @rmtoll OAR2 ADD2 LL_I2C_SetOwnAddress2
653 * @param I2Cx I2C Instance.
654 * @param OwnAddress2 This parameter must be a value between Min_Data=0 and Max_Data=0x7F.
655 * @retval None
656 */
LL_I2C_SetOwnAddress2(I2C_TypeDef * I2Cx,uint32_t OwnAddress2)657 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2)
658 {
659 MODIFY_REG(I2Cx->OAR2, I2C_OAR2_ADD2, OwnAddress2);
660 }
661
662 /**
663 * @brief Enable acknowledge on Own Address2 match address.
664 * @rmtoll OAR2 ENDUAL LL_I2C_EnableOwnAddress2
665 * @param I2Cx I2C Instance.
666 * @retval None
667 */
LL_I2C_EnableOwnAddress2(I2C_TypeDef * I2Cx)668 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
669 {
670 SET_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
671 }
672
673 /**
674 * @brief Disable acknowledge on Own Address2 match address.
675 * @rmtoll OAR2 ENDUAL LL_I2C_DisableOwnAddress2
676 * @param I2Cx I2C Instance.
677 * @retval None
678 */
LL_I2C_DisableOwnAddress2(I2C_TypeDef * I2Cx)679 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
680 {
681 CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
682 }
683
684 /**
685 * @brief Check if Own Address1 acknowledge is enabled or disabled.
686 * @rmtoll OAR2 ENDUAL LL_I2C_IsEnabledOwnAddress2
687 * @param I2Cx I2C Instance.
688 * @retval State of bit (1 or 0).
689 */
LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef * I2Cx)690 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
691 {
692 return (READ_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL) == (I2C_OAR2_ENDUAL));
693 }
694
695 /**
696 * @brief Configure the Peripheral clock frequency.
697 * @rmtoll CR2 FREQ LL_I2C_SetPeriphClock
698 * @param I2Cx I2C Instance.
699 * @param PeriphClock Peripheral Clock (in Hz)
700 * @retval None
701 */
LL_I2C_SetPeriphClock(I2C_TypeDef * I2Cx,uint32_t PeriphClock)702 __STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock)
703 {
704 MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock));
705 }
706
707 /**
708 * @brief Get the Peripheral clock frequency.
709 * @rmtoll CR2 FREQ LL_I2C_GetPeriphClock
710 * @param I2Cx I2C Instance.
711 * @retval Value of Peripheral Clock (in Hz)
712 */
LL_I2C_GetPeriphClock(I2C_TypeDef * I2Cx)713 __STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx)
714 {
715 return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ)));
716 }
717
718 /**
719 * @brief Configure the Duty cycle (Fast mode only).
720 * @rmtoll CCR DUTY LL_I2C_SetDutyCycle
721 * @param I2Cx I2C Instance.
722 * @param DutyCycle This parameter can be one of the following values:
723 * @arg @ref LL_I2C_DUTYCYCLE_2
724 * @arg @ref LL_I2C_DUTYCYCLE_16_9
725 * @retval None
726 */
LL_I2C_SetDutyCycle(I2C_TypeDef * I2Cx,uint32_t DutyCycle)727 __STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle)
728 {
729 MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle);
730 }
731
732 /**
733 * @brief Get the Duty cycle (Fast mode only).
734 * @rmtoll CCR DUTY LL_I2C_GetDutyCycle
735 * @param I2Cx I2C Instance.
736 * @retval Returned value can be one of the following values:
737 * @arg @ref LL_I2C_DUTYCYCLE_2
738 * @arg @ref LL_I2C_DUTYCYCLE_16_9
739 */
LL_I2C_GetDutyCycle(I2C_TypeDef * I2Cx)740 __STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx)
741 {
742 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY));
743 }
744
745 /**
746 * @brief Configure the I2C master clock speed mode.
747 * @rmtoll CCR FS LL_I2C_SetClockSpeedMode
748 * @param I2Cx I2C Instance.
749 * @param ClockSpeedMode This parameter can be one of the following values:
750 * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
751 * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
752 * @retval None
753 */
LL_I2C_SetClockSpeedMode(I2C_TypeDef * I2Cx,uint32_t ClockSpeedMode)754 __STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode)
755 {
756 MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode);
757 }
758
759 /**
760 * @brief Get the the I2C master speed mode.
761 * @rmtoll CCR FS LL_I2C_GetClockSpeedMode
762 * @param I2Cx I2C Instance.
763 * @retval Returned value can be one of the following values:
764 * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
765 * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
766 */
LL_I2C_GetClockSpeedMode(I2C_TypeDef * I2Cx)767 __STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx)
768 {
769 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS));
770 }
771
772 /**
773 * @brief Configure the SCL, SDA rising time.
774 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
775 * @rmtoll TRISE TRISE LL_I2C_SetRiseTime
776 * @param I2Cx I2C Instance.
777 * @param RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F.
778 * @retval None
779 */
LL_I2C_SetRiseTime(I2C_TypeDef * I2Cx,uint32_t RiseTime)780 __STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime)
781 {
782 MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime);
783 }
784
785 /**
786 * @brief Get the SCL, SDA rising time.
787 * @rmtoll TRISE TRISE LL_I2C_GetRiseTime
788 * @param I2Cx I2C Instance.
789 * @retval Value between Min_Data=0x02 and Max_Data=0x3F
790 */
LL_I2C_GetRiseTime(I2C_TypeDef * I2Cx)791 __STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx)
792 {
793 return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE));
794 }
795
796 /**
797 * @brief Configure the SCL high and low period.
798 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
799 * @rmtoll CCR CCR LL_I2C_SetClockPeriod
800 * @param I2Cx I2C Instance.
801 * @param ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
802 * @retval None
803 */
LL_I2C_SetClockPeriod(I2C_TypeDef * I2Cx,uint32_t ClockPeriod)804 __STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod)
805 {
806 MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod);
807 }
808
809 /**
810 * @brief Get the SCL high and low period.
811 * @rmtoll CCR CCR LL_I2C_GetClockPeriod
812 * @param I2Cx I2C Instance.
813 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
814 */
LL_I2C_GetClockPeriod(I2C_TypeDef * I2Cx)815 __STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx)
816 {
817 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR));
818 }
819
820 /**
821 * @brief Configure the SCL speed.
822 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
823 * @rmtoll CR2 FREQ LL_I2C_ConfigSpeed\n
824 * TRISE TRISE LL_I2C_ConfigSpeed\n
825 * CCR FS LL_I2C_ConfigSpeed\n
826 * CCR DUTY LL_I2C_ConfigSpeed\n
827 * CCR CCR LL_I2C_ConfigSpeed
828 * @param I2Cx I2C Instance.
829 * @param PeriphClock Peripheral Clock (in Hz)
830 * @param ClockSpeed This parameter must be a value lower than 400kHz (in Hz).
831 * @param DutyCycle This parameter can be one of the following values:
832 * @arg @ref LL_I2C_DUTYCYCLE_2
833 * @arg @ref LL_I2C_DUTYCYCLE_16_9
834 * @retval None
835 */
LL_I2C_ConfigSpeed(I2C_TypeDef * I2Cx,uint32_t PeriphClock,uint32_t ClockSpeed,uint32_t DutyCycle)836 __STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed,
837 uint32_t DutyCycle)
838 {
839 uint32_t freqrange = 0x0U;
840 uint32_t clockconfig = 0x0U;
841
842 /* Compute frequency range */
843 freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock);
844
845 /* Configure I2Cx: Frequency range register */
846 MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange);
847
848 /* Configure I2Cx: Rise Time register */
849 MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed));
850
851 /* Configure Speed mode, Duty Cycle and Clock control register value */
852 if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD)
853 {
854 /* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */
855 clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE | \
856 __LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle) | \
857 DutyCycle;
858 }
859 else
860 {
861 /* Set Speed mode at standard for Clock Speed request in standard clock range */
862 clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE | \
863 __LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed);
864 }
865
866 /* Configure I2Cx: Clock control register */
867 MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), clockconfig);
868 }
869
870 /**
871 * @brief Configure peripheral mode.
872 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
873 * SMBus feature is supported by the I2Cx Instance.
874 * @rmtoll CR1 SMBUS LL_I2C_SetMode\n
875 * CR1 SMBTYPE LL_I2C_SetMode\n
876 * CR1 ENARP LL_I2C_SetMode
877 * @param I2Cx I2C Instance.
878 * @param PeripheralMode This parameter can be one of the following values:
879 * @arg @ref LL_I2C_MODE_I2C
880 * @arg @ref LL_I2C_MODE_SMBUS_HOST
881 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
882 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
883 * @retval None
884 */
LL_I2C_SetMode(I2C_TypeDef * I2Cx,uint32_t PeripheralMode)885 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
886 {
887 MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP, PeripheralMode);
888 }
889
890 /**
891 * @brief Get peripheral mode.
892 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
893 * SMBus feature is supported by the I2Cx Instance.
894 * @rmtoll CR1 SMBUS LL_I2C_GetMode\n
895 * CR1 SMBTYPE LL_I2C_GetMode\n
896 * CR1 ENARP LL_I2C_GetMode
897 * @param I2Cx I2C Instance.
898 * @retval Returned value can be one of the following values:
899 * @arg @ref LL_I2C_MODE_I2C
900 * @arg @ref LL_I2C_MODE_SMBUS_HOST
901 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
902 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
903 */
LL_I2C_GetMode(I2C_TypeDef * I2Cx)904 __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
905 {
906 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP));
907 }
908
909 /**
910 * @brief Enable SMBus alert (Host or Device mode)
911 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
912 * SMBus feature is supported by the I2Cx Instance.
913 * @note SMBus Device mode:
914 * - SMBus Alert pin is drived low and
915 * Alert Response Address Header acknowledge is enabled.
916 * SMBus Host mode:
917 * - SMBus Alert pin management is supported.
918 * @rmtoll CR1 ALERT LL_I2C_EnableSMBusAlert
919 * @param I2Cx I2C Instance.
920 * @retval None
921 */
LL_I2C_EnableSMBusAlert(I2C_TypeDef * I2Cx)922 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
923 {
924 SET_BIT(I2Cx->CR1, I2C_CR1_ALERT);
925 }
926
927 /**
928 * @brief Disable SMBus alert (Host or Device mode)
929 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
930 * SMBus feature is supported by the I2Cx Instance.
931 * @note SMBus Device mode:
932 * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
933 * Alert Response Address Header acknowledge is disabled.
934 * SMBus Host mode:
935 * - SMBus Alert pin management is not supported.
936 * @rmtoll CR1 ALERT LL_I2C_DisableSMBusAlert
937 * @param I2Cx I2C Instance.
938 * @retval None
939 */
LL_I2C_DisableSMBusAlert(I2C_TypeDef * I2Cx)940 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
941 {
942 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERT);
943 }
944
945 /**
946 * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
947 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
948 * SMBus feature is supported by the I2Cx Instance.
949 * @rmtoll CR1 ALERT LL_I2C_IsEnabledSMBusAlert
950 * @param I2Cx I2C Instance.
951 * @retval State of bit (1 or 0).
952 */
LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef * I2Cx)953 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
954 {
955 return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERT) == (I2C_CR1_ALERT));
956 }
957
958 /**
959 * @brief Enable SMBus Packet Error Calculation (PEC).
960 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
961 * SMBus feature is supported by the I2Cx Instance.
962 * @rmtoll CR1 ENPEC LL_I2C_EnableSMBusPEC
963 * @param I2Cx I2C Instance.
964 * @retval None
965 */
LL_I2C_EnableSMBusPEC(I2C_TypeDef * I2Cx)966 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
967 {
968 SET_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
969 }
970
971 /**
972 * @brief Disable SMBus Packet Error Calculation (PEC).
973 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
974 * SMBus feature is supported by the I2Cx Instance.
975 * @rmtoll CR1 ENPEC LL_I2C_DisableSMBusPEC
976 * @param I2Cx I2C Instance.
977 * @retval None
978 */
LL_I2C_DisableSMBusPEC(I2C_TypeDef * I2Cx)979 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
980 {
981 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
982 }
983
984 /**
985 * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
986 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
987 * SMBus feature is supported by the I2Cx Instance.
988 * @rmtoll CR1 ENPEC LL_I2C_IsEnabledSMBusPEC
989 * @param I2Cx I2C Instance.
990 * @retval State of bit (1 or 0).
991 */
LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef * I2Cx)992 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
993 {
994 return (READ_BIT(I2Cx->CR1, I2C_CR1_ENPEC) == (I2C_CR1_ENPEC));
995 }
996
997 /**
998 * @}
999 */
1000
1001 /** @defgroup I2C_LL_EF_IT_Management IT_Management
1002 * @{
1003 */
1004
1005 /**
1006 * @brief Enable TXE interrupt.
1007 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_TX\n
1008 * CR2 ITBUFEN LL_I2C_EnableIT_TX
1009 * @param I2Cx I2C Instance.
1010 * @retval None
1011 */
LL_I2C_EnableIT_TX(I2C_TypeDef * I2Cx)1012 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
1013 {
1014 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
1015 }
1016
1017 /**
1018 * @brief Disable TXE interrupt.
1019 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_TX\n
1020 * CR2 ITBUFEN LL_I2C_DisableIT_TX
1021 * @param I2Cx I2C Instance.
1022 * @retval None
1023 */
LL_I2C_DisableIT_TX(I2C_TypeDef * I2Cx)1024 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
1025 {
1026 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
1027 }
1028
1029 /**
1030 * @brief Check if the TXE Interrupt is enabled or disabled.
1031 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_TX\n
1032 * CR2 ITBUFEN LL_I2C_IsEnabledIT_TX
1033 * @param I2Cx I2C Instance.
1034 * @retval State of bit (1 or 0).
1035 */
LL_I2C_IsEnabledIT_TX(I2C_TypeDef * I2Cx)1036 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
1037 {
1038 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
1039 }
1040
1041 /**
1042 * @brief Enable RXNE interrupt.
1043 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_RX\n
1044 * CR2 ITBUFEN LL_I2C_EnableIT_RX
1045 * @param I2Cx I2C Instance.
1046 * @retval None
1047 */
LL_I2C_EnableIT_RX(I2C_TypeDef * I2Cx)1048 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
1049 {
1050 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
1051 }
1052
1053 /**
1054 * @brief Disable RXNE interrupt.
1055 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_RX\n
1056 * CR2 ITBUFEN LL_I2C_DisableIT_RX
1057 * @param I2Cx I2C Instance.
1058 * @retval None
1059 */
LL_I2C_DisableIT_RX(I2C_TypeDef * I2Cx)1060 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
1061 {
1062 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
1063 }
1064
1065 /**
1066 * @brief Check if the RXNE Interrupt is enabled or disabled.
1067 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_RX\n
1068 * CR2 ITBUFEN LL_I2C_IsEnabledIT_RX
1069 * @param I2Cx I2C Instance.
1070 * @retval State of bit (1 or 0).
1071 */
LL_I2C_IsEnabledIT_RX(I2C_TypeDef * I2Cx)1072 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
1073 {
1074 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
1075 }
1076
1077 /**
1078 * @brief Enable Events interrupts.
1079 * @note Any of these events will generate interrupt :
1080 * Start Bit (SB)
1081 * Address sent, Address matched (ADDR)
1082 * 10-bit header sent (ADD10)
1083 * Stop detection (STOPF)
1084 * Byte transfer finished (BTF)
1085 *
1086 * @note Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) :
1087 * Receive buffer not empty (RXNE)
1088 * Transmit buffer empty (TXE)
1089 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_EVT
1090 * @param I2Cx I2C Instance.
1091 * @retval None
1092 */
LL_I2C_EnableIT_EVT(I2C_TypeDef * I2Cx)1093 __STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx)
1094 {
1095 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
1096 }
1097
1098 /**
1099 * @brief Disable Events interrupts.
1100 * @note Any of these events will generate interrupt :
1101 * Start Bit (SB)
1102 * Address sent, Address matched (ADDR)
1103 * 10-bit header sent (ADD10)
1104 * Stop detection (STOPF)
1105 * Byte transfer finished (BTF)
1106 * Receive buffer not empty (RXNE)
1107 * Transmit buffer empty (TXE)
1108 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_EVT
1109 * @param I2Cx I2C Instance.
1110 * @retval None
1111 */
LL_I2C_DisableIT_EVT(I2C_TypeDef * I2Cx)1112 __STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx)
1113 {
1114 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
1115 }
1116
1117 /**
1118 * @brief Check if Events interrupts are enabled or disabled.
1119 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_EVT
1120 * @param I2Cx I2C Instance.
1121 * @retval State of bit (1 or 0).
1122 */
LL_I2C_IsEnabledIT_EVT(I2C_TypeDef * I2Cx)1123 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx)
1124 {
1125 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN));
1126 }
1127
1128 /**
1129 * @brief Enable Buffer interrupts.
1130 * @note Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) :
1131 * Receive buffer not empty (RXNE)
1132 * Transmit buffer empty (TXE)
1133 * @rmtoll CR2 ITBUFEN LL_I2C_EnableIT_BUF
1134 * @param I2Cx I2C Instance.
1135 * @retval None
1136 */
LL_I2C_EnableIT_BUF(I2C_TypeDef * I2Cx)1137 __STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx)
1138 {
1139 SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
1140 }
1141
1142 /**
1143 * @brief Disable Buffer interrupts.
1144 * @note Any of these Buffer events will generate interrupt :
1145 * Receive buffer not empty (RXNE)
1146 * Transmit buffer empty (TXE)
1147 * @rmtoll CR2 ITBUFEN LL_I2C_DisableIT_BUF
1148 * @param I2Cx I2C Instance.
1149 * @retval None
1150 */
LL_I2C_DisableIT_BUF(I2C_TypeDef * I2Cx)1151 __STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx)
1152 {
1153 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
1154 }
1155
1156 /**
1157 * @brief Check if Buffer interrupts are enabled or disabled.
1158 * @rmtoll CR2 ITBUFEN LL_I2C_IsEnabledIT_BUF
1159 * @param I2Cx I2C Instance.
1160 * @retval State of bit (1 or 0).
1161 */
LL_I2C_IsEnabledIT_BUF(I2C_TypeDef * I2Cx)1162 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx)
1163 {
1164 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN));
1165 }
1166
1167 /**
1168 * @brief Enable Error interrupts.
1169 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1170 * SMBus feature is supported by the I2Cx Instance.
1171 * @note Any of these errors will generate interrupt :
1172 * Bus Error detection (BERR)
1173 * Arbitration Loss (ARLO)
1174 * Acknowledge Failure(AF)
1175 * Overrun/Underrun (OVR)
1176 * SMBus Timeout detection (TIMEOUT)
1177 * SMBus PEC error detection (PECERR)
1178 * SMBus Alert pin event detection (SMBALERT)
1179 * @rmtoll CR2 ITERREN LL_I2C_EnableIT_ERR
1180 * @param I2Cx I2C Instance.
1181 * @retval None
1182 */
LL_I2C_EnableIT_ERR(I2C_TypeDef * I2Cx)1183 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
1184 {
1185 SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
1186 }
1187
1188 /**
1189 * @brief Disable Error interrupts.
1190 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1191 * SMBus feature is supported by the I2Cx Instance.
1192 * @note Any of these errors will generate interrupt :
1193 * Bus Error detection (BERR)
1194 * Arbitration Loss (ARLO)
1195 * Acknowledge Failure(AF)
1196 * Overrun/Underrun (OVR)
1197 * SMBus Timeout detection (TIMEOUT)
1198 * SMBus PEC error detection (PECERR)
1199 * SMBus Alert pin event detection (SMBALERT)
1200 * @rmtoll CR2 ITERREN LL_I2C_DisableIT_ERR
1201 * @param I2Cx I2C Instance.
1202 * @retval None
1203 */
LL_I2C_DisableIT_ERR(I2C_TypeDef * I2Cx)1204 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
1205 {
1206 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
1207 }
1208
1209 /**
1210 * @brief Check if Error interrupts are enabled or disabled.
1211 * @rmtoll CR2 ITERREN LL_I2C_IsEnabledIT_ERR
1212 * @param I2Cx I2C Instance.
1213 * @retval State of bit (1 or 0).
1214 */
LL_I2C_IsEnabledIT_ERR(I2C_TypeDef * I2Cx)1215 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
1216 {
1217 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN));
1218 }
1219
1220 /**
1221 * @}
1222 */
1223
1224 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
1225 * @{
1226 */
1227
1228 /**
1229 * @brief Indicate the status of Transmit data register empty flag.
1230 * @note RESET: When next data is written in Transmit data register.
1231 * SET: When Transmit data register is empty.
1232 * @rmtoll SR1 TXE LL_I2C_IsActiveFlag_TXE
1233 * @param I2Cx I2C Instance.
1234 * @retval State of bit (1 or 0).
1235 */
LL_I2C_IsActiveFlag_TXE(I2C_TypeDef * I2Cx)1236 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
1237 {
1238 return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE));
1239 }
1240
1241 /**
1242 * @brief Indicate the status of Byte Transfer Finished flag.
1243 * RESET: When Data byte transfer not done.
1244 * SET: When Data byte transfer succeeded.
1245 * @rmtoll SR1 BTF LL_I2C_IsActiveFlag_BTF
1246 * @param I2Cx I2C Instance.
1247 * @retval State of bit (1 or 0).
1248 */
LL_I2C_IsActiveFlag_BTF(I2C_TypeDef * I2Cx)1249 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx)
1250 {
1251 return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF));
1252 }
1253
1254 /**
1255 * @brief Indicate the status of Receive data register not empty flag.
1256 * @note RESET: When Receive data register is read.
1257 * SET: When the received data is copied in Receive data register.
1258 * @rmtoll SR1 RXNE LL_I2C_IsActiveFlag_RXNE
1259 * @param I2Cx I2C Instance.
1260 * @retval State of bit (1 or 0).
1261 */
LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef * I2Cx)1262 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
1263 {
1264 return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE));
1265 }
1266
1267 /**
1268 * @brief Indicate the status of Start Bit (master mode).
1269 * @note RESET: When No Start condition.
1270 * SET: When Start condition is generated.
1271 * @rmtoll SR1 SB LL_I2C_IsActiveFlag_SB
1272 * @param I2Cx I2C Instance.
1273 * @retval State of bit (1 or 0).
1274 */
LL_I2C_IsActiveFlag_SB(I2C_TypeDef * I2Cx)1275 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx)
1276 {
1277 return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB));
1278 }
1279
1280 /**
1281 * @brief Indicate the status of Address sent (master mode) or Address matched flag (slave mode).
1282 * @note RESET: Clear default value.
1283 * SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode).
1284 * @rmtoll SR1 ADDR LL_I2C_IsActiveFlag_ADDR
1285 * @param I2Cx I2C Instance.
1286 * @retval State of bit (1 or 0).
1287 */
LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef * I2Cx)1288 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
1289 {
1290 return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR));
1291 }
1292
1293 /**
1294 * @brief Indicate the status of 10-bit header sent (master mode).
1295 * @note RESET: When no ADD10 event occurred.
1296 * SET: When the master has sent the first address byte (header).
1297 * @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10
1298 * @param I2Cx I2C Instance.
1299 * @retval State of bit (1 or 0).
1300 */
LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef * I2Cx)1301 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx)
1302 {
1303 return (READ_BIT(I2Cx->SR1, I2C_SR1_ADD10) == (I2C_SR1_ADD10));
1304 }
1305
1306 /**
1307 * @brief Indicate the status of Acknowledge failure flag.
1308 * @note RESET: No acknowledge failure.
1309 * SET: When an acknowledge failure is received after a byte transmission.
1310 * @rmtoll SR1 AF LL_I2C_IsActiveFlag_AF
1311 * @param I2Cx I2C Instance.
1312 * @retval State of bit (1 or 0).
1313 */
LL_I2C_IsActiveFlag_AF(I2C_TypeDef * I2Cx)1314 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx)
1315 {
1316 return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF));
1317 }
1318
1319 /**
1320 * @brief Indicate the status of Stop detection flag (slave mode).
1321 * @note RESET: Clear default value.
1322 * SET: When a Stop condition is detected.
1323 * @rmtoll SR1 STOPF LL_I2C_IsActiveFlag_STOP
1324 * @param I2Cx I2C Instance.
1325 * @retval State of bit (1 or 0).
1326 */
LL_I2C_IsActiveFlag_STOP(I2C_TypeDef * I2Cx)1327 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
1328 {
1329 return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF));
1330 }
1331
1332 /**
1333 * @brief Indicate the status of Bus error flag.
1334 * @note RESET: Clear default value.
1335 * SET: When a misplaced Start or Stop condition is detected.
1336 * @rmtoll SR1 BERR LL_I2C_IsActiveFlag_BERR
1337 * @param I2Cx I2C Instance.
1338 * @retval State of bit (1 or 0).
1339 */
LL_I2C_IsActiveFlag_BERR(I2C_TypeDef * I2Cx)1340 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
1341 {
1342 return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR));
1343 }
1344
1345 /**
1346 * @brief Indicate the status of Arbitration lost flag.
1347 * @note RESET: Clear default value.
1348 * SET: When arbitration lost.
1349 * @rmtoll SR1 ARLO LL_I2C_IsActiveFlag_ARLO
1350 * @param I2Cx I2C Instance.
1351 * @retval State of bit (1 or 0).
1352 */
LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef * I2Cx)1353 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
1354 {
1355 return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO));
1356 }
1357
1358 /**
1359 * @brief Indicate the status of Overrun/Underrun flag.
1360 * @note RESET: Clear default value.
1361 * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
1362 * @rmtoll SR1 OVR LL_I2C_IsActiveFlag_OVR
1363 * @param I2Cx I2C Instance.
1364 * @retval State of bit (1 or 0).
1365 */
LL_I2C_IsActiveFlag_OVR(I2C_TypeDef * I2Cx)1366 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
1367 {
1368 return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR));
1369 }
1370
1371 /**
1372 * @brief Indicate the status of SMBus PEC error flag in reception.
1373 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1374 * SMBus feature is supported by the I2Cx Instance.
1375 * @rmtoll SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR
1376 * @param I2Cx I2C Instance.
1377 * @retval State of bit (1 or 0).
1378 */
LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef * I2Cx)1379 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
1380 {
1381 return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR));
1382 }
1383
1384 /**
1385 * @brief Indicate the status of SMBus Timeout detection flag.
1386 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1387 * SMBus feature is supported by the I2Cx Instance.
1388 * @rmtoll SR1 TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
1389 * @param I2Cx I2C Instance.
1390 * @retval State of bit (1 or 0).
1391 */
LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef * I2Cx)1392 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
1393 {
1394 return (READ_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT) == (I2C_SR1_TIMEOUT));
1395 }
1396
1397 /**
1398 * @brief Indicate the status of SMBus alert flag.
1399 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1400 * SMBus feature is supported by the I2Cx Instance.
1401 * @rmtoll SR1 SMBALERT LL_I2C_IsActiveSMBusFlag_ALERT
1402 * @param I2Cx I2C Instance.
1403 * @retval State of bit (1 or 0).
1404 */
LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef * I2Cx)1405 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
1406 {
1407 return (READ_BIT(I2Cx->SR1, I2C_SR1_SMBALERT) == (I2C_SR1_SMBALERT));
1408 }
1409
1410 /**
1411 * @brief Indicate the status of Bus Busy flag.
1412 * @note RESET: Clear default value.
1413 * SET: When a Start condition is detected.
1414 * @rmtoll SR2 BUSY LL_I2C_IsActiveFlag_BUSY
1415 * @param I2Cx I2C Instance.
1416 * @retval State of bit (1 or 0).
1417 */
LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef * I2Cx)1418 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
1419 {
1420 return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY));
1421 }
1422
1423 /**
1424 * @brief Indicate the status of Dual flag.
1425 * @note RESET: Received address matched with OAR1.
1426 * SET: Received address matched with OAR2.
1427 * @rmtoll SR2 DUALF LL_I2C_IsActiveFlag_DUAL
1428 * @param I2Cx I2C Instance.
1429 * @retval State of bit (1 or 0).
1430 */
LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef * I2Cx)1431 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx)
1432 {
1433 return (READ_BIT(I2Cx->SR2, I2C_SR2_DUALF) == (I2C_SR2_DUALF));
1434 }
1435
1436 /**
1437 * @brief Indicate the status of SMBus Host address reception (Slave mode).
1438 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1439 * SMBus feature is supported by the I2Cx Instance.
1440 * @note RESET: No SMBus Host address
1441 * SET: SMBus Host address received.
1442 * @note This status is cleared by hardware after a STOP condition or repeated START condition.
1443 * @rmtoll SR2 SMBHOST LL_I2C_IsActiveSMBusFlag_SMBHOST
1444 * @param I2Cx I2C Instance.
1445 * @retval State of bit (1 or 0).
1446 */
LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef * I2Cx)1447 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx)
1448 {
1449 return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBHOST) == (I2C_SR2_SMBHOST));
1450 }
1451
1452 /**
1453 * @brief Indicate the status of SMBus Device default address reception (Slave mode).
1454 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1455 * SMBus feature is supported by the I2Cx Instance.
1456 * @note RESET: No SMBus Device default address
1457 * SET: SMBus Device default address received.
1458 * @note This status is cleared by hardware after a STOP condition or repeated START condition.
1459 * @rmtoll SR2 SMBDEFAULT LL_I2C_IsActiveSMBusFlag_SMBDEFAULT
1460 * @param I2Cx I2C Instance.
1461 * @retval State of bit (1 or 0).
1462 */
LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef * I2Cx)1463 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx)
1464 {
1465 return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBDEFAULT) == (I2C_SR2_SMBDEFAULT));
1466 }
1467
1468 /**
1469 * @brief Indicate the status of General call address reception (Slave mode).
1470 * @note RESET: No General call address
1471 * SET: General call address received.
1472 * @note This status is cleared by hardware after a STOP condition or repeated START condition.
1473 * @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL
1474 * @param I2Cx I2C Instance.
1475 * @retval State of bit (1 or 0).
1476 */
LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef * I2Cx)1477 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx)
1478 {
1479 return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL));
1480 }
1481
1482 /**
1483 * @brief Indicate the status of Master/Slave flag.
1484 * @note RESET: Slave Mode.
1485 * SET: Master Mode.
1486 * @rmtoll SR2 MSL LL_I2C_IsActiveFlag_MSL
1487 * @param I2Cx I2C Instance.
1488 * @retval State of bit (1 or 0).
1489 */
LL_I2C_IsActiveFlag_MSL(I2C_TypeDef * I2Cx)1490 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx)
1491 {
1492 return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL));
1493 }
1494
1495 /**
1496 * @brief Clear Address Matched flag.
1497 * @note Clearing this flag is done by a read access to the I2Cx_SR1
1498 * register followed by a read access to the I2Cx_SR2 register.
1499 * @rmtoll SR1 ADDR LL_I2C_ClearFlag_ADDR
1500 * @param I2Cx I2C Instance.
1501 * @retval None
1502 */
LL_I2C_ClearFlag_ADDR(I2C_TypeDef * I2Cx)1503 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
1504 {
1505 __IO uint32_t tmpreg;
1506 tmpreg = I2Cx->SR1;
1507 (void) tmpreg;
1508 tmpreg = I2Cx->SR2;
1509 (void) tmpreg;
1510 }
1511
1512 /**
1513 * @brief Clear Acknowledge failure flag.
1514 * @rmtoll SR1 AF LL_I2C_ClearFlag_AF
1515 * @param I2Cx I2C Instance.
1516 * @retval None
1517 */
LL_I2C_ClearFlag_AF(I2C_TypeDef * I2Cx)1518 __STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx)
1519 {
1520 CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF);
1521 }
1522
1523 /**
1524 * @brief Clear Stop detection flag.
1525 * @note Clearing this flag is done by a read access to the I2Cx_SR1
1526 * register followed by a write access to I2Cx_CR1 register.
1527 * @rmtoll SR1 STOPF LL_I2C_ClearFlag_STOP\n
1528 * CR1 PE LL_I2C_ClearFlag_STOP
1529 * @param I2Cx I2C Instance.
1530 * @retval None
1531 */
LL_I2C_ClearFlag_STOP(I2C_TypeDef * I2Cx)1532 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
1533 {
1534 __IO uint32_t tmpreg;
1535 tmpreg = I2Cx->SR1;
1536 (void) tmpreg;
1537 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
1538 }
1539
1540 /**
1541 * @brief Clear Bus error flag.
1542 * @rmtoll SR1 BERR LL_I2C_ClearFlag_BERR
1543 * @param I2Cx I2C Instance.
1544 * @retval None
1545 */
LL_I2C_ClearFlag_BERR(I2C_TypeDef * I2Cx)1546 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
1547 {
1548 CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR);
1549 }
1550
1551 /**
1552 * @brief Clear Arbitration lost flag.
1553 * @rmtoll SR1 ARLO LL_I2C_ClearFlag_ARLO
1554 * @param I2Cx I2C Instance.
1555 * @retval None
1556 */
LL_I2C_ClearFlag_ARLO(I2C_TypeDef * I2Cx)1557 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
1558 {
1559 CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO);
1560 }
1561
1562 /**
1563 * @brief Clear Overrun/Underrun flag.
1564 * @rmtoll SR1 OVR LL_I2C_ClearFlag_OVR
1565 * @param I2Cx I2C Instance.
1566 * @retval None
1567 */
LL_I2C_ClearFlag_OVR(I2C_TypeDef * I2Cx)1568 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
1569 {
1570 CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR);
1571 }
1572
1573 /**
1574 * @brief Clear SMBus PEC error flag.
1575 * @rmtoll SR1 PECERR LL_I2C_ClearSMBusFlag_PECERR
1576 * @param I2Cx I2C Instance.
1577 * @retval None
1578 */
LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef * I2Cx)1579 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
1580 {
1581 CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR);
1582 }
1583
1584 /**
1585 * @brief Clear SMBus Timeout detection flag.
1586 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1587 * SMBus feature is supported by the I2Cx Instance.
1588 * @rmtoll SR1 TIMEOUT LL_I2C_ClearSMBusFlag_TIMEOUT
1589 * @param I2Cx I2C Instance.
1590 * @retval None
1591 */
LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef * I2Cx)1592 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
1593 {
1594 CLEAR_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT);
1595 }
1596
1597 /**
1598 * @brief Clear SMBus Alert flag.
1599 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1600 * SMBus feature is supported by the I2Cx Instance.
1601 * @rmtoll SR1 SMBALERT LL_I2C_ClearSMBusFlag_ALERT
1602 * @param I2Cx I2C Instance.
1603 * @retval None
1604 */
LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef * I2Cx)1605 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
1606 {
1607 CLEAR_BIT(I2Cx->SR1, I2C_SR1_SMBALERT);
1608 }
1609
1610 /**
1611 * @}
1612 */
1613
1614 /** @defgroup I2C_LL_EF_Data_Management Data_Management
1615 * @{
1616 */
1617
1618 /**
1619 * @brief Enable Reset of I2C peripheral.
1620 * @rmtoll CR1 SWRST LL_I2C_EnableReset
1621 * @param I2Cx I2C Instance.
1622 * @retval None
1623 */
LL_I2C_EnableReset(I2C_TypeDef * I2Cx)1624 __STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx)
1625 {
1626 SET_BIT(I2Cx->CR1, I2C_CR1_SWRST);
1627 }
1628
1629 /**
1630 * @brief Disable Reset of I2C peripheral.
1631 * @rmtoll CR1 SWRST LL_I2C_DisableReset
1632 * @param I2Cx I2C Instance.
1633 * @retval None
1634 */
LL_I2C_DisableReset(I2C_TypeDef * I2Cx)1635 __STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx)
1636 {
1637 CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST);
1638 }
1639
1640 /**
1641 * @brief Check if the I2C peripheral is under reset state or not.
1642 * @rmtoll CR1 SWRST LL_I2C_IsResetEnabled
1643 * @param I2Cx I2C Instance.
1644 * @retval State of bit (1 or 0).
1645 */
LL_I2C_IsResetEnabled(I2C_TypeDef * I2Cx)1646 __STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx)
1647 {
1648 return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST));
1649 }
1650
1651 /**
1652 * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
1653 * @note Usage in Slave or Master mode.
1654 * @rmtoll CR1 ACK LL_I2C_AcknowledgeNextData
1655 * @param I2Cx I2C Instance.
1656 * @param TypeAcknowledge This parameter can be one of the following values:
1657 * @arg @ref LL_I2C_ACK
1658 * @arg @ref LL_I2C_NACK
1659 * @retval None
1660 */
LL_I2C_AcknowledgeNextData(I2C_TypeDef * I2Cx,uint32_t TypeAcknowledge)1661 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
1662 {
1663 MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge);
1664 }
1665
1666 /**
1667 * @brief Generate a START or RESTART condition
1668 * @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
1669 * This action has no effect when RELOAD is set.
1670 * @rmtoll CR1 START LL_I2C_GenerateStartCondition
1671 * @param I2Cx I2C Instance.
1672 * @retval None
1673 */
LL_I2C_GenerateStartCondition(I2C_TypeDef * I2Cx)1674 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
1675 {
1676 SET_BIT(I2Cx->CR1, I2C_CR1_START);
1677 }
1678
1679 /**
1680 * @brief Generate a STOP condition after the current byte transfer (master mode).
1681 * @rmtoll CR1 STOP LL_I2C_GenerateStopCondition
1682 * @param I2Cx I2C Instance.
1683 * @retval None
1684 */
LL_I2C_GenerateStopCondition(I2C_TypeDef * I2Cx)1685 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
1686 {
1687 SET_BIT(I2Cx->CR1, I2C_CR1_STOP);
1688 }
1689
1690 /**
1691 * @brief Enable bit POS (master/host mode).
1692 * @note In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC.
1693 * @rmtoll CR1 POS LL_I2C_EnableBitPOS
1694 * @param I2Cx I2C Instance.
1695 * @retval None
1696 */
LL_I2C_EnableBitPOS(I2C_TypeDef * I2Cx)1697 __STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx)
1698 {
1699 SET_BIT(I2Cx->CR1, I2C_CR1_POS);
1700 }
1701
1702 /**
1703 * @brief Disable bit POS (master/host mode).
1704 * @note In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC.
1705 * @rmtoll CR1 POS LL_I2C_DisableBitPOS
1706 * @param I2Cx I2C Instance.
1707 * @retval None
1708 */
LL_I2C_DisableBitPOS(I2C_TypeDef * I2Cx)1709 __STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx)
1710 {
1711 CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS);
1712 }
1713
1714 /**
1715 * @brief Check if bit POS is enabled or disabled.
1716 * @rmtoll CR1 POS LL_I2C_IsEnabledBitPOS
1717 * @param I2Cx I2C Instance.
1718 * @retval State of bit (1 or 0).
1719 */
LL_I2C_IsEnabledBitPOS(I2C_TypeDef * I2Cx)1720 __STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx)
1721 {
1722 return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS));
1723 }
1724
1725 /**
1726 * @brief Indicate the value of transfer direction.
1727 * @note RESET: Bus is in read transfer (peripheral point of view).
1728 * SET: Bus is in write transfer (peripheral point of view).
1729 * @rmtoll SR2 TRA LL_I2C_GetTransferDirection
1730 * @param I2Cx I2C Instance.
1731 * @retval Returned value can be one of the following values:
1732 * @arg @ref LL_I2C_DIRECTION_WRITE
1733 * @arg @ref LL_I2C_DIRECTION_READ
1734 */
LL_I2C_GetTransferDirection(I2C_TypeDef * I2Cx)1735 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
1736 {
1737 return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA));
1738 }
1739
1740 /**
1741 * @brief Enable DMA last transfer.
1742 * @note This action mean that next DMA EOT is the last transfer.
1743 * @rmtoll CR2 LAST LL_I2C_EnableLastDMA
1744 * @param I2Cx I2C Instance.
1745 * @retval None
1746 */
LL_I2C_EnableLastDMA(I2C_TypeDef * I2Cx)1747 __STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx)
1748 {
1749 SET_BIT(I2Cx->CR2, I2C_CR2_LAST);
1750 }
1751
1752 /**
1753 * @brief Disable DMA last transfer.
1754 * @note This action mean that next DMA EOT is not the last transfer.
1755 * @rmtoll CR2 LAST LL_I2C_DisableLastDMA
1756 * @param I2Cx I2C Instance.
1757 * @retval None
1758 */
LL_I2C_DisableLastDMA(I2C_TypeDef * I2Cx)1759 __STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx)
1760 {
1761 CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST);
1762 }
1763
1764 /**
1765 * @brief Check if DMA last transfer is enabled or disabled.
1766 * @rmtoll CR2 LAST LL_I2C_IsEnabledLastDMA
1767 * @param I2Cx I2C Instance.
1768 * @retval State of bit (1 or 0).
1769 */
LL_I2C_IsEnabledLastDMA(I2C_TypeDef * I2Cx)1770 __STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx)
1771 {
1772 return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST));
1773 }
1774
1775 /**
1776 * @brief Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
1777 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1778 * SMBus feature is supported by the I2Cx Instance.
1779 * @note This feature is cleared by hardware when the PEC byte is transferred or compared,
1780 * or by a START or STOP condition, it is also cleared by software.
1781 * @rmtoll CR1 PEC LL_I2C_EnableSMBusPECCompare
1782 * @param I2Cx I2C Instance.
1783 * @retval None
1784 */
LL_I2C_EnableSMBusPECCompare(I2C_TypeDef * I2Cx)1785 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
1786 {
1787 SET_BIT(I2Cx->CR1, I2C_CR1_PEC);
1788 }
1789
1790 /**
1791 * @brief Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
1792 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1793 * SMBus feature is supported by the I2Cx Instance.
1794 * @rmtoll CR1 PEC LL_I2C_DisableSMBusPECCompare
1795 * @param I2Cx I2C Instance.
1796 * @retval None
1797 */
LL_I2C_DisableSMBusPECCompare(I2C_TypeDef * I2Cx)1798 __STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx)
1799 {
1800 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PEC);
1801 }
1802
1803 /**
1804 * @brief Check if the SMBus Packet Error byte transfer or internal comparison is requested or not.
1805 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1806 * SMBus feature is supported by the I2Cx Instance.
1807 * @rmtoll CR1 PEC LL_I2C_IsEnabledSMBusPECCompare
1808 * @param I2Cx I2C Instance.
1809 * @retval State of bit (1 or 0).
1810 */
LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef * I2Cx)1811 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
1812 {
1813 return (READ_BIT(I2Cx->CR1, I2C_CR1_PEC) == (I2C_CR1_PEC));
1814 }
1815
1816 /**
1817 * @brief Get the SMBus Packet Error byte calculated.
1818 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1819 * SMBus feature is supported by the I2Cx Instance.
1820 * @rmtoll SR2 PEC LL_I2C_GetSMBusPEC
1821 * @param I2Cx I2C Instance.
1822 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1823 */
LL_I2C_GetSMBusPEC(I2C_TypeDef * I2Cx)1824 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
1825 {
1826 return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> I2C_SR2_PEC_Pos);
1827 }
1828
1829 /**
1830 * @brief Read Receive Data register.
1831 * @rmtoll DR DR LL_I2C_ReceiveData8
1832 * @param I2Cx I2C Instance.
1833 * @retval Value between Min_Data=0x0 and Max_Data=0xFF
1834 */
LL_I2C_ReceiveData8(I2C_TypeDef * I2Cx)1835 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
1836 {
1837 return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR));
1838 }
1839
1840 /**
1841 * @brief Write in Transmit Data Register .
1842 * @rmtoll DR DR LL_I2C_TransmitData8
1843 * @param I2Cx I2C Instance.
1844 * @param Data Value between Min_Data=0x0 and Max_Data=0xFF
1845 * @retval None
1846 */
LL_I2C_TransmitData8(I2C_TypeDef * I2Cx,uint8_t Data)1847 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
1848 {
1849 MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data);
1850 }
1851
1852 /**
1853 * @}
1854 */
1855
1856 #if defined(USE_FULL_LL_DRIVER)
1857 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
1858 * @{
1859 */
1860
1861 uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
1862 uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
1863 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
1864
1865
1866 /**
1867 * @}
1868 */
1869 #endif /* USE_FULL_LL_DRIVER */
1870
1871 /**
1872 * @}
1873 */
1874
1875 /**
1876 * @}
1877 */
1878
1879 #endif /* I2C1 || I2C2 || I2C3 */
1880
1881 /**
1882 * @}
1883 */
1884
1885 #ifdef __cplusplus
1886 }
1887 #endif
1888
1889 #endif /* __STM32F4xx_LL_I2C_H */
1890
1891
