1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32F4xx_LL_DMA_H
21 #define __STM32F4xx_LL_DMA_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f4xx.h"
29
30 /** @addtogroup STM32F4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (DMA1) || defined (DMA2)
35
36 /** @defgroup DMA_LL DMA
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
43 * @{
44 */
45 /* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
46 static const uint8_t STREAM_OFFSET_TAB[] =
47 {
48 (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
49 (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
50 (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
51 (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
52 (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
53 (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
54 (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
55 (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
56 };
57
58 /**
59 * @}
60 */
61
62 /* Private constants ---------------------------------------------------------*/
63 /** @defgroup DMA_LL_Private_Constants DMA Private Constants
64 * @{
65 */
66 /**
67 * @}
68 */
69
70
71 /* Private macros ------------------------------------------------------------*/
72 /* Exported types ------------------------------------------------------------*/
73 #if defined(USE_FULL_LL_DRIVER)
74 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
75 * @{
76 */
77 typedef struct
78 {
79 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
80 or as Source base address in case of memory to memory transfer direction.
81
82 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
83
84 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
85 or as Destination base address in case of memory to memory transfer direction.
86
87 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
88
89 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
90 from memory to memory or from peripheral to memory.
91 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
92
93 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
94
95 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
96 This parameter can be a value of @ref DMA_LL_EC_MODE
97 @note The circular buffer mode cannot be used if the memory to memory
98 data transfer direction is configured on the selected Stream
99
100 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
101
102 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
103 is incremented or not.
104 This parameter can be a value of @ref DMA_LL_EC_PERIPH
105
106 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
107
108 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
109 is incremented or not.
110 This parameter can be a value of @ref DMA_LL_EC_MEMORY
111
112 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
113
114 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
115 in case of memory to memory transfer direction.
116 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
117
118 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
119
120 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
121 in case of memory to memory transfer direction.
122 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
123
124 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
125
126 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
127 The data unit is equal to the source buffer configuration set in PeripheralSize
128 or MemorySize parameters depending in the transfer direction.
129 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
130
131 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
132
133 uint32_t Channel; /*!< Specifies the peripheral channel.
134 This parameter can be a value of @ref DMA_LL_EC_CHANNEL
135
136 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */
137
138 uint32_t Priority; /*!< Specifies the channel priority level.
139 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
140
141 This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
142
143 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
144 This parameter can be a value of @ref DMA_LL_FIFOMODE
145 @note The Direct mode (FIFO mode disabled) cannot be used if the
146 memory-to-memory data transfer is configured on the selected stream
147
148 This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
149
150 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
151 This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
152
153 This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
154
155 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
156 It specifies the amount of data to be transferred in a single non interruptible
157 transaction.
158 This parameter can be a value of @ref DMA_LL_EC_MBURST
159 @note The burst mode is possible only if the address Increment mode is enabled.
160
161 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
162
163 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
164 It specifies the amount of data to be transferred in a single non interruptible
165 transaction.
166 This parameter can be a value of @ref DMA_LL_EC_PBURST
167 @note The burst mode is possible only if the address Increment mode is enabled.
168
169 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
170
171 } LL_DMA_InitTypeDef;
172 /**
173 * @}
174 */
175 #endif /*USE_FULL_LL_DRIVER*/
176 /* Exported constants --------------------------------------------------------*/
177 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
178 * @{
179 */
180
181 /** @defgroup DMA_LL_EC_STREAM STREAM
182 * @{
183 */
184 #define LL_DMA_STREAM_0 0x00000000U
185 #define LL_DMA_STREAM_1 0x00000001U
186 #define LL_DMA_STREAM_2 0x00000002U
187 #define LL_DMA_STREAM_3 0x00000003U
188 #define LL_DMA_STREAM_4 0x00000004U
189 #define LL_DMA_STREAM_5 0x00000005U
190 #define LL_DMA_STREAM_6 0x00000006U
191 #define LL_DMA_STREAM_7 0x00000007U
192 #define LL_DMA_STREAM_ALL 0xFFFF0000U
193 /**
194 * @}
195 */
196
197 /** @defgroup DMA_LL_EC_DIRECTION DIRECTION
198 * @{
199 */
200 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
201 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */
202 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */
203 /**
204 * @}
205 */
206
207 /** @defgroup DMA_LL_EC_MODE MODE
208 * @{
209 */
210 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
211 #define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode */
212 #define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */
213 /**
214 * @}
215 */
216
217 /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLEBUFFER MODE
218 * @{
219 */
220 #define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */
221 #define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mode */
222 /**
223 * @}
224 */
225
226 /** @defgroup DMA_LL_EC_PERIPH PERIPH
227 * @{
228 */
229 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
230 #define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode Enable */
231 /**
232 * @}
233 */
234
235 /** @defgroup DMA_LL_EC_MEMORY MEMORY
236 * @{
237 */
238 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
239 #define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enable */
240 /**
241 * @}
242 */
243
244 /** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
245 * @{
246 */
247 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
248 #define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
249 #define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment : Word */
250 /**
251 * @}
252 */
253
254 /** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
255 * @{
256 */
257 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
258 #define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
259 #define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Word */
260 /**
261 * @}
262 */
263
264 /** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
265 * @{
266 */
267 #define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */
268 #define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */
269 /**
270 * @}
271 */
272
273 /** @defgroup DMA_LL_EC_PRIORITY PRIORITY
274 * @{
275 */
276 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
277 #define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium */
278 #define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High */
279 #define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High */
280 /**
281 * @}
282 */
283
284 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
285 * @{
286 */
287 #define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */
288 #define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */
289 #define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */
290 #define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */
291 #define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */
292 #define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */
293 #define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */
294 #define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */
295 #if defined (DMA_SxCR_CHSEL_3)
296 #define LL_DMA_CHANNEL_8 DMA_SxCR_CHSEL_3 /* Select Channel8 of DMA Instance */
297 #define LL_DMA_CHANNEL_9 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_0) /* Select Channel9 of DMA Instance */
298 #define LL_DMA_CHANNEL_10 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1) /* Select Channel10 of DMA Instance */
299 #define LL_DMA_CHANNEL_11 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel11 of DMA Instance */
300 #define LL_DMA_CHANNEL_12 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2) /* Select Channel12 of DMA Instance */
301 #define LL_DMA_CHANNEL_13 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel13 of DMA Instance */
302 #define LL_DMA_CHANNEL_14 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel14 of DMA Instance */
303 #define LL_DMA_CHANNEL_15 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel15 of DMA Instance */
304 #endif /* DMA_SxCR_CHSEL_3 */
305 /**
306 * @}
307 */
308
309 /** @defgroup DMA_LL_EC_MBURST MBURST
310 * @{
311 */
312 #define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst single transfer configuration */
313 #define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */
314 #define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */
315 #define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */
316 /**
317 * @}
318 */
319
320 /** @defgroup DMA_LL_EC_PBURST PBURST
321 * @{
322 */
323 #define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral burst single transfer configuration */
324 #define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */
325 #define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */
326 #define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */
327 /**
328 * @}
329 */
330
331 /** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
332 * @{
333 */
334 #define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable (direct mode is enabled) */
335 #define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */
336 /**
337 * @}
338 */
339
340 /** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
341 * @{
342 */
343 #define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_level < 1/4 */
344 #define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_level < 1/2 */
345 #define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_level < 3/4 */
346 #define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */
347 #define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empty */
348 #define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full */
349 /**
350 * @}
351 */
352
353 /** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
354 * @{
355 */
356 #define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO threshold 1 quart full configuration */
357 #define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */
358 #define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */
359 #define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */
360 /**
361 * @}
362 */
363
364 /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
365 * @{
366 */
367 #define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */
368 #define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */
369 /**
370 * @}
371 */
372
373 /**
374 * @}
375 */
376
377 /* Exported macro ------------------------------------------------------------*/
378 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
379 * @{
380 */
381
382 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
383 * @{
384 */
385 /**
386 * @brief Write a value in DMA register
387 * @param __INSTANCE__ DMA Instance
388 * @param __REG__ Register to be written
389 * @param __VALUE__ Value to be written in the register
390 * @retval None
391 */
392 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
393
394 /**
395 * @brief Read a value in DMA register
396 * @param __INSTANCE__ DMA Instance
397 * @param __REG__ Register to be read
398 * @retval Register value
399 */
400 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
401 /**
402 * @}
403 */
404
405 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
406 * @{
407 */
408 /**
409 * @brief Convert DMAx_Streamy into DMAx
410 * @param __STREAM_INSTANCE__ DMAx_Streamy
411 * @retval DMAx
412 */
413 #define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \
414 (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1)
415
416 /**
417 * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y
418 * @param __STREAM_INSTANCE__ DMAx_Streamy
419 * @retval LL_DMA_CHANNEL_y
420 */
421 #define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \
422 (((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
423 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
424 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
425 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
426 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
427 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
428 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
429 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
430 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
431 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
432 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
433 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
434 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
435 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
436 LL_DMA_STREAM_7)
437
438 /**
439 * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
440 * @param __DMA_INSTANCE__ DMAx
441 * @param __STREAM__ LL_DMA_STREAM_y
442 * @retval DMAx_Streamy
443 */
444 #define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \
445 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
446 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
447 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
448 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
449 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
450 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
451 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
452 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
453 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
454 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
455 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
456 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
457 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
458 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
459 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
460 DMA2_Stream7)
461
462 /**
463 * @}
464 */
465
466 /**
467 * @}
468 */
469
470
471 /* Exported functions --------------------------------------------------------*/
472 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
473 * @{
474 */
475
476 /** @defgroup DMA_LL_EF_Configuration Configuration
477 * @{
478 */
479 /**
480 * @brief Enable DMA stream.
481 * @rmtoll CR EN LL_DMA_EnableStream
482 * @param DMAx DMAx Instance
483 * @param Stream This parameter can be one of the following values:
484 * @arg @ref LL_DMA_STREAM_0
485 * @arg @ref LL_DMA_STREAM_1
486 * @arg @ref LL_DMA_STREAM_2
487 * @arg @ref LL_DMA_STREAM_3
488 * @arg @ref LL_DMA_STREAM_4
489 * @arg @ref LL_DMA_STREAM_5
490 * @arg @ref LL_DMA_STREAM_6
491 * @arg @ref LL_DMA_STREAM_7
492 * @retval None
493 */
LL_DMA_EnableStream(DMA_TypeDef * DMAx,uint32_t Stream)494 __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
495 {
496 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
497 }
498
499 /**
500 * @brief Disable DMA stream.
501 * @rmtoll CR EN LL_DMA_DisableStream
502 * @param DMAx DMAx Instance
503 * @param Stream This parameter can be one of the following values:
504 * @arg @ref LL_DMA_STREAM_0
505 * @arg @ref LL_DMA_STREAM_1
506 * @arg @ref LL_DMA_STREAM_2
507 * @arg @ref LL_DMA_STREAM_3
508 * @arg @ref LL_DMA_STREAM_4
509 * @arg @ref LL_DMA_STREAM_5
510 * @arg @ref LL_DMA_STREAM_6
511 * @arg @ref LL_DMA_STREAM_7
512 * @retval None
513 */
LL_DMA_DisableStream(DMA_TypeDef * DMAx,uint32_t Stream)514 __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
515 {
516 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
517 }
518
519 /**
520 * @brief Check if DMA stream is enabled or disabled.
521 * @rmtoll CR EN LL_DMA_IsEnabledStream
522 * @param DMAx DMAx Instance
523 * @param Stream This parameter can be one of the following values:
524 * @arg @ref LL_DMA_STREAM_0
525 * @arg @ref LL_DMA_STREAM_1
526 * @arg @ref LL_DMA_STREAM_2
527 * @arg @ref LL_DMA_STREAM_3
528 * @arg @ref LL_DMA_STREAM_4
529 * @arg @ref LL_DMA_STREAM_5
530 * @arg @ref LL_DMA_STREAM_6
531 * @arg @ref LL_DMA_STREAM_7
532 * @retval State of bit (1 or 0).
533 */
LL_DMA_IsEnabledStream(DMA_TypeDef * DMAx,uint32_t Stream)534 __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
535 {
536 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN));
537 }
538
539 /**
540 * @brief Configure all parameters linked to DMA transfer.
541 * @rmtoll CR DIR LL_DMA_ConfigTransfer\n
542 * CR CIRC LL_DMA_ConfigTransfer\n
543 * CR PINC LL_DMA_ConfigTransfer\n
544 * CR MINC LL_DMA_ConfigTransfer\n
545 * CR PSIZE LL_DMA_ConfigTransfer\n
546 * CR MSIZE LL_DMA_ConfigTransfer\n
547 * CR PL LL_DMA_ConfigTransfer\n
548 * CR PFCTRL LL_DMA_ConfigTransfer
549 * @param DMAx DMAx Instance
550 * @param Stream This parameter can be one of the following values:
551 * @arg @ref LL_DMA_STREAM_0
552 * @arg @ref LL_DMA_STREAM_1
553 * @arg @ref LL_DMA_STREAM_2
554 * @arg @ref LL_DMA_STREAM_3
555 * @arg @ref LL_DMA_STREAM_4
556 * @arg @ref LL_DMA_STREAM_5
557 * @arg @ref LL_DMA_STREAM_6
558 * @arg @ref LL_DMA_STREAM_7
559 * @param Configuration This parameter must be a combination of all the following values:
560 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
561 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL
562 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
563 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
564 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
565 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
566 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
567 *@retval None
568 */
LL_DMA_ConfigTransfer(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Configuration)569 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
570 {
571 MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR,
572 DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL,
573 Configuration);
574 }
575
576 /**
577 * @brief Set Data transfer direction (read from peripheral or from memory).
578 * @rmtoll CR DIR LL_DMA_SetDataTransferDirection
579 * @param DMAx DMAx Instance
580 * @param Stream This parameter can be one of the following values:
581 * @arg @ref LL_DMA_STREAM_0
582 * @arg @ref LL_DMA_STREAM_1
583 * @arg @ref LL_DMA_STREAM_2
584 * @arg @ref LL_DMA_STREAM_3
585 * @arg @ref LL_DMA_STREAM_4
586 * @arg @ref LL_DMA_STREAM_5
587 * @arg @ref LL_DMA_STREAM_6
588 * @arg @ref LL_DMA_STREAM_7
589 * @param Direction This parameter can be one of the following values:
590 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
591 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
592 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
593 * @retval None
594 */
LL_DMA_SetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Direction)595 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction)
596 {
597 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction);
598 }
599
600 /**
601 * @brief Get Data transfer direction (read from peripheral or from memory).
602 * @rmtoll CR DIR LL_DMA_GetDataTransferDirection
603 * @param DMAx DMAx Instance
604 * @param Stream This parameter can be one of the following values:
605 * @arg @ref LL_DMA_STREAM_0
606 * @arg @ref LL_DMA_STREAM_1
607 * @arg @ref LL_DMA_STREAM_2
608 * @arg @ref LL_DMA_STREAM_3
609 * @arg @ref LL_DMA_STREAM_4
610 * @arg @ref LL_DMA_STREAM_5
611 * @arg @ref LL_DMA_STREAM_6
612 * @arg @ref LL_DMA_STREAM_7
613 * @retval Returned value can be one of the following values:
614 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
615 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
616 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
617 */
LL_DMA_GetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Stream)618 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
619 {
620 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR));
621 }
622
623 /**
624 * @brief Set DMA mode normal, circular or peripheral flow control.
625 * @rmtoll CR CIRC LL_DMA_SetMode\n
626 * CR PFCTRL LL_DMA_SetMode
627 * @param DMAx DMAx Instance
628 * @param Stream This parameter can be one of the following values:
629 * @arg @ref LL_DMA_STREAM_0
630 * @arg @ref LL_DMA_STREAM_1
631 * @arg @ref LL_DMA_STREAM_2
632 * @arg @ref LL_DMA_STREAM_3
633 * @arg @ref LL_DMA_STREAM_4
634 * @arg @ref LL_DMA_STREAM_5
635 * @arg @ref LL_DMA_STREAM_6
636 * @arg @ref LL_DMA_STREAM_7
637 * @param Mode This parameter can be one of the following values:
638 * @arg @ref LL_DMA_MODE_NORMAL
639 * @arg @ref LL_DMA_MODE_CIRCULAR
640 * @arg @ref LL_DMA_MODE_PFCTRL
641 * @retval None
642 */
LL_DMA_SetMode(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Mode)643 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
644 {
645 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode);
646 }
647
648 /**
649 * @brief Get DMA mode normal, circular or peripheral flow control.
650 * @rmtoll CR CIRC LL_DMA_GetMode\n
651 * CR PFCTRL LL_DMA_GetMode
652 * @param DMAx DMAx Instance
653 * @param Stream This parameter can be one of the following values:
654 * @arg @ref LL_DMA_STREAM_0
655 * @arg @ref LL_DMA_STREAM_1
656 * @arg @ref LL_DMA_STREAM_2
657 * @arg @ref LL_DMA_STREAM_3
658 * @arg @ref LL_DMA_STREAM_4
659 * @arg @ref LL_DMA_STREAM_5
660 * @arg @ref LL_DMA_STREAM_6
661 * @arg @ref LL_DMA_STREAM_7
662 * @retval Returned value can be one of the following values:
663 * @arg @ref LL_DMA_MODE_NORMAL
664 * @arg @ref LL_DMA_MODE_CIRCULAR
665 * @arg @ref LL_DMA_MODE_PFCTRL
666 */
LL_DMA_GetMode(DMA_TypeDef * DMAx,uint32_t Stream)667 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
668 {
669 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL));
670 }
671
672 /**
673 * @brief Set Peripheral increment mode.
674 * @rmtoll CR PINC LL_DMA_SetPeriphIncMode
675 * @param DMAx DMAx Instance
676 * @param Stream This parameter can be one of the following values:
677 * @arg @ref LL_DMA_STREAM_0
678 * @arg @ref LL_DMA_STREAM_1
679 * @arg @ref LL_DMA_STREAM_2
680 * @arg @ref LL_DMA_STREAM_3
681 * @arg @ref LL_DMA_STREAM_4
682 * @arg @ref LL_DMA_STREAM_5
683 * @arg @ref LL_DMA_STREAM_6
684 * @arg @ref LL_DMA_STREAM_7
685 * @param IncrementMode This parameter can be one of the following values:
686 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
687 * @arg @ref LL_DMA_PERIPH_INCREMENT
688 * @retval None
689 */
LL_DMA_SetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t IncrementMode)690 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
691 {
692 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode);
693 }
694
695 /**
696 * @brief Get Peripheral increment mode.
697 * @rmtoll CR PINC LL_DMA_GetPeriphIncMode
698 * @param DMAx DMAx Instance
699 * @param Stream This parameter can be one of the following values:
700 * @arg @ref LL_DMA_STREAM_0
701 * @arg @ref LL_DMA_STREAM_1
702 * @arg @ref LL_DMA_STREAM_2
703 * @arg @ref LL_DMA_STREAM_3
704 * @arg @ref LL_DMA_STREAM_4
705 * @arg @ref LL_DMA_STREAM_5
706 * @arg @ref LL_DMA_STREAM_6
707 * @arg @ref LL_DMA_STREAM_7
708 * @retval Returned value can be one of the following values:
709 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
710 * @arg @ref LL_DMA_PERIPH_INCREMENT
711 */
LL_DMA_GetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Stream)712 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
713 {
714 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC));
715 }
716
717 /**
718 * @brief Set Memory increment mode.
719 * @rmtoll CR MINC LL_DMA_SetMemoryIncMode
720 * @param DMAx DMAx Instance
721 * @param Stream This parameter can be one of the following values:
722 * @arg @ref LL_DMA_STREAM_0
723 * @arg @ref LL_DMA_STREAM_1
724 * @arg @ref LL_DMA_STREAM_2
725 * @arg @ref LL_DMA_STREAM_3
726 * @arg @ref LL_DMA_STREAM_4
727 * @arg @ref LL_DMA_STREAM_5
728 * @arg @ref LL_DMA_STREAM_6
729 * @arg @ref LL_DMA_STREAM_7
730 * @param IncrementMode This parameter can be one of the following values:
731 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
732 * @arg @ref LL_DMA_MEMORY_INCREMENT
733 * @retval None
734 */
LL_DMA_SetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t IncrementMode)735 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
736 {
737 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode);
738 }
739
740 /**
741 * @brief Get Memory increment mode.
742 * @rmtoll CR MINC LL_DMA_GetMemoryIncMode
743 * @param DMAx DMAx Instance
744 * @param Stream This parameter can be one of the following values:
745 * @arg @ref LL_DMA_STREAM_0
746 * @arg @ref LL_DMA_STREAM_1
747 * @arg @ref LL_DMA_STREAM_2
748 * @arg @ref LL_DMA_STREAM_3
749 * @arg @ref LL_DMA_STREAM_4
750 * @arg @ref LL_DMA_STREAM_5
751 * @arg @ref LL_DMA_STREAM_6
752 * @arg @ref LL_DMA_STREAM_7
753 * @retval Returned value can be one of the following values:
754 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
755 * @arg @ref LL_DMA_MEMORY_INCREMENT
756 */
LL_DMA_GetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Stream)757 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
758 {
759 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC));
760 }
761
762 /**
763 * @brief Set Peripheral size.
764 * @rmtoll CR PSIZE LL_DMA_SetPeriphSize
765 * @param DMAx DMAx Instance
766 * @param Stream This parameter can be one of the following values:
767 * @arg @ref LL_DMA_STREAM_0
768 * @arg @ref LL_DMA_STREAM_1
769 * @arg @ref LL_DMA_STREAM_2
770 * @arg @ref LL_DMA_STREAM_3
771 * @arg @ref LL_DMA_STREAM_4
772 * @arg @ref LL_DMA_STREAM_5
773 * @arg @ref LL_DMA_STREAM_6
774 * @arg @ref LL_DMA_STREAM_7
775 * @param Size This parameter can be one of the following values:
776 * @arg @ref LL_DMA_PDATAALIGN_BYTE
777 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
778 * @arg @ref LL_DMA_PDATAALIGN_WORD
779 * @retval None
780 */
LL_DMA_SetPeriphSize(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Size)781 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
782 {
783 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size);
784 }
785
786 /**
787 * @brief Get Peripheral size.
788 * @rmtoll CR PSIZE LL_DMA_GetPeriphSize
789 * @param DMAx DMAx Instance
790 * @param Stream This parameter can be one of the following values:
791 * @arg @ref LL_DMA_STREAM_0
792 * @arg @ref LL_DMA_STREAM_1
793 * @arg @ref LL_DMA_STREAM_2
794 * @arg @ref LL_DMA_STREAM_3
795 * @arg @ref LL_DMA_STREAM_4
796 * @arg @ref LL_DMA_STREAM_5
797 * @arg @ref LL_DMA_STREAM_6
798 * @arg @ref LL_DMA_STREAM_7
799 * @retval Returned value can be one of the following values:
800 * @arg @ref LL_DMA_PDATAALIGN_BYTE
801 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
802 * @arg @ref LL_DMA_PDATAALIGN_WORD
803 */
LL_DMA_GetPeriphSize(DMA_TypeDef * DMAx,uint32_t Stream)804 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
805 {
806 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE));
807 }
808
809 /**
810 * @brief Set Memory size.
811 * @rmtoll CR MSIZE LL_DMA_SetMemorySize
812 * @param DMAx DMAx Instance
813 * @param Stream This parameter can be one of the following values:
814 * @arg @ref LL_DMA_STREAM_0
815 * @arg @ref LL_DMA_STREAM_1
816 * @arg @ref LL_DMA_STREAM_2
817 * @arg @ref LL_DMA_STREAM_3
818 * @arg @ref LL_DMA_STREAM_4
819 * @arg @ref LL_DMA_STREAM_5
820 * @arg @ref LL_DMA_STREAM_6
821 * @arg @ref LL_DMA_STREAM_7
822 * @param Size This parameter can be one of the following values:
823 * @arg @ref LL_DMA_MDATAALIGN_BYTE
824 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
825 * @arg @ref LL_DMA_MDATAALIGN_WORD
826 * @retval None
827 */
LL_DMA_SetMemorySize(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Size)828 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
829 {
830 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size);
831 }
832
833 /**
834 * @brief Get Memory size.
835 * @rmtoll CR MSIZE LL_DMA_GetMemorySize
836 * @param DMAx DMAx Instance
837 * @param Stream This parameter can be one of the following values:
838 * @arg @ref LL_DMA_STREAM_0
839 * @arg @ref LL_DMA_STREAM_1
840 * @arg @ref LL_DMA_STREAM_2
841 * @arg @ref LL_DMA_STREAM_3
842 * @arg @ref LL_DMA_STREAM_4
843 * @arg @ref LL_DMA_STREAM_5
844 * @arg @ref LL_DMA_STREAM_6
845 * @arg @ref LL_DMA_STREAM_7
846 * @retval Returned value can be one of the following values:
847 * @arg @ref LL_DMA_MDATAALIGN_BYTE
848 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
849 * @arg @ref LL_DMA_MDATAALIGN_WORD
850 */
LL_DMA_GetMemorySize(DMA_TypeDef * DMAx,uint32_t Stream)851 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
852 {
853 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE));
854 }
855
856 /**
857 * @brief Set Peripheral increment offset size.
858 * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize
859 * @param DMAx DMAx Instance
860 * @param Stream This parameter can be one of the following values:
861 * @arg @ref LL_DMA_STREAM_0
862 * @arg @ref LL_DMA_STREAM_1
863 * @arg @ref LL_DMA_STREAM_2
864 * @arg @ref LL_DMA_STREAM_3
865 * @arg @ref LL_DMA_STREAM_4
866 * @arg @ref LL_DMA_STREAM_5
867 * @arg @ref LL_DMA_STREAM_6
868 * @arg @ref LL_DMA_STREAM_7
869 * @param OffsetSize This parameter can be one of the following values:
870 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
871 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
872 * @retval None
873 */
LL_DMA_SetIncOffsetSize(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t OffsetSize)874 __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
875 {
876 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize);
877 }
878
879 /**
880 * @brief Get Peripheral increment offset size.
881 * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize
882 * @param DMAx DMAx Instance
883 * @param Stream This parameter can be one of the following values:
884 * @arg @ref LL_DMA_STREAM_0
885 * @arg @ref LL_DMA_STREAM_1
886 * @arg @ref LL_DMA_STREAM_2
887 * @arg @ref LL_DMA_STREAM_3
888 * @arg @ref LL_DMA_STREAM_4
889 * @arg @ref LL_DMA_STREAM_5
890 * @arg @ref LL_DMA_STREAM_6
891 * @arg @ref LL_DMA_STREAM_7
892 * @retval Returned value can be one of the following values:
893 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
894 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
895 */
LL_DMA_GetIncOffsetSize(DMA_TypeDef * DMAx,uint32_t Stream)896 __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
897 {
898 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS));
899 }
900
901 /**
902 * @brief Set Stream priority level.
903 * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel
904 * @param DMAx DMAx Instance
905 * @param Stream This parameter can be one of the following values:
906 * @arg @ref LL_DMA_STREAM_0
907 * @arg @ref LL_DMA_STREAM_1
908 * @arg @ref LL_DMA_STREAM_2
909 * @arg @ref LL_DMA_STREAM_3
910 * @arg @ref LL_DMA_STREAM_4
911 * @arg @ref LL_DMA_STREAM_5
912 * @arg @ref LL_DMA_STREAM_6
913 * @arg @ref LL_DMA_STREAM_7
914 * @param Priority This parameter can be one of the following values:
915 * @arg @ref LL_DMA_PRIORITY_LOW
916 * @arg @ref LL_DMA_PRIORITY_MEDIUM
917 * @arg @ref LL_DMA_PRIORITY_HIGH
918 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
919 * @retval None
920 */
LL_DMA_SetStreamPriorityLevel(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Priority)921 __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority)
922 {
923 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority);
924 }
925
926 /**
927 * @brief Get Stream priority level.
928 * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel
929 * @param DMAx DMAx Instance
930 * @param Stream This parameter can be one of the following values:
931 * @arg @ref LL_DMA_STREAM_0
932 * @arg @ref LL_DMA_STREAM_1
933 * @arg @ref LL_DMA_STREAM_2
934 * @arg @ref LL_DMA_STREAM_3
935 * @arg @ref LL_DMA_STREAM_4
936 * @arg @ref LL_DMA_STREAM_5
937 * @arg @ref LL_DMA_STREAM_6
938 * @arg @ref LL_DMA_STREAM_7
939 * @retval Returned value can be one of the following values:
940 * @arg @ref LL_DMA_PRIORITY_LOW
941 * @arg @ref LL_DMA_PRIORITY_MEDIUM
942 * @arg @ref LL_DMA_PRIORITY_HIGH
943 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
944 */
LL_DMA_GetStreamPriorityLevel(DMA_TypeDef * DMAx,uint32_t Stream)945 __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
946 {
947 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL));
948 }
949
950 /**
951 * @brief Set Number of data to transfer.
952 * @rmtoll NDTR NDT LL_DMA_SetDataLength
953 * @note This action has no effect if
954 * stream is enabled.
955 * @param DMAx DMAx Instance
956 * @param Stream This parameter can be one of the following values:
957 * @arg @ref LL_DMA_STREAM_0
958 * @arg @ref LL_DMA_STREAM_1
959 * @arg @ref LL_DMA_STREAM_2
960 * @arg @ref LL_DMA_STREAM_3
961 * @arg @ref LL_DMA_STREAM_4
962 * @arg @ref LL_DMA_STREAM_5
963 * @arg @ref LL_DMA_STREAM_6
964 * @arg @ref LL_DMA_STREAM_7
965 * @param NbData Between 0 to 0xFFFFFFFF
966 * @retval None
967 */
LL_DMA_SetDataLength(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t NbData)968 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData)
969 {
970 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData);
971 }
972
973 /**
974 * @brief Get Number of data to transfer.
975 * @rmtoll NDTR NDT LL_DMA_GetDataLength
976 * @note Once the stream is enabled, the return value indicate the
977 * remaining bytes to be transmitted.
978 * @param DMAx DMAx Instance
979 * @param Stream This parameter can be one of the following values:
980 * @arg @ref LL_DMA_STREAM_0
981 * @arg @ref LL_DMA_STREAM_1
982 * @arg @ref LL_DMA_STREAM_2
983 * @arg @ref LL_DMA_STREAM_3
984 * @arg @ref LL_DMA_STREAM_4
985 * @arg @ref LL_DMA_STREAM_5
986 * @arg @ref LL_DMA_STREAM_6
987 * @arg @ref LL_DMA_STREAM_7
988 * @retval Between 0 to 0xFFFFFFFF
989 */
LL_DMA_GetDataLength(DMA_TypeDef * DMAx,uint32_t Stream)990 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream)
991 {
992 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT));
993 }
994
995 /**
996 * @brief Select Channel number associated to the Stream.
997 * @rmtoll CR CHSEL LL_DMA_SetChannelSelection
998 * @param DMAx DMAx Instance
999 * @param Stream This parameter can be one of the following values:
1000 * @arg @ref LL_DMA_STREAM_0
1001 * @arg @ref LL_DMA_STREAM_1
1002 * @arg @ref LL_DMA_STREAM_2
1003 * @arg @ref LL_DMA_STREAM_3
1004 * @arg @ref LL_DMA_STREAM_4
1005 * @arg @ref LL_DMA_STREAM_5
1006 * @arg @ref LL_DMA_STREAM_6
1007 * @arg @ref LL_DMA_STREAM_7
1008 * @param Channel This parameter can be one of the following values:
1009 * @arg @ref LL_DMA_CHANNEL_0
1010 * @arg @ref LL_DMA_CHANNEL_1
1011 * @arg @ref LL_DMA_CHANNEL_2
1012 * @arg @ref LL_DMA_CHANNEL_3
1013 * @arg @ref LL_DMA_CHANNEL_4
1014 * @arg @ref LL_DMA_CHANNEL_5
1015 * @arg @ref LL_DMA_CHANNEL_6
1016 * @arg @ref LL_DMA_CHANNEL_7
1017 * @retval None
1018 */
LL_DMA_SetChannelSelection(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Channel)1019 __STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel)
1020 {
1021 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel);
1022 }
1023
1024 /**
1025 * @brief Get the Channel number associated to the Stream.
1026 * @rmtoll CR CHSEL LL_DMA_GetChannelSelection
1027 * @param DMAx DMAx Instance
1028 * @param Stream This parameter can be one of the following values:
1029 * @arg @ref LL_DMA_STREAM_0
1030 * @arg @ref LL_DMA_STREAM_1
1031 * @arg @ref LL_DMA_STREAM_2
1032 * @arg @ref LL_DMA_STREAM_3
1033 * @arg @ref LL_DMA_STREAM_4
1034 * @arg @ref LL_DMA_STREAM_5
1035 * @arg @ref LL_DMA_STREAM_6
1036 * @arg @ref LL_DMA_STREAM_7
1037 * @retval Returned value can be one of the following values:
1038 * @arg @ref LL_DMA_CHANNEL_0
1039 * @arg @ref LL_DMA_CHANNEL_1
1040 * @arg @ref LL_DMA_CHANNEL_2
1041 * @arg @ref LL_DMA_CHANNEL_3
1042 * @arg @ref LL_DMA_CHANNEL_4
1043 * @arg @ref LL_DMA_CHANNEL_5
1044 * @arg @ref LL_DMA_CHANNEL_6
1045 * @arg @ref LL_DMA_CHANNEL_7
1046 */
LL_DMA_GetChannelSelection(DMA_TypeDef * DMAx,uint32_t Stream)1047 __STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream)
1048 {
1049 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL));
1050 }
1051
1052 /**
1053 * @brief Set Memory burst transfer configuration.
1054 * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer
1055 * @param DMAx DMAx Instance
1056 * @param Stream This parameter can be one of the following values:
1057 * @arg @ref LL_DMA_STREAM_0
1058 * @arg @ref LL_DMA_STREAM_1
1059 * @arg @ref LL_DMA_STREAM_2
1060 * @arg @ref LL_DMA_STREAM_3
1061 * @arg @ref LL_DMA_STREAM_4
1062 * @arg @ref LL_DMA_STREAM_5
1063 * @arg @ref LL_DMA_STREAM_6
1064 * @arg @ref LL_DMA_STREAM_7
1065 * @param Mburst This parameter can be one of the following values:
1066 * @arg @ref LL_DMA_MBURST_SINGLE
1067 * @arg @ref LL_DMA_MBURST_INC4
1068 * @arg @ref LL_DMA_MBURST_INC8
1069 * @arg @ref LL_DMA_MBURST_INC16
1070 * @retval None
1071 */
LL_DMA_SetMemoryBurstxfer(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Mburst)1072 __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
1073 {
1074 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst);
1075 }
1076
1077 /**
1078 * @brief Get Memory burst transfer configuration.
1079 * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer
1080 * @param DMAx DMAx Instance
1081 * @param Stream This parameter can be one of the following values:
1082 * @arg @ref LL_DMA_STREAM_0
1083 * @arg @ref LL_DMA_STREAM_1
1084 * @arg @ref LL_DMA_STREAM_2
1085 * @arg @ref LL_DMA_STREAM_3
1086 * @arg @ref LL_DMA_STREAM_4
1087 * @arg @ref LL_DMA_STREAM_5
1088 * @arg @ref LL_DMA_STREAM_6
1089 * @arg @ref LL_DMA_STREAM_7
1090 * @retval Returned value can be one of the following values:
1091 * @arg @ref LL_DMA_MBURST_SINGLE
1092 * @arg @ref LL_DMA_MBURST_INC4
1093 * @arg @ref LL_DMA_MBURST_INC8
1094 * @arg @ref LL_DMA_MBURST_INC16
1095 */
LL_DMA_GetMemoryBurstxfer(DMA_TypeDef * DMAx,uint32_t Stream)1096 __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
1097 {
1098 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST));
1099 }
1100
1101 /**
1102 * @brief Set Peripheral burst transfer configuration.
1103 * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer
1104 * @param DMAx DMAx Instance
1105 * @param Stream This parameter can be one of the following values:
1106 * @arg @ref LL_DMA_STREAM_0
1107 * @arg @ref LL_DMA_STREAM_1
1108 * @arg @ref LL_DMA_STREAM_2
1109 * @arg @ref LL_DMA_STREAM_3
1110 * @arg @ref LL_DMA_STREAM_4
1111 * @arg @ref LL_DMA_STREAM_5
1112 * @arg @ref LL_DMA_STREAM_6
1113 * @arg @ref LL_DMA_STREAM_7
1114 * @param Pburst This parameter can be one of the following values:
1115 * @arg @ref LL_DMA_PBURST_SINGLE
1116 * @arg @ref LL_DMA_PBURST_INC4
1117 * @arg @ref LL_DMA_PBURST_INC8
1118 * @arg @ref LL_DMA_PBURST_INC16
1119 * @retval None
1120 */
LL_DMA_SetPeriphBurstxfer(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Pburst)1121 __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
1122 {
1123 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst);
1124 }
1125
1126 /**
1127 * @brief Get Peripheral burst transfer configuration.
1128 * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer
1129 * @param DMAx DMAx Instance
1130 * @param Stream This parameter can be one of the following values:
1131 * @arg @ref LL_DMA_STREAM_0
1132 * @arg @ref LL_DMA_STREAM_1
1133 * @arg @ref LL_DMA_STREAM_2
1134 * @arg @ref LL_DMA_STREAM_3
1135 * @arg @ref LL_DMA_STREAM_4
1136 * @arg @ref LL_DMA_STREAM_5
1137 * @arg @ref LL_DMA_STREAM_6
1138 * @arg @ref LL_DMA_STREAM_7
1139 * @retval Returned value can be one of the following values:
1140 * @arg @ref LL_DMA_PBURST_SINGLE
1141 * @arg @ref LL_DMA_PBURST_INC4
1142 * @arg @ref LL_DMA_PBURST_INC8
1143 * @arg @ref LL_DMA_PBURST_INC16
1144 */
LL_DMA_GetPeriphBurstxfer(DMA_TypeDef * DMAx,uint32_t Stream)1145 __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
1146 {
1147 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST));
1148 }
1149
1150 /**
1151 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1152 * @rmtoll CR CT LL_DMA_SetCurrentTargetMem
1153 * @param DMAx DMAx Instance
1154 * @param Stream This parameter can be one of the following values:
1155 * @arg @ref LL_DMA_STREAM_0
1156 * @arg @ref LL_DMA_STREAM_1
1157 * @arg @ref LL_DMA_STREAM_2
1158 * @arg @ref LL_DMA_STREAM_3
1159 * @arg @ref LL_DMA_STREAM_4
1160 * @arg @ref LL_DMA_STREAM_5
1161 * @arg @ref LL_DMA_STREAM_6
1162 * @arg @ref LL_DMA_STREAM_7
1163 * @param CurrentMemory This parameter can be one of the following values:
1164 * @arg @ref LL_DMA_CURRENTTARGETMEM0
1165 * @arg @ref LL_DMA_CURRENTTARGETMEM1
1166 * @retval None
1167 */
LL_DMA_SetCurrentTargetMem(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t CurrentMemory)1168 __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
1169 {
1170 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory);
1171 }
1172
1173 /**
1174 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1175 * @rmtoll CR CT LL_DMA_GetCurrentTargetMem
1176 * @param DMAx DMAx Instance
1177 * @param Stream This parameter can be one of the following values:
1178 * @arg @ref LL_DMA_STREAM_0
1179 * @arg @ref LL_DMA_STREAM_1
1180 * @arg @ref LL_DMA_STREAM_2
1181 * @arg @ref LL_DMA_STREAM_3
1182 * @arg @ref LL_DMA_STREAM_4
1183 * @arg @ref LL_DMA_STREAM_5
1184 * @arg @ref LL_DMA_STREAM_6
1185 * @arg @ref LL_DMA_STREAM_7
1186 * @retval Returned value can be one of the following values:
1187 * @arg @ref LL_DMA_CURRENTTARGETMEM0
1188 * @arg @ref LL_DMA_CURRENTTARGETMEM1
1189 */
LL_DMA_GetCurrentTargetMem(DMA_TypeDef * DMAx,uint32_t Stream)1190 __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
1191 {
1192 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT));
1193 }
1194
1195 /**
1196 * @brief Enable the double buffer mode.
1197 * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode
1198 * @param DMAx DMAx Instance
1199 * @param Stream This parameter can be one of the following values:
1200 * @arg @ref LL_DMA_STREAM_0
1201 * @arg @ref LL_DMA_STREAM_1
1202 * @arg @ref LL_DMA_STREAM_2
1203 * @arg @ref LL_DMA_STREAM_3
1204 * @arg @ref LL_DMA_STREAM_4
1205 * @arg @ref LL_DMA_STREAM_5
1206 * @arg @ref LL_DMA_STREAM_6
1207 * @arg @ref LL_DMA_STREAM_7
1208 * @retval None
1209 */
LL_DMA_EnableDoubleBufferMode(DMA_TypeDef * DMAx,uint32_t Stream)1210 __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
1211 {
1212 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
1213 }
1214
1215 /**
1216 * @brief Disable the double buffer mode.
1217 * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode
1218 * @param DMAx DMAx Instance
1219 * @param Stream This parameter can be one of the following values:
1220 * @arg @ref LL_DMA_STREAM_0
1221 * @arg @ref LL_DMA_STREAM_1
1222 * @arg @ref LL_DMA_STREAM_2
1223 * @arg @ref LL_DMA_STREAM_3
1224 * @arg @ref LL_DMA_STREAM_4
1225 * @arg @ref LL_DMA_STREAM_5
1226 * @arg @ref LL_DMA_STREAM_6
1227 * @arg @ref LL_DMA_STREAM_7
1228 * @retval None
1229 */
LL_DMA_DisableDoubleBufferMode(DMA_TypeDef * DMAx,uint32_t Stream)1230 __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
1231 {
1232 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
1233 }
1234
1235 /**
1236 * @brief Get FIFO status.
1237 * @rmtoll FCR FS LL_DMA_GetFIFOStatus
1238 * @param DMAx DMAx Instance
1239 * @param Stream This parameter can be one of the following values:
1240 * @arg @ref LL_DMA_STREAM_0
1241 * @arg @ref LL_DMA_STREAM_1
1242 * @arg @ref LL_DMA_STREAM_2
1243 * @arg @ref LL_DMA_STREAM_3
1244 * @arg @ref LL_DMA_STREAM_4
1245 * @arg @ref LL_DMA_STREAM_5
1246 * @arg @ref LL_DMA_STREAM_6
1247 * @arg @ref LL_DMA_STREAM_7
1248 * @retval Returned value can be one of the following values:
1249 * @arg @ref LL_DMA_FIFOSTATUS_0_25
1250 * @arg @ref LL_DMA_FIFOSTATUS_25_50
1251 * @arg @ref LL_DMA_FIFOSTATUS_50_75
1252 * @arg @ref LL_DMA_FIFOSTATUS_75_100
1253 * @arg @ref LL_DMA_FIFOSTATUS_EMPTY
1254 * @arg @ref LL_DMA_FIFOSTATUS_FULL
1255 */
LL_DMA_GetFIFOStatus(DMA_TypeDef * DMAx,uint32_t Stream)1256 __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
1257 {
1258 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS));
1259 }
1260
1261 /**
1262 * @brief Disable Fifo mode.
1263 * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode
1264 * @param DMAx DMAx Instance
1265 * @param Stream This parameter can be one of the following values:
1266 * @arg @ref LL_DMA_STREAM_0
1267 * @arg @ref LL_DMA_STREAM_1
1268 * @arg @ref LL_DMA_STREAM_2
1269 * @arg @ref LL_DMA_STREAM_3
1270 * @arg @ref LL_DMA_STREAM_4
1271 * @arg @ref LL_DMA_STREAM_5
1272 * @arg @ref LL_DMA_STREAM_6
1273 * @arg @ref LL_DMA_STREAM_7
1274 * @retval None
1275 */
LL_DMA_DisableFifoMode(DMA_TypeDef * DMAx,uint32_t Stream)1276 __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
1277 {
1278 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
1279 }
1280
1281 /**
1282 * @brief Enable Fifo mode.
1283 * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode
1284 * @param DMAx DMAx Instance
1285 * @param Stream This parameter can be one of the following values:
1286 * @arg @ref LL_DMA_STREAM_0
1287 * @arg @ref LL_DMA_STREAM_1
1288 * @arg @ref LL_DMA_STREAM_2
1289 * @arg @ref LL_DMA_STREAM_3
1290 * @arg @ref LL_DMA_STREAM_4
1291 * @arg @ref LL_DMA_STREAM_5
1292 * @arg @ref LL_DMA_STREAM_6
1293 * @arg @ref LL_DMA_STREAM_7
1294 * @retval None
1295 */
LL_DMA_EnableFifoMode(DMA_TypeDef * DMAx,uint32_t Stream)1296 __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
1297 {
1298 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
1299 }
1300
1301 /**
1302 * @brief Select FIFO threshold.
1303 * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold
1304 * @param DMAx DMAx Instance
1305 * @param Stream This parameter can be one of the following values:
1306 * @arg @ref LL_DMA_STREAM_0
1307 * @arg @ref LL_DMA_STREAM_1
1308 * @arg @ref LL_DMA_STREAM_2
1309 * @arg @ref LL_DMA_STREAM_3
1310 * @arg @ref LL_DMA_STREAM_4
1311 * @arg @ref LL_DMA_STREAM_5
1312 * @arg @ref LL_DMA_STREAM_6
1313 * @arg @ref LL_DMA_STREAM_7
1314 * @param Threshold This parameter can be one of the following values:
1315 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1316 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1317 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1318 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1319 * @retval None
1320 */
LL_DMA_SetFIFOThreshold(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Threshold)1321 __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
1322 {
1323 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold);
1324 }
1325
1326 /**
1327 * @brief Get FIFO threshold.
1328 * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold
1329 * @param DMAx DMAx Instance
1330 * @param Stream This parameter can be one of the following values:
1331 * @arg @ref LL_DMA_STREAM_0
1332 * @arg @ref LL_DMA_STREAM_1
1333 * @arg @ref LL_DMA_STREAM_2
1334 * @arg @ref LL_DMA_STREAM_3
1335 * @arg @ref LL_DMA_STREAM_4
1336 * @arg @ref LL_DMA_STREAM_5
1337 * @arg @ref LL_DMA_STREAM_6
1338 * @arg @ref LL_DMA_STREAM_7
1339 * @retval Returned value can be one of the following values:
1340 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1341 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1342 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1343 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1344 */
LL_DMA_GetFIFOThreshold(DMA_TypeDef * DMAx,uint32_t Stream)1345 __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
1346 {
1347 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH));
1348 }
1349
1350 /**
1351 * @brief Configure the FIFO .
1352 * @rmtoll FCR FTH LL_DMA_ConfigFifo\n
1353 * FCR DMDIS LL_DMA_ConfigFifo
1354 * @param DMAx DMAx Instance
1355 * @param Stream This parameter can be one of the following values:
1356 * @arg @ref LL_DMA_STREAM_0
1357 * @arg @ref LL_DMA_STREAM_1
1358 * @arg @ref LL_DMA_STREAM_2
1359 * @arg @ref LL_DMA_STREAM_3
1360 * @arg @ref LL_DMA_STREAM_4
1361 * @arg @ref LL_DMA_STREAM_5
1362 * @arg @ref LL_DMA_STREAM_6
1363 * @arg @ref LL_DMA_STREAM_7
1364 * @param FifoMode This parameter can be one of the following values:
1365 * @arg @ref LL_DMA_FIFOMODE_ENABLE
1366 * @arg @ref LL_DMA_FIFOMODE_DISABLE
1367 * @param FifoThreshold This parameter can be one of the following values:
1368 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1369 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1370 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1371 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1372 * @retval None
1373 */
LL_DMA_ConfigFifo(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t FifoMode,uint32_t FifoThreshold)1374 __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
1375 {
1376 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH|DMA_SxFCR_DMDIS, FifoMode|FifoThreshold);
1377 }
1378
1379 /**
1380 * @brief Configure the Source and Destination addresses.
1381 * @note This API must not be called when the DMA stream is enabled.
1382 * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n
1383 * PAR PA LL_DMA_ConfigAddresses
1384 * @param DMAx DMAx Instance
1385 * @param Stream This parameter can be one of the following values:
1386 * @arg @ref LL_DMA_STREAM_0
1387 * @arg @ref LL_DMA_STREAM_1
1388 * @arg @ref LL_DMA_STREAM_2
1389 * @arg @ref LL_DMA_STREAM_3
1390 * @arg @ref LL_DMA_STREAM_4
1391 * @arg @ref LL_DMA_STREAM_5
1392 * @arg @ref LL_DMA_STREAM_6
1393 * @arg @ref LL_DMA_STREAM_7
1394 * @param SrcAddress Between 0 to 0xFFFFFFFF
1395 * @param DstAddress Between 0 to 0xFFFFFFFF
1396 * @param Direction This parameter can be one of the following values:
1397 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
1398 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
1399 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
1400 * @retval None
1401 */
LL_DMA_ConfigAddresses(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t SrcAddress,uint32_t DstAddress,uint32_t Direction)1402 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
1403 {
1404 /* Direction Memory to Periph */
1405 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
1406 {
1407 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress);
1408 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress);
1409 }
1410 /* Direction Periph to Memory and Memory to Memory */
1411 else
1412 {
1413 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress);
1414 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress);
1415 }
1416 }
1417
1418 /**
1419 * @brief Set the Memory address.
1420 * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress
1421 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1422 * @note This API must not be called when the DMA channel is enabled.
1423 * @param DMAx DMAx Instance
1424 * @param Stream This parameter can be one of the following values:
1425 * @arg @ref LL_DMA_STREAM_0
1426 * @arg @ref LL_DMA_STREAM_1
1427 * @arg @ref LL_DMA_STREAM_2
1428 * @arg @ref LL_DMA_STREAM_3
1429 * @arg @ref LL_DMA_STREAM_4
1430 * @arg @ref LL_DMA_STREAM_5
1431 * @arg @ref LL_DMA_STREAM_6
1432 * @arg @ref LL_DMA_STREAM_7
1433 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1434 * @retval None
1435 */
LL_DMA_SetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t MemoryAddress)1436 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
1437 {
1438 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
1439 }
1440
1441 /**
1442 * @brief Set the Peripheral address.
1443 * @rmtoll PAR PA LL_DMA_SetPeriphAddress
1444 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1445 * @note This API must not be called when the DMA channel is enabled.
1446 * @param DMAx DMAx Instance
1447 * @param Stream This parameter can be one of the following values:
1448 * @arg @ref LL_DMA_STREAM_0
1449 * @arg @ref LL_DMA_STREAM_1
1450 * @arg @ref LL_DMA_STREAM_2
1451 * @arg @ref LL_DMA_STREAM_3
1452 * @arg @ref LL_DMA_STREAM_4
1453 * @arg @ref LL_DMA_STREAM_5
1454 * @arg @ref LL_DMA_STREAM_6
1455 * @arg @ref LL_DMA_STREAM_7
1456 * @param PeriphAddress Between 0 to 0xFFFFFFFF
1457 * @retval None
1458 */
LL_DMA_SetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t PeriphAddress)1459 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress)
1460 {
1461 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress);
1462 }
1463
1464 /**
1465 * @brief Get the Memory address.
1466 * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress
1467 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1468 * @param DMAx DMAx Instance
1469 * @param Stream This parameter can be one of the following values:
1470 * @arg @ref LL_DMA_STREAM_0
1471 * @arg @ref LL_DMA_STREAM_1
1472 * @arg @ref LL_DMA_STREAM_2
1473 * @arg @ref LL_DMA_STREAM_3
1474 * @arg @ref LL_DMA_STREAM_4
1475 * @arg @ref LL_DMA_STREAM_5
1476 * @arg @ref LL_DMA_STREAM_6
1477 * @arg @ref LL_DMA_STREAM_7
1478 * @retval Between 0 to 0xFFFFFFFF
1479 */
LL_DMA_GetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Stream)1480 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1481 {
1482 return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
1483 }
1484
1485 /**
1486 * @brief Get the Peripheral address.
1487 * @rmtoll PAR PA LL_DMA_GetPeriphAddress
1488 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1489 * @param DMAx DMAx Instance
1490 * @param Stream This parameter can be one of the following values:
1491 * @arg @ref LL_DMA_STREAM_0
1492 * @arg @ref LL_DMA_STREAM_1
1493 * @arg @ref LL_DMA_STREAM_2
1494 * @arg @ref LL_DMA_STREAM_3
1495 * @arg @ref LL_DMA_STREAM_4
1496 * @arg @ref LL_DMA_STREAM_5
1497 * @arg @ref LL_DMA_STREAM_6
1498 * @arg @ref LL_DMA_STREAM_7
1499 * @retval Between 0 to 0xFFFFFFFF
1500 */
LL_DMA_GetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Stream)1501 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1502 {
1503 return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
1504 }
1505
1506 /**
1507 * @brief Set the Memory to Memory Source address.
1508 * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress
1509 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1510 * @note This API must not be called when the DMA channel is enabled.
1511 * @param DMAx DMAx Instance
1512 * @param Stream This parameter can be one of the following values:
1513 * @arg @ref LL_DMA_STREAM_0
1514 * @arg @ref LL_DMA_STREAM_1
1515 * @arg @ref LL_DMA_STREAM_2
1516 * @arg @ref LL_DMA_STREAM_3
1517 * @arg @ref LL_DMA_STREAM_4
1518 * @arg @ref LL_DMA_STREAM_5
1519 * @arg @ref LL_DMA_STREAM_6
1520 * @arg @ref LL_DMA_STREAM_7
1521 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1522 * @retval None
1523 */
LL_DMA_SetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t MemoryAddress)1524 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
1525 {
1526 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress);
1527 }
1528
1529 /**
1530 * @brief Set the Memory to Memory Destination address.
1531 * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress
1532 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1533 * @note This API must not be called when the DMA channel is enabled.
1534 * @param DMAx DMAx Instance
1535 * @param Stream This parameter can be one of the following values:
1536 * @arg @ref LL_DMA_STREAM_0
1537 * @arg @ref LL_DMA_STREAM_1
1538 * @arg @ref LL_DMA_STREAM_2
1539 * @arg @ref LL_DMA_STREAM_3
1540 * @arg @ref LL_DMA_STREAM_4
1541 * @arg @ref LL_DMA_STREAM_5
1542 * @arg @ref LL_DMA_STREAM_6
1543 * @arg @ref LL_DMA_STREAM_7
1544 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1545 * @retval None
1546 */
LL_DMA_SetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t MemoryAddress)1547 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
1548 {
1549 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
1550 }
1551
1552 /**
1553 * @brief Get the Memory to Memory Source address.
1554 * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress
1555 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1556 * @param DMAx DMAx Instance
1557 * @param Stream This parameter can be one of the following values:
1558 * @arg @ref LL_DMA_STREAM_0
1559 * @arg @ref LL_DMA_STREAM_1
1560 * @arg @ref LL_DMA_STREAM_2
1561 * @arg @ref LL_DMA_STREAM_3
1562 * @arg @ref LL_DMA_STREAM_4
1563 * @arg @ref LL_DMA_STREAM_5
1564 * @arg @ref LL_DMA_STREAM_6
1565 * @arg @ref LL_DMA_STREAM_7
1566 * @retval Between 0 to 0xFFFFFFFF
1567 */
LL_DMA_GetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Stream)1568 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1569 {
1570 return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
1571 }
1572
1573 /**
1574 * @brief Get the Memory to Memory Destination address.
1575 * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress
1576 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1577 * @param DMAx DMAx Instance
1578 * @param Stream This parameter can be one of the following values:
1579 * @arg @ref LL_DMA_STREAM_0
1580 * @arg @ref LL_DMA_STREAM_1
1581 * @arg @ref LL_DMA_STREAM_2
1582 * @arg @ref LL_DMA_STREAM_3
1583 * @arg @ref LL_DMA_STREAM_4
1584 * @arg @ref LL_DMA_STREAM_5
1585 * @arg @ref LL_DMA_STREAM_6
1586 * @arg @ref LL_DMA_STREAM_7
1587 * @retval Between 0 to 0xFFFFFFFF
1588 */
LL_DMA_GetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Stream)1589 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1590 {
1591 return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
1592 }
1593
1594 /**
1595 * @brief Set Memory 1 address (used in case of Double buffer mode).
1596 * @rmtoll M1AR M1A LL_DMA_SetMemory1Address
1597 * @param DMAx DMAx Instance
1598 * @param Stream This parameter can be one of the following values:
1599 * @arg @ref LL_DMA_STREAM_0
1600 * @arg @ref LL_DMA_STREAM_1
1601 * @arg @ref LL_DMA_STREAM_2
1602 * @arg @ref LL_DMA_STREAM_3
1603 * @arg @ref LL_DMA_STREAM_4
1604 * @arg @ref LL_DMA_STREAM_5
1605 * @arg @ref LL_DMA_STREAM_6
1606 * @arg @ref LL_DMA_STREAM_7
1607 * @param Address Between 0 to 0xFFFFFFFF
1608 * @retval None
1609 */
LL_DMA_SetMemory1Address(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Address)1610 __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
1611 {
1612 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, DMA_SxM1AR_M1A, Address);
1613 }
1614
1615 /**
1616 * @brief Get Memory 1 address (used in case of Double buffer mode).
1617 * @rmtoll M1AR M1A LL_DMA_GetMemory1Address
1618 * @param DMAx DMAx Instance
1619 * @param Stream This parameter can be one of the following values:
1620 * @arg @ref LL_DMA_STREAM_0
1621 * @arg @ref LL_DMA_STREAM_1
1622 * @arg @ref LL_DMA_STREAM_2
1623 * @arg @ref LL_DMA_STREAM_3
1624 * @arg @ref LL_DMA_STREAM_4
1625 * @arg @ref LL_DMA_STREAM_5
1626 * @arg @ref LL_DMA_STREAM_6
1627 * @arg @ref LL_DMA_STREAM_7
1628 * @retval Between 0 to 0xFFFFFFFF
1629 */
LL_DMA_GetMemory1Address(DMA_TypeDef * DMAx,uint32_t Stream)1630 __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
1631 {
1632 return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR);
1633 }
1634
1635 /**
1636 * @}
1637 */
1638
1639 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1640 * @{
1641 */
1642
1643 /**
1644 * @brief Get Stream 0 half transfer flag.
1645 * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0
1646 * @param DMAx DMAx Instance
1647 * @retval State of bit (1 or 0).
1648 */
LL_DMA_IsActiveFlag_HT0(DMA_TypeDef * DMAx)1649 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
1650 {
1651 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0));
1652 }
1653
1654 /**
1655 * @brief Get Stream 1 half transfer flag.
1656 * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1
1657 * @param DMAx DMAx Instance
1658 * @retval State of bit (1 or 0).
1659 */
LL_DMA_IsActiveFlag_HT1(DMA_TypeDef * DMAx)1660 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
1661 {
1662 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1));
1663 }
1664
1665 /**
1666 * @brief Get Stream 2 half transfer flag.
1667 * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2
1668 * @param DMAx DMAx Instance
1669 * @retval State of bit (1 or 0).
1670 */
LL_DMA_IsActiveFlag_HT2(DMA_TypeDef * DMAx)1671 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
1672 {
1673 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2));
1674 }
1675
1676 /**
1677 * @brief Get Stream 3 half transfer flag.
1678 * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3
1679 * @param DMAx DMAx Instance
1680 * @retval State of bit (1 or 0).
1681 */
LL_DMA_IsActiveFlag_HT3(DMA_TypeDef * DMAx)1682 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
1683 {
1684 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3));
1685 }
1686
1687 /**
1688 * @brief Get Stream 4 half transfer flag.
1689 * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4
1690 * @param DMAx DMAx Instance
1691 * @retval State of bit (1 or 0).
1692 */
LL_DMA_IsActiveFlag_HT4(DMA_TypeDef * DMAx)1693 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
1694 {
1695 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4));
1696 }
1697
1698 /**
1699 * @brief Get Stream 5 half transfer flag.
1700 * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5
1701 * @param DMAx DMAx Instance
1702 * @retval State of bit (1 or 0).
1703 */
LL_DMA_IsActiveFlag_HT5(DMA_TypeDef * DMAx)1704 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
1705 {
1706 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5));
1707 }
1708
1709 /**
1710 * @brief Get Stream 6 half transfer flag.
1711 * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6
1712 * @param DMAx DMAx Instance
1713 * @retval State of bit (1 or 0).
1714 */
LL_DMA_IsActiveFlag_HT6(DMA_TypeDef * DMAx)1715 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
1716 {
1717 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6));
1718 }
1719
1720 /**
1721 * @brief Get Stream 7 half transfer flag.
1722 * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7
1723 * @param DMAx DMAx Instance
1724 * @retval State of bit (1 or 0).
1725 */
LL_DMA_IsActiveFlag_HT7(DMA_TypeDef * DMAx)1726 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
1727 {
1728 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7));
1729 }
1730
1731 /**
1732 * @brief Get Stream 0 transfer complete flag.
1733 * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0
1734 * @param DMAx DMAx Instance
1735 * @retval State of bit (1 or 0).
1736 */
LL_DMA_IsActiveFlag_TC0(DMA_TypeDef * DMAx)1737 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
1738 {
1739 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0));
1740 }
1741
1742 /**
1743 * @brief Get Stream 1 transfer complete flag.
1744 * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1
1745 * @param DMAx DMAx Instance
1746 * @retval State of bit (1 or 0).
1747 */
LL_DMA_IsActiveFlag_TC1(DMA_TypeDef * DMAx)1748 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
1749 {
1750 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1));
1751 }
1752
1753 /**
1754 * @brief Get Stream 2 transfer complete flag.
1755 * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2
1756 * @param DMAx DMAx Instance
1757 * @retval State of bit (1 or 0).
1758 */
LL_DMA_IsActiveFlag_TC2(DMA_TypeDef * DMAx)1759 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
1760 {
1761 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2));
1762 }
1763
1764 /**
1765 * @brief Get Stream 3 transfer complete flag.
1766 * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3
1767 * @param DMAx DMAx Instance
1768 * @retval State of bit (1 or 0).
1769 */
LL_DMA_IsActiveFlag_TC3(DMA_TypeDef * DMAx)1770 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
1771 {
1772 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3));
1773 }
1774
1775 /**
1776 * @brief Get Stream 4 transfer complete flag.
1777 * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4
1778 * @param DMAx DMAx Instance
1779 * @retval State of bit (1 or 0).
1780 */
LL_DMA_IsActiveFlag_TC4(DMA_TypeDef * DMAx)1781 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
1782 {
1783 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4));
1784 }
1785
1786 /**
1787 * @brief Get Stream 5 transfer complete flag.
1788 * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5
1789 * @param DMAx DMAx Instance
1790 * @retval State of bit (1 or 0).
1791 */
LL_DMA_IsActiveFlag_TC5(DMA_TypeDef * DMAx)1792 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
1793 {
1794 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5));
1795 }
1796
1797 /**
1798 * @brief Get Stream 6 transfer complete flag.
1799 * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6
1800 * @param DMAx DMAx Instance
1801 * @retval State of bit (1 or 0).
1802 */
LL_DMA_IsActiveFlag_TC6(DMA_TypeDef * DMAx)1803 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
1804 {
1805 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6));
1806 }
1807
1808 /**
1809 * @brief Get Stream 7 transfer complete flag.
1810 * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7
1811 * @param DMAx DMAx Instance
1812 * @retval State of bit (1 or 0).
1813 */
LL_DMA_IsActiveFlag_TC7(DMA_TypeDef * DMAx)1814 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
1815 {
1816 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7));
1817 }
1818
1819 /**
1820 * @brief Get Stream 0 transfer error flag.
1821 * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0
1822 * @param DMAx DMAx Instance
1823 * @retval State of bit (1 or 0).
1824 */
LL_DMA_IsActiveFlag_TE0(DMA_TypeDef * DMAx)1825 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
1826 {
1827 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0));
1828 }
1829
1830 /**
1831 * @brief Get Stream 1 transfer error flag.
1832 * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1
1833 * @param DMAx DMAx Instance
1834 * @retval State of bit (1 or 0).
1835 */
LL_DMA_IsActiveFlag_TE1(DMA_TypeDef * DMAx)1836 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
1837 {
1838 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1));
1839 }
1840
1841 /**
1842 * @brief Get Stream 2 transfer error flag.
1843 * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2
1844 * @param DMAx DMAx Instance
1845 * @retval State of bit (1 or 0).
1846 */
LL_DMA_IsActiveFlag_TE2(DMA_TypeDef * DMAx)1847 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
1848 {
1849 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2));
1850 }
1851
1852 /**
1853 * @brief Get Stream 3 transfer error flag.
1854 * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3
1855 * @param DMAx DMAx Instance
1856 * @retval State of bit (1 or 0).
1857 */
LL_DMA_IsActiveFlag_TE3(DMA_TypeDef * DMAx)1858 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
1859 {
1860 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3));
1861 }
1862
1863 /**
1864 * @brief Get Stream 4 transfer error flag.
1865 * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4
1866 * @param DMAx DMAx Instance
1867 * @retval State of bit (1 or 0).
1868 */
LL_DMA_IsActiveFlag_TE4(DMA_TypeDef * DMAx)1869 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
1870 {
1871 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4));
1872 }
1873
1874 /**
1875 * @brief Get Stream 5 transfer error flag.
1876 * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5
1877 * @param DMAx DMAx Instance
1878 * @retval State of bit (1 or 0).
1879 */
LL_DMA_IsActiveFlag_TE5(DMA_TypeDef * DMAx)1880 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
1881 {
1882 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5));
1883 }
1884
1885 /**
1886 * @brief Get Stream 6 transfer error flag.
1887 * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6
1888 * @param DMAx DMAx Instance
1889 * @retval State of bit (1 or 0).
1890 */
LL_DMA_IsActiveFlag_TE6(DMA_TypeDef * DMAx)1891 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
1892 {
1893 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6));
1894 }
1895
1896 /**
1897 * @brief Get Stream 7 transfer error flag.
1898 * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7
1899 * @param DMAx DMAx Instance
1900 * @retval State of bit (1 or 0).
1901 */
LL_DMA_IsActiveFlag_TE7(DMA_TypeDef * DMAx)1902 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
1903 {
1904 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7));
1905 }
1906
1907 /**
1908 * @brief Get Stream 0 direct mode error flag.
1909 * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0
1910 * @param DMAx DMAx Instance
1911 * @retval State of bit (1 or 0).
1912 */
LL_DMA_IsActiveFlag_DME0(DMA_TypeDef * DMAx)1913 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
1914 {
1915 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0));
1916 }
1917
1918 /**
1919 * @brief Get Stream 1 direct mode error flag.
1920 * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1
1921 * @param DMAx DMAx Instance
1922 * @retval State of bit (1 or 0).
1923 */
LL_DMA_IsActiveFlag_DME1(DMA_TypeDef * DMAx)1924 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
1925 {
1926 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1));
1927 }
1928
1929 /**
1930 * @brief Get Stream 2 direct mode error flag.
1931 * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2
1932 * @param DMAx DMAx Instance
1933 * @retval State of bit (1 or 0).
1934 */
LL_DMA_IsActiveFlag_DME2(DMA_TypeDef * DMAx)1935 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
1936 {
1937 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2));
1938 }
1939
1940 /**
1941 * @brief Get Stream 3 direct mode error flag.
1942 * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3
1943 * @param DMAx DMAx Instance
1944 * @retval State of bit (1 or 0).
1945 */
LL_DMA_IsActiveFlag_DME3(DMA_TypeDef * DMAx)1946 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
1947 {
1948 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3));
1949 }
1950
1951 /**
1952 * @brief Get Stream 4 direct mode error flag.
1953 * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4
1954 * @param DMAx DMAx Instance
1955 * @retval State of bit (1 or 0).
1956 */
LL_DMA_IsActiveFlag_DME4(DMA_TypeDef * DMAx)1957 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
1958 {
1959 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4));
1960 }
1961
1962 /**
1963 * @brief Get Stream 5 direct mode error flag.
1964 * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5
1965 * @param DMAx DMAx Instance
1966 * @retval State of bit (1 or 0).
1967 */
LL_DMA_IsActiveFlag_DME5(DMA_TypeDef * DMAx)1968 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
1969 {
1970 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5));
1971 }
1972
1973 /**
1974 * @brief Get Stream 6 direct mode error flag.
1975 * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6
1976 * @param DMAx DMAx Instance
1977 * @retval State of bit (1 or 0).
1978 */
LL_DMA_IsActiveFlag_DME6(DMA_TypeDef * DMAx)1979 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
1980 {
1981 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6));
1982 }
1983
1984 /**
1985 * @brief Get Stream 7 direct mode error flag.
1986 * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7
1987 * @param DMAx DMAx Instance
1988 * @retval State of bit (1 or 0).
1989 */
LL_DMA_IsActiveFlag_DME7(DMA_TypeDef * DMAx)1990 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
1991 {
1992 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7));
1993 }
1994
1995 /**
1996 * @brief Get Stream 0 FIFO error flag.
1997 * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0
1998 * @param DMAx DMAx Instance
1999 * @retval State of bit (1 or 0).
2000 */
LL_DMA_IsActiveFlag_FE0(DMA_TypeDef * DMAx)2001 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
2002 {
2003 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0));
2004 }
2005
2006 /**
2007 * @brief Get Stream 1 FIFO error flag.
2008 * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1
2009 * @param DMAx DMAx Instance
2010 * @retval State of bit (1 or 0).
2011 */
LL_DMA_IsActiveFlag_FE1(DMA_TypeDef * DMAx)2012 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
2013 {
2014 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1));
2015 }
2016
2017 /**
2018 * @brief Get Stream 2 FIFO error flag.
2019 * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2
2020 * @param DMAx DMAx Instance
2021 * @retval State of bit (1 or 0).
2022 */
LL_DMA_IsActiveFlag_FE2(DMA_TypeDef * DMAx)2023 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
2024 {
2025 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2));
2026 }
2027
2028 /**
2029 * @brief Get Stream 3 FIFO error flag.
2030 * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3
2031 * @param DMAx DMAx Instance
2032 * @retval State of bit (1 or 0).
2033 */
LL_DMA_IsActiveFlag_FE3(DMA_TypeDef * DMAx)2034 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
2035 {
2036 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3));
2037 }
2038
2039 /**
2040 * @brief Get Stream 4 FIFO error flag.
2041 * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4
2042 * @param DMAx DMAx Instance
2043 * @retval State of bit (1 or 0).
2044 */
LL_DMA_IsActiveFlag_FE4(DMA_TypeDef * DMAx)2045 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
2046 {
2047 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4));
2048 }
2049
2050 /**
2051 * @brief Get Stream 5 FIFO error flag.
2052 * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5
2053 * @param DMAx DMAx Instance
2054 * @retval State of bit (1 or 0).
2055 */
LL_DMA_IsActiveFlag_FE5(DMA_TypeDef * DMAx)2056 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
2057 {
2058 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5));
2059 }
2060
2061 /**
2062 * @brief Get Stream 6 FIFO error flag.
2063 * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6
2064 * @param DMAx DMAx Instance
2065 * @retval State of bit (1 or 0).
2066 */
LL_DMA_IsActiveFlag_FE6(DMA_TypeDef * DMAx)2067 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
2068 {
2069 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6));
2070 }
2071
2072 /**
2073 * @brief Get Stream 7 FIFO error flag.
2074 * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7
2075 * @param DMAx DMAx Instance
2076 * @retval State of bit (1 or 0).
2077 */
LL_DMA_IsActiveFlag_FE7(DMA_TypeDef * DMAx)2078 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
2079 {
2080 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7));
2081 }
2082
2083 /**
2084 * @brief Clear Stream 0 half transfer flag.
2085 * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0
2086 * @param DMAx DMAx Instance
2087 * @retval None
2088 */
LL_DMA_ClearFlag_HT0(DMA_TypeDef * DMAx)2089 __STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
2090 {
2091 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0);
2092 }
2093
2094 /**
2095 * @brief Clear Stream 1 half transfer flag.
2096 * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1
2097 * @param DMAx DMAx Instance
2098 * @retval None
2099 */
LL_DMA_ClearFlag_HT1(DMA_TypeDef * DMAx)2100 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
2101 {
2102 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1);
2103 }
2104
2105 /**
2106 * @brief Clear Stream 2 half transfer flag.
2107 * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2
2108 * @param DMAx DMAx Instance
2109 * @retval None
2110 */
LL_DMA_ClearFlag_HT2(DMA_TypeDef * DMAx)2111 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
2112 {
2113 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2);
2114 }
2115
2116 /**
2117 * @brief Clear Stream 3 half transfer flag.
2118 * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3
2119 * @param DMAx DMAx Instance
2120 * @retval None
2121 */
LL_DMA_ClearFlag_HT3(DMA_TypeDef * DMAx)2122 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
2123 {
2124 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3);
2125 }
2126
2127 /**
2128 * @brief Clear Stream 4 half transfer flag.
2129 * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4
2130 * @param DMAx DMAx Instance
2131 * @retval None
2132 */
LL_DMA_ClearFlag_HT4(DMA_TypeDef * DMAx)2133 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
2134 {
2135 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4);
2136 }
2137
2138 /**
2139 * @brief Clear Stream 5 half transfer flag.
2140 * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5
2141 * @param DMAx DMAx Instance
2142 * @retval None
2143 */
LL_DMA_ClearFlag_HT5(DMA_TypeDef * DMAx)2144 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
2145 {
2146 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5);
2147 }
2148
2149 /**
2150 * @brief Clear Stream 6 half transfer flag.
2151 * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6
2152 * @param DMAx DMAx Instance
2153 * @retval None
2154 */
LL_DMA_ClearFlag_HT6(DMA_TypeDef * DMAx)2155 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
2156 {
2157 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6);
2158 }
2159
2160 /**
2161 * @brief Clear Stream 7 half transfer flag.
2162 * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7
2163 * @param DMAx DMAx Instance
2164 * @retval None
2165 */
LL_DMA_ClearFlag_HT7(DMA_TypeDef * DMAx)2166 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
2167 {
2168 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7);
2169 }
2170
2171 /**
2172 * @brief Clear Stream 0 transfer complete flag.
2173 * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0
2174 * @param DMAx DMAx Instance
2175 * @retval None
2176 */
LL_DMA_ClearFlag_TC0(DMA_TypeDef * DMAx)2177 __STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
2178 {
2179 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0);
2180 }
2181
2182 /**
2183 * @brief Clear Stream 1 transfer complete flag.
2184 * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1
2185 * @param DMAx DMAx Instance
2186 * @retval None
2187 */
LL_DMA_ClearFlag_TC1(DMA_TypeDef * DMAx)2188 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
2189 {
2190 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1);
2191 }
2192
2193 /**
2194 * @brief Clear Stream 2 transfer complete flag.
2195 * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2
2196 * @param DMAx DMAx Instance
2197 * @retval None
2198 */
LL_DMA_ClearFlag_TC2(DMA_TypeDef * DMAx)2199 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
2200 {
2201 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2);
2202 }
2203
2204 /**
2205 * @brief Clear Stream 3 transfer complete flag.
2206 * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3
2207 * @param DMAx DMAx Instance
2208 * @retval None
2209 */
LL_DMA_ClearFlag_TC3(DMA_TypeDef * DMAx)2210 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
2211 {
2212 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3);
2213 }
2214
2215 /**
2216 * @brief Clear Stream 4 transfer complete flag.
2217 * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4
2218 * @param DMAx DMAx Instance
2219 * @retval None
2220 */
LL_DMA_ClearFlag_TC4(DMA_TypeDef * DMAx)2221 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
2222 {
2223 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4);
2224 }
2225
2226 /**
2227 * @brief Clear Stream 5 transfer complete flag.
2228 * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5
2229 * @param DMAx DMAx Instance
2230 * @retval None
2231 */
LL_DMA_ClearFlag_TC5(DMA_TypeDef * DMAx)2232 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
2233 {
2234 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5);
2235 }
2236
2237 /**
2238 * @brief Clear Stream 6 transfer complete flag.
2239 * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6
2240 * @param DMAx DMAx Instance
2241 * @retval None
2242 */
LL_DMA_ClearFlag_TC6(DMA_TypeDef * DMAx)2243 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
2244 {
2245 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6);
2246 }
2247
2248 /**
2249 * @brief Clear Stream 7 transfer complete flag.
2250 * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7
2251 * @param DMAx DMAx Instance
2252 * @retval None
2253 */
LL_DMA_ClearFlag_TC7(DMA_TypeDef * DMAx)2254 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
2255 {
2256 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7);
2257 }
2258
2259 /**
2260 * @brief Clear Stream 0 transfer error flag.
2261 * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0
2262 * @param DMAx DMAx Instance
2263 * @retval None
2264 */
LL_DMA_ClearFlag_TE0(DMA_TypeDef * DMAx)2265 __STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
2266 {
2267 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0);
2268 }
2269
2270 /**
2271 * @brief Clear Stream 1 transfer error flag.
2272 * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1
2273 * @param DMAx DMAx Instance
2274 * @retval None
2275 */
LL_DMA_ClearFlag_TE1(DMA_TypeDef * DMAx)2276 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
2277 {
2278 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1);
2279 }
2280
2281 /**
2282 * @brief Clear Stream 2 transfer error flag.
2283 * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2
2284 * @param DMAx DMAx Instance
2285 * @retval None
2286 */
LL_DMA_ClearFlag_TE2(DMA_TypeDef * DMAx)2287 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
2288 {
2289 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2);
2290 }
2291
2292 /**
2293 * @brief Clear Stream 3 transfer error flag.
2294 * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3
2295 * @param DMAx DMAx Instance
2296 * @retval None
2297 */
LL_DMA_ClearFlag_TE3(DMA_TypeDef * DMAx)2298 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
2299 {
2300 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3);
2301 }
2302
2303 /**
2304 * @brief Clear Stream 4 transfer error flag.
2305 * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4
2306 * @param DMAx DMAx Instance
2307 * @retval None
2308 */
LL_DMA_ClearFlag_TE4(DMA_TypeDef * DMAx)2309 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
2310 {
2311 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4);
2312 }
2313
2314 /**
2315 * @brief Clear Stream 5 transfer error flag.
2316 * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5
2317 * @param DMAx DMAx Instance
2318 * @retval None
2319 */
LL_DMA_ClearFlag_TE5(DMA_TypeDef * DMAx)2320 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
2321 {
2322 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5);
2323 }
2324
2325 /**
2326 * @brief Clear Stream 6 transfer error flag.
2327 * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6
2328 * @param DMAx DMAx Instance
2329 * @retval None
2330 */
LL_DMA_ClearFlag_TE6(DMA_TypeDef * DMAx)2331 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
2332 {
2333 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6);
2334 }
2335
2336 /**
2337 * @brief Clear Stream 7 transfer error flag.
2338 * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7
2339 * @param DMAx DMAx Instance
2340 * @retval None
2341 */
LL_DMA_ClearFlag_TE7(DMA_TypeDef * DMAx)2342 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
2343 {
2344 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7);
2345 }
2346
2347 /**
2348 * @brief Clear Stream 0 direct mode error flag.
2349 * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0
2350 * @param DMAx DMAx Instance
2351 * @retval None
2352 */
LL_DMA_ClearFlag_DME0(DMA_TypeDef * DMAx)2353 __STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
2354 {
2355 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0);
2356 }
2357
2358 /**
2359 * @brief Clear Stream 1 direct mode error flag.
2360 * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1
2361 * @param DMAx DMAx Instance
2362 * @retval None
2363 */
LL_DMA_ClearFlag_DME1(DMA_TypeDef * DMAx)2364 __STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
2365 {
2366 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1);
2367 }
2368
2369 /**
2370 * @brief Clear Stream 2 direct mode error flag.
2371 * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2
2372 * @param DMAx DMAx Instance
2373 * @retval None
2374 */
LL_DMA_ClearFlag_DME2(DMA_TypeDef * DMAx)2375 __STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
2376 {
2377 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2);
2378 }
2379
2380 /**
2381 * @brief Clear Stream 3 direct mode error flag.
2382 * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3
2383 * @param DMAx DMAx Instance
2384 * @retval None
2385 */
LL_DMA_ClearFlag_DME3(DMA_TypeDef * DMAx)2386 __STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
2387 {
2388 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3);
2389 }
2390
2391 /**
2392 * @brief Clear Stream 4 direct mode error flag.
2393 * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4
2394 * @param DMAx DMAx Instance
2395 * @retval None
2396 */
LL_DMA_ClearFlag_DME4(DMA_TypeDef * DMAx)2397 __STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
2398 {
2399 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4);
2400 }
2401
2402 /**
2403 * @brief Clear Stream 5 direct mode error flag.
2404 * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5
2405 * @param DMAx DMAx Instance
2406 * @retval None
2407 */
LL_DMA_ClearFlag_DME5(DMA_TypeDef * DMAx)2408 __STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
2409 {
2410 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5);
2411 }
2412
2413 /**
2414 * @brief Clear Stream 6 direct mode error flag.
2415 * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6
2416 * @param DMAx DMAx Instance
2417 * @retval None
2418 */
LL_DMA_ClearFlag_DME6(DMA_TypeDef * DMAx)2419 __STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
2420 {
2421 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6);
2422 }
2423
2424 /**
2425 * @brief Clear Stream 7 direct mode error flag.
2426 * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7
2427 * @param DMAx DMAx Instance
2428 * @retval None
2429 */
LL_DMA_ClearFlag_DME7(DMA_TypeDef * DMAx)2430 __STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
2431 {
2432 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7);
2433 }
2434
2435 /**
2436 * @brief Clear Stream 0 FIFO error flag.
2437 * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0
2438 * @param DMAx DMAx Instance
2439 * @retval None
2440 */
LL_DMA_ClearFlag_FE0(DMA_TypeDef * DMAx)2441 __STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
2442 {
2443 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0);
2444 }
2445
2446 /**
2447 * @brief Clear Stream 1 FIFO error flag.
2448 * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1
2449 * @param DMAx DMAx Instance
2450 * @retval None
2451 */
LL_DMA_ClearFlag_FE1(DMA_TypeDef * DMAx)2452 __STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
2453 {
2454 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1);
2455 }
2456
2457 /**
2458 * @brief Clear Stream 2 FIFO error flag.
2459 * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2
2460 * @param DMAx DMAx Instance
2461 * @retval None
2462 */
LL_DMA_ClearFlag_FE2(DMA_TypeDef * DMAx)2463 __STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
2464 {
2465 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2);
2466 }
2467
2468 /**
2469 * @brief Clear Stream 3 FIFO error flag.
2470 * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3
2471 * @param DMAx DMAx Instance
2472 * @retval None
2473 */
LL_DMA_ClearFlag_FE3(DMA_TypeDef * DMAx)2474 __STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
2475 {
2476 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3);
2477 }
2478
2479 /**
2480 * @brief Clear Stream 4 FIFO error flag.
2481 * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4
2482 * @param DMAx DMAx Instance
2483 * @retval None
2484 */
LL_DMA_ClearFlag_FE4(DMA_TypeDef * DMAx)2485 __STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
2486 {
2487 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4);
2488 }
2489
2490 /**
2491 * @brief Clear Stream 5 FIFO error flag.
2492 * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5
2493 * @param DMAx DMAx Instance
2494 * @retval None
2495 */
LL_DMA_ClearFlag_FE5(DMA_TypeDef * DMAx)2496 __STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
2497 {
2498 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5);
2499 }
2500
2501 /**
2502 * @brief Clear Stream 6 FIFO error flag.
2503 * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6
2504 * @param DMAx DMAx Instance
2505 * @retval None
2506 */
LL_DMA_ClearFlag_FE6(DMA_TypeDef * DMAx)2507 __STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
2508 {
2509 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6);
2510 }
2511
2512 /**
2513 * @brief Clear Stream 7 FIFO error flag.
2514 * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7
2515 * @param DMAx DMAx Instance
2516 * @retval None
2517 */
LL_DMA_ClearFlag_FE7(DMA_TypeDef * DMAx)2518 __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
2519 {
2520 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7);
2521 }
2522
2523 /**
2524 * @}
2525 */
2526
2527 /** @defgroup DMA_LL_EF_IT_Management IT_Management
2528 * @{
2529 */
2530
2531 /**
2532 * @brief Enable Half transfer interrupt.
2533 * @rmtoll CR HTIE LL_DMA_EnableIT_HT
2534 * @param DMAx DMAx Instance
2535 * @param Stream This parameter can be one of the following values:
2536 * @arg @ref LL_DMA_STREAM_0
2537 * @arg @ref LL_DMA_STREAM_1
2538 * @arg @ref LL_DMA_STREAM_2
2539 * @arg @ref LL_DMA_STREAM_3
2540 * @arg @ref LL_DMA_STREAM_4
2541 * @arg @ref LL_DMA_STREAM_5
2542 * @arg @ref LL_DMA_STREAM_6
2543 * @arg @ref LL_DMA_STREAM_7
2544 * @retval None
2545 */
LL_DMA_EnableIT_HT(DMA_TypeDef * DMAx,uint32_t Stream)2546 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
2547 {
2548 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
2549 }
2550
2551 /**
2552 * @brief Enable Transfer error interrupt.
2553 * @rmtoll CR TEIE LL_DMA_EnableIT_TE
2554 * @param DMAx DMAx Instance
2555 * @param Stream This parameter can be one of the following values:
2556 * @arg @ref LL_DMA_STREAM_0
2557 * @arg @ref LL_DMA_STREAM_1
2558 * @arg @ref LL_DMA_STREAM_2
2559 * @arg @ref LL_DMA_STREAM_3
2560 * @arg @ref LL_DMA_STREAM_4
2561 * @arg @ref LL_DMA_STREAM_5
2562 * @arg @ref LL_DMA_STREAM_6
2563 * @arg @ref LL_DMA_STREAM_7
2564 * @retval None
2565 */
LL_DMA_EnableIT_TE(DMA_TypeDef * DMAx,uint32_t Stream)2566 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
2567 {
2568 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
2569 }
2570
2571 /**
2572 * @brief Enable Transfer complete interrupt.
2573 * @rmtoll CR TCIE LL_DMA_EnableIT_TC
2574 * @param DMAx DMAx Instance
2575 * @param Stream This parameter can be one of the following values:
2576 * @arg @ref LL_DMA_STREAM_0
2577 * @arg @ref LL_DMA_STREAM_1
2578 * @arg @ref LL_DMA_STREAM_2
2579 * @arg @ref LL_DMA_STREAM_3
2580 * @arg @ref LL_DMA_STREAM_4
2581 * @arg @ref LL_DMA_STREAM_5
2582 * @arg @ref LL_DMA_STREAM_6
2583 * @arg @ref LL_DMA_STREAM_7
2584 * @retval None
2585 */
LL_DMA_EnableIT_TC(DMA_TypeDef * DMAx,uint32_t Stream)2586 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
2587 {
2588 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
2589 }
2590
2591 /**
2592 * @brief Enable Direct mode error interrupt.
2593 * @rmtoll CR DMEIE LL_DMA_EnableIT_DME
2594 * @param DMAx DMAx Instance
2595 * @param Stream This parameter can be one of the following values:
2596 * @arg @ref LL_DMA_STREAM_0
2597 * @arg @ref LL_DMA_STREAM_1
2598 * @arg @ref LL_DMA_STREAM_2
2599 * @arg @ref LL_DMA_STREAM_3
2600 * @arg @ref LL_DMA_STREAM_4
2601 * @arg @ref LL_DMA_STREAM_5
2602 * @arg @ref LL_DMA_STREAM_6
2603 * @arg @ref LL_DMA_STREAM_7
2604 * @retval None
2605 */
LL_DMA_EnableIT_DME(DMA_TypeDef * DMAx,uint32_t Stream)2606 __STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
2607 {
2608 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
2609 }
2610
2611 /**
2612 * @brief Enable FIFO error interrupt.
2613 * @rmtoll FCR FEIE LL_DMA_EnableIT_FE
2614 * @param DMAx DMAx Instance
2615 * @param Stream This parameter can be one of the following values:
2616 * @arg @ref LL_DMA_STREAM_0
2617 * @arg @ref LL_DMA_STREAM_1
2618 * @arg @ref LL_DMA_STREAM_2
2619 * @arg @ref LL_DMA_STREAM_3
2620 * @arg @ref LL_DMA_STREAM_4
2621 * @arg @ref LL_DMA_STREAM_5
2622 * @arg @ref LL_DMA_STREAM_6
2623 * @arg @ref LL_DMA_STREAM_7
2624 * @retval None
2625 */
LL_DMA_EnableIT_FE(DMA_TypeDef * DMAx,uint32_t Stream)2626 __STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
2627 {
2628 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
2629 }
2630
2631 /**
2632 * @brief Disable Half transfer interrupt.
2633 * @rmtoll CR HTIE LL_DMA_DisableIT_HT
2634 * @param DMAx DMAx Instance
2635 * @param Stream This parameter can be one of the following values:
2636 * @arg @ref LL_DMA_STREAM_0
2637 * @arg @ref LL_DMA_STREAM_1
2638 * @arg @ref LL_DMA_STREAM_2
2639 * @arg @ref LL_DMA_STREAM_3
2640 * @arg @ref LL_DMA_STREAM_4
2641 * @arg @ref LL_DMA_STREAM_5
2642 * @arg @ref LL_DMA_STREAM_6
2643 * @arg @ref LL_DMA_STREAM_7
2644 * @retval None
2645 */
LL_DMA_DisableIT_HT(DMA_TypeDef * DMAx,uint32_t Stream)2646 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
2647 {
2648 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
2649 }
2650
2651 /**
2652 * @brief Disable Transfer error interrupt.
2653 * @rmtoll CR TEIE LL_DMA_DisableIT_TE
2654 * @param DMAx DMAx Instance
2655 * @param Stream This parameter can be one of the following values:
2656 * @arg @ref LL_DMA_STREAM_0
2657 * @arg @ref LL_DMA_STREAM_1
2658 * @arg @ref LL_DMA_STREAM_2
2659 * @arg @ref LL_DMA_STREAM_3
2660 * @arg @ref LL_DMA_STREAM_4
2661 * @arg @ref LL_DMA_STREAM_5
2662 * @arg @ref LL_DMA_STREAM_6
2663 * @arg @ref LL_DMA_STREAM_7
2664 * @retval None
2665 */
LL_DMA_DisableIT_TE(DMA_TypeDef * DMAx,uint32_t Stream)2666 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
2667 {
2668 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
2669 }
2670
2671 /**
2672 * @brief Disable Transfer complete interrupt.
2673 * @rmtoll CR TCIE LL_DMA_DisableIT_TC
2674 * @param DMAx DMAx Instance
2675 * @param Stream This parameter can be one of the following values:
2676 * @arg @ref LL_DMA_STREAM_0
2677 * @arg @ref LL_DMA_STREAM_1
2678 * @arg @ref LL_DMA_STREAM_2
2679 * @arg @ref LL_DMA_STREAM_3
2680 * @arg @ref LL_DMA_STREAM_4
2681 * @arg @ref LL_DMA_STREAM_5
2682 * @arg @ref LL_DMA_STREAM_6
2683 * @arg @ref LL_DMA_STREAM_7
2684 * @retval None
2685 */
LL_DMA_DisableIT_TC(DMA_TypeDef * DMAx,uint32_t Stream)2686 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
2687 {
2688 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
2689 }
2690
2691 /**
2692 * @brief Disable Direct mode error interrupt.
2693 * @rmtoll CR DMEIE LL_DMA_DisableIT_DME
2694 * @param DMAx DMAx Instance
2695 * @param Stream This parameter can be one of the following values:
2696 * @arg @ref LL_DMA_STREAM_0
2697 * @arg @ref LL_DMA_STREAM_1
2698 * @arg @ref LL_DMA_STREAM_2
2699 * @arg @ref LL_DMA_STREAM_3
2700 * @arg @ref LL_DMA_STREAM_4
2701 * @arg @ref LL_DMA_STREAM_5
2702 * @arg @ref LL_DMA_STREAM_6
2703 * @arg @ref LL_DMA_STREAM_7
2704 * @retval None
2705 */
LL_DMA_DisableIT_DME(DMA_TypeDef * DMAx,uint32_t Stream)2706 __STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
2707 {
2708 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
2709 }
2710
2711 /**
2712 * @brief Disable FIFO error interrupt.
2713 * @rmtoll FCR FEIE LL_DMA_DisableIT_FE
2714 * @param DMAx DMAx Instance
2715 * @param Stream This parameter can be one of the following values:
2716 * @arg @ref LL_DMA_STREAM_0
2717 * @arg @ref LL_DMA_STREAM_1
2718 * @arg @ref LL_DMA_STREAM_2
2719 * @arg @ref LL_DMA_STREAM_3
2720 * @arg @ref LL_DMA_STREAM_4
2721 * @arg @ref LL_DMA_STREAM_5
2722 * @arg @ref LL_DMA_STREAM_6
2723 * @arg @ref LL_DMA_STREAM_7
2724 * @retval None
2725 */
LL_DMA_DisableIT_FE(DMA_TypeDef * DMAx,uint32_t Stream)2726 __STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
2727 {
2728 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
2729 }
2730
2731 /**
2732 * @brief Check if Half transfer interrupt is enabled.
2733 * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT
2734 * @param DMAx DMAx Instance
2735 * @param Stream This parameter can be one of the following values:
2736 * @arg @ref LL_DMA_STREAM_0
2737 * @arg @ref LL_DMA_STREAM_1
2738 * @arg @ref LL_DMA_STREAM_2
2739 * @arg @ref LL_DMA_STREAM_3
2740 * @arg @ref LL_DMA_STREAM_4
2741 * @arg @ref LL_DMA_STREAM_5
2742 * @arg @ref LL_DMA_STREAM_6
2743 * @arg @ref LL_DMA_STREAM_7
2744 * @retval State of bit (1 or 0).
2745 */
LL_DMA_IsEnabledIT_HT(DMA_TypeDef * DMAx,uint32_t Stream)2746 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
2747 {
2748 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE);
2749 }
2750
2751 /**
2752 * @brief Check if Transfer error nterrup is enabled.
2753 * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE
2754 * @param DMAx DMAx Instance
2755 * @param Stream This parameter can be one of the following values:
2756 * @arg @ref LL_DMA_STREAM_0
2757 * @arg @ref LL_DMA_STREAM_1
2758 * @arg @ref LL_DMA_STREAM_2
2759 * @arg @ref LL_DMA_STREAM_3
2760 * @arg @ref LL_DMA_STREAM_4
2761 * @arg @ref LL_DMA_STREAM_5
2762 * @arg @ref LL_DMA_STREAM_6
2763 * @arg @ref LL_DMA_STREAM_7
2764 * @retval State of bit (1 or 0).
2765 */
LL_DMA_IsEnabledIT_TE(DMA_TypeDef * DMAx,uint32_t Stream)2766 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
2767 {
2768 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE);
2769 }
2770
2771 /**
2772 * @brief Check if Transfer complete interrupt is enabled.
2773 * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC
2774 * @param DMAx DMAx Instance
2775 * @param Stream This parameter can be one of the following values:
2776 * @arg @ref LL_DMA_STREAM_0
2777 * @arg @ref LL_DMA_STREAM_1
2778 * @arg @ref LL_DMA_STREAM_2
2779 * @arg @ref LL_DMA_STREAM_3
2780 * @arg @ref LL_DMA_STREAM_4
2781 * @arg @ref LL_DMA_STREAM_5
2782 * @arg @ref LL_DMA_STREAM_6
2783 * @arg @ref LL_DMA_STREAM_7
2784 * @retval State of bit (1 or 0).
2785 */
LL_DMA_IsEnabledIT_TC(DMA_TypeDef * DMAx,uint32_t Stream)2786 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
2787 {
2788 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE);
2789 }
2790
2791 /**
2792 * @brief Check if Direct mode error interrupt is enabled.
2793 * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME
2794 * @param DMAx DMAx Instance
2795 * @param Stream This parameter can be one of the following values:
2796 * @arg @ref LL_DMA_STREAM_0
2797 * @arg @ref LL_DMA_STREAM_1
2798 * @arg @ref LL_DMA_STREAM_2
2799 * @arg @ref LL_DMA_STREAM_3
2800 * @arg @ref LL_DMA_STREAM_4
2801 * @arg @ref LL_DMA_STREAM_5
2802 * @arg @ref LL_DMA_STREAM_6
2803 * @arg @ref LL_DMA_STREAM_7
2804 * @retval State of bit (1 or 0).
2805 */
LL_DMA_IsEnabledIT_DME(DMA_TypeDef * DMAx,uint32_t Stream)2806 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
2807 {
2808 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE);
2809 }
2810
2811 /**
2812 * @brief Check if FIFO error interrupt is enabled.
2813 * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE
2814 * @param DMAx DMAx Instance
2815 * @param Stream This parameter can be one of the following values:
2816 * @arg @ref LL_DMA_STREAM_0
2817 * @arg @ref LL_DMA_STREAM_1
2818 * @arg @ref LL_DMA_STREAM_2
2819 * @arg @ref LL_DMA_STREAM_3
2820 * @arg @ref LL_DMA_STREAM_4
2821 * @arg @ref LL_DMA_STREAM_5
2822 * @arg @ref LL_DMA_STREAM_6
2823 * @arg @ref LL_DMA_STREAM_7
2824 * @retval State of bit (1 or 0).
2825 */
LL_DMA_IsEnabledIT_FE(DMA_TypeDef * DMAx,uint32_t Stream)2826 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
2827 {
2828 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE);
2829 }
2830
2831 /**
2832 * @}
2833 */
2834
2835 #if defined(USE_FULL_LL_DRIVER)
2836 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
2837 * @{
2838 */
2839
2840 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct);
2841 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);
2842 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
2843
2844 /**
2845 * @}
2846 */
2847 #endif /* USE_FULL_LL_DRIVER */
2848
2849 /**
2850 * @}
2851 */
2852
2853 /**
2854 * @}
2855 */
2856
2857 #endif /* DMA1 || DMA2 */
2858
2859 /**
2860 * @}
2861 */
2862
2863 #ifdef __cplusplus
2864 }
2865 #endif
2866
2867 #endif /* __STM32F4xx_LL_DMA_H */
2868
2869
