1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_dac.h
4 * @author MCD Application Team
5 * @brief Header file of DAC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32F4xx_LL_DAC_H
21 #define STM32F4xx_LL_DAC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f4xx.h"
29
30 /** @addtogroup STM32F4xx_LL_Driver
31 * @{
32 */
33
34 #if defined(DAC)
35
36 /** @defgroup DAC_LL DAC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
45 * @{
46 */
47
48 /* Internal masks for DAC channels definition */
49 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
50 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
51 /* - channel bits position into register SWTRIG */
52 /* - channel register offset of data holding register DHRx */
53 /* - channel register offset of data output register DORx */
54 #define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
55 CR, MCR, CCR, SHHR, SHRR of channel 1 */
56 #if defined(DAC_CHANNEL2_SUPPORT)
57 #define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers
58 CR, MCR, CCR, SHHR, SHRR of channel 2 */
59 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
60 #else
61 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET)
62 #endif /* DAC_CHANNEL2_SUPPORT */
63
64 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
65 #if defined(DAC_CHANNEL2_SUPPORT)
66 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
67 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
68 #else
69 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
70 #endif /* DAC_CHANNEL2_SUPPORT */
71
72 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
73 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
74 DHR12Rx channel 1 (shifted left of 20 bits) */
75 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
76 DHR12Rx channel 1 (shifted left of 24 bits) */
77 #if defined(DAC_CHANNEL2_SUPPORT)
78 #define DAC_REG_DHR12R2_REGOFFSET 0x00030000UL /* Register offset of DHR12Rx channel 2 versus
79 DHR12Rx channel 1 (shifted left of 16 bits) */
80 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus
81 DHR12Rx channel 1 (shifted left of 20 bits) */
82 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus
83 DHR12Rx channel 1 (shifted left of 24 bits) */
84 #endif /* DAC_CHANNEL2_SUPPORT */
85 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000UL
86 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
87 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
88 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
89 | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
90
91 #define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
92 #if defined(DAC_CHANNEL2_SUPPORT)
93 #define DAC_REG_DOR2_REGOFFSET 0x10000000UL /* Register offset of DORx channel 1 versus
94 DORx channel 2 (shifted left of 28 bits) */
95 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
96 #endif /* DAC_CHANNEL2_SUPPORT */
97
98
99 #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
100 DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
101 #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
102 to position 0 */
103 #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
104 to position 0 */
105
106 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16UL /* Position of bits register offset of DHR12Rx
107 channel 1 or 2 versus DHR12Rx channel 1
108 (shifted left of 16 bits) */
109 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
110 channel 1 or 2 versus DHR12Rx channel 1
111 (shifted left of 20 bits) */
112 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
113 channel 1 or 2 versus DHR12Rx channel 1
114 (shifted left of 24 bits) */
115 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DORx
116 channel 1 or 2 versus DORx channel 1
117 (shifted left of 28 bits) */
118
119 /* DAC registers bits positions */
120 #if defined(DAC_CHANNEL2_SUPPORT)
121 #endif
122 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
123 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
124 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
125
126 /* Miscellaneous data */
127 #define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
128 bits (voltage range determined by analog voltage
129 references Vref+ and Vref-, refer to reference manual) */
130
131 /**
132 * @}
133 */
134
135
136 /* Private macros ------------------------------------------------------------*/
137 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
138 * @{
139 */
140
141 /**
142 * @brief Driver macro reserved for internal use: set a pointer to
143 * a register from a register basis from which an offset
144 * is applied.
145 * @param __REG__ Register basis from which the offset is applied.
146 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
147 * @retval Pointer to register address
148 */
149 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
150 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
151
152 /**
153 * @}
154 */
155
156
157 /* Exported types ------------------------------------------------------------*/
158 #if defined(USE_FULL_LL_DRIVER)
159 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
160 * @{
161 */
162
163 /**
164 * @brief Structure definition of some features of DAC instance.
165 */
166 typedef struct
167 {
168 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel:
169 internal (SW start) or from external peripheral
170 (timer event, external interrupt line).
171 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
172
173 This feature can be modified afterwards using unitary
174 function @ref LL_DAC_SetTriggerSource(). */
175
176 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
177 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
178
179 This feature can be modified afterwards using unitary
180 function @ref LL_DAC_SetWaveAutoGeneration(). */
181
182 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
183 If waveform automatic generation mode is set to noise, this parameter
184 can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
185 If waveform automatic generation mode is set to triangle,
186 this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
187 @note If waveform automatic generation mode is disabled,
188 this parameter is discarded.
189
190 This feature can be modified afterwards using unitary
191 function @ref LL_DAC_SetWaveNoiseLFSR(),
192 @ref LL_DAC_SetWaveTriangleAmplitude()
193 depending on the wave automatic generation selected. */
194
195 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
196 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
197
198 This feature can be modified afterwards using unitary
199 function @ref LL_DAC_SetOutputBuffer(). */
200 } LL_DAC_InitTypeDef;
201
202 /**
203 * @}
204 */
205 #endif /* USE_FULL_LL_DRIVER */
206
207 /* Exported constants --------------------------------------------------------*/
208 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
209 * @{
210 */
211
212 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
213 * @brief Flags defines which can be used with LL_DAC_ReadReg function
214 * @{
215 */
216 /* DAC channel 1 flags */
217 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
218 #if defined(DAC_CHANNEL2_SUPPORT)
219 /* DAC channel 2 flags */
220 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
221 #endif /* DAC_CHANNEL2_SUPPORT */
222 /**
223 * @}
224 */
225
226 /** @defgroup DAC_LL_EC_IT DAC interruptions
227 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
228 * @{
229 */
230 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
231 #if defined(DAC_CHANNEL2_SUPPORT)
232 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
233 #endif /* DAC_CHANNEL2_SUPPORT */
234 /**
235 * @}
236 */
237
238 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
239 * @{
240 */
241 #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
242 #if defined(DAC_CHANNEL2_SUPPORT)
243 #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
244 #endif /* DAC_CHANNEL2_SUPPORT */
245 /**
246 * @}
247 */
248
249 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
250 * @{
251 */
252 #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
253 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */
254 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */
255 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */
256 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000UL /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */
257 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */
258 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */
259 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
260 /**
261 * @}
262 */
263
264 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
265 * @{
266 */
267 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */
268 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
269 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
270 /**
271 * @}
272 */
273
274 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
275 * @{
276 */
277 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
278 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
279 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
280 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
281 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
282 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
283 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
284 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
285 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
286 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
287 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
288 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
289 /**
290 * @}
291 */
292
293 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
294 * @{
295 */
296 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
297 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
298 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
299 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
300 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
301 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
302 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
303 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
304 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
305 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
306 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
307 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
308 /**
309 * @}
310 */
311
312 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
313 * @{
314 */
315 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
316 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
317 /**
318 * @}
319 */
320
321 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
322 * @{
323 */
324 #define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */
325 #define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */
326 /**
327 * @}
328 */
329
330 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
331 * @{
332 */
333 /* List of DAC registers intended to be used (most commonly) with */
334 /* DMA transfer. */
335 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
336 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
337 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
338 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
339 /**
340 * @}
341 */
342
343 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
344 * @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
345 * not timeout values.
346 * For details on delays values, refer to descriptions in source code
347 * above each literal definition.
348 * @{
349 */
350
351 /* Delay for DAC channel voltage settling time from DAC channel startup */
352 /* (transition from disable to enable). */
353 /* Note: DAC channel startup time depends on board application environment: */
354 /* impedance connected to DAC channel output. */
355 /* The delay below is specified under conditions: */
356 /* - voltage maximum transition (lowest to highest value) */
357 /* - until voltage reaches final value +-1LSB */
358 /* - DAC channel output buffer enabled */
359 /* - load impedance of 5kOhm (min), 50pF (max) */
360 /* Literal set to maximum value (refer to device datasheet, */
361 /* parameter "tWAKEUP"). */
362 /* Unit: us */
363 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
364
365 /* Delay for DAC channel voltage settling time. */
366 /* Note: DAC channel startup time depends on board application environment: */
367 /* impedance connected to DAC channel output. */
368 /* The delay below is specified under conditions: */
369 /* - voltage maximum transition (lowest to highest value) */
370 /* - until voltage reaches final value +-1LSB */
371 /* - DAC channel output buffer enabled */
372 /* - load impedance of 5kOhm min, 50pF max */
373 /* Literal set to maximum value (refer to device datasheet, */
374 /* parameter "tSETTLING"). */
375 /* Unit: us */
376 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12UL /*!< Delay for DAC channel voltage settling time */
377
378 /**
379 * @}
380 */
381
382 /**
383 * @}
384 */
385
386 /* Exported macro ------------------------------------------------------------*/
387 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
388 * @{
389 */
390
391 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
392 * @{
393 */
394
395 /**
396 * @brief Write a value in DAC register
397 * @param __INSTANCE__ DAC Instance
398 * @param __REG__ Register to be written
399 * @param __VALUE__ Value to be written in the register
400 * @retval None
401 */
402 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
403
404 /**
405 * @brief Read a value in DAC register
406 * @param __INSTANCE__ DAC Instance
407 * @param __REG__ Register to be read
408 * @retval Register value
409 */
410 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
411
412 /**
413 * @}
414 */
415
416 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
417 * @{
418 */
419
420 /**
421 * @brief Helper macro to get DAC channel number in decimal format
422 * from literals LL_DAC_CHANNEL_x.
423 * Example:
424 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
425 * will return decimal number "1".
426 * @note The input can be a value from functions where a channel
427 * number is returned.
428 * @param __CHANNEL__ This parameter can be one of the following values:
429 * @arg @ref LL_DAC_CHANNEL_1
430 * @arg @ref LL_DAC_CHANNEL_2 (1)
431 *
432 * (1) On this STM32 serie, parameter not available on all devices.
433 * Refer to device datasheet for channels availability.
434 * @retval 1...2 (value "2" depending on DAC channel 2 availability)
435 */
436 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
437 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
438
439 /**
440 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
441 * from number in decimal format.
442 * Example:
443 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
444 * will return a data equivalent to "LL_DAC_CHANNEL_1".
445 * @note If the input parameter does not correspond to a DAC channel,
446 * this macro returns value '0'.
447 * @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability)
448 * @retval Returned value can be one of the following values:
449 * @arg @ref LL_DAC_CHANNEL_1
450 * @arg @ref LL_DAC_CHANNEL_2 (1)
451 *
452 * (1) On this STM32 serie, parameter not available on all devices.
453 * Refer to device datasheet for channels availability.
454 */
455 #if defined(DAC_CHANNEL2_SUPPORT)
456 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
457 (((__DECIMAL_NB__) == 1UL) \
458 ? ( \
459 LL_DAC_CHANNEL_1 \
460 ) \
461 : \
462 (((__DECIMAL_NB__) == 2UL) \
463 ? ( \
464 LL_DAC_CHANNEL_2 \
465 ) \
466 : \
467 ( \
468 0UL \
469 ) \
470 ) \
471 )
472 #else
473 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
474 (((__DECIMAL_NB__) == 1UL) \
475 ? ( \
476 LL_DAC_CHANNEL_1 \
477 ) \
478 : \
479 ( \
480 0UL \
481 ) \
482 )
483 #endif /* DAC_CHANNEL2_SUPPORT */
484
485 /**
486 * @brief Helper macro to define the DAC conversion data full-scale digital
487 * value corresponding to the selected DAC resolution.
488 * @note DAC conversion data full-scale corresponds to voltage range
489 * determined by analog voltage references Vref+ and Vref-
490 * (refer to reference manual).
491 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
492 * @arg @ref LL_DAC_RESOLUTION_12B
493 * @arg @ref LL_DAC_RESOLUTION_8B
494 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
495 */
496 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
497 ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
498
499 /**
500 * @brief Helper macro to calculate the DAC conversion data (unit: digital
501 * value) corresponding to a voltage (unit: mVolt).
502 * @note This helper macro is intended to provide input data in voltage
503 * rather than digital value,
504 * to be used with LL DAC functions such as
505 * @ref LL_DAC_ConvertData12RightAligned().
506 * @note Analog reference voltage (Vref+) must be either known from
507 * user board environment or can be calculated using ADC measurement
508 * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
509 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
510 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
511 * (unit: mVolt).
512 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
513 * @arg @ref LL_DAC_RESOLUTION_12B
514 * @arg @ref LL_DAC_RESOLUTION_8B
515 * @retval DAC conversion data (unit: digital value)
516 */
517 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
518 __DAC_VOLTAGE__,\
519 __DAC_RESOLUTION__) \
520 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
521 / (__VREFANALOG_VOLTAGE__) \
522 )
523
524 /**
525 * @}
526 */
527
528 /**
529 * @}
530 */
531
532
533 /* Exported functions --------------------------------------------------------*/
534 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
535 * @{
536 */
537 /**
538 * @brief Set the conversion trigger source for the selected DAC channel.
539 * @note For conversion trigger source to be effective, DAC trigger
540 * must be enabled using function @ref LL_DAC_EnableTrigger().
541 * @note To set conversion trigger source, DAC channel must be disabled.
542 * Otherwise, the setting is discarded.
543 * @note Availability of parameters of trigger sources from timer
544 * depends on timers availability on the selected device.
545 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
546 * CR TSEL2 LL_DAC_SetTriggerSource
547 * @param DACx DAC instance
548 * @param DAC_Channel This parameter can be one of the following values:
549 * @arg @ref LL_DAC_CHANNEL_1
550 * @arg @ref LL_DAC_CHANNEL_2 (1)
551 *
552 * (1) On this STM32 serie, parameter not available on all devices.
553 * Refer to device datasheet for channels availability.
554 * @param TriggerSource This parameter can be one of the following values:
555 * @arg @ref LL_DAC_TRIG_SOFTWARE
556 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
557 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
558 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
559 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
560 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
561 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
562 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
563 * @retval None
564 */
LL_DAC_SetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriggerSource)565 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
566 {
567 MODIFY_REG(DACx->CR,
568 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
569 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
570 }
571
572 /**
573 * @brief Get the conversion trigger source for the selected DAC channel.
574 * @note For conversion trigger source to be effective, DAC trigger
575 * must be enabled using function @ref LL_DAC_EnableTrigger().
576 * @note Availability of parameters of trigger sources from timer
577 * depends on timers availability on the selected device.
578 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
579 * CR TSEL2 LL_DAC_GetTriggerSource
580 * @param DACx DAC instance
581 * @param DAC_Channel This parameter can be one of the following values:
582 * @arg @ref LL_DAC_CHANNEL_1
583 * @arg @ref LL_DAC_CHANNEL_2 (1)
584 *
585 * (1) On this STM32 serie, parameter not available on all devices.
586 * Refer to device datasheet for channels availability.
587 * @retval Returned value can be one of the following values:
588 * @arg @ref LL_DAC_TRIG_SOFTWARE
589 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
590 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
591 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
592 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
593 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
594 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
595 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
596 */
LL_DAC_GetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel)597 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
598 {
599 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
600 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
601 );
602 }
603
604 /**
605 * @brief Set the waveform automatic generation mode
606 * for the selected DAC channel.
607 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
608 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
609 * @param DACx DAC instance
610 * @param DAC_Channel This parameter can be one of the following values:
611 * @arg @ref LL_DAC_CHANNEL_1
612 * @arg @ref LL_DAC_CHANNEL_2 (1)
613 *
614 * (1) On this STM32 serie, parameter not available on all devices.
615 * Refer to device datasheet for channels availability.
616 * @param WaveAutoGeneration This parameter can be one of the following values:
617 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
618 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
619 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
620 * @retval None
621 */
LL_DAC_SetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t WaveAutoGeneration)622 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
623 {
624 MODIFY_REG(DACx->CR,
625 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
626 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
627 }
628
629 /**
630 * @brief Get the waveform automatic generation mode
631 * for the selected DAC channel.
632 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
633 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
634 * @param DACx DAC instance
635 * @param DAC_Channel This parameter can be one of the following values:
636 * @arg @ref LL_DAC_CHANNEL_1
637 * @arg @ref LL_DAC_CHANNEL_2 (1)
638 *
639 * (1) On this STM32 serie, parameter not available on all devices.
640 * Refer to device datasheet for channels availability.
641 * @retval Returned value can be one of the following values:
642 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
643 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
644 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
645 */
LL_DAC_GetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel)646 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
647 {
648 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
649 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
650 );
651 }
652
653 /**
654 * @brief Set the noise waveform generation for the selected DAC channel:
655 * Noise mode and parameters LFSR (linear feedback shift register).
656 * @note For wave generation to be effective, DAC channel
657 * wave generation mode must be enabled using
658 * function @ref LL_DAC_SetWaveAutoGeneration().
659 * @note This setting can be set when the selected DAC channel is disabled
660 * (otherwise, the setting operation is ignored).
661 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
662 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
663 * @param DACx DAC instance
664 * @param DAC_Channel This parameter can be one of the following values:
665 * @arg @ref LL_DAC_CHANNEL_1
666 * @arg @ref LL_DAC_CHANNEL_2 (1)
667 *
668 * (1) On this STM32 serie, parameter not available on all devices.
669 * Refer to device datasheet for channels availability.
670 * @param NoiseLFSRMask This parameter can be one of the following values:
671 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
672 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
673 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
674 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
675 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
676 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
677 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
678 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
679 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
680 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
681 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
682 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
683 * @retval None
684 */
LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t NoiseLFSRMask)685 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
686 {
687 MODIFY_REG(DACx->CR,
688 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
689 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
690 }
691
692 /**
693 * @brief Get the noise waveform generation for the selected DAC channel:
694 * Noise mode and parameters LFSR (linear feedback shift register).
695 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
696 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
697 * @param DACx DAC instance
698 * @param DAC_Channel This parameter can be one of the following values:
699 * @arg @ref LL_DAC_CHANNEL_1
700 * @arg @ref LL_DAC_CHANNEL_2 (1)
701 *
702 * (1) On this STM32 serie, parameter not available on all devices.
703 * Refer to device datasheet for channels availability.
704 * @retval Returned value can be one of the following values:
705 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
706 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
707 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
708 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
709 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
710 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
711 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
712 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
713 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
714 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
715 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
716 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
717 */
LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel)718 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
719 {
720 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
721 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
722 );
723 }
724
725 /**
726 * @brief Set the triangle waveform generation for the selected DAC channel:
727 * triangle mode and amplitude.
728 * @note For wave generation to be effective, DAC channel
729 * wave generation mode must be enabled using
730 * function @ref LL_DAC_SetWaveAutoGeneration().
731 * @note This setting can be set when the selected DAC channel is disabled
732 * (otherwise, the setting operation is ignored).
733 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
734 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
735 * @param DACx DAC instance
736 * @param DAC_Channel This parameter can be one of the following values:
737 * @arg @ref LL_DAC_CHANNEL_1
738 * @arg @ref LL_DAC_CHANNEL_2 (1)
739 *
740 * (1) On this STM32 serie, parameter not available on all devices.
741 * Refer to device datasheet for channels availability.
742 * @param TriangleAmplitude This parameter can be one of the following values:
743 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
744 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
745 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
746 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
747 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
748 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
749 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
750 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
751 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
752 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
753 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
754 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
755 * @retval None
756 */
LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriangleAmplitude)757 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
758 uint32_t TriangleAmplitude)
759 {
760 MODIFY_REG(DACx->CR,
761 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
762 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
763 }
764
765 /**
766 * @brief Get the triangle waveform generation for the selected DAC channel:
767 * triangle mode and amplitude.
768 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
769 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
770 * @param DACx DAC instance
771 * @param DAC_Channel This parameter can be one of the following values:
772 * @arg @ref LL_DAC_CHANNEL_1
773 * @arg @ref LL_DAC_CHANNEL_2 (1)
774 *
775 * (1) On this STM32 serie, parameter not available on all devices.
776 * Refer to device datasheet for channels availability.
777 * @retval Returned value can be one of the following values:
778 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
779 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
780 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
781 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
782 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
783 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
784 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
785 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
786 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
787 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
788 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
789 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
790 */
LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel)791 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
792 {
793 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
794 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
795 );
796 }
797
798 /**
799 * @brief Set the output buffer for the selected DAC channel.
800 * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
801 * CR BOFF2 LL_DAC_SetOutputBuffer
802 * @param DACx DAC instance
803 * @param DAC_Channel This parameter can be one of the following values:
804 * @arg @ref LL_DAC_CHANNEL_1
805 * @arg @ref LL_DAC_CHANNEL_2 (1)
806 *
807 * (1) On this STM32 serie, parameter not available on all devices.
808 * Refer to device datasheet for channels availability.
809 * @param OutputBuffer This parameter can be one of the following values:
810 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
811 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
812 * @retval None
813 */
LL_DAC_SetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputBuffer)814 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
815 {
816 MODIFY_REG(DACx->CR,
817 DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
818 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
819 }
820
821 /**
822 * @brief Get the output buffer state for the selected DAC channel.
823 * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
824 * CR BOFF2 LL_DAC_GetOutputBuffer
825 * @param DACx DAC instance
826 * @param DAC_Channel This parameter can be one of the following values:
827 * @arg @ref LL_DAC_CHANNEL_1
828 * @arg @ref LL_DAC_CHANNEL_2 (1)
829 *
830 * (1) On this STM32 serie, parameter not available on all devices.
831 * Refer to device datasheet for channels availability.
832 * @retval Returned value can be one of the following values:
833 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
834 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
835 */
LL_DAC_GetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel)836 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
837 {
838 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
839 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
840 );
841 }
842
843 /**
844 * @}
845 */
846
847 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
848 * @{
849 */
850
851 /**
852 * @brief Enable DAC DMA transfer request of the selected channel.
853 * @note To configure DMA source address (peripheral address),
854 * use function @ref LL_DAC_DMA_GetRegAddr().
855 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
856 * CR DMAEN2 LL_DAC_EnableDMAReq
857 * @param DACx DAC instance
858 * @param DAC_Channel This parameter can be one of the following values:
859 * @arg @ref LL_DAC_CHANNEL_1
860 * @arg @ref LL_DAC_CHANNEL_2 (1)
861 *
862 * (1) On this STM32 serie, parameter not available on all devices.
863 * Refer to device datasheet for channels availability.
864 * @retval None
865 */
LL_DAC_EnableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)866 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
867 {
868 SET_BIT(DACx->CR,
869 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
870 }
871
872 /**
873 * @brief Disable DAC DMA transfer request of the selected channel.
874 * @note To configure DMA source address (peripheral address),
875 * use function @ref LL_DAC_DMA_GetRegAddr().
876 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
877 * CR DMAEN2 LL_DAC_DisableDMAReq
878 * @param DACx DAC instance
879 * @param DAC_Channel This parameter can be one of the following values:
880 * @arg @ref LL_DAC_CHANNEL_1
881 * @arg @ref LL_DAC_CHANNEL_2 (1)
882 *
883 * (1) On this STM32 serie, parameter not available on all devices.
884 * Refer to device datasheet for channels availability.
885 * @retval None
886 */
LL_DAC_DisableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)887 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
888 {
889 CLEAR_BIT(DACx->CR,
890 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
891 }
892
893 /**
894 * @brief Get DAC DMA transfer request state of the selected channel.
895 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
896 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
897 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
898 * @param DACx DAC instance
899 * @param DAC_Channel This parameter can be one of the following values:
900 * @arg @ref LL_DAC_CHANNEL_1
901 * @arg @ref LL_DAC_CHANNEL_2 (1)
902 *
903 * (1) On this STM32 serie, parameter not available on all devices.
904 * Refer to device datasheet for channels availability.
905 * @retval State of bit (1 or 0).
906 */
LL_DAC_IsDMAReqEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)907 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
908 {
909 return ((READ_BIT(DACx->CR,
910 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
911 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
912 }
913
914 /**
915 * @brief Function to help to configure DMA transfer to DAC: retrieve the
916 * DAC register address from DAC instance and a list of DAC registers
917 * intended to be used (most commonly) with DMA transfer.
918 * @note These DAC registers are data holding registers:
919 * when DAC conversion is requested, DAC generates a DMA transfer
920 * request to have data available in DAC data holding registers.
921 * @note This macro is intended to be used with LL DMA driver, refer to
922 * function "LL_DMA_ConfigAddresses()".
923 * Example:
924 * LL_DMA_ConfigAddresses(DMA1,
925 * LL_DMA_CHANNEL_1,
926 * (uint32_t)&< array or variable >,
927 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
928 * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
929 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
930 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
931 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
932 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
933 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
934 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
935 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
936 * @param DACx DAC instance
937 * @param DAC_Channel This parameter can be one of the following values:
938 * @arg @ref LL_DAC_CHANNEL_1
939 * @arg @ref LL_DAC_CHANNEL_2 (1)
940 *
941 * (1) On this STM32 serie, parameter not available on all devices.
942 * Refer to device datasheet for channels availability.
943 * @param Register This parameter can be one of the following values:
944 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
945 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
946 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
947 * @retval DAC register address
948 */
LL_DAC_DMA_GetRegAddr(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Register)949 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
950 {
951 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
952 /* DAC channel selected. */
953 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
954 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
955 }
956 /**
957 * @}
958 */
959
960 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
961 * @{
962 */
963
964 /**
965 * @brief Enable DAC selected channel.
966 * @rmtoll CR EN1 LL_DAC_Enable\n
967 * CR EN2 LL_DAC_Enable
968 * @note After enable from off state, DAC channel requires a delay
969 * for output voltage to reach accuracy +/- 1 LSB.
970 * Refer to device datasheet, parameter "tWAKEUP".
971 * @param DACx DAC instance
972 * @param DAC_Channel This parameter can be one of the following values:
973 * @arg @ref LL_DAC_CHANNEL_1
974 * @arg @ref LL_DAC_CHANNEL_2 (1)
975 *
976 * (1) On this STM32 serie, parameter not available on all devices.
977 * Refer to device datasheet for channels availability.
978 * @retval None
979 */
LL_DAC_Enable(DAC_TypeDef * DACx,uint32_t DAC_Channel)980 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
981 {
982 SET_BIT(DACx->CR,
983 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
984 }
985
986 /**
987 * @brief Disable DAC selected channel.
988 * @rmtoll CR EN1 LL_DAC_Disable\n
989 * CR EN2 LL_DAC_Disable
990 * @param DACx DAC instance
991 * @param DAC_Channel This parameter can be one of the following values:
992 * @arg @ref LL_DAC_CHANNEL_1
993 * @arg @ref LL_DAC_CHANNEL_2 (1)
994 *
995 * (1) On this STM32 serie, parameter not available on all devices.
996 * Refer to device datasheet for channels availability.
997 * @retval None
998 */
LL_DAC_Disable(DAC_TypeDef * DACx,uint32_t DAC_Channel)999 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1000 {
1001 CLEAR_BIT(DACx->CR,
1002 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1003 }
1004
1005 /**
1006 * @brief Get DAC enable state of the selected channel.
1007 * (0: DAC channel is disabled, 1: DAC channel is enabled)
1008 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
1009 * CR EN2 LL_DAC_IsEnabled
1010 * @param DACx DAC instance
1011 * @param DAC_Channel This parameter can be one of the following values:
1012 * @arg @ref LL_DAC_CHANNEL_1
1013 * @arg @ref LL_DAC_CHANNEL_2 (1)
1014 *
1015 * (1) On this STM32 serie, parameter not available on all devices.
1016 * Refer to device datasheet for channels availability.
1017 * @retval State of bit (1 or 0).
1018 */
LL_DAC_IsEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)1019 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1020 {
1021 return ((READ_BIT(DACx->CR,
1022 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1023 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1024 }
1025
1026 /**
1027 * @brief Enable DAC trigger of the selected channel.
1028 * @note - If DAC trigger is disabled, DAC conversion is performed
1029 * automatically once the data holding register is updated,
1030 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1031 * @ref LL_DAC_ConvertData12RightAligned(), ...
1032 * - If DAC trigger is enabled, DAC conversion is performed
1033 * only when a hardware of software trigger event is occurring.
1034 * Select trigger source using
1035 * function @ref LL_DAC_SetTriggerSource().
1036 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
1037 * CR TEN2 LL_DAC_EnableTrigger
1038 * @param DACx DAC instance
1039 * @param DAC_Channel This parameter can be one of the following values:
1040 * @arg @ref LL_DAC_CHANNEL_1
1041 * @arg @ref LL_DAC_CHANNEL_2 (1)
1042 *
1043 * (1) On this STM32 serie, parameter not available on all devices.
1044 * Refer to device datasheet for channels availability.
1045 * @retval None
1046 */
LL_DAC_EnableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1047 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1048 {
1049 SET_BIT(DACx->CR,
1050 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1051 }
1052
1053 /**
1054 * @brief Disable DAC trigger of the selected channel.
1055 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
1056 * CR TEN2 LL_DAC_DisableTrigger
1057 * @param DACx DAC instance
1058 * @param DAC_Channel This parameter can be one of the following values:
1059 * @arg @ref LL_DAC_CHANNEL_1
1060 * @arg @ref LL_DAC_CHANNEL_2 (1)
1061 *
1062 * (1) On this STM32 serie, parameter not available on all devices.
1063 * Refer to device datasheet for channels availability.
1064 * @retval None
1065 */
LL_DAC_DisableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1066 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1067 {
1068 CLEAR_BIT(DACx->CR,
1069 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1070 }
1071
1072 /**
1073 * @brief Get DAC trigger state of the selected channel.
1074 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
1075 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
1076 * CR TEN2 LL_DAC_IsTriggerEnabled
1077 * @param DACx DAC instance
1078 * @param DAC_Channel This parameter can be one of the following values:
1079 * @arg @ref LL_DAC_CHANNEL_1
1080 * @arg @ref LL_DAC_CHANNEL_2 (1)
1081 *
1082 * (1) On this STM32 serie, parameter not available on all devices.
1083 * Refer to device datasheet for channels availability.
1084 * @retval State of bit (1 or 0).
1085 */
LL_DAC_IsTriggerEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)1086 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1087 {
1088 return ((READ_BIT(DACx->CR,
1089 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1090 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1091 }
1092
1093 /**
1094 * @brief Trig DAC conversion by software for the selected DAC channel.
1095 * @note Preliminarily, DAC trigger must be set to software trigger
1096 * using function
1097 * @ref LL_DAC_Init()
1098 * @ref LL_DAC_SetTriggerSource()
1099 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
1100 * and DAC trigger must be enabled using
1101 * function @ref LL_DAC_EnableTrigger().
1102 * @note For devices featuring DAC with 2 channels: this function
1103 * can perform a SW start of both DAC channels simultaneously.
1104 * Two channels can be selected as parameter.
1105 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
1106 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
1107 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
1108 * @param DACx DAC instance
1109 * @param DAC_Channel This parameter can a combination of the following values:
1110 * @arg @ref LL_DAC_CHANNEL_1
1111 * @arg @ref LL_DAC_CHANNEL_2 (1)
1112 *
1113 * (1) On this STM32 serie, parameter not available on all devices.
1114 * Refer to device datasheet for channels availability.
1115 * @retval None
1116 */
LL_DAC_TrigSWConversion(DAC_TypeDef * DACx,uint32_t DAC_Channel)1117 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1118 {
1119 SET_BIT(DACx->SWTRIGR,
1120 (DAC_Channel & DAC_SWTR_CHX_MASK));
1121 }
1122
1123 /**
1124 * @brief Set the data to be loaded in the data holding register
1125 * in format 12 bits left alignment (LSB aligned on bit 0),
1126 * for the selected DAC channel.
1127 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
1128 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
1129 * @param DACx DAC instance
1130 * @param DAC_Channel This parameter can be one of the following values:
1131 * @arg @ref LL_DAC_CHANNEL_1
1132 * @arg @ref LL_DAC_CHANNEL_2 (1)
1133 *
1134 * (1) On this STM32 serie, parameter not available on all devices.
1135 * Refer to device datasheet for channels availability.
1136 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1137 * @retval None
1138 */
LL_DAC_ConvertData12RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1139 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1140 {
1141 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
1142 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1143
1144 MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
1145 }
1146
1147 /**
1148 * @brief Set the data to be loaded in the data holding register
1149 * in format 12 bits left alignment (MSB aligned on bit 15),
1150 * for the selected DAC channel.
1151 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
1152 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
1153 * @param DACx DAC instance
1154 * @param DAC_Channel This parameter can be one of the following values:
1155 * @arg @ref LL_DAC_CHANNEL_1
1156 * @arg @ref LL_DAC_CHANNEL_2 (1)
1157 *
1158 * (1) On this STM32 serie, parameter not available on all devices.
1159 * Refer to device datasheet for channels availability.
1160 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1161 * @retval None
1162 */
LL_DAC_ConvertData12LeftAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1163 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1164 {
1165 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
1166 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1167
1168 MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
1169 }
1170
1171 /**
1172 * @brief Set the data to be loaded in the data holding register
1173 * in format 8 bits left alignment (LSB aligned on bit 0),
1174 * for the selected DAC channel.
1175 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
1176 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
1177 * @param DACx DAC instance
1178 * @param DAC_Channel This parameter can be one of the following values:
1179 * @arg @ref LL_DAC_CHANNEL_1
1180 * @arg @ref LL_DAC_CHANNEL_2 (1)
1181 *
1182 * (1) On this STM32 serie, parameter not available on all devices.
1183 * Refer to device datasheet for channels availability.
1184 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1185 * @retval None
1186 */
LL_DAC_ConvertData8RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1187 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1188 {
1189 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
1190 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1191
1192 MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
1193 }
1194
1195 #if defined(DAC_CHANNEL2_SUPPORT)
1196 /**
1197 * @brief Set the data to be loaded in the data holding register
1198 * in format 12 bits left alignment (LSB aligned on bit 0),
1199 * for both DAC channels.
1200 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
1201 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
1202 * @param DACx DAC instance
1203 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1204 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1205 * @retval None
1206 */
LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1207 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1208 uint32_t DataChannel2)
1209 {
1210 MODIFY_REG(DACx->DHR12RD,
1211 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
1212 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1213 }
1214
1215 /**
1216 * @brief Set the data to be loaded in the data holding register
1217 * in format 12 bits left alignment (MSB aligned on bit 15),
1218 * for both DAC channels.
1219 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
1220 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
1221 * @param DACx DAC instance
1222 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1223 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1224 * @retval None
1225 */
LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1226 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1227 uint32_t DataChannel2)
1228 {
1229 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
1230 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
1231 /* the 4 LSB must be taken into account for the shift value. */
1232 MODIFY_REG(DACx->DHR12LD,
1233 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
1234 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
1235 }
1236
1237 /**
1238 * @brief Set the data to be loaded in the data holding register
1239 * in format 8 bits left alignment (LSB aligned on bit 0),
1240 * for both DAC channels.
1241 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
1242 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
1243 * @param DACx DAC instance
1244 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
1245 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
1246 * @retval None
1247 */
LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1248 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1249 uint32_t DataChannel2)
1250 {
1251 MODIFY_REG(DACx->DHR8RD,
1252 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
1253 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1254 }
1255 #endif /* DAC_CHANNEL2_SUPPORT */
1256
1257 /**
1258 * @brief Retrieve output data currently generated for the selected DAC channel.
1259 * @note Whatever alignment and resolution settings
1260 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1261 * @ref LL_DAC_ConvertData12RightAligned(), ...),
1262 * output data format is 12 bits right aligned (LSB aligned on bit 0).
1263 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
1264 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
1265 * @param DACx DAC instance
1266 * @param DAC_Channel This parameter can be one of the following values:
1267 * @arg @ref LL_DAC_CHANNEL_1
1268 * @arg @ref LL_DAC_CHANNEL_2 (1)
1269 *
1270 * (1) On this STM32 serie, parameter not available on all devices.
1271 * Refer to device datasheet for channels availability.
1272 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1273 */
LL_DAC_RetrieveOutputData(DAC_TypeDef * DACx,uint32_t DAC_Channel)1274 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1275 {
1276 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
1277 & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
1278
1279 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1280 }
1281
1282 /**
1283 * @}
1284 */
1285
1286 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
1287 * @{
1288 */
1289
1290 /**
1291 * @brief Get DAC underrun flag for DAC channel 1
1292 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
1293 * @param DACx DAC instance
1294 * @retval State of bit (1 or 0).
1295 */
LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef * DACx)1296 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
1297 {
1298 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
1299 }
1300
1301 #if defined(DAC_CHANNEL2_SUPPORT)
1302 /**
1303 * @brief Get DAC underrun flag for DAC channel 2
1304 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
1305 * @param DACx DAC instance
1306 * @retval State of bit (1 or 0).
1307 */
LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef * DACx)1308 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
1309 {
1310 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
1311 }
1312 #endif /* DAC_CHANNEL2_SUPPORT */
1313
1314 /**
1315 * @brief Clear DAC underrun flag for DAC channel 1
1316 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
1317 * @param DACx DAC instance
1318 * @retval None
1319 */
LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef * DACx)1320 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1321 {
1322 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1323 }
1324
1325 #if defined(DAC_CHANNEL2_SUPPORT)
1326 /**
1327 * @brief Clear DAC underrun flag for DAC channel 2
1328 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
1329 * @param DACx DAC instance
1330 * @retval None
1331 */
LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef * DACx)1332 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1333 {
1334 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1335 }
1336 #endif /* DAC_CHANNEL2_SUPPORT */
1337
1338 /**
1339 * @}
1340 */
1341
1342 /** @defgroup DAC_LL_EF_IT_Management IT management
1343 * @{
1344 */
1345
1346 /**
1347 * @brief Enable DMA underrun interrupt for DAC channel 1
1348 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
1349 * @param DACx DAC instance
1350 * @retval None
1351 */
LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef * DACx)1352 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1353 {
1354 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1355 }
1356
1357 #if defined(DAC_CHANNEL2_SUPPORT)
1358 /**
1359 * @brief Enable DMA underrun interrupt for DAC channel 2
1360 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
1361 * @param DACx DAC instance
1362 * @retval None
1363 */
LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef * DACx)1364 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1365 {
1366 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1367 }
1368 #endif /* DAC_CHANNEL2_SUPPORT */
1369
1370 /**
1371 * @brief Disable DMA underrun interrupt for DAC channel 1
1372 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
1373 * @param DACx DAC instance
1374 * @retval None
1375 */
LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef * DACx)1376 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1377 {
1378 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1379 }
1380
1381 #if defined(DAC_CHANNEL2_SUPPORT)
1382 /**
1383 * @brief Disable DMA underrun interrupt for DAC channel 2
1384 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
1385 * @param DACx DAC instance
1386 * @retval None
1387 */
LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef * DACx)1388 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1389 {
1390 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1391 }
1392 #endif /* DAC_CHANNEL2_SUPPORT */
1393
1394 /**
1395 * @brief Get DMA underrun interrupt for DAC channel 1
1396 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
1397 * @param DACx DAC instance
1398 * @retval State of bit (1 or 0).
1399 */
LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef * DACx)1400 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
1401 {
1402 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
1403 }
1404
1405 #if defined(DAC_CHANNEL2_SUPPORT)
1406 /**
1407 * @brief Get DMA underrun interrupt for DAC channel 2
1408 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
1409 * @param DACx DAC instance
1410 * @retval State of bit (1 or 0).
1411 */
LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef * DACx)1412 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
1413 {
1414 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
1415 }
1416 #endif /* DAC_CHANNEL2_SUPPORT */
1417
1418 /**
1419 * @}
1420 */
1421
1422 #if defined(USE_FULL_LL_DRIVER)
1423 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
1424 * @{
1425 */
1426
1427 ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
1428 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);
1429 void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
1430
1431 /**
1432 * @}
1433 */
1434 #endif /* USE_FULL_LL_DRIVER */
1435
1436 /**
1437 * @}
1438 */
1439
1440 /**
1441 * @}
1442 */
1443
1444 #endif /* DAC */
1445
1446 /**
1447 * @}
1448 */
1449
1450 #ifdef __cplusplus
1451 }
1452 #endif
1453
1454 #endif /* STM32F4xx_LL_DAC_H */
1455
1456
