1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_hal_tim.h 4 * @author MCD Application Team 5 * @brief Header file of TIM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32F4xx_HAL_TIM_H 21 #define STM32F4xx_HAL_TIM_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f4xx_hal_def.h" 29 30 /** @addtogroup STM32F4xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup TIM 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup TIM_Exported_Types TIM Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief TIM Time base Configuration Structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 49 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 50 51 uint32_t CounterMode; /*!< Specifies the counter mode. 52 This parameter can be a value of @ref TIM_Counter_Mode */ 53 54 uint32_t Period; /*!< Specifies the period value to be loaded into the active 55 Auto-Reload Register at the next update event. 56 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 57 58 uint32_t ClockDivision; /*!< Specifies the clock division. 59 This parameter can be a value of @ref TIM_ClockDivision */ 60 61 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 62 reaches zero, an update event is generated and counting restarts 63 from the RCR value (N). 64 This means in PWM mode that (N+1) corresponds to: 65 - the number of PWM periods in edge-aligned mode 66 - the number of half PWM period in center-aligned mode 67 GP timers: this parameter must be a number between Min_Data = 0x00 and 68 Max_Data = 0xFF. 69 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and 70 Max_Data = 0xFFFF. */ 71 72 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. 73 This parameter can be a value of @ref TIM_AutoReloadPreload */ 74 } TIM_Base_InitTypeDef; 75 76 /** 77 * @brief TIM Output Compare Configuration Structure definition 78 */ 79 typedef struct 80 { 81 uint32_t OCMode; /*!< Specifies the TIM mode. 82 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 83 84 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 85 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 86 87 uint32_t OCPolarity; /*!< Specifies the output polarity. 88 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 89 90 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 91 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 92 @note This parameter is valid only for timer instances supporting break feature. */ 93 94 uint32_t OCFastMode; /*!< Specifies the Fast mode state. 95 This parameter can be a value of @ref TIM_Output_Fast_State 96 @note This parameter is valid only in PWM1 and PWM2 mode. */ 97 98 99 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 100 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 101 @note This parameter is valid only for timer instances supporting break feature. */ 102 103 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 104 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 105 @note This parameter is valid only for timer instances supporting break feature. */ 106 } TIM_OC_InitTypeDef; 107 108 /** 109 * @brief TIM One Pulse Mode Configuration Structure definition 110 */ 111 typedef struct 112 { 113 uint32_t OCMode; /*!< Specifies the TIM mode. 114 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 115 116 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 117 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 118 119 uint32_t OCPolarity; /*!< Specifies the output polarity. 120 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 121 122 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 123 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 124 @note This parameter is valid only for timer instances supporting break feature. */ 125 126 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 127 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 128 @note This parameter is valid only for timer instances supporting break feature. */ 129 130 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 131 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 132 @note This parameter is valid only for timer instances supporting break feature. */ 133 134 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 135 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 136 137 uint32_t ICSelection; /*!< Specifies the input. 138 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 139 140 uint32_t ICFilter; /*!< Specifies the input capture filter. 141 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 142 } TIM_OnePulse_InitTypeDef; 143 144 /** 145 * @brief TIM Input Capture Configuration Structure definition 146 */ 147 typedef struct 148 { 149 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 150 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 151 152 uint32_t ICSelection; /*!< Specifies the input. 153 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 154 155 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 156 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 157 158 uint32_t ICFilter; /*!< Specifies the input capture filter. 159 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 160 } TIM_IC_InitTypeDef; 161 162 /** 163 * @brief TIM Encoder Configuration Structure definition 164 */ 165 typedef struct 166 { 167 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. 168 This parameter can be a value of @ref TIM_Encoder_Mode */ 169 170 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. 171 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ 172 173 uint32_t IC1Selection; /*!< Specifies the input. 174 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 175 176 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. 177 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 178 179 uint32_t IC1Filter; /*!< Specifies the input capture filter. 180 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 181 182 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. 183 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ 184 185 uint32_t IC2Selection; /*!< Specifies the input. 186 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 187 188 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. 189 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 190 191 uint32_t IC2Filter; /*!< Specifies the input capture filter. 192 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 193 } TIM_Encoder_InitTypeDef; 194 195 /** 196 * @brief Clock Configuration Handle Structure definition 197 */ 198 typedef struct 199 { 200 uint32_t ClockSource; /*!< TIM clock sources 201 This parameter can be a value of @ref TIM_Clock_Source */ 202 uint32_t ClockPolarity; /*!< TIM clock polarity 203 This parameter can be a value of @ref TIM_Clock_Polarity */ 204 uint32_t ClockPrescaler; /*!< TIM clock prescaler 205 This parameter can be a value of @ref TIM_Clock_Prescaler */ 206 uint32_t ClockFilter; /*!< TIM clock filter 207 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 208 } TIM_ClockConfigTypeDef; 209 210 /** 211 * @brief TIM Clear Input Configuration Handle Structure definition 212 */ 213 typedef struct 214 { 215 uint32_t ClearInputState; /*!< TIM clear Input state 216 This parameter can be ENABLE or DISABLE */ 217 uint32_t ClearInputSource; /*!< TIM clear Input sources 218 This parameter can be a value of @ref TIM_ClearInput_Source */ 219 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity 220 This parameter can be a value of @ref TIM_ClearInput_Polarity */ 221 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler 222 This parameter must be 0: When OCRef clear feature is used with ETR source, 223 ETR prescaler must be off */ 224 uint32_t ClearInputFilter; /*!< TIM Clear Input filter 225 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 226 } TIM_ClearInputConfigTypeDef; 227 228 /** 229 * @brief TIM Master configuration Structure definition 230 */ 231 typedef struct 232 { 233 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection 234 This parameter can be a value of @ref TIM_Master_Mode_Selection */ 235 uint32_t MasterSlaveMode; /*!< Master/slave mode selection 236 This parameter can be a value of @ref TIM_Master_Slave_Mode 237 @note When the Master/slave mode is enabled, the effect of 238 an event on the trigger input (TRGI) is delayed to allow a 239 perfect synchronization between the current timer and its 240 slaves (through TRGO). It is not mandatory in case of timer 241 synchronization mode. */ 242 } TIM_MasterConfigTypeDef; 243 244 /** 245 * @brief TIM Slave configuration Structure definition 246 */ 247 typedef struct 248 { 249 uint32_t SlaveMode; /*!< Slave mode selection 250 This parameter can be a value of @ref TIM_Slave_Mode */ 251 uint32_t InputTrigger; /*!< Input Trigger source 252 This parameter can be a value of @ref TIM_Trigger_Selection */ 253 uint32_t TriggerPolarity; /*!< Input Trigger polarity 254 This parameter can be a value of @ref TIM_Trigger_Polarity */ 255 uint32_t TriggerPrescaler; /*!< Input trigger prescaler 256 This parameter can be a value of @ref TIM_Trigger_Prescaler */ 257 uint32_t TriggerFilter; /*!< Input trigger filter 258 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 259 260 } TIM_SlaveConfigTypeDef; 261 262 /** 263 * @brief TIM Break input(s) and Dead time configuration Structure definition 264 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable 265 * filter and polarity. 266 */ 267 typedef struct 268 { 269 uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ 270 271 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ 272 273 uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ 274 275 uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 276 277 uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ 278 279 uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ 280 281 uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 282 283 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ 284 285 } TIM_BreakDeadTimeConfigTypeDef; 286 287 /** 288 * @brief HAL State structures definition 289 */ 290 typedef enum 291 { 292 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ 293 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 294 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 295 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 296 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ 297 } HAL_TIM_StateTypeDef; 298 299 /** 300 * @brief TIM Channel States definition 301 */ 302 typedef enum 303 { 304 HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ 305 HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ 306 HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ 307 } HAL_TIM_ChannelStateTypeDef; 308 309 /** 310 * @brief DMA Burst States definition 311 */ 312 typedef enum 313 { 314 HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ 315 HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ 316 HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ 317 } HAL_TIM_DMABurstStateTypeDef; 318 319 /** 320 * @brief HAL Active channel structures definition 321 */ 322 typedef enum 323 { 324 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ 325 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ 326 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ 327 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ 328 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ 329 } HAL_TIM_ActiveChannel; 330 331 /** 332 * @brief TIM Time Base Handle Structure definition 333 */ 334 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 335 typedef struct __TIM_HandleTypeDef 336 #else 337 typedef struct 338 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 339 { 340 TIM_TypeDef *Instance; /*!< Register base address */ 341 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ 342 HAL_TIM_ActiveChannel Channel; /*!< Active channel */ 343 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array 344 This array is accessed by a @ref DMA_Handle_index */ 345 HAL_LockTypeDef Lock; /*!< Locking object */ 346 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ 347 __IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */ 348 __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ 349 __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ 350 351 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 352 void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ 353 void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ 354 void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ 355 void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ 356 void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ 357 void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ 358 void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ 359 void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ 360 void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ 361 void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ 362 void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ 363 void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ 364 void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ 365 void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ 366 void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ 367 void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ 368 void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ 369 void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ 370 void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ 371 void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ 372 void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ 373 void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ 374 void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ 375 void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ 376 void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ 377 void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ 378 void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ 379 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 380 } TIM_HandleTypeDef; 381 382 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 383 /** 384 * @brief HAL TIM Callback ID enumeration definition 385 */ 386 typedef enum 387 { 388 HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ 389 , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ 390 , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ 391 , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ 392 , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ 393 , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ 394 , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ 395 , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ 396 , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ 397 , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ 398 , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ 399 , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ 400 , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ 401 , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ 402 , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ 403 , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ 404 , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ 405 , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ 406 407 , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ 408 , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ 409 , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ 410 , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ 411 , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ 412 , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ 413 , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ 414 , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ 415 , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ 416 } HAL_TIM_CallbackIDTypeDef; 417 418 /** 419 * @brief HAL TIM Callback pointer definition 420 */ 421 typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ 422 423 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 424 425 /** 426 * @} 427 */ 428 /* End of exported types -----------------------------------------------------*/ 429 430 /* Exported constants --------------------------------------------------------*/ 431 /** @defgroup TIM_Exported_Constants TIM Exported Constants 432 * @{ 433 */ 434 435 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source 436 * @{ 437 */ 438 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ 439 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ 440 /** 441 * @} 442 */ 443 444 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address 445 * @{ 446 */ 447 #define TIM_DMABASE_CR1 0x00000000U 448 #define TIM_DMABASE_CR2 0x00000001U 449 #define TIM_DMABASE_SMCR 0x00000002U 450 #define TIM_DMABASE_DIER 0x00000003U 451 #define TIM_DMABASE_SR 0x00000004U 452 #define TIM_DMABASE_EGR 0x00000005U 453 #define TIM_DMABASE_CCMR1 0x00000006U 454 #define TIM_DMABASE_CCMR2 0x00000007U 455 #define TIM_DMABASE_CCER 0x00000008U 456 #define TIM_DMABASE_CNT 0x00000009U 457 #define TIM_DMABASE_PSC 0x0000000AU 458 #define TIM_DMABASE_ARR 0x0000000BU 459 #define TIM_DMABASE_RCR 0x0000000CU 460 #define TIM_DMABASE_CCR1 0x0000000DU 461 #define TIM_DMABASE_CCR2 0x0000000EU 462 #define TIM_DMABASE_CCR3 0x0000000FU 463 #define TIM_DMABASE_CCR4 0x00000010U 464 #define TIM_DMABASE_BDTR 0x00000011U 465 #define TIM_DMABASE_DCR 0x00000012U 466 #define TIM_DMABASE_DMAR 0x00000013U 467 /** 468 * @} 469 */ 470 471 /** @defgroup TIM_Event_Source TIM Event Source 472 * @{ 473 */ 474 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ 475 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ 476 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ 477 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ 478 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ 479 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ 480 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ 481 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ 482 /** 483 * @} 484 */ 485 486 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity 487 * @{ 488 */ 489 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ 490 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ 491 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ 492 /** 493 * @} 494 */ 495 496 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity 497 * @{ 498 */ 499 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ 500 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ 501 /** 502 * @} 503 */ 504 505 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler 506 * @{ 507 */ 508 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ 509 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ 510 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ 511 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ 512 /** 513 * @} 514 */ 515 516 /** @defgroup TIM_Counter_Mode TIM Counter Mode 517 * @{ 518 */ 519 #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ 520 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ 521 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ 522 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ 523 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ 524 /** 525 * @} 526 */ 527 528 /** @defgroup TIM_ClockDivision TIM Clock Division 529 * @{ 530 */ 531 #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ 532 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ 533 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ 534 /** 535 * @} 536 */ 537 538 /** @defgroup TIM_Output_Compare_State TIM Output Compare State 539 * @{ 540 */ 541 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ 542 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ 543 /** 544 * @} 545 */ 546 547 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload 548 * @{ 549 */ 550 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ 551 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ 552 553 /** 554 * @} 555 */ 556 557 /** @defgroup TIM_Output_Fast_State TIM Output Fast State 558 * @{ 559 */ 560 #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ 561 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ 562 /** 563 * @} 564 */ 565 566 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State 567 * @{ 568 */ 569 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ 570 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ 571 /** 572 * @} 573 */ 574 575 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity 576 * @{ 577 */ 578 #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ 579 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ 580 /** 581 * @} 582 */ 583 584 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity 585 * @{ 586 */ 587 #define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ 588 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ 589 /** 590 * @} 591 */ 592 593 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State 594 * @{ 595 */ 596 #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ 597 #define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ 598 /** 599 * @} 600 */ 601 602 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State 603 * @{ 604 */ 605 #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ 606 #define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ 607 /** 608 * @} 609 */ 610 611 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity 612 * @{ 613 */ 614 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ 615 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ 616 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ 617 /** 618 * @} 619 */ 620 621 /** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity 622 * @{ 623 */ 624 #define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ 625 #define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ 626 /** 627 * @} 628 */ 629 630 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection 631 * @{ 632 */ 633 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ 634 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ 635 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ 636 /** 637 * @} 638 */ 639 640 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler 641 * @{ 642 */ 643 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ 644 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ 645 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ 646 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ 647 /** 648 * @} 649 */ 650 651 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode 652 * @{ 653 */ 654 #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ 655 #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ 656 /** 657 * @} 658 */ 659 660 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode 661 * @{ 662 */ 663 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ 664 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ 665 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ 666 /** 667 * @} 668 */ 669 670 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition 671 * @{ 672 */ 673 #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ 674 #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ 675 #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ 676 #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ 677 #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ 678 #define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ 679 #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ 680 #define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ 681 /** 682 * @} 683 */ 684 685 /** @defgroup TIM_Commutation_Source TIM Commutation Source 686 * @{ 687 */ 688 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ 689 #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ 690 /** 691 * @} 692 */ 693 694 /** @defgroup TIM_DMA_sources TIM DMA Sources 695 * @{ 696 */ 697 #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ 698 #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ 699 #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ 700 #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ 701 #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ 702 #define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ 703 #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ 704 /** 705 * @} 706 */ 707 708 /** @defgroup TIM_CC_DMA_Request CCx DMA request selection 709 * @{ 710 */ 711 #define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */ 712 #define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ 713 /** 714 * @} 715 */ 716 717 /** @defgroup TIM_Flag_definition TIM Flag Definition 718 * @{ 719 */ 720 #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ 721 #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ 722 #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ 723 #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ 724 #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ 725 #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ 726 #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ 727 #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ 728 #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ 729 #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ 730 #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ 731 #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ 732 /** 733 * @} 734 */ 735 736 /** @defgroup TIM_Channel TIM Channel 737 * @{ 738 */ 739 #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ 740 #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ 741 #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ 742 #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ 743 #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ 744 /** 745 * @} 746 */ 747 748 /** @defgroup TIM_Clock_Source TIM Clock Source 749 * @{ 750 */ 751 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ 752 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ 753 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ 754 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ 755 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ 756 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ 757 #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ 758 #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ 759 #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ 760 #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ 761 /** 762 * @} 763 */ 764 765 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity 766 * @{ 767 */ 768 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ 769 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ 770 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ 771 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ 772 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ 773 /** 774 * @} 775 */ 776 777 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler 778 * @{ 779 */ 780 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 781 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ 782 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ 783 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ 784 /** 785 * @} 786 */ 787 788 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity 789 * @{ 790 */ 791 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ 792 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ 793 /** 794 * @} 795 */ 796 797 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler 798 * @{ 799 */ 800 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 801 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ 802 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ 803 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ 804 /** 805 * @} 806 */ 807 808 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state 809 * @{ 810 */ 811 #define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 812 #define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 813 /** 814 * @} 815 */ 816 817 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state 818 * @{ 819 */ 820 #define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 821 #define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 822 /** 823 * @} 824 */ 825 /** @defgroup TIM_Lock_level TIM Lock level 826 * @{ 827 */ 828 #define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ 829 #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ 830 #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ 831 #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ 832 /** 833 * @} 834 */ 835 836 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable 837 * @{ 838 */ 839 #define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ 840 #define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ 841 /** 842 * @} 843 */ 844 845 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity 846 * @{ 847 */ 848 #define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ 849 #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ 850 /** 851 * @} 852 */ 853 854 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable 855 * @{ 856 */ 857 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ 858 #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ 859 /** 860 * @} 861 */ 862 863 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection 864 * @{ 865 */ 866 #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ 867 #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ 868 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ 869 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ 870 #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ 871 #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ 872 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ 873 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ 874 /** 875 * @} 876 */ 877 878 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode 879 * @{ 880 */ 881 #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ 882 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ 883 /** 884 * @} 885 */ 886 887 /** @defgroup TIM_Slave_Mode TIM Slave mode 888 * @{ 889 */ 890 #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ 891 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ 892 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ 893 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ 894 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ 895 /** 896 * @} 897 */ 898 899 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes 900 * @{ 901 */ 902 #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ 903 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ 904 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ 905 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ 906 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ 907 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ 908 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ 909 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ 910 /** 911 * @} 912 */ 913 914 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection 915 * @{ 916 */ 917 #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ 918 #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ 919 #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ 920 #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ 921 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ 922 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ 923 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ 924 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ 925 #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ 926 /** 927 * @} 928 */ 929 930 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity 931 * @{ 932 */ 933 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ 934 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ 935 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 936 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 937 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 938 /** 939 * @} 940 */ 941 942 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler 943 * @{ 944 */ 945 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 946 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ 947 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ 948 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ 949 /** 950 * @} 951 */ 952 953 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection 954 * @{ 955 */ 956 #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ 957 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ 958 /** 959 * @} 960 */ 961 962 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length 963 * @{ 964 */ 965 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ 966 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 967 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 968 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 969 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 970 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 971 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 972 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 973 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 974 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 975 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 976 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 977 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 978 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 979 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 980 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 981 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 982 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 983 /** 984 * @} 985 */ 986 987 /** @defgroup DMA_Handle_index TIM DMA Handle Index 988 * @{ 989 */ 990 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ 991 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ 992 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ 993 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ 994 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ 995 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ 996 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ 997 /** 998 * @} 999 */ 1000 1001 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State 1002 * @{ 1003 */ 1004 #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ 1005 #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ 1006 #define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ 1007 #define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ 1008 /** 1009 * @} 1010 */ 1011 1012 /** 1013 * @} 1014 */ 1015 /* End of exported constants -------------------------------------------------*/ 1016 1017 /* Exported macros -----------------------------------------------------------*/ 1018 /** @defgroup TIM_Exported_Macros TIM Exported Macros 1019 * @{ 1020 */ 1021 1022 /** @brief Reset TIM handle state. 1023 * @param __HANDLE__ TIM handle. 1024 * @retval None 1025 */ 1026 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 1027 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 1028 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 1029 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1030 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1031 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1032 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1033 (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1034 (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1035 (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1036 (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1037 (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ 1038 (__HANDLE__)->Base_MspInitCallback = NULL; \ 1039 (__HANDLE__)->Base_MspDeInitCallback = NULL; \ 1040 (__HANDLE__)->IC_MspInitCallback = NULL; \ 1041 (__HANDLE__)->IC_MspDeInitCallback = NULL; \ 1042 (__HANDLE__)->OC_MspInitCallback = NULL; \ 1043 (__HANDLE__)->OC_MspDeInitCallback = NULL; \ 1044 (__HANDLE__)->PWM_MspInitCallback = NULL; \ 1045 (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ 1046 (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ 1047 (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ 1048 (__HANDLE__)->Encoder_MspInitCallback = NULL; \ 1049 (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ 1050 (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ 1051 (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ 1052 } while(0) 1053 #else 1054 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 1055 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 1056 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1057 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1058 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1059 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1060 (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1061 (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1062 (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1063 (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1064 (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ 1065 } while(0) 1066 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 1067 1068 /** 1069 * @brief Enable the TIM peripheral. 1070 * @param __HANDLE__ TIM handle 1071 * @retval None 1072 */ 1073 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) 1074 1075 /** 1076 * @brief Enable the TIM main Output. 1077 * @param __HANDLE__ TIM handle 1078 * @retval None 1079 */ 1080 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) 1081 1082 /** 1083 * @brief Disable the TIM peripheral. 1084 * @param __HANDLE__ TIM handle 1085 * @retval None 1086 */ 1087 #define __HAL_TIM_DISABLE(__HANDLE__) \ 1088 do { \ 1089 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 1090 { \ 1091 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 1092 { \ 1093 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ 1094 } \ 1095 } \ 1096 } while(0) 1097 1098 /** 1099 * @brief Disable the TIM main Output. 1100 * @param __HANDLE__ TIM handle 1101 * @retval None 1102 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been 1103 * disabled 1104 */ 1105 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ 1106 do { \ 1107 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 1108 { \ 1109 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 1110 { \ 1111 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ 1112 } \ 1113 } \ 1114 } while(0) 1115 1116 /** 1117 * @brief Disable the TIM main Output. 1118 * @param __HANDLE__ TIM handle 1119 * @retval None 1120 * @note The Main Output Enable of a timer instance is disabled unconditionally 1121 */ 1122 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) 1123 1124 /** @brief Enable the specified TIM interrupt. 1125 * @param __HANDLE__ specifies the TIM Handle. 1126 * @param __INTERRUPT__ specifies the TIM interrupt source to enable. 1127 * This parameter can be one of the following values: 1128 * @arg TIM_IT_UPDATE: Update interrupt 1129 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1130 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1131 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1132 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1133 * @arg TIM_IT_COM: Commutation interrupt 1134 * @arg TIM_IT_TRIGGER: Trigger interrupt 1135 * @arg TIM_IT_BREAK: Break interrupt 1136 * @retval None 1137 */ 1138 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) 1139 1140 /** @brief Disable the specified TIM interrupt. 1141 * @param __HANDLE__ specifies the TIM Handle. 1142 * @param __INTERRUPT__ specifies the TIM interrupt source to disable. 1143 * This parameter can be one of the following values: 1144 * @arg TIM_IT_UPDATE: Update interrupt 1145 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1146 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1147 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1148 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1149 * @arg TIM_IT_COM: Commutation interrupt 1150 * @arg TIM_IT_TRIGGER: Trigger interrupt 1151 * @arg TIM_IT_BREAK: Break interrupt 1152 * @retval None 1153 */ 1154 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) 1155 1156 /** @brief Enable the specified DMA request. 1157 * @param __HANDLE__ specifies the TIM Handle. 1158 * @param __DMA__ specifies the TIM DMA request to enable. 1159 * This parameter can be one of the following values: 1160 * @arg TIM_DMA_UPDATE: Update DMA request 1161 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 1162 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 1163 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 1164 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 1165 * @arg TIM_DMA_COM: Commutation DMA request 1166 * @arg TIM_DMA_TRIGGER: Trigger DMA request 1167 * @retval None 1168 */ 1169 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) 1170 1171 /** @brief Disable the specified DMA request. 1172 * @param __HANDLE__ specifies the TIM Handle. 1173 * @param __DMA__ specifies the TIM DMA request to disable. 1174 * This parameter can be one of the following values: 1175 * @arg TIM_DMA_UPDATE: Update DMA request 1176 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 1177 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 1178 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 1179 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 1180 * @arg TIM_DMA_COM: Commutation DMA request 1181 * @arg TIM_DMA_TRIGGER: Trigger DMA request 1182 * @retval None 1183 */ 1184 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) 1185 1186 /** @brief Check whether the specified TIM interrupt flag is set or not. 1187 * @param __HANDLE__ specifies the TIM Handle. 1188 * @param __FLAG__ specifies the TIM interrupt flag to check. 1189 * This parameter can be one of the following values: 1190 * @arg TIM_FLAG_UPDATE: Update interrupt flag 1191 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 1192 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 1193 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 1194 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 1195 * @arg TIM_FLAG_COM: Commutation interrupt flag 1196 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 1197 * @arg TIM_FLAG_BREAK: Break interrupt flag 1198 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1199 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1200 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1201 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1202 * @retval The new state of __FLAG__ (TRUE or FALSE). 1203 */ 1204 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) 1205 1206 /** @brief Clear the specified TIM interrupt flag. 1207 * @param __HANDLE__ specifies the TIM Handle. 1208 * @param __FLAG__ specifies the TIM interrupt flag to clear. 1209 * This parameter can be one of the following values: 1210 * @arg TIM_FLAG_UPDATE: Update interrupt flag 1211 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 1212 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 1213 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 1214 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 1215 * @arg TIM_FLAG_COM: Commutation interrupt flag 1216 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 1217 * @arg TIM_FLAG_BREAK: Break interrupt flag 1218 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1219 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1220 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1221 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1222 * @retval The new state of __FLAG__ (TRUE or FALSE). 1223 */ 1224 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) 1225 1226 /** 1227 * @brief Check whether the specified TIM interrupt source is enabled or not. 1228 * @param __HANDLE__ TIM handle 1229 * @param __INTERRUPT__ specifies the TIM interrupt source to check. 1230 * This parameter can be one of the following values: 1231 * @arg TIM_IT_UPDATE: Update interrupt 1232 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1233 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1234 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1235 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1236 * @arg TIM_IT_COM: Commutation interrupt 1237 * @arg TIM_IT_TRIGGER: Trigger interrupt 1238 * @arg TIM_IT_BREAK: Break interrupt 1239 * @retval The state of TIM_IT (SET or RESET). 1240 */ 1241 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ 1242 == (__INTERRUPT__)) ? SET : RESET) 1243 1244 /** @brief Clear the TIM interrupt pending bits. 1245 * @param __HANDLE__ TIM handle 1246 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1247 * This parameter can be one of the following values: 1248 * @arg TIM_IT_UPDATE: Update interrupt 1249 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1250 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1251 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1252 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1253 * @arg TIM_IT_COM: Commutation interrupt 1254 * @arg TIM_IT_TRIGGER: Trigger interrupt 1255 * @arg TIM_IT_BREAK: Break interrupt 1256 * @retval None 1257 */ 1258 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) 1259 1260 /** 1261 * @brief Indicates whether or not the TIM Counter is used as downcounter. 1262 * @param __HANDLE__ TIM handle. 1263 * @retval False (Counter used as upcounter) or True (Counter used as downcounter) 1264 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode 1265 * or Encoder mode. 1266 */ 1267 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) 1268 1269 /** 1270 * @brief Set the TIM Prescaler on runtime. 1271 * @param __HANDLE__ TIM handle. 1272 * @param __PRESC__ specifies the Prescaler new value. 1273 * @retval None 1274 */ 1275 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) 1276 1277 /** 1278 * @brief Set the TIM Counter Register value on runtime. 1279 * @param __HANDLE__ TIM handle. 1280 * @param __COUNTER__ specifies the Counter register new value. 1281 * @retval None 1282 */ 1283 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) 1284 1285 /** 1286 * @brief Get the TIM Counter Register value on runtime. 1287 * @param __HANDLE__ TIM handle. 1288 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) 1289 */ 1290 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) 1291 1292 /** 1293 * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. 1294 * @param __HANDLE__ TIM handle. 1295 * @param __AUTORELOAD__ specifies the Counter register new value. 1296 * @retval None 1297 */ 1298 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ 1299 do{ \ 1300 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ 1301 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ 1302 } while(0) 1303 1304 /** 1305 * @brief Get the TIM Autoreload Register value on runtime. 1306 * @param __HANDLE__ TIM handle. 1307 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) 1308 */ 1309 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) 1310 1311 /** 1312 * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. 1313 * @param __HANDLE__ TIM handle. 1314 * @param __CKD__ specifies the clock division value. 1315 * This parameter can be one of the following value: 1316 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1317 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1318 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1319 * @retval None 1320 */ 1321 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ 1322 do{ \ 1323 (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ 1324 (__HANDLE__)->Instance->CR1 |= (__CKD__); \ 1325 (__HANDLE__)->Init.ClockDivision = (__CKD__); \ 1326 } while(0) 1327 1328 /** 1329 * @brief Get the TIM Clock Division value on runtime. 1330 * @param __HANDLE__ TIM handle. 1331 * @retval The clock division can be one of the following values: 1332 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1333 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1334 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1335 */ 1336 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) 1337 1338 /** 1339 * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() 1340 * function. 1341 * @param __HANDLE__ TIM handle. 1342 * @param __CHANNEL__ TIM Channels to be configured. 1343 * This parameter can be one of the following values: 1344 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1345 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1346 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1347 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1348 * @param __ICPSC__ specifies the Input Capture4 prescaler new value. 1349 * This parameter can be one of the following values: 1350 * @arg TIM_ICPSC_DIV1: no prescaler 1351 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1352 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1353 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1354 * @retval None 1355 */ 1356 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ 1357 do{ \ 1358 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ 1359 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ 1360 } while(0) 1361 1362 /** 1363 * @brief Get the TIM Input Capture prescaler on runtime. 1364 * @param __HANDLE__ TIM handle. 1365 * @param __CHANNEL__ TIM Channels to be configured. 1366 * This parameter can be one of the following values: 1367 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value 1368 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value 1369 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value 1370 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value 1371 * @retval The input capture prescaler can be one of the following values: 1372 * @arg TIM_ICPSC_DIV1: no prescaler 1373 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1374 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1375 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1376 */ 1377 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ 1378 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ 1379 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ 1380 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ 1381 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) 1382 1383 /** 1384 * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. 1385 * @param __HANDLE__ TIM handle. 1386 * @param __CHANNEL__ TIM Channels to be configured. 1387 * This parameter can be one of the following values: 1388 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1389 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1390 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1391 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1392 * @param __COMPARE__ specifies the Capture Compare register new value. 1393 * @retval None 1394 */ 1395 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ 1396 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ 1397 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ 1398 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ 1399 ((__HANDLE__)->Instance->CCR4 = (__COMPARE__))) 1400 1401 /** 1402 * @brief Get the TIM Capture Compare Register value on runtime. 1403 * @param __HANDLE__ TIM handle. 1404 * @param __CHANNEL__ TIM Channel associated with the capture compare register 1405 * This parameter can be one of the following values: 1406 * @arg TIM_CHANNEL_1: get capture/compare 1 register value 1407 * @arg TIM_CHANNEL_2: get capture/compare 2 register value 1408 * @arg TIM_CHANNEL_3: get capture/compare 3 register value 1409 * @arg TIM_CHANNEL_4: get capture/compare 4 register value 1410 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) 1411 */ 1412 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ 1413 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ 1414 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ 1415 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ 1416 ((__HANDLE__)->Instance->CCR4)) 1417 1418 /** 1419 * @brief Set the TIM Output compare preload. 1420 * @param __HANDLE__ TIM handle. 1421 * @param __CHANNEL__ TIM Channels to be configured. 1422 * This parameter can be one of the following values: 1423 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1424 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1425 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1426 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1427 * @retval None 1428 */ 1429 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1430 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ 1431 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ 1432 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ 1433 ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) 1434 1435 /** 1436 * @brief Reset the TIM Output compare preload. 1437 * @param __HANDLE__ TIM handle. 1438 * @param __CHANNEL__ TIM Channels to be configured. 1439 * This parameter can be one of the following values: 1440 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1441 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1442 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1443 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1444 * @retval None 1445 */ 1446 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1447 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ 1448 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ 1449 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ 1450 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE)) 1451 1452 /** 1453 * @brief Enable fast mode for a given channel. 1454 * @param __HANDLE__ TIM handle. 1455 * @param __CHANNEL__ TIM Channels to be configured. 1456 * This parameter can be one of the following values: 1457 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1458 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1459 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1460 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1461 * @note When fast mode is enabled an active edge on the trigger input acts 1462 * like a compare match on CCx output. Delay to sample the trigger 1463 * input and to activate CCx output is reduced to 3 clock cycles. 1464 * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. 1465 * @retval None 1466 */ 1467 #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1468 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ 1469 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ 1470 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ 1471 ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE)) 1472 1473 /** 1474 * @brief Disable fast mode for a given channel. 1475 * @param __HANDLE__ TIM handle. 1476 * @param __CHANNEL__ TIM Channels to be configured. 1477 * This parameter can be one of the following values: 1478 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1479 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1480 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1481 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1482 * @note When fast mode is disabled CCx output behaves normally depending 1483 * on counter and CCRx values even when the trigger is ON. The minimum 1484 * delay to activate CCx output when an active edge occurs on the 1485 * trigger input is 5 clock cycles. 1486 * @retval None 1487 */ 1488 #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1489 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ 1490 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ 1491 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ 1492 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE)) 1493 1494 /** 1495 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. 1496 * @param __HANDLE__ TIM handle. 1497 * @note When the URS bit of the TIMx_CR1 register is set, only counter 1498 * overflow/underflow generates an update interrupt or DMA request (if 1499 * enabled) 1500 * @retval None 1501 */ 1502 #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) 1503 1504 /** 1505 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. 1506 * @param __HANDLE__ TIM handle. 1507 * @note When the URS bit of the TIMx_CR1 register is reset, any of the 1508 * following events generate an update interrupt or DMA request (if 1509 * enabled): 1510 * _ Counter overflow underflow 1511 * _ Setting the UG bit 1512 * _ Update generation through the slave mode controller 1513 * @retval None 1514 */ 1515 #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) 1516 1517 /** 1518 * @brief Set the TIM Capture x input polarity on runtime. 1519 * @param __HANDLE__ TIM handle. 1520 * @param __CHANNEL__ TIM Channels to be configured. 1521 * This parameter can be one of the following values: 1522 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1523 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1524 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1525 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1526 * @param __POLARITY__ Polarity for TIx source 1527 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge 1528 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge 1529 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge 1530 * @retval None 1531 */ 1532 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 1533 do{ \ 1534 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ 1535 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ 1536 }while(0) 1537 1538 /** @brief Select the Capture/compare DMA request source. 1539 * @param __HANDLE__ specifies the TIM Handle. 1540 * @param __CCDMA__ specifies Capture/compare DMA request source 1541 * This parameter can be one of the following values: 1542 * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event 1543 * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event 1544 * @retval None 1545 */ 1546 #define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \ 1547 MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__)) 1548 1549 /** 1550 * @} 1551 */ 1552 /* End of exported macros ----------------------------------------------------*/ 1553 1554 /* Private constants ---------------------------------------------------------*/ 1555 /** @defgroup TIM_Private_Constants TIM Private Constants 1556 * @{ 1557 */ 1558 /* The counter of a timer instance is disabled only if all the CCx and CCxN 1559 channels have been disabled */ 1560 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) 1561 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) 1562 /** 1563 * @} 1564 */ 1565 /* End of private constants --------------------------------------------------*/ 1566 1567 /* Private macros ------------------------------------------------------------*/ 1568 /** @defgroup TIM_Private_Macros TIM Private Macros 1569 * @{ 1570 */ 1571 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ 1572 ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) 1573 1574 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ 1575 ((__BASE__) == TIM_DMABASE_CR2) || \ 1576 ((__BASE__) == TIM_DMABASE_SMCR) || \ 1577 ((__BASE__) == TIM_DMABASE_DIER) || \ 1578 ((__BASE__) == TIM_DMABASE_SR) || \ 1579 ((__BASE__) == TIM_DMABASE_EGR) || \ 1580 ((__BASE__) == TIM_DMABASE_CCMR1) || \ 1581 ((__BASE__) == TIM_DMABASE_CCMR2) || \ 1582 ((__BASE__) == TIM_DMABASE_CCER) || \ 1583 ((__BASE__) == TIM_DMABASE_CNT) || \ 1584 ((__BASE__) == TIM_DMABASE_PSC) || \ 1585 ((__BASE__) == TIM_DMABASE_ARR) || \ 1586 ((__BASE__) == TIM_DMABASE_RCR) || \ 1587 ((__BASE__) == TIM_DMABASE_CCR1) || \ 1588 ((__BASE__) == TIM_DMABASE_CCR2) || \ 1589 ((__BASE__) == TIM_DMABASE_CCR3) || \ 1590 ((__BASE__) == TIM_DMABASE_CCR4) || \ 1591 ((__BASE__) == TIM_DMABASE_BDTR)) 1592 1593 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1594 1595 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ 1596 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ 1597 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ 1598 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ 1599 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) 1600 1601 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ 1602 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ 1603 ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) 1604 1605 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ 1606 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) 1607 1608 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ 1609 ((__STATE__) == TIM_OCFAST_ENABLE)) 1610 1611 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ 1612 ((__POLARITY__) == TIM_OCPOLARITY_LOW)) 1613 1614 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ 1615 ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) 1616 1617 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ 1618 ((__STATE__) == TIM_OCIDLESTATE_RESET)) 1619 1620 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ 1621 ((__STATE__) == TIM_OCNIDLESTATE_RESET)) 1622 1623 #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ 1624 ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) 1625 1626 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ 1627 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ 1628 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) 1629 1630 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ 1631 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ 1632 ((__SELECTION__) == TIM_ICSELECTION_TRC)) 1633 1634 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ 1635 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ 1636 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ 1637 ((__PRESCALER__) == TIM_ICPSC_DIV8)) 1638 1639 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ 1640 ((__MODE__) == TIM_OPMODE_REPETITIVE)) 1641 1642 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ 1643 ((__MODE__) == TIM_ENCODERMODE_TI2) || \ 1644 ((__MODE__) == TIM_ENCODERMODE_TI12)) 1645 1646 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1647 1648 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1649 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1650 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 1651 ((__CHANNEL__) == TIM_CHANNEL_4) || \ 1652 ((__CHANNEL__) == TIM_CHANNEL_ALL)) 1653 1654 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1655 ((__CHANNEL__) == TIM_CHANNEL_2)) 1656 1657 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1658 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1659 ((__CHANNEL__) == TIM_CHANNEL_3)) 1660 1661 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 1662 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ 1663 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 1664 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 1665 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 1666 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 1667 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ 1668 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ 1669 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ 1670 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)) 1671 1672 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ 1673 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ 1674 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ 1675 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ 1676 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) 1677 1678 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ 1679 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ 1680 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ 1681 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) 1682 1683 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1684 1685 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ 1686 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) 1687 1688 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ 1689 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ 1690 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ 1691 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) 1692 1693 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1694 1695 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ 1696 ((__STATE__) == TIM_OSSR_DISABLE)) 1697 1698 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ 1699 ((__STATE__) == TIM_OSSI_DISABLE)) 1700 1701 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ 1702 ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ 1703 ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ 1704 ((__LEVEL__) == TIM_LOCKLEVEL_3)) 1705 1706 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) 1707 1708 1709 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ 1710 ((__STATE__) == TIM_BREAK_DISABLE)) 1711 1712 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ 1713 ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) 1714 1715 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ 1716 ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) 1717 1718 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ 1719 ((__SOURCE__) == TIM_TRGO_ENABLE) || \ 1720 ((__SOURCE__) == TIM_TRGO_UPDATE) || \ 1721 ((__SOURCE__) == TIM_TRGO_OC1) || \ 1722 ((__SOURCE__) == TIM_TRGO_OC1REF) || \ 1723 ((__SOURCE__) == TIM_TRGO_OC2REF) || \ 1724 ((__SOURCE__) == TIM_TRGO_OC3REF) || \ 1725 ((__SOURCE__) == TIM_TRGO_OC4REF)) 1726 1727 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ 1728 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) 1729 1730 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ 1731 ((__MODE__) == TIM_SLAVEMODE_RESET) || \ 1732 ((__MODE__) == TIM_SLAVEMODE_GATED) || \ 1733 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ 1734 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1)) 1735 1736 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ 1737 ((__MODE__) == TIM_OCMODE_PWM2)) 1738 1739 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ 1740 ((__MODE__) == TIM_OCMODE_ACTIVE) || \ 1741 ((__MODE__) == TIM_OCMODE_INACTIVE) || \ 1742 ((__MODE__) == TIM_OCMODE_TOGGLE) || \ 1743 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ 1744 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)) 1745 1746 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 1747 ((__SELECTION__) == TIM_TS_ITR1) || \ 1748 ((__SELECTION__) == TIM_TS_ITR2) || \ 1749 ((__SELECTION__) == TIM_TS_ITR3) || \ 1750 ((__SELECTION__) == TIM_TS_TI1F_ED) || \ 1751 ((__SELECTION__) == TIM_TS_TI1FP1) || \ 1752 ((__SELECTION__) == TIM_TS_TI2FP2) || \ 1753 ((__SELECTION__) == TIM_TS_ETRF)) 1754 1755 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 1756 ((__SELECTION__) == TIM_TS_ITR1) || \ 1757 ((__SELECTION__) == TIM_TS_ITR2) || \ 1758 ((__SELECTION__) == TIM_TS_ITR3) || \ 1759 ((__SELECTION__) == TIM_TS_NONE)) 1760 1761 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ 1762 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ 1763 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ 1764 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ 1765 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) 1766 1767 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ 1768 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ 1769 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ 1770 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) 1771 1772 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1773 1774 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ 1775 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) 1776 1777 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ 1778 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ 1779 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ 1780 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ 1781 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ 1782 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ 1783 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ 1784 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ 1785 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ 1786 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ 1787 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ 1788 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ 1789 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ 1790 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ 1791 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ 1792 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ 1793 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ 1794 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) 1795 1796 #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) 1797 1798 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1799 1800 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) 1801 1802 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) 1803 1804 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ 1805 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ 1806 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ 1807 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ 1808 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) 1809 1810 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ 1811 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ 1812 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ 1813 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ 1814 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) 1815 1816 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 1817 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ 1818 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ 1819 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ 1820 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) 1821 1822 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ 1823 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ 1824 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ 1825 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ 1826 ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) 1827 1828 #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ 1829 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ 1830 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ 1831 ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ 1832 (__HANDLE__)->ChannelState[3]) 1833 1834 #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ 1835 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ 1836 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ 1837 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ 1838 ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__))) 1839 1840 #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ 1841 (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ 1842 (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ 1843 (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ 1844 (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ 1845 } while(0) 1846 1847 #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ 1848 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ 1849 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ 1850 ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ 1851 (__HANDLE__)->ChannelNState[3]) 1852 1853 #define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ 1854 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ 1855 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ 1856 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ 1857 ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) 1858 1859 #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ 1860 (__HANDLE__)->ChannelNState[0] = \ 1861 (__CHANNEL_STATE__); \ 1862 (__HANDLE__)->ChannelNState[1] = \ 1863 (__CHANNEL_STATE__); \ 1864 (__HANDLE__)->ChannelNState[2] = \ 1865 (__CHANNEL_STATE__); \ 1866 (__HANDLE__)->ChannelNState[3] = \ 1867 (__CHANNEL_STATE__); \ 1868 } while(0) 1869 1870 /** 1871 * @} 1872 */ 1873 /* End of private macros -----------------------------------------------------*/ 1874 1875 /* Include TIM HAL Extended module */ 1876 #include "stm32f4xx_hal_tim_ex.h" 1877 1878 /* Exported functions --------------------------------------------------------*/ 1879 /** @addtogroup TIM_Exported_Functions TIM Exported Functions 1880 * @{ 1881 */ 1882 1883 /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions 1884 * @brief Time Base functions 1885 * @{ 1886 */ 1887 /* Time Base functions ********************************************************/ 1888 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); 1889 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); 1890 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); 1891 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); 1892 /* Blocking mode: Polling */ 1893 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); 1894 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); 1895 /* Non-Blocking mode: Interrupt */ 1896 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); 1897 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); 1898 /* Non-Blocking mode: DMA */ 1899 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); 1900 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); 1901 /** 1902 * @} 1903 */ 1904 1905 /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions 1906 * @brief TIM Output Compare functions 1907 * @{ 1908 */ 1909 /* Timer Output Compare functions *********************************************/ 1910 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); 1911 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); 1912 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); 1913 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); 1914 /* Blocking mode: Polling */ 1915 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 1916 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 1917 /* Non-Blocking mode: Interrupt */ 1918 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1919 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1920 /* Non-Blocking mode: DMA */ 1921 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 1922 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 1923 /** 1924 * @} 1925 */ 1926 1927 /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions 1928 * @brief TIM PWM functions 1929 * @{ 1930 */ 1931 /* Timer PWM functions ********************************************************/ 1932 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); 1933 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); 1934 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); 1935 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); 1936 /* Blocking mode: Polling */ 1937 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 1938 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 1939 /* Non-Blocking mode: Interrupt */ 1940 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1941 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1942 /* Non-Blocking mode: DMA */ 1943 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 1944 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 1945 /** 1946 * @} 1947 */ 1948 1949 /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions 1950 * @brief TIM Input Capture functions 1951 * @{ 1952 */ 1953 /* Timer Input Capture functions **********************************************/ 1954 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); 1955 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); 1956 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); 1957 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); 1958 /* Blocking mode: Polling */ 1959 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 1960 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 1961 /* Non-Blocking mode: Interrupt */ 1962 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1963 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1964 /* Non-Blocking mode: DMA */ 1965 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 1966 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 1967 /** 1968 * @} 1969 */ 1970 1971 /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions 1972 * @brief TIM One Pulse functions 1973 * @{ 1974 */ 1975 /* Timer One Pulse functions **************************************************/ 1976 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); 1977 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); 1978 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); 1979 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); 1980 /* Blocking mode: Polling */ 1981 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 1982 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 1983 /* Non-Blocking mode: Interrupt */ 1984 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 1985 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 1986 /** 1987 * @} 1988 */ 1989 1990 /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions 1991 * @brief TIM Encoder functions 1992 * @{ 1993 */ 1994 /* Timer Encoder functions ****************************************************/ 1995 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); 1996 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); 1997 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); 1998 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); 1999 /* Blocking mode: Polling */ 2000 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2001 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2002 /* Non-Blocking mode: Interrupt */ 2003 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2004 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2005 /* Non-Blocking mode: DMA */ 2006 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, 2007 uint32_t *pData2, uint16_t Length); 2008 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2009 /** 2010 * @} 2011 */ 2012 2013 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management 2014 * @brief IRQ handler management 2015 * @{ 2016 */ 2017 /* Interrupt Handler functions ***********************************************/ 2018 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); 2019 /** 2020 * @} 2021 */ 2022 2023 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions 2024 * @brief Peripheral Control functions 2025 * @{ 2026 */ 2027 /* Control functions *********************************************************/ 2028 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); 2029 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); 2030 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); 2031 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, 2032 uint32_t OutputChannel, uint32_t InputChannel); 2033 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, 2034 uint32_t Channel); 2035 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); 2036 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); 2037 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); 2038 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); 2039 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2040 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); 2041 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2042 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, 2043 uint32_t BurstLength, uint32_t DataLength); 2044 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 2045 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2046 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); 2047 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2048 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, 2049 uint32_t BurstLength, uint32_t DataLength); 2050 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 2051 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); 2052 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); 2053 /** 2054 * @} 2055 */ 2056 2057 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions 2058 * @brief TIM Callbacks functions 2059 * @{ 2060 */ 2061 /* Callback in non blocking modes (Interrupt and DMA) *************************/ 2062 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); 2063 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); 2064 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); 2065 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); 2066 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); 2067 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); 2068 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); 2069 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); 2070 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); 2071 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); 2072 2073 /* Callbacks Register/UnRegister functions ***********************************/ 2074 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 2075 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, 2076 pTIM_CallbackTypeDef pCallback); 2077 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); 2078 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 2079 2080 /** 2081 * @} 2082 */ 2083 2084 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions 2085 * @brief Peripheral State functions 2086 * @{ 2087 */ 2088 /* Peripheral State functions ************************************************/ 2089 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); 2090 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); 2091 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); 2092 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); 2093 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); 2094 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); 2095 2096 /* Peripheral Channel state functions ************************************************/ 2097 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); 2098 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); 2099 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); 2100 /** 2101 * @} 2102 */ 2103 2104 /** 2105 * @} 2106 */ 2107 /* End of exported functions -------------------------------------------------*/ 2108 2109 /* Private functions----------------------------------------------------------*/ 2110 /** @defgroup TIM_Private_Functions TIM Private Functions 2111 * @{ 2112 */ 2113 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); 2114 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); 2115 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); 2116 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, 2117 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); 2118 2119 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); 2120 void TIM_DMAError(DMA_HandleTypeDef *hdma); 2121 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); 2122 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); 2123 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); 2124 2125 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 2126 void TIM_ResetCallback(TIM_HandleTypeDef *htim); 2127 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 2128 2129 /** 2130 * @} 2131 */ 2132 /* End of private functions --------------------------------------------------*/ 2133 2134 /** 2135 * @} 2136 */ 2137 2138 /** 2139 * @} 2140 */ 2141 2142 #ifdef __cplusplus 2143 } 2144 #endif 2145 2146 #endif /* STM32F4xx_HAL_TIM_H */ 2147
