1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_hal_sram.h 4 * @author MCD Application Team 5 * @brief Header file of SRAM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32F4xx_HAL_SRAM_H 21 #define STM32F4xx_HAL_SRAM_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 #if defined(FMC_Bank1) || defined(FSMC_Bank1) 28 29 /* Includes ------------------------------------------------------------------*/ 30 #if defined(FSMC_Bank1) 31 #include "stm32f4xx_ll_fsmc.h" 32 #else 33 #include "stm32f4xx_ll_fmc.h" 34 #endif /* FSMC_Bank1 */ 35 36 /** @addtogroup STM32F4xx_HAL_Driver 37 * @{ 38 */ 39 /** @addtogroup SRAM 40 * @{ 41 */ 42 43 /* Exported typedef ----------------------------------------------------------*/ 44 45 /** @defgroup SRAM_Exported_Types SRAM Exported Types 46 * @{ 47 */ 48 /** 49 * @brief HAL SRAM State structures definition 50 */ 51 typedef enum 52 { 53 HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */ 54 HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */ 55 HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */ 56 HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */ 57 HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */ 58 59 } HAL_SRAM_StateTypeDef; 60 61 /** 62 * @brief SRAM handle Structure definition 63 */ 64 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) 65 typedef struct __SRAM_HandleTypeDef 66 #else 67 typedef struct 68 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ 69 { 70 FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ 71 72 FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ 73 74 FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */ 75 76 HAL_LockTypeDef Lock; /*!< SRAM locking object */ 77 78 __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */ 79 80 DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ 81 82 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) 83 void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */ 84 void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */ 85 void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Complete callback */ 86 void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Error callback */ 87 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ 88 } SRAM_HandleTypeDef; 89 90 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) 91 /** 92 * @brief HAL SRAM Callback ID enumeration definition 93 */ 94 typedef enum 95 { 96 HAL_SRAM_MSP_INIT_CB_ID = 0x00U, /*!< SRAM MspInit Callback ID */ 97 HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */ 98 HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */ 99 HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */ 100 } HAL_SRAM_CallbackIDTypeDef; 101 102 /** 103 * @brief HAL SRAM Callback pointer definition 104 */ 105 typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram); 106 typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); 107 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ 108 /** 109 * @} 110 */ 111 112 /* Exported constants --------------------------------------------------------*/ 113 /* Exported macro ------------------------------------------------------------*/ 114 115 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros 116 * @{ 117 */ 118 119 /** @brief Reset SRAM handle state 120 * @param __HANDLE__ SRAM handle 121 * @retval None 122 */ 123 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) 124 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) do { \ 125 (__HANDLE__)->State = HAL_SRAM_STATE_RESET; \ 126 (__HANDLE__)->MspInitCallback = NULL; \ 127 (__HANDLE__)->MspDeInitCallback = NULL; \ 128 } while(0) 129 #else 130 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) 131 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ 132 133 /** 134 * @} 135 */ 136 137 /* Exported functions --------------------------------------------------------*/ 138 /** @addtogroup SRAM_Exported_Functions SRAM Exported Functions 139 * @{ 140 */ 141 142 /** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions 143 * @{ 144 */ 145 146 /* Initialization/de-initialization functions ********************************/ 147 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, 148 FMC_NORSRAM_TimingTypeDef *ExtTiming); 149 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram); 150 void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); 151 void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); 152 153 /** 154 * @} 155 */ 156 157 /** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions 158 * @{ 159 */ 160 161 /* I/O operation functions ***************************************************/ 162 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, 163 uint32_t BufferSize); 164 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, 165 uint32_t BufferSize); 166 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, 167 uint32_t BufferSize); 168 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, 169 uint32_t BufferSize); 170 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, 171 uint32_t BufferSize); 172 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, 173 uint32_t BufferSize); 174 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, 175 uint32_t BufferSize); 176 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, 177 uint32_t BufferSize); 178 179 void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); 180 void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); 181 182 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) 183 /* SRAM callback registering/unregistering */ 184 HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, 185 pSRAM_CallbackTypeDef pCallback); 186 HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId); 187 HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, 188 pSRAM_DmaCallbackTypeDef pCallback); 189 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ 190 191 /** 192 * @} 193 */ 194 195 /** @addtogroup SRAM_Exported_Functions_Group3 Control functions 196 * @{ 197 */ 198 199 /* SRAM Control functions ****************************************************/ 200 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram); 201 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); 202 203 /** 204 * @} 205 */ 206 207 /** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions 208 * @{ 209 */ 210 211 /* SRAM State functions ******************************************************/ 212 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); 213 214 /** 215 * @} 216 */ 217 218 /** 219 * @} 220 */ 221 222 /** 223 * @} 224 */ 225 226 /** 227 * @} 228 */ 229 230 #endif /* FMC_Bank1 || FSMC_Bank1 */ 231 232 #ifdef __cplusplus 233 } 234 #endif 235 236 #endif /* STM32F4xx_HAL_SRAM_H */ 237
