1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_hal_nand.h 4 * @author MCD Application Team 5 * @brief Header file of NAND HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32F4xx_HAL_NAND_H 21 #define STM32F4xx_HAL_NAND_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 #if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FSMC_Bank2_3) 28 29 /* Includes ------------------------------------------------------------------*/ 30 #if defined(FSMC_Bank2_3) 31 #include "stm32f4xx_ll_fsmc.h" 32 #else 33 #include "stm32f4xx_ll_fmc.h" 34 #endif /* FSMC_Bank2_3 */ 35 36 /** @addtogroup STM32F4xx_HAL_Driver 37 * @{ 38 */ 39 40 /** @addtogroup NAND 41 * @{ 42 */ 43 44 /* Exported typedef ----------------------------------------------------------*/ 45 /* Exported types ------------------------------------------------------------*/ 46 /** @defgroup NAND_Exported_Types NAND Exported Types 47 * @{ 48 */ 49 50 /** 51 * @brief HAL NAND State structures definition 52 */ 53 typedef enum 54 { 55 HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */ 56 HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */ 57 HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */ 58 HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */ 59 } HAL_NAND_StateTypeDef; 60 61 /** 62 * @brief NAND Memory electronic signature Structure definition 63 */ 64 typedef struct 65 { 66 /*<! NAND memory electronic signature maker and device IDs */ 67 68 uint8_t Maker_Id; 69 70 uint8_t Device_Id; 71 72 uint8_t Third_Id; 73 74 uint8_t Fourth_Id; 75 } NAND_IDTypeDef; 76 77 /** 78 * @brief NAND Memory address Structure definition 79 */ 80 typedef struct 81 { 82 uint16_t Page; /*!< NAND memory Page address */ 83 84 uint16_t Plane; /*!< NAND memory Zone address */ 85 86 uint16_t Block; /*!< NAND memory Block address */ 87 88 } NAND_AddressTypeDef; 89 90 /** 91 * @brief NAND Memory info Structure definition 92 */ 93 typedef struct 94 { 95 uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes 96 for 8 bits addressing or words for 16 bits addressing */ 97 98 uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes 99 for 8 bits addressing or words for 16 bits addressing */ 100 101 uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */ 102 103 uint32_t BlockNbr; /*!< NAND memory number of total blocks */ 104 105 uint32_t PlaneNbr; /*!< NAND memory number of planes */ 106 107 uint32_t PlaneSize; /*!< NAND memory zone size measured in number of blocks */ 108 109 FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This 110 parameter is mandatory for some NAND parts after the read 111 command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence. 112 Example: Toshiba THTH58BYG3S0HBAI6. 113 This parameter could be ENABLE or DISABLE 114 Please check the Read Mode sequnece in the NAND device datasheet */ 115 } NAND_DeviceConfigTypeDef; 116 117 /** 118 * @brief NAND handle Structure definition 119 */ 120 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 121 typedef struct __NAND_HandleTypeDef 122 #else 123 typedef struct 124 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 125 { 126 FMC_NAND_TypeDef *Instance; /*!< Register base address */ 127 128 FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */ 129 130 HAL_LockTypeDef Lock; /*!< NAND locking object */ 131 132 __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */ 133 134 NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */ 135 136 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 137 void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */ 138 void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp DeInit callback */ 139 void (* ItCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND IT callback */ 140 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 141 } NAND_HandleTypeDef; 142 143 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 144 /** 145 * @brief HAL NAND Callback ID enumeration definition 146 */ 147 typedef enum 148 { 149 HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */ 150 HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */ 151 HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */ 152 } HAL_NAND_CallbackIDTypeDef; 153 154 /** 155 * @brief HAL NAND Callback pointer definition 156 */ 157 typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand); 158 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 159 160 /** 161 * @} 162 */ 163 164 /* Exported constants --------------------------------------------------------*/ 165 /* Exported macro ------------------------------------------------------------*/ 166 /** @defgroup NAND_Exported_Macros NAND Exported Macros 167 * @{ 168 */ 169 170 /** @brief Reset NAND handle state 171 * @param __HANDLE__ specifies the NAND handle. 172 * @retval None 173 */ 174 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 175 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) do { \ 176 (__HANDLE__)->State = HAL_NAND_STATE_RESET; \ 177 (__HANDLE__)->MspInitCallback = NULL; \ 178 (__HANDLE__)->MspDeInitCallback = NULL; \ 179 } while(0) 180 #else 181 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET) 182 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 183 184 /** 185 * @} 186 */ 187 188 /* Exported functions --------------------------------------------------------*/ 189 /** @addtogroup NAND_Exported_Functions NAND Exported Functions 190 * @{ 191 */ 192 193 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions 194 * @{ 195 */ 196 197 /* Initialization/de-initialization functions ********************************/ 198 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, 199 FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); 200 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); 201 202 HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); 203 204 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); 205 206 void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand); 207 void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand); 208 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand); 209 void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); 210 211 /** 212 * @} 213 */ 214 215 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions 216 * @{ 217 */ 218 219 /* IO operation functions ****************************************************/ 220 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); 221 222 HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, 223 uint32_t NumPageToRead); 224 HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, 225 uint32_t NumPageToWrite); 226 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, 227 uint8_t *pBuffer, uint32_t NumSpareAreaToRead); 228 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, 229 uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); 230 231 HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, 232 uint32_t NumPageToRead); 233 HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, 234 uint32_t NumPageToWrite); 235 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, 236 uint16_t *pBuffer, uint32_t NumSpareAreaToRead); 237 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, 238 uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); 239 240 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); 241 242 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); 243 244 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 245 /* NAND callback registering/unregistering */ 246 HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, 247 pNAND_CallbackTypeDef pCallback); 248 HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId); 249 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 250 251 /** 252 * @} 253 */ 254 255 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions 256 * @{ 257 */ 258 259 /* NAND Control functions ****************************************************/ 260 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand); 261 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand); 262 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout); 263 264 /** 265 * @} 266 */ 267 268 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions 269 * @{ 270 */ 271 /* NAND State functions *******************************************************/ 272 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); 273 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); 274 /** 275 * @} 276 */ 277 278 /** 279 * @} 280 */ 281 282 /* Private types -------------------------------------------------------------*/ 283 /* Private variables ---------------------------------------------------------*/ 284 /* Private constants ---------------------------------------------------------*/ 285 /** @defgroup NAND_Private_Constants NAND Private Constants 286 * @{ 287 */ 288 #if defined(FMC_Bank2_3) 289 #define NAND_DEVICE1 0x70000000UL 290 #define NAND_DEVICE2 0x80000000UL 291 #else 292 #define NAND_DEVICE 0x80000000UL 293 #endif 294 #define NAND_WRITE_TIMEOUT 0x01000000UL 295 296 #define CMD_AREA (1UL<<16U) /* A16 = CLE high */ 297 #define ADDR_AREA (1UL<<17U) /* A17 = ALE high */ 298 299 #define NAND_CMD_AREA_A ((uint8_t)0x00) 300 #define NAND_CMD_AREA_B ((uint8_t)0x01) 301 #define NAND_CMD_AREA_C ((uint8_t)0x50) 302 #define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30) 303 304 #define NAND_CMD_WRITE0 ((uint8_t)0x80) 305 #define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) 306 #define NAND_CMD_ERASE0 ((uint8_t)0x60) 307 #define NAND_CMD_ERASE1 ((uint8_t)0xD0) 308 #define NAND_CMD_READID ((uint8_t)0x90) 309 #define NAND_CMD_STATUS ((uint8_t)0x70) 310 #define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) 311 #define NAND_CMD_RESET ((uint8_t)0xFF) 312 313 /* NAND memory status */ 314 #define NAND_VALID_ADDRESS 0x00000100UL 315 #define NAND_INVALID_ADDRESS 0x00000200UL 316 #define NAND_TIMEOUT_ERROR 0x00000400UL 317 #define NAND_BUSY 0x00000000UL 318 #define NAND_ERROR 0x00000001UL 319 #define NAND_READY 0x00000040UL 320 /** 321 * @} 322 */ 323 324 /* Private macros ------------------------------------------------------------*/ 325 /** @defgroup NAND_Private_Macros NAND Private Macros 326 * @{ 327 */ 328 329 /** 330 * @brief NAND memory address computation. 331 * @param __ADDRESS__ NAND memory address. 332 * @param __HANDLE__ NAND handle. 333 * @retval NAND Raw address value 334 */ 335 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ 336 (((__ADDRESS__)->Block + \ 337 (((__ADDRESS__)->Plane) * \ 338 ((__HANDLE__)->Config.PlaneSize))) * \ 339 ((__HANDLE__)->Config.BlockSize))) 340 341 /** 342 * @brief NAND memory Column address computation. 343 * @param __HANDLE__ NAND handle. 344 * @retval NAND Raw address value 345 */ 346 #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize) 347 348 /** 349 * @brief NAND memory address cycling. 350 * @param __ADDRESS__ NAND memory address. 351 * @retval NAND address cycling value. 352 */ 353 #define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ 354 #define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */ 355 #define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */ 356 #define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */ 357 358 /** 359 * @brief NAND memory Columns cycling. 360 * @param __ADDRESS__ NAND memory address. 361 * @retval NAND Column address cycling value. 362 */ 363 #define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) & 0xFFU) /* 1st Column addressing cycle */ 364 #define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */ 365 366 /** 367 * @} 368 */ 369 370 /** 371 * @} 372 */ 373 374 /** 375 * @} 376 */ 377 378 /** 379 * @} 380 */ 381 382 #endif /* FMC_Bank3) || defined(FMC_Bank2_3) || defined(FSMC_Bank2_3 */ 383 384 #ifdef __cplusplus 385 } 386 #endif 387 388 #endif /* STM32F4xx_HAL_NAND_H */ 389
