1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_hal_i2s.h 4 * @author MCD Application Team 5 * @brief Header file of I2S HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32F4xx_HAL_I2S_H 21 #define STM32F4xx_HAL_I2S_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f4xx_hal_def.h" 29 30 /** @addtogroup STM32F4xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup I2S 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup I2S_Exported_Types I2S Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief I2S Init structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Mode; /*!< Specifies the I2S operating mode. 49 This parameter can be a value of @ref I2S_Mode */ 50 51 uint32_t Standard; /*!< Specifies the standard used for the I2S communication. 52 This parameter can be a value of @ref I2S_Standard */ 53 54 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. 55 This parameter can be a value of @ref I2S_Data_Format */ 56 57 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. 58 This parameter can be a value of @ref I2S_MCLK_Output */ 59 60 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. 61 This parameter can be a value of @ref I2S_Audio_Frequency */ 62 63 uint32_t CPOL; /*!< Specifies the idle state of the I2S clock. 64 This parameter can be a value of @ref I2S_Clock_Polarity */ 65 66 uint32_t ClockSource; /*!< Specifies the I2S Clock Source. 67 This parameter can be a value of @ref I2S_Clock_Source */ 68 uint32_t FullDuplexMode; /*!< Specifies the I2S FullDuplex mode. 69 This parameter can be a value of @ref I2S_FullDuplex_Mode */ 70 } I2S_InitTypeDef; 71 72 /** 73 * @brief HAL State structures definition 74 */ 75 typedef enum 76 { 77 HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */ 78 HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */ 79 HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */ 80 HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ 81 HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ 82 HAL_I2S_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */ 83 HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */ 84 HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */ 85 } HAL_I2S_StateTypeDef; 86 87 /** 88 * @brief I2S handle Structure definition 89 */ 90 typedef struct __I2S_HandleTypeDef 91 { 92 SPI_TypeDef *Instance; /*!< I2S registers base address */ 93 94 I2S_InitTypeDef Init; /*!< I2S communication parameters */ 95 96 uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */ 97 98 __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */ 99 100 __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */ 101 102 uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */ 103 104 __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */ 105 106 __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter 107 (This field is initialized at the 108 same value as transfer size at the 109 beginning of the transfer and 110 decremented when a sample is received 111 NbSamplesReceived = RxBufferSize-RxBufferCount) */ 112 void (*IrqHandlerISR)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S function pointer on IrqHandler */ 113 114 DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */ 115 116 DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */ 117 118 __IO HAL_LockTypeDef Lock; /*!< I2S locking object */ 119 120 __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */ 121 122 __IO uint32_t ErrorCode; /*!< I2S Error code 123 This parameter can be a value of @ref I2S_Error */ 124 125 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) 126 void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */ 127 void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */ 128 void (* TxRxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S TxRx Completed callback */ 129 void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */ 130 void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */ 131 void (* TxRxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S TxRx Half Completed callback */ 132 void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */ 133 void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */ 134 void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */ 135 136 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ 137 } I2S_HandleTypeDef; 138 139 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) 140 /** 141 * @brief HAL I2S Callback ID enumeration definition 142 */ 143 typedef enum 144 { 145 HAL_I2S_TX_COMPLETE_CB_ID = 0x00U, /*!< I2S Tx Completed callback ID */ 146 HAL_I2S_RX_COMPLETE_CB_ID = 0x01U, /*!< I2S Rx Completed callback ID */ 147 HAL_I2S_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< I2S TxRx Completed callback ID */ 148 HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< I2S Tx Half Completed callback ID */ 149 HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< I2S Rx Half Completed callback ID */ 150 HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< I2S TxRx Half Completed callback ID */ 151 HAL_I2S_ERROR_CB_ID = 0x06U, /*!< I2S Error callback ID */ 152 HAL_I2S_MSPINIT_CB_ID = 0x07U, /*!< I2S Msp Init callback ID */ 153 HAL_I2S_MSPDEINIT_CB_ID = 0x08U /*!< I2S Msp DeInit callback ID */ 154 155 } HAL_I2S_CallbackIDTypeDef; 156 157 /** 158 * @brief HAL I2S Callback pointer definition 159 */ 160 typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */ 161 162 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ 163 /** 164 * @} 165 */ 166 167 /* Exported constants --------------------------------------------------------*/ 168 /** @defgroup I2S_Exported_Constants I2S Exported Constants 169 * @{ 170 */ 171 /** @defgroup I2S_Error I2S Error 172 * @{ 173 */ 174 #define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */ 175 #define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */ 176 #define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */ 177 #define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */ 178 #define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */ 179 #define HAL_I2S_ERROR_PRESCALER (0x00000010U) /*!< Prescaler Calculation error */ 180 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) 181 #define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */ 182 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ 183 #define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U) /*!< Busy Rx Line error */ 184 /** 185 * @} 186 */ 187 188 /** @defgroup I2S_Mode I2S Mode 189 * @{ 190 */ 191 #define I2S_MODE_SLAVE_TX (0x00000000U) 192 #define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) 193 #define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) 194 #define I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)) 195 /** 196 * @} 197 */ 198 199 /** @defgroup I2S_Standard I2S Standard 200 * @{ 201 */ 202 #define I2S_STANDARD_PHILIPS (0x00000000U) 203 #define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) 204 #define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) 205 #define I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)) 206 #define I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)) 207 /** 208 * @} 209 */ 210 211 /** @defgroup I2S_Data_Format I2S Data Format 212 * @{ 213 */ 214 #define I2S_DATAFORMAT_16B (0x00000000U) 215 #define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) 216 #define I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)) 217 #define I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)) 218 /** 219 * @} 220 */ 221 222 /** @defgroup I2S_MCLK_Output I2S MCLK Output 223 * @{ 224 */ 225 #define I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE) 226 #define I2S_MCLKOUTPUT_DISABLE (0x00000000U) 227 /** 228 * @} 229 */ 230 231 /** @defgroup I2S_Audio_Frequency I2S Audio Frequency 232 * @{ 233 */ 234 #define I2S_AUDIOFREQ_192K (192000U) 235 #define I2S_AUDIOFREQ_96K (96000U) 236 #define I2S_AUDIOFREQ_48K (48000U) 237 #define I2S_AUDIOFREQ_44K (44100U) 238 #define I2S_AUDIOFREQ_32K (32000U) 239 #define I2S_AUDIOFREQ_22K (22050U) 240 #define I2S_AUDIOFREQ_16K (16000U) 241 #define I2S_AUDIOFREQ_11K (11025U) 242 #define I2S_AUDIOFREQ_8K (8000U) 243 #define I2S_AUDIOFREQ_DEFAULT (2U) 244 /** 245 * @} 246 */ 247 248 /** @defgroup I2S_FullDuplex_Mode I2S FullDuplex Mode 249 * @{ 250 */ 251 #define I2S_FULLDUPLEXMODE_DISABLE (0x00000000U) 252 #define I2S_FULLDUPLEXMODE_ENABLE (0x00000001U) 253 /** 254 * @} 255 */ 256 257 /** @defgroup I2S_Clock_Polarity I2S Clock Polarity 258 * @{ 259 */ 260 #define I2S_CPOL_LOW (0x00000000U) 261 #define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL) 262 /** 263 * @} 264 */ 265 266 /** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition 267 * @{ 268 */ 269 #define I2S_IT_TXE SPI_CR2_TXEIE 270 #define I2S_IT_RXNE SPI_CR2_RXNEIE 271 #define I2S_IT_ERR SPI_CR2_ERRIE 272 /** 273 * @} 274 */ 275 276 /** @defgroup I2S_Flags_Definition I2S Flags Definition 277 * @{ 278 */ 279 #define I2S_FLAG_TXE SPI_SR_TXE 280 #define I2S_FLAG_RXNE SPI_SR_RXNE 281 282 #define I2S_FLAG_UDR SPI_SR_UDR 283 #define I2S_FLAG_OVR SPI_SR_OVR 284 #define I2S_FLAG_FRE SPI_SR_FRE 285 286 #define I2S_FLAG_CHSIDE SPI_SR_CHSIDE 287 #define I2S_FLAG_BSY SPI_SR_BSY 288 289 #define I2S_FLAG_MASK (SPI_SR_RXNE\ 290 | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY) 291 /** 292 * @} 293 */ 294 295 /** @defgroup I2S_Clock_Source I2S Clock Source Definition 296 * @{ 297 */ 298 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || defined(STM32F479xx) 299 #define I2S_CLOCK_PLL (0x00000000U) 300 #define I2S_CLOCK_EXTERNAL (0x00000001U) 301 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 302 STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */ 303 304 #if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 305 #define I2S_CLOCK_PLL (0x00000000U) 306 #define I2S_CLOCK_EXTERNAL (0x00000001U) 307 #define I2S_CLOCK_PLLR (0x00000002U) 308 #define I2S_CLOCK_PLLSRC (0x00000003U) 309 #endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 310 311 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 312 #define I2S_CLOCK_PLLSRC (0x00000000U) 313 #define I2S_CLOCK_EXTERNAL (0x00000001U) 314 #define I2S_CLOCK_PLLR (0x00000002U) 315 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 316 /** 317 * @} 318 */ 319 320 /** 321 * @} 322 */ 323 324 /* Exported macros -----------------------------------------------------------*/ 325 /** @defgroup I2S_Exported_macros I2S Exported Macros 326 * @{ 327 */ 328 329 /** @brief Reset I2S handle state 330 * @param __HANDLE__ specifies the I2S Handle. 331 * @retval None 332 */ 333 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) 334 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \ 335 (__HANDLE__)->State = HAL_I2S_STATE_RESET; \ 336 (__HANDLE__)->MspInitCallback = NULL; \ 337 (__HANDLE__)->MspDeInitCallback = NULL; \ 338 } while(0) 339 #else 340 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET) 341 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ 342 343 /** @brief Enable the specified SPI peripheral (in I2S mode). 344 * @param __HANDLE__ specifies the I2S Handle. 345 * @retval None 346 */ 347 #define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) 348 349 /** @brief Disable the specified SPI peripheral (in I2S mode). 350 * @param __HANDLE__ specifies the I2S Handle. 351 * @retval None 352 */ 353 #define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) 354 355 /** @brief Enable the specified I2S interrupts. 356 * @param __HANDLE__ specifies the I2S Handle. 357 * @param __INTERRUPT__ specifies the interrupt source to enable or disable. 358 * This parameter can be one of the following values: 359 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable 360 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable 361 * @arg I2S_IT_ERR: Error interrupt enable 362 * @retval None 363 */ 364 #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))) 365 366 /** @brief Disable the specified I2S interrupts. 367 * @param __HANDLE__ specifies the I2S Handle. 368 * @param __INTERRUPT__ specifies the interrupt source to enable or disable. 369 * This parameter can be one of the following values: 370 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable 371 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable 372 * @arg I2S_IT_ERR: Error interrupt enable 373 * @retval None 374 */ 375 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))) 376 377 /** @brief Checks if the specified I2S interrupt source is enabled or disabled. 378 * @param __HANDLE__ specifies the I2S Handle. 379 * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral. 380 * @param __INTERRUPT__ specifies the I2S interrupt source to check. 381 * This parameter can be one of the following values: 382 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable 383 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable 384 * @arg I2S_IT_ERR: Error interrupt enable 385 * @retval The new state of __IT__ (TRUE or FALSE). 386 */ 387 #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\ 388 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 389 390 /** @brief Checks whether the specified I2S flag is set or not. 391 * @param __HANDLE__ specifies the I2S Handle. 392 * @param __FLAG__ specifies the flag to check. 393 * This parameter can be one of the following values: 394 * @arg I2S_FLAG_RXNE: Receive buffer not empty flag 395 * @arg I2S_FLAG_TXE: Transmit buffer empty flag 396 * @arg I2S_FLAG_UDR: Underrun flag 397 * @arg I2S_FLAG_OVR: Overrun flag 398 * @arg I2S_FLAG_FRE: Frame error flag 399 * @arg I2S_FLAG_CHSIDE: Channel Side flag 400 * @arg I2S_FLAG_BSY: Busy flag 401 * @retval The new state of __FLAG__ (TRUE or FALSE). 402 */ 403 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 404 405 /** @brief Clears the I2S OVR pending flag. 406 * @param __HANDLE__ specifies the I2S Handle. 407 * @retval None 408 */ 409 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \ 410 __IO uint32_t tmpreg_ovr = 0x00U; \ 411 tmpreg_ovr = (__HANDLE__)->Instance->DR; \ 412 tmpreg_ovr = (__HANDLE__)->Instance->SR; \ 413 UNUSED(tmpreg_ovr); \ 414 }while(0U) 415 /** @brief Clears the I2S UDR pending flag. 416 * @param __HANDLE__ specifies the I2S Handle. 417 * @retval None 418 */ 419 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\ 420 __IO uint32_t tmpreg_udr = 0x00U;\ 421 tmpreg_udr = ((__HANDLE__)->Instance->SR);\ 422 UNUSED(tmpreg_udr); \ 423 }while(0U) 424 /** @brief Flush the I2S DR Register. 425 * @param __HANDLE__ specifies the I2S Handle. 426 * @retval None 427 */ 428 #define __HAL_I2S_FLUSH_RX_DR(__HANDLE__) do{\ 429 __IO uint32_t tmpreg_dr = 0x00U;\ 430 tmpreg_dr = ((__HANDLE__)->Instance->DR);\ 431 UNUSED(tmpreg_dr); \ 432 }while(0U) 433 /** 434 * @} 435 */ 436 437 /* Include I2S Extension module */ 438 #include "stm32f4xx_hal_i2s_ex.h" 439 440 /* Exported functions --------------------------------------------------------*/ 441 /** @addtogroup I2S_Exported_Functions 442 * @{ 443 */ 444 445 /** @addtogroup I2S_Exported_Functions_Group1 446 * @{ 447 */ 448 /* Initialization/de-initialization functions ********************************/ 449 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s); 450 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s); 451 void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s); 452 void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s); 453 454 /* Callbacks Register/UnRegister functions ***********************************/ 455 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) 456 HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, 457 pI2S_CallbackTypeDef pCallback); 458 HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID); 459 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ 460 /** 461 * @} 462 */ 463 464 /** @addtogroup I2S_Exported_Functions_Group2 465 * @{ 466 */ 467 /* I/O operation functions ***************************************************/ 468 /* Blocking mode: Polling */ 469 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); 470 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); 471 472 /* Non-Blocking mode: Interrupt */ 473 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); 474 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); 475 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s); 476 477 /* Non-Blocking mode: DMA */ 478 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); 479 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); 480 481 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s); 482 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s); 483 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s); 484 485 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/ 486 void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s); 487 void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s); 488 void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s); 489 void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s); 490 void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s); 491 /** 492 * @} 493 */ 494 495 /** @addtogroup I2S_Exported_Functions_Group3 496 * @{ 497 */ 498 /* Peripheral Control and State functions ************************************/ 499 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s); 500 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); 501 /** 502 * @} 503 */ 504 505 /** 506 * @} 507 */ 508 509 /* Private types -------------------------------------------------------------*/ 510 /* Private variables ---------------------------------------------------------*/ 511 /* Private constants ---------------------------------------------------------*/ 512 /* Private macros ------------------------------------------------------------*/ 513 /** @defgroup I2S_Private_Macros I2S Private Macros 514 * @{ 515 */ 516 517 /** @brief Check whether the specified SPI flag is set or not. 518 * @param __SR__ copy of I2S SR register. 519 * @param __FLAG__ specifies the flag to check. 520 * This parameter can be one of the following values: 521 * @arg I2S_FLAG_RXNE: Receive buffer not empty flag 522 * @arg I2S_FLAG_TXE: Transmit buffer empty flag 523 * @arg I2S_FLAG_UDR: Underrun error flag 524 * @arg I2S_FLAG_OVR: Overrun flag 525 * @arg I2S_FLAG_CHSIDE: Channel side flag 526 * @arg I2S_FLAG_BSY: Busy flag 527 * @retval SET or RESET. 528 */ 529 #define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\ 530 & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET) 531 532 /** @brief Check whether the specified SPI Interrupt is set or not. 533 * @param __CR2__ copy of I2S CR2 register. 534 * @param __INTERRUPT__ specifies the SPI interrupt source to check. 535 * This parameter can be one of the following values: 536 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable 537 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable 538 * @arg I2S_IT_ERR: Error interrupt enable 539 * @retval SET or RESET. 540 */ 541 #define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__)\ 542 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 543 544 /** @brief Checks if I2S Mode parameter is in allowed range. 545 * @param __MODE__ specifies the I2S Mode. 546 * This parameter can be a value of @ref I2S_Mode 547 * @retval None 548 */ 549 #define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \ 550 ((__MODE__) == I2S_MODE_SLAVE_RX) || \ 551 ((__MODE__) == I2S_MODE_MASTER_TX) || \ 552 ((__MODE__) == I2S_MODE_MASTER_RX)) 553 554 #define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \ 555 ((__STANDARD__) == I2S_STANDARD_MSB) || \ 556 ((__STANDARD__) == I2S_STANDARD_LSB) || \ 557 ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \ 558 ((__STANDARD__) == I2S_STANDARD_PCM_LONG)) 559 560 #define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \ 561 ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \ 562 ((__FORMAT__) == I2S_DATAFORMAT_24B) || \ 563 ((__FORMAT__) == I2S_DATAFORMAT_32B)) 564 565 #define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \ 566 ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE)) 567 568 #define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \ 569 ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \ 570 ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT)) 571 572 #define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \ 573 ((MODE) == I2S_FULLDUPLEXMODE_ENABLE)) 574 575 /** @brief Checks if I2S Serial clock steady state parameter is in allowed range. 576 * @param __CPOL__ specifies the I2S serial clock steady state. 577 * This parameter can be a value of @ref I2S_Clock_Polarity 578 * @retval None 579 */ 580 #define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \ 581 ((__CPOL__) == I2S_CPOL_HIGH)) 582 583 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || defined(STM32F479xx) 584 #define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\ 585 ((CLOCK) == I2S_CLOCK_PLL)) 586 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 587 STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */ 588 589 #if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined (STM32F413xx) || defined(STM32F423xx) 590 #define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\ 591 ((CLOCK) == I2S_CLOCK_PLL) ||\ 592 ((CLOCK) == I2S_CLOCK_PLLSRC) ||\ 593 ((CLOCK) == I2S_CLOCK_PLLR)) 594 #endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 595 596 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 597 #define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\ 598 ((CLOCK) == I2S_CLOCK_PLLSRC) ||\ 599 ((CLOCK) == I2S_CLOCK_PLLR)) 600 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 601 /** 602 * @} 603 */ 604 605 /** 606 * @} 607 */ 608 609 /** 610 * @} 611 */ 612 613 #ifdef __cplusplus 614 } 615 #endif 616 617 #endif /* STM32F4xx_HAL_I2S_H */ 618 619
