1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_hal_dma2d.h 4 * @author MCD Application Team 5 * @brief Header file of DMA2D HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32F4xx_HAL_DMA2D_H 21 #define STM32F4xx_HAL_DMA2D_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f4xx_hal_def.h" 29 30 /** @addtogroup STM32F4xx_HAL_Driver 31 * @{ 32 */ 33 34 #if defined (DMA2D) 35 36 /** @addtogroup DMA2D DMA2D 37 * @brief DMA2D HAL module driver 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup DMA2D_Exported_Types DMA2D Exported Types 43 * @{ 44 */ 45 #define MAX_DMA2D_LAYER 2U /*!< DMA2D maximum number of layers */ 46 47 /** 48 * @brief DMA2D CLUT Structure definition 49 */ 50 typedef struct 51 { 52 uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/ 53 54 uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode. 55 This parameter can be one value of @ref DMA2D_CLUT_CM. */ 56 57 uint32_t Size; /*!< Configures the DMA2D CLUT size. 58 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/ 59 } DMA2D_CLUTCfgTypeDef; 60 61 /** 62 * @brief DMA2D Init structure definition 63 */ 64 typedef struct 65 { 66 uint32_t Mode; /*!< Configures the DMA2D transfer mode. 67 This parameter can be one value of @ref DMA2D_Mode. */ 68 69 uint32_t ColorMode; /*!< Configures the color format of the output image. 70 This parameter can be one value of @ref DMA2D_Output_Color_Mode. */ 71 72 uint32_t OutputOffset; /*!< Specifies the Offset value. 73 This parameter must be a number between 74 Min_Data = 0x0000 and Max_Data = 0x3FFF. */ 75 76 77 78 79 } DMA2D_InitTypeDef; 80 81 82 /** 83 * @brief DMA2D Layer structure definition 84 */ 85 typedef struct 86 { 87 uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset. 88 This parameter must be a number between 89 Min_Data = 0x0000 and Max_Data = 0x3FFF. */ 90 91 uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode. 92 This parameter can be one value of @ref DMA2D_Input_Color_Mode. */ 93 94 uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode. 95 This parameter can be one value of @ref DMA2D_Alpha_Mode. */ 96 97 uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value 98 in case of A8 or A4 color mode. 99 This parameter must be a number between Min_Data = 0x00 100 and Max_Data = 0xFF except for the color modes detailed below. 101 @note In case of A8 or A4 color mode (ARGB), 102 this parameter must be a number between 103 Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where 104 - InputAlpha[24:31] is the alpha value ALPHA[0:7] 105 - InputAlpha[16:23] is the red value RED[0:7] 106 - InputAlpha[8:15] is the green value GREEN[0:7] 107 - InputAlpha[0:7] is the blue value BLUE[0:7]. */ 108 109 110 } DMA2D_LayerCfgTypeDef; 111 112 /** 113 * @brief HAL DMA2D State structures definition 114 */ 115 typedef enum 116 { 117 HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */ 118 HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 119 HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 120 HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 121 HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */ 122 HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */ 123 } HAL_DMA2D_StateTypeDef; 124 125 /** 126 * @brief DMA2D handle Structure definition 127 */ 128 typedef struct __DMA2D_HandleTypeDef 129 { 130 DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */ 131 132 DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */ 133 134 void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer complete callback. */ 135 136 void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer error callback. */ 137 138 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 139 void (* LineEventCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D line event callback. */ 140 141 void (* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D CLUT loading completion callback */ 142 143 void (* MspInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp Init callback. */ 144 145 void (* MspDeInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp DeInit callback. */ 146 147 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ 148 149 DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ 150 151 HAL_LockTypeDef Lock; /*!< DMA2D lock. */ 152 153 __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */ 154 155 __IO uint32_t ErrorCode; /*!< DMA2D error code. */ 156 } DMA2D_HandleTypeDef; 157 158 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 159 /** 160 * @brief HAL DMA2D Callback pointer definition 161 */ 162 typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointer to a DMA2D common callback function */ 163 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 164 /** 165 * @} 166 */ 167 168 /* Exported constants --------------------------------------------------------*/ 169 /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants 170 * @{ 171 */ 172 173 /** @defgroup DMA2D_Error_Code DMA2D Error Code 174 * @{ 175 */ 176 #define HAL_DMA2D_ERROR_NONE 0x00000000U /*!< No error */ 177 #define HAL_DMA2D_ERROR_TE 0x00000001U /*!< Transfer error */ 178 #define HAL_DMA2D_ERROR_CE 0x00000002U /*!< Configuration error */ 179 #define HAL_DMA2D_ERROR_CAE 0x00000004U /*!< CLUT access error */ 180 #define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 181 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 182 #define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid callback error */ 183 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ 184 185 /** 186 * @} 187 */ 188 189 /** @defgroup DMA2D_Mode DMA2D Mode 190 * @{ 191 */ 192 #define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ 193 #define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ 194 #define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ 195 #define DMA2D_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */ 196 /** 197 * @} 198 */ 199 200 /** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode 201 * @{ 202 */ 203 #define DMA2D_OUTPUT_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D color mode */ 204 #define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */ 205 #define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */ 206 #define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */ 207 #define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */ 208 /** 209 * @} 210 */ 211 212 /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode 213 * @{ 214 */ 215 #define DMA2D_INPUT_ARGB8888 0x00000000U /*!< ARGB8888 color mode */ 216 #define DMA2D_INPUT_RGB888 0x00000001U /*!< RGB888 color mode */ 217 #define DMA2D_INPUT_RGB565 0x00000002U /*!< RGB565 color mode */ 218 #define DMA2D_INPUT_ARGB1555 0x00000003U /*!< ARGB1555 color mode */ 219 #define DMA2D_INPUT_ARGB4444 0x00000004U /*!< ARGB4444 color mode */ 220 #define DMA2D_INPUT_L8 0x00000005U /*!< L8 color mode */ 221 #define DMA2D_INPUT_AL44 0x00000006U /*!< AL44 color mode */ 222 #define DMA2D_INPUT_AL88 0x00000007U /*!< AL88 color mode */ 223 #define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */ 224 #define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */ 225 #define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */ 226 /** 227 * @} 228 */ 229 230 /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode 231 * @{ 232 */ 233 #define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ 234 #define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */ 235 #define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value 236 with original alpha channel value */ 237 /** 238 * @} 239 */ 240 241 242 243 244 245 246 /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode 247 * @{ 248 */ 249 #define DMA2D_CCM_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D CLUT color mode */ 250 #define DMA2D_CCM_RGB888 0x00000001U /*!< RGB888 DMA2D CLUT color mode */ 251 /** 252 * @} 253 */ 254 255 /** @defgroup DMA2D_Interrupts DMA2D Interrupts 256 * @{ 257 */ 258 #define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ 259 #define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */ 260 #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */ 261 #define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ 262 #define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ 263 #define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ 264 /** 265 * @} 266 */ 267 268 /** @defgroup DMA2D_Flags DMA2D Flags 269 * @{ 270 */ 271 #define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ 272 #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ 273 #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ 274 #define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ 275 #define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ 276 #define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ 277 /** 278 * @} 279 */ 280 281 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 282 /** 283 * @brief HAL DMA2D common Callback ID enumeration definition 284 */ 285 typedef enum 286 { 287 HAL_DMA2D_MSPINIT_CB_ID = 0x00U, /*!< DMA2D MspInit callback ID */ 288 HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U, /*!< DMA2D MspDeInit callback ID */ 289 HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U, /*!< DMA2D transfer complete callback ID */ 290 HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */ 291 HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */ 292 HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */ 293 } HAL_DMA2D_CallbackIDTypeDef; 294 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 295 296 297 /** 298 * @} 299 */ 300 /* Exported macros ------------------------------------------------------------*/ 301 /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros 302 * @{ 303 */ 304 305 /** @brief Reset DMA2D handle state 306 * @param __HANDLE__ specifies the DMA2D handle. 307 * @retval None 308 */ 309 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 310 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \ 311 (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\ 312 (__HANDLE__)->MspInitCallback = NULL; \ 313 (__HANDLE__)->MspDeInitCallback = NULL; \ 314 }while(0) 315 #else 316 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) 317 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 318 319 320 /** 321 * @brief Enable the DMA2D. 322 * @param __HANDLE__ DMA2D handle 323 * @retval None. 324 */ 325 #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) 326 327 328 /* Interrupt & Flag management */ 329 /** 330 * @brief Get the DMA2D pending flags. 331 * @param __HANDLE__ DMA2D handle 332 * @param __FLAG__ flag to check. 333 * This parameter can be any combination of the following values: 334 * @arg DMA2D_FLAG_CE: Configuration error flag 335 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag 336 * @arg DMA2D_FLAG_CAE: CLUT access error flag 337 * @arg DMA2D_FLAG_TW: Transfer Watermark flag 338 * @arg DMA2D_FLAG_TC: Transfer complete flag 339 * @arg DMA2D_FLAG_TE: Transfer error flag 340 * @retval The state of FLAG. 341 */ 342 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) 343 344 /** 345 * @brief Clear the DMA2D pending flags. 346 * @param __HANDLE__ DMA2D handle 347 * @param __FLAG__ specifies the flag to clear. 348 * This parameter can be any combination of the following values: 349 * @arg DMA2D_FLAG_CE: Configuration error flag 350 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag 351 * @arg DMA2D_FLAG_CAE: CLUT access error flag 352 * @arg DMA2D_FLAG_TW: Transfer Watermark flag 353 * @arg DMA2D_FLAG_TC: Transfer complete flag 354 * @arg DMA2D_FLAG_TE: Transfer error flag 355 * @retval None 356 */ 357 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__)) 358 359 /** 360 * @brief Enable the specified DMA2D interrupts. 361 * @param __HANDLE__ DMA2D handle 362 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled. 363 * This parameter can be any combination of the following values: 364 * @arg DMA2D_IT_CE: Configuration error interrupt mask 365 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 366 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 367 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 368 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 369 * @arg DMA2D_IT_TE: Transfer error interrupt mask 370 * @retval None 371 */ 372 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) 373 374 /** 375 * @brief Disable the specified DMA2D interrupts. 376 * @param __HANDLE__ DMA2D handle 377 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled. 378 * This parameter can be any combination of the following values: 379 * @arg DMA2D_IT_CE: Configuration error interrupt mask 380 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 381 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 382 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 383 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 384 * @arg DMA2D_IT_TE: Transfer error interrupt mask 385 * @retval None 386 */ 387 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) 388 389 /** 390 * @brief Check whether the specified DMA2D interrupt source is enabled or not. 391 * @param __HANDLE__ DMA2D handle 392 * @param __INTERRUPT__ specifies the DMA2D interrupt source to check. 393 * This parameter can be one of the following values: 394 * @arg DMA2D_IT_CE: Configuration error interrupt mask 395 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 396 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 397 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 398 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 399 * @arg DMA2D_IT_TE: Transfer error interrupt mask 400 * @retval The state of INTERRUPT source. 401 */ 402 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) 403 404 /** 405 * @} 406 */ 407 408 /* Exported functions --------------------------------------------------------*/ 409 /** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions 410 * @{ 411 */ 412 413 /** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions 414 * @{ 415 */ 416 417 /* Initialization and de-initialization functions *******************************/ 418 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); 419 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d); 420 void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d); 421 void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d); 422 /* Callbacks Register/UnRegister functions ***********************************/ 423 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 424 HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, 425 pDMA2D_CallbackTypeDef pCallback); 426 HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID); 427 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 428 429 /** 430 * @} 431 */ 432 433 434 /** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions 435 * @{ 436 */ 437 438 /* IO operation functions *******************************************************/ 439 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, 440 uint32_t Height); 441 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, 442 uint32_t DstAddress, uint32_t Width, uint32_t Height); 443 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, 444 uint32_t Height); 445 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, 446 uint32_t DstAddress, uint32_t Width, uint32_t Height); 447 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); 448 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); 449 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); 450 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 451 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, 452 uint32_t LayerIdx); 453 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, 454 uint32_t LayerIdx); 455 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 456 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 457 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 458 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 459 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 460 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout); 461 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d); 462 void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d); 463 void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d); 464 465 /** 466 * @} 467 */ 468 469 /** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions 470 * @{ 471 */ 472 473 /* Peripheral Control functions *************************************************/ 474 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 475 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 476 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line); 477 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d); 478 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d); 479 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime); 480 481 /** 482 * @} 483 */ 484 485 /** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions 486 * @{ 487 */ 488 489 /* Peripheral State functions ***************************************************/ 490 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d); 491 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); 492 493 /** 494 * @} 495 */ 496 497 /** 498 * @} 499 */ 500 501 /* Private constants ---------------------------------------------------------*/ 502 503 /** @addtogroup DMA2D_Private_Constants DMA2D Private Constants 504 * @{ 505 */ 506 507 /** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark 508 * @{ 509 */ 510 #define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */ 511 /** 512 * @} 513 */ 514 515 /** @defgroup DMA2D_Color_Value DMA2D Color Value 516 * @{ 517 */ 518 #define DMA2D_COLOR_VALUE 0x000000FFU /*!< Color value mask */ 519 /** 520 * @} 521 */ 522 523 /** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers 524 * @{ 525 */ 526 #define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */ 527 /** 528 * @} 529 */ 530 531 /** @defgroup DMA2D_Layers DMA2D Layers 532 * @{ 533 */ 534 #define DMA2D_BACKGROUND_LAYER 0x00000000U /*!< DMA2D Background Layer (layer 0) */ 535 #define DMA2D_FOREGROUND_LAYER 0x00000001U /*!< DMA2D Foreground Layer (layer 1) */ 536 /** 537 * @} 538 */ 539 540 /** @defgroup DMA2D_Offset DMA2D Offset 541 * @{ 542 */ 543 #define DMA2D_OFFSET DMA2D_FGOR_LO /*!< maximum Line Offset */ 544 /** 545 * @} 546 */ 547 548 /** @defgroup DMA2D_Size DMA2D Size 549 * @{ 550 */ 551 #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D maximum number of pixels per line */ 552 #define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D maximum number of lines */ 553 /** 554 * @} 555 */ 556 557 /** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size 558 * @{ 559 */ 560 #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D maximum CLUT size */ 561 /** 562 * @} 563 */ 564 565 /** 566 * @} 567 */ 568 569 570 /* Private macros ------------------------------------------------------------*/ 571 /** @defgroup DMA2D_Private_Macros DMA2D Private Macros 572 * @{ 573 */ 574 #define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER)\ 575 || ((LAYER) == DMA2D_FOREGROUND_LAYER)) 576 577 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ 578 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) 579 580 #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || \ 581 ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ 582 ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || \ 583 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ 584 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) 585 586 #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE) 587 #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE) 588 #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) 589 #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) 590 591 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \ 592 ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ 593 ((INPUT_CM) == DMA2D_INPUT_RGB565) || \ 594 ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ 595 ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \ 596 ((INPUT_CM) == DMA2D_INPUT_L8) || \ 597 ((INPUT_CM) == DMA2D_INPUT_AL44) || \ 598 ((INPUT_CM) == DMA2D_INPUT_AL88) || \ 599 ((INPUT_CM) == DMA2D_INPUT_L4) || \ 600 ((INPUT_CM) == DMA2D_INPUT_A8) || \ 601 ((INPUT_CM) == DMA2D_INPUT_A4)) 602 603 #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ 604 ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \ 605 ((AlphaMode) == DMA2D_COMBINE_ALPHA)) 606 607 608 609 610 611 #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) 612 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) 613 #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX) 614 #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ 615 ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ 616 ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) 617 #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ 618 ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ 619 ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) 620 /** 621 * @} 622 */ 623 624 /** 625 * @} 626 */ 627 628 #endif /* defined (DMA2D) */ 629 630 /** 631 * @} 632 */ 633 634 #ifdef __cplusplus 635 } 636 #endif 637 638 #endif /* STM32F4xx_HAL_DMA2D_H */ 639
