1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32F4xx_HAL_DMA_H 21 #define __STM32F4xx_HAL_DMA_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f4xx_hal_def.h" 29 30 /** @addtogroup STM32F4xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup DMA 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 40 /** @defgroup DMA_Exported_Types DMA Exported Types 41 * @brief DMA Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief DMA Configuration Structure definition 47 */ 48 typedef struct 49 { 50 uint32_t Channel; /*!< Specifies the channel used for the specified stream. 51 This parameter can be a value of @ref DMA_Channel_selection */ 52 53 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 54 from memory to memory or from peripheral to memory. 55 This parameter can be a value of @ref DMA_Data_transfer_direction */ 56 57 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 58 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 59 60 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 61 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 62 63 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 64 This parameter can be a value of @ref DMA_Peripheral_data_size */ 65 66 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 67 This parameter can be a value of @ref DMA_Memory_data_size */ 68 69 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. 70 This parameter can be a value of @ref DMA_mode 71 @note The circular buffer mode cannot be used if the memory-to-memory 72 data transfer is configured on the selected Stream */ 73 74 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. 75 This parameter can be a value of @ref DMA_Priority_level */ 76 77 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. 78 This parameter can be a value of @ref DMA_FIFO_direct_mode 79 @note The Direct mode (FIFO mode disabled) cannot be used if the 80 memory-to-memory data transfer is configured on the selected stream */ 81 82 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. 83 This parameter can be a value of @ref DMA_FIFO_threshold_level */ 84 85 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. 86 It specifies the amount of data to be transferred in a single non interruptible 87 transaction. 88 This parameter can be a value of @ref DMA_Memory_burst 89 @note The burst mode is possible only if the address Increment mode is enabled. */ 90 91 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. 92 It specifies the amount of data to be transferred in a single non interruptible 93 transaction. 94 This parameter can be a value of @ref DMA_Peripheral_burst 95 @note The burst mode is possible only if the address Increment mode is enabled. */ 96 }DMA_InitTypeDef; 97 98 99 /** 100 * @brief HAL DMA State structures definition 101 */ 102 typedef enum 103 { 104 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 105 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 106 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 107 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ 108 HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */ 109 HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */ 110 }HAL_DMA_StateTypeDef; 111 112 /** 113 * @brief HAL DMA Error Code structure definition 114 */ 115 typedef enum 116 { 117 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 118 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ 119 }HAL_DMA_LevelCompleteTypeDef; 120 121 /** 122 * @brief HAL DMA Error Code structure definition 123 */ 124 typedef enum 125 { 126 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 127 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */ 128 HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */ 129 HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */ 130 HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ 131 HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ 132 HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ 133 }HAL_DMA_CallbackIDTypeDef; 134 135 /** 136 * @brief DMA handle Structure definition 137 */ 138 typedef struct __DMA_HandleTypeDef 139 { 140 DMA_Stream_TypeDef *Instance; /*!< Register base address */ 141 142 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 143 144 HAL_LockTypeDef Lock; /*!< DMA locking object */ 145 146 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 147 148 void *Parent; /*!< Parent object state */ 149 150 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ 151 152 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ 153 154 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ 155 156 void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */ 157 158 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ 159 160 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */ 161 162 __IO uint32_t ErrorCode; /*!< DMA Error code */ 163 164 uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ 165 166 uint32_t StreamIndex; /*!< DMA Stream Index */ 167 168 }DMA_HandleTypeDef; 169 170 /** 171 * @} 172 */ 173 174 /* Exported constants --------------------------------------------------------*/ 175 176 /** @defgroup DMA_Exported_Constants DMA Exported Constants 177 * @brief DMA Exported constants 178 * @{ 179 */ 180 181 /** @defgroup DMA_Error_Code DMA Error Code 182 * @brief DMA Error Code 183 * @{ 184 */ 185 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ 186 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ 187 #define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */ 188 #define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */ 189 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 190 #define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */ 191 #define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */ 192 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ 193 /** 194 * @} 195 */ 196 197 /** @defgroup DMA_Channel_selection DMA Channel selection 198 * @brief DMA channel selection 199 * @{ 200 */ 201 #define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */ 202 #define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */ 203 #define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */ 204 #define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */ 205 #define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */ 206 #define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */ 207 #define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */ 208 #define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */ 209 #if defined (DMA_SxCR_CHSEL_3) 210 #define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */ 211 #define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */ 212 #define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10 */ 213 #define DMA_CHANNEL_11 0x16000000U /*!< DMA Channel 11 */ 214 #define DMA_CHANNEL_12 0x18000000U /*!< DMA Channel 12 */ 215 #define DMA_CHANNEL_13 0x1A000000U /*!< DMA Channel 13 */ 216 #define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14 */ 217 #define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15 */ 218 #endif /* DMA_SxCR_CHSEL_3 */ 219 /** 220 * @} 221 */ 222 223 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 224 * @brief DMA data transfer direction 225 * @{ 226 */ 227 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 228 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ 229 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ 230 /** 231 * @} 232 */ 233 234 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 235 * @brief DMA peripheral incremented mode 236 * @{ 237 */ 238 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ 239 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */ 240 /** 241 * @} 242 */ 243 244 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 245 * @brief DMA memory incremented mode 246 * @{ 247 */ 248 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ 249 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */ 250 /** 251 * @} 252 */ 253 254 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 255 * @brief DMA peripheral data size 256 * @{ 257 */ 258 #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ 259 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ 260 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ 261 /** 262 * @} 263 */ 264 265 /** @defgroup DMA_Memory_data_size DMA Memory data size 266 * @brief DMA memory data size 267 * @{ 268 */ 269 #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ 270 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ 271 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */ 272 /** 273 * @} 274 */ 275 276 /** @defgroup DMA_mode DMA mode 277 * @brief DMA mode 278 * @{ 279 */ 280 #define DMA_NORMAL 0x00000000U /*!< Normal mode */ 281 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ 282 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ 283 /** 284 * @} 285 */ 286 287 /** @defgroup DMA_Priority_level DMA Priority level 288 * @brief DMA priority levels 289 * @{ 290 */ 291 #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */ 292 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */ 293 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */ 294 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ 295 /** 296 * @} 297 */ 298 299 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode 300 * @brief DMA FIFO direct mode 301 * @{ 302 */ 303 #define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ 304 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ 305 /** 306 * @} 307 */ 308 309 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level 310 * @brief DMA FIFO level 311 * @{ 312 */ 313 #define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */ 314 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */ 315 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */ 316 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ 317 /** 318 * @} 319 */ 320 321 /** @defgroup DMA_Memory_burst DMA Memory burst 322 * @brief DMA memory burst 323 * @{ 324 */ 325 #define DMA_MBURST_SINGLE 0x00000000U 326 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) 327 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) 328 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) 329 /** 330 * @} 331 */ 332 333 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst 334 * @brief DMA peripheral burst 335 * @{ 336 */ 337 #define DMA_PBURST_SINGLE 0x00000000U 338 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) 339 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) 340 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) 341 /** 342 * @} 343 */ 344 345 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 346 * @brief DMA interrupts definition 347 * @{ 348 */ 349 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) 350 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) 351 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) 352 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) 353 #define DMA_IT_FE 0x00000080U 354 /** 355 * @} 356 */ 357 358 /** @defgroup DMA_flag_definitions DMA flag definitions 359 * @brief DMA flag definitions 360 * @{ 361 */ 362 #define DMA_FLAG_FEIF0_4 0x00000001U 363 #define DMA_FLAG_DMEIF0_4 0x00000004U 364 #define DMA_FLAG_TEIF0_4 0x00000008U 365 #define DMA_FLAG_HTIF0_4 0x00000010U 366 #define DMA_FLAG_TCIF0_4 0x00000020U 367 #define DMA_FLAG_FEIF1_5 0x00000040U 368 #define DMA_FLAG_DMEIF1_5 0x00000100U 369 #define DMA_FLAG_TEIF1_5 0x00000200U 370 #define DMA_FLAG_HTIF1_5 0x00000400U 371 #define DMA_FLAG_TCIF1_5 0x00000800U 372 #define DMA_FLAG_FEIF2_6 0x00010000U 373 #define DMA_FLAG_DMEIF2_6 0x00040000U 374 #define DMA_FLAG_TEIF2_6 0x00080000U 375 #define DMA_FLAG_HTIF2_6 0x00100000U 376 #define DMA_FLAG_TCIF2_6 0x00200000U 377 #define DMA_FLAG_FEIF3_7 0x00400000U 378 #define DMA_FLAG_DMEIF3_7 0x01000000U 379 #define DMA_FLAG_TEIF3_7 0x02000000U 380 #define DMA_FLAG_HTIF3_7 0x04000000U 381 #define DMA_FLAG_TCIF3_7 0x08000000U 382 /** 383 * @} 384 */ 385 386 /** 387 * @} 388 */ 389 390 /* Exported macro ------------------------------------------------------------*/ 391 392 /** @brief Reset DMA handle state 393 * @param __HANDLE__ specifies the DMA handle. 394 * @retval None 395 */ 396 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 397 398 /** 399 * @brief Return the current DMA Stream FIFO filled level. 400 * @param __HANDLE__ DMA handle 401 * @retval The FIFO filling state. 402 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full 403 * and not empty. 404 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. 405 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. 406 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. 407 * - DMA_FIFOStatus_Empty: when FIFO is empty 408 * - DMA_FIFOStatus_Full: when FIFO is full 409 */ 410 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS))) 411 412 /** 413 * @brief Enable the specified DMA Stream. 414 * @param __HANDLE__ DMA handle 415 * @retval None 416 */ 417 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN) 418 419 /** 420 * @brief Disable the specified DMA Stream. 421 * @param __HANDLE__ DMA handle 422 * @retval None 423 */ 424 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN) 425 426 /* Interrupt & Flag management */ 427 428 /** 429 * @brief Return the current DMA Stream transfer complete flag. 430 * @param __HANDLE__ DMA handle 431 * @retval The specified transfer complete flag index. 432 */ 433 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 434 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ 435 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ 436 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ 437 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ 438 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ 439 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ 440 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ 441 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ 442 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ 443 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ 444 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ 445 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ 446 DMA_FLAG_TCIF3_7) 447 448 /** 449 * @brief Return the current DMA Stream half transfer complete flag. 450 * @param __HANDLE__ DMA handle 451 * @retval The specified half transfer complete flag index. 452 */ 453 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 454 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ 455 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ 456 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ 457 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ 458 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ 459 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ 460 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ 461 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ 462 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ 463 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ 464 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ 465 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ 466 DMA_FLAG_HTIF3_7) 467 468 /** 469 * @brief Return the current DMA Stream transfer error flag. 470 * @param __HANDLE__ DMA handle 471 * @retval The specified transfer error flag index. 472 */ 473 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 474 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ 475 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ 476 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ 477 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ 478 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ 479 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ 480 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ 481 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ 482 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ 483 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ 484 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ 485 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ 486 DMA_FLAG_TEIF3_7) 487 488 /** 489 * @brief Return the current DMA Stream FIFO error flag. 490 * @param __HANDLE__ DMA handle 491 * @retval The specified FIFO error flag index. 492 */ 493 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ 494 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ 495 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ 496 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ 497 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ 498 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ 499 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ 500 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ 501 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ 502 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ 503 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ 504 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ 505 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ 506 DMA_FLAG_FEIF3_7) 507 508 /** 509 * @brief Return the current DMA Stream direct mode error flag. 510 * @param __HANDLE__ DMA handle 511 * @retval The specified direct mode error flag index. 512 */ 513 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ 514 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ 515 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ 516 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ 517 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ 518 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ 519 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ 520 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ 521 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ 522 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ 523 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ 524 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ 525 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ 526 DMA_FLAG_DMEIF3_7) 527 528 /** 529 * @brief Get the DMA Stream pending flags. 530 * @param __HANDLE__ DMA handle 531 * @param __FLAG__ Get the specified flag. 532 * This parameter can be any combination of the following values: 533 * @arg DMA_FLAG_TCIFx: Transfer complete flag. 534 * @arg DMA_FLAG_HTIFx: Half transfer complete flag. 535 * @arg DMA_FLAG_TEIFx: Transfer error flag. 536 * @arg DMA_FLAG_DMEIFx: Direct mode error flag. 537 * @arg DMA_FLAG_FEIFx: FIFO error flag. 538 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. 539 * @retval The state of FLAG (SET or RESET). 540 */ 541 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ 542 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ 543 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ 544 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) 545 546 /** 547 * @brief Clear the DMA Stream pending flags. 548 * @param __HANDLE__ DMA handle 549 * @param __FLAG__ specifies the flag to clear. 550 * This parameter can be any combination of the following values: 551 * @arg DMA_FLAG_TCIFx: Transfer complete flag. 552 * @arg DMA_FLAG_HTIFx: Half transfer complete flag. 553 * @arg DMA_FLAG_TEIFx: Transfer error flag. 554 * @arg DMA_FLAG_DMEIFx: Direct mode error flag. 555 * @arg DMA_FLAG_FEIFx: FIFO error flag. 556 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. 557 * @retval None 558 */ 559 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 560 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ 561 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ 562 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) 563 564 /** 565 * @brief Enable the specified DMA Stream interrupts. 566 * @param __HANDLE__ DMA handle 567 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 568 * This parameter can be any combination of the following values: 569 * @arg DMA_IT_TC: Transfer complete interrupt mask. 570 * @arg DMA_IT_HT: Half transfer complete interrupt mask. 571 * @arg DMA_IT_TE: Transfer error interrupt mask. 572 * @arg DMA_IT_FE: FIFO error interrupt mask. 573 * @arg DMA_IT_DME: Direct mode error interrupt. 574 * @retval None 575 */ 576 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ 577 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__))) 578 579 /** 580 * @brief Disable the specified DMA Stream interrupts. 581 * @param __HANDLE__ DMA handle 582 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 583 * This parameter can be any combination of the following values: 584 * @arg DMA_IT_TC: Transfer complete interrupt mask. 585 * @arg DMA_IT_HT: Half transfer complete interrupt mask. 586 * @arg DMA_IT_TE: Transfer error interrupt mask. 587 * @arg DMA_IT_FE: FIFO error interrupt mask. 588 * @arg DMA_IT_DME: Direct mode error interrupt. 589 * @retval None 590 */ 591 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ 592 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__))) 593 594 /** 595 * @brief Check whether the specified DMA Stream interrupt is enabled or disabled. 596 * @param __HANDLE__ DMA handle 597 * @param __INTERRUPT__ specifies the DMA interrupt source to check. 598 * This parameter can be one of the following values: 599 * @arg DMA_IT_TC: Transfer complete interrupt mask. 600 * @arg DMA_IT_HT: Half transfer complete interrupt mask. 601 * @arg DMA_IT_TE: Transfer error interrupt mask. 602 * @arg DMA_IT_FE: FIFO error interrupt mask. 603 * @arg DMA_IT_DME: Direct mode error interrupt. 604 * @retval The state of DMA_IT. 605 */ 606 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ 607 ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \ 608 ((__HANDLE__)->Instance->FCR & (__INTERRUPT__))) 609 610 /** 611 * @brief Writes the number of data units to be transferred on the DMA Stream. 612 * @param __HANDLE__ DMA handle 613 * @param __COUNTER__ Number of data units to be transferred (from 0 to 65535) 614 * Number of data items depends only on the Peripheral data format. 615 * 616 * @note If Peripheral data format is Bytes: number of data units is equal 617 * to total number of bytes to be transferred. 618 * 619 * @note If Peripheral data format is Half-Word: number of data units is 620 * equal to total number of bytes to be transferred / 2. 621 * 622 * @note If Peripheral data format is Word: number of data units is equal 623 * to total number of bytes to be transferred / 4. 624 * 625 * @retval The number of remaining data units in the current DMAy Streamx transfer. 626 */ 627 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__)) 628 629 /** 630 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. 631 * @param __HANDLE__ DMA handle 632 * 633 * @retval The number of remaining data units in the current DMA Stream transfer. 634 */ 635 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR) 636 637 638 /* Include DMA HAL Extension module */ 639 #include "stm32f4xx_hal_dma_ex.h" 640 641 /* Exported functions --------------------------------------------------------*/ 642 643 /** @defgroup DMA_Exported_Functions DMA Exported Functions 644 * @brief DMA Exported functions 645 * @{ 646 */ 647 648 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions 649 * @brief Initialization and de-initialization functions 650 * @{ 651 */ 652 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 653 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); 654 /** 655 * @} 656 */ 657 658 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions 659 * @brief I/O operation functions 660 * @{ 661 */ 662 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 663 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 664 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 665 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 666 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); 667 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 668 HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma); 669 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); 670 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 671 672 /** 673 * @} 674 */ 675 676 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions 677 * @brief Peripheral State functions 678 * @{ 679 */ 680 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 681 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 682 /** 683 * @} 684 */ 685 /** 686 * @} 687 */ 688 /* Private Constants -------------------------------------------------------------*/ 689 /** @defgroup DMA_Private_Constants DMA Private Constants 690 * @brief DMA private defines and constants 691 * @{ 692 */ 693 /** 694 * @} 695 */ 696 697 /* Private macros ------------------------------------------------------------*/ 698 /** @defgroup DMA_Private_Macros DMA Private Macros 699 * @brief DMA private macros 700 * @{ 701 */ 702 #if defined (DMA_SxCR_CHSEL_3) 703 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ 704 ((CHANNEL) == DMA_CHANNEL_1) || \ 705 ((CHANNEL) == DMA_CHANNEL_2) || \ 706 ((CHANNEL) == DMA_CHANNEL_3) || \ 707 ((CHANNEL) == DMA_CHANNEL_4) || \ 708 ((CHANNEL) == DMA_CHANNEL_5) || \ 709 ((CHANNEL) == DMA_CHANNEL_6) || \ 710 ((CHANNEL) == DMA_CHANNEL_7) || \ 711 ((CHANNEL) == DMA_CHANNEL_8) || \ 712 ((CHANNEL) == DMA_CHANNEL_9) || \ 713 ((CHANNEL) == DMA_CHANNEL_10)|| \ 714 ((CHANNEL) == DMA_CHANNEL_11)|| \ 715 ((CHANNEL) == DMA_CHANNEL_12)|| \ 716 ((CHANNEL) == DMA_CHANNEL_13)|| \ 717 ((CHANNEL) == DMA_CHANNEL_14)|| \ 718 ((CHANNEL) == DMA_CHANNEL_15)) 719 #else 720 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ 721 ((CHANNEL) == DMA_CHANNEL_1) || \ 722 ((CHANNEL) == DMA_CHANNEL_2) || \ 723 ((CHANNEL) == DMA_CHANNEL_3) || \ 724 ((CHANNEL) == DMA_CHANNEL_4) || \ 725 ((CHANNEL) == DMA_CHANNEL_5) || \ 726 ((CHANNEL) == DMA_CHANNEL_6) || \ 727 ((CHANNEL) == DMA_CHANNEL_7)) 728 #endif /* DMA_SxCR_CHSEL_3 */ 729 730 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 731 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 732 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 733 734 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) 735 736 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 737 ((STATE) == DMA_PINC_DISABLE)) 738 739 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 740 ((STATE) == DMA_MINC_DISABLE)) 741 742 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 743 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 744 ((SIZE) == DMA_PDATAALIGN_WORD)) 745 746 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 747 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 748 ((SIZE) == DMA_MDATAALIGN_WORD )) 749 750 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 751 ((MODE) == DMA_CIRCULAR) || \ 752 ((MODE) == DMA_PFCTRL)) 753 754 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 755 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 756 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 757 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 758 759 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ 760 ((STATE) == DMA_FIFOMODE_ENABLE)) 761 762 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ 763 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ 764 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ 765 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) 766 767 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ 768 ((BURST) == DMA_MBURST_INC4) || \ 769 ((BURST) == DMA_MBURST_INC8) || \ 770 ((BURST) == DMA_MBURST_INC16)) 771 772 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ 773 ((BURST) == DMA_PBURST_INC4) || \ 774 ((BURST) == DMA_PBURST_INC8) || \ 775 ((BURST) == DMA_PBURST_INC16)) 776 /** 777 * @} 778 */ 779 780 /* Private functions ---------------------------------------------------------*/ 781 /** @defgroup DMA_Private_Functions DMA Private Functions 782 * @brief DMA private functions 783 * @{ 784 */ 785 /** 786 * @} 787 */ 788 789 /** 790 * @} 791 */ 792 793 /** 794 * @} 795 */ 796 797 #ifdef __cplusplus 798 } 799 #endif 800 801 #endif /* __STM32F4xx_HAL_DMA_H */ 802 803
