1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_hal_eth_legacy.h 4 * @author MCD Application Team 5 * @brief Header file of ETH HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32F4xx_HAL_ETH_LEGACY_H 21 #define __STM32F4xx_HAL_ETH_LEGACY_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\ 28 defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 29 /* Includes ------------------------------------------------------------------*/ 30 #include "stm32f4xx_hal_def.h" 31 32 /** @addtogroup STM32F4xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup ETH 37 * @{ 38 */ 39 40 /** @addtogroup ETH_Private_Macros 41 * @{ 42 */ 43 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U) 44 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \ 45 ((CMD) == ETH_AUTONEGOTIATION_DISABLE)) 46 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \ 47 ((SPEED) == ETH_SPEED_100M)) 48 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \ 49 ((MODE) == ETH_MODE_HALFDUPLEX)) 50 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \ 51 ((MODE) == ETH_RXINTERRUPT_MODE)) 52 #define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \ 53 ((MODE) == ETH_CHECKSUM_BY_SOFTWARE)) 54 #define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \ 55 ((MODE) == ETH_MEDIA_INTERFACE_RMII)) 56 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \ 57 ((CMD) == ETH_WATCHDOG_DISABLE)) 58 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \ 59 ((CMD) == ETH_JABBER_DISABLE)) 60 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \ 61 ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \ 62 ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \ 63 ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \ 64 ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \ 65 ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \ 66 ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \ 67 ((GAP) == ETH_INTERFRAMEGAP_40BIT)) 68 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \ 69 ((CMD) == ETH_CARRIERSENCE_DISABLE)) 70 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \ 71 ((CMD) == ETH_RECEIVEOWN_DISABLE)) 72 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \ 73 ((CMD) == ETH_LOOPBACKMODE_DISABLE)) 74 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \ 75 ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE)) 76 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \ 77 ((CMD) == ETH_RETRYTRANSMISSION_DISABLE)) 78 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \ 79 ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE)) 80 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \ 81 ((LIMIT) == ETH_BACKOFFLIMIT_8) || \ 82 ((LIMIT) == ETH_BACKOFFLIMIT_4) || \ 83 ((LIMIT) == ETH_BACKOFFLIMIT_1)) 84 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \ 85 ((CMD) == ETH_DEFFERRALCHECK_DISABLE)) 86 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \ 87 ((CMD) == ETH_RECEIVEAll_DISABLE)) 88 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \ 89 ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \ 90 ((CMD) == ETH_SOURCEADDRFILTER_DISABLE)) 91 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \ 92 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \ 93 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER)) 94 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \ 95 ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE)) 96 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \ 97 ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE)) 98 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \ 99 ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE)) 100 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \ 101 ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \ 102 ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \ 103 ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE)) 104 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \ 105 ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \ 106 ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT)) 107 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU) 108 #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \ 109 ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE)) 110 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \ 111 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \ 112 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \ 113 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256)) 114 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \ 115 ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE)) 116 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \ 117 ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE)) 118 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \ 119 ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE)) 120 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \ 121 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT)) 122 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU) 123 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \ 124 ((ADDRESS) == ETH_MAC_ADDRESS1) || \ 125 ((ADDRESS) == ETH_MAC_ADDRESS2) || \ 126 ((ADDRESS) == ETH_MAC_ADDRESS3)) 127 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \ 128 ((ADDRESS) == ETH_MAC_ADDRESS2) || \ 129 ((ADDRESS) == ETH_MAC_ADDRESS3)) 130 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \ 131 ((FILTER) == ETH_MAC_ADDRESSFILTER_DA)) 132 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \ 133 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \ 134 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \ 135 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \ 136 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \ 137 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1)) 138 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \ 139 ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE)) 140 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \ 141 ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE)) 142 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \ 143 ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE)) 144 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \ 145 ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE)) 146 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \ 147 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \ 148 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \ 149 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \ 150 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \ 151 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \ 152 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \ 153 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES)) 154 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \ 155 ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE)) 156 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \ 157 ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE)) 158 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \ 159 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \ 160 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \ 161 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES)) 162 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \ 163 ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE)) 164 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \ 165 ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE)) 166 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \ 167 ((CMD) == ETH_FIXEDBURST_DISABLE)) 168 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \ 169 ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \ 170 ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \ 171 ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \ 172 ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \ 173 ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \ 174 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \ 175 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \ 176 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \ 177 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \ 178 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \ 179 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT)) 180 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \ 181 ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \ 182 ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \ 183 ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \ 184 ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \ 185 ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \ 186 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \ 187 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \ 188 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \ 189 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \ 190 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \ 191 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT)) 192 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU) 193 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \ 194 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \ 195 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \ 196 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \ 197 ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX)) 198 #define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \ 199 ((FLAG) == ETH_DMATXDESC_IC) || \ 200 ((FLAG) == ETH_DMATXDESC_LS) || \ 201 ((FLAG) == ETH_DMATXDESC_FS) || \ 202 ((FLAG) == ETH_DMATXDESC_DC) || \ 203 ((FLAG) == ETH_DMATXDESC_DP) || \ 204 ((FLAG) == ETH_DMATXDESC_TTSE) || \ 205 ((FLAG) == ETH_DMATXDESC_TER) || \ 206 ((FLAG) == ETH_DMATXDESC_TCH) || \ 207 ((FLAG) == ETH_DMATXDESC_TTSS) || \ 208 ((FLAG) == ETH_DMATXDESC_IHE) || \ 209 ((FLAG) == ETH_DMATXDESC_ES) || \ 210 ((FLAG) == ETH_DMATXDESC_JT) || \ 211 ((FLAG) == ETH_DMATXDESC_FF) || \ 212 ((FLAG) == ETH_DMATXDESC_PCE) || \ 213 ((FLAG) == ETH_DMATXDESC_LCA) || \ 214 ((FLAG) == ETH_DMATXDESC_NC) || \ 215 ((FLAG) == ETH_DMATXDESC_LCO) || \ 216 ((FLAG) == ETH_DMATXDESC_EC) || \ 217 ((FLAG) == ETH_DMATXDESC_VF) || \ 218 ((FLAG) == ETH_DMATXDESC_CC) || \ 219 ((FLAG) == ETH_DMATXDESC_ED) || \ 220 ((FLAG) == ETH_DMATXDESC_UF) || \ 221 ((FLAG) == ETH_DMATXDESC_DB)) 222 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \ 223 ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT)) 224 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \ 225 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \ 226 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \ 227 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL)) 228 #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU) 229 #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \ 230 ((FLAG) == ETH_DMARXDESC_AFM) || \ 231 ((FLAG) == ETH_DMARXDESC_ES) || \ 232 ((FLAG) == ETH_DMARXDESC_DE) || \ 233 ((FLAG) == ETH_DMARXDESC_SAF) || \ 234 ((FLAG) == ETH_DMARXDESC_LE) || \ 235 ((FLAG) == ETH_DMARXDESC_OE) || \ 236 ((FLAG) == ETH_DMARXDESC_VLAN) || \ 237 ((FLAG) == ETH_DMARXDESC_FS) || \ 238 ((FLAG) == ETH_DMARXDESC_LS) || \ 239 ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \ 240 ((FLAG) == ETH_DMARXDESC_LC) || \ 241 ((FLAG) == ETH_DMARXDESC_FT) || \ 242 ((FLAG) == ETH_DMARXDESC_RWT) || \ 243 ((FLAG) == ETH_DMARXDESC_RE) || \ 244 ((FLAG) == ETH_DMARXDESC_DBE) || \ 245 ((FLAG) == ETH_DMARXDESC_CE) || \ 246 ((FLAG) == ETH_DMARXDESC_MAMPCE)) 247 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \ 248 ((BUFFER) == ETH_DMARXDESC_BUFFER2)) 249 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ 250 ((FLAG) == ETH_PMT_FLAG_MPR)) 251 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U)) 252 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ 253 ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \ 254 ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \ 255 ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ 256 ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ 257 ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ 258 ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ 259 ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ 260 ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ 261 ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ 262 ((FLAG) == ETH_DMA_FLAG_T)) 263 #define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U)) 264 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ 265 ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ 266 ((IT) == ETH_MAC_IT_PMT)) 267 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ 268 ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ 269 ((FLAG) == ETH_MAC_FLAG_PMT)) 270 #define IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U)) 271 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ 272 ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ 273 ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ 274 ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ 275 ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ 276 ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ 277 ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ 278 ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ 279 ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) 280 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \ 281 ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER)) 282 #define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFFU) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \ 283 ((IT) != 0x00U)) 284 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ 285 ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ 286 ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) 287 #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \ 288 ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE)) 289 290 /** 291 * @} 292 */ 293 294 /** @addtogroup ETH_Private_Defines 295 * @{ 296 */ 297 /* Delay to wait when writing to some Ethernet registers */ 298 #define ETH_REG_WRITE_DELAY 0x00000001U 299 300 /* ETHERNET Errors */ 301 #define ETH_SUCCESS 0U 302 #define ETH_ERROR 1U 303 304 /* ETHERNET DMA Tx descriptors Collision Count Shift */ 305 #define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U 306 307 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ 308 #define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U 309 310 /* ETHERNET DMA Rx descriptors Frame Length Shift */ 311 #define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U 312 313 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ 314 #define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U 315 316 /* ETHERNET DMA Rx descriptors Frame length Shift */ 317 #define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U 318 319 /* ETHERNET MAC address offsets */ 320 #define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */ 321 #define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */ 322 323 /* ETHERNET MACMIIAR register Mask */ 324 #define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U 325 326 /* ETHERNET MACCR register Mask */ 327 #define ETH_MACCR_CLEAR_MASK 0xFF20810FU 328 329 /* ETHERNET MACFCR register Mask */ 330 #define ETH_MACFCR_CLEAR_MASK 0x0000FF41U 331 332 /* ETHERNET DMAOMR register Mask */ 333 #define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U 334 335 /* ETHERNET Remote Wake-up frame register length */ 336 #define ETH_WAKEUP_REGISTER_LENGTH 8U 337 338 /* ETHERNET Missed frames counter Shift */ 339 #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U 340 /** 341 * @} 342 */ 343 344 /* Exported types ------------------------------------------------------------*/ 345 /** @defgroup ETH_Exported_Types ETH Exported Types 346 * @{ 347 */ 348 349 /** 350 * @brief HAL State structures definition 351 */ 352 typedef enum 353 { 354 HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */ 355 HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 356 HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ 357 HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ 358 HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ 359 HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */ 360 HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */ 361 HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */ 362 HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 363 HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ 364 }HAL_ETH_StateTypeDef; 365 366 /** 367 * @brief ETH Init Structure definition 368 */ 369 370 typedef struct 371 { 372 uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY 373 The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) 374 and the mode (half/full-duplex). 375 This parameter can be a value of @ref ETH_AutoNegotiation */ 376 377 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps. 378 This parameter can be a value of @ref ETH_Speed */ 379 380 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode 381 This parameter can be a value of @ref ETH_Duplex_Mode */ 382 383 uint16_t PhyAddress; /*!< Ethernet PHY address. 384 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ 385 386 uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */ 387 388 uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode. 389 This parameter can be a value of @ref ETH_Rx_Mode */ 390 391 uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software. 392 This parameter can be a value of @ref ETH_Checksum_Mode */ 393 394 uint32_t MediaInterface; /*!< Selects the media-independent interface or the reduced media-independent interface. 395 This parameter can be a value of @ref ETH_Media_Interface */ 396 397 } ETH_InitTypeDef; 398 399 400 /** 401 * @brief ETH MAC Configuration Structure definition 402 */ 403 404 typedef struct 405 { 406 uint32_t Watchdog; /*!< Selects or not the Watchdog timer 407 When enabled, the MAC allows no more then 2048 bytes to be received. 408 When disabled, the MAC can receive up to 16384 bytes. 409 This parameter can be a value of @ref ETH_Watchdog */ 410 411 uint32_t Jabber; /*!< Selects or not Jabber timer 412 When enabled, the MAC allows no more then 2048 bytes to be sent. 413 When disabled, the MAC can send up to 16384 bytes. 414 This parameter can be a value of @ref ETH_Jabber */ 415 416 uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission. 417 This parameter can be a value of @ref ETH_Inter_Frame_Gap */ 418 419 uint32_t CarrierSense; /*!< Selects or not the Carrier Sense. 420 This parameter can be a value of @ref ETH_Carrier_Sense */ 421 422 uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn, 423 ReceiveOwn allows the reception of frames when the TX_EN signal is asserted 424 in Half-Duplex mode. 425 This parameter can be a value of @ref ETH_Receive_Own */ 426 427 uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode. 428 This parameter can be a value of @ref ETH_Loop_Back_Mode */ 429 430 uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. 431 This parameter can be a value of @ref ETH_Checksum_Offload */ 432 433 uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL, 434 when a collision occurs (Half-Duplex mode). 435 This parameter can be a value of @ref ETH_Retry_Transmission */ 436 437 uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping. 438 This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ 439 440 uint32_t BackOffLimit; /*!< Selects the BackOff limit value. 441 This parameter can be a value of @ref ETH_Back_Off_Limit */ 442 443 uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode). 444 This parameter can be a value of @ref ETH_Deferral_Check */ 445 446 uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering). 447 This parameter can be a value of @ref ETH_Receive_All */ 448 449 uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode. 450 This parameter can be a value of @ref ETH_Source_Addr_Filter */ 451 452 uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) 453 This parameter can be a value of @ref ETH_Pass_Control_Frames */ 454 455 uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames. 456 This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ 457 458 uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames. 459 This parameter can be a value of @ref ETH_Destination_Addr_Filter */ 460 461 uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode 462 This parameter can be a value of @ref ETH_Promiscuous_Mode */ 463 464 uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter. 465 This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ 466 467 uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter. 468 This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ 469 470 uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. 471 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */ 472 473 uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table. 474 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */ 475 476 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame. 477 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFU */ 478 479 uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames. 480 This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ 481 482 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for 483 automatic retransmission of PAUSE Frame. 484 This parameter can be a value of @ref ETH_Pause_Low_Threshold */ 485 486 uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0 487 unicast address and unique multicast address). 488 This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ 489 490 uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and 491 disable its transmitter for a specified time (Pause Time) 492 This parameter can be a value of @ref ETH_Receive_Flow_Control */ 493 494 uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) 495 or the MAC back-pressure operation (Half-Duplex mode) 496 This parameter can be a value of @ref ETH_Transmit_Flow_Control */ 497 498 uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for 499 comparison and filtering. 500 This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ 501 502 uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */ 503 504 } ETH_MACInitTypeDef; 505 506 /** 507 * @brief ETH DMA Configuration Structure definition 508 */ 509 510 typedef struct 511 { 512 uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames. 513 This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ 514 515 uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode. 516 This parameter can be a value of @ref ETH_Receive_Store_Forward */ 517 518 uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames. 519 This parameter can be a value of @ref ETH_Flush_Received_Frame */ 520 521 uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode. 522 This parameter can be a value of @ref ETH_Transmit_Store_Forward */ 523 524 uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control. 525 This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ 526 527 uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames. 528 This parameter can be a value of @ref ETH_Forward_Error_Frames */ 529 530 uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error 531 and length less than 64 bytes) including pad-bytes and CRC) 532 This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ 533 534 uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO. 535 This parameter can be a value of @ref ETH_Receive_Threshold_Control */ 536 537 uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second 538 frame of Transmit data even before obtaining the status for the first frame. 539 This parameter can be a value of @ref ETH_Second_Frame_Operate */ 540 541 uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats. 542 This parameter can be a value of @ref ETH_Address_Aligned_Beats */ 543 544 uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers. 545 This parameter can be a value of @ref ETH_Fixed_Burst */ 546 547 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction. 548 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ 549 550 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction. 551 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ 552 553 uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format. 554 This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */ 555 556 uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) 557 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ 558 559 uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration. 560 This parameter can be a value of @ref ETH_DMA_Arbitration */ 561 } ETH_DMAInitTypeDef; 562 563 564 /** 565 * @brief ETH DMA Descriptors data structure definition 566 */ 567 568 typedef struct 569 { 570 __IO uint32_t Status; /*!< Status */ 571 572 uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ 573 574 uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ 575 576 uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ 577 578 /*!< Enhanced ETHERNET DMA PTP Descriptors */ 579 uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */ 580 581 uint32_t Reserved1; /*!< Reserved */ 582 583 uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */ 584 585 uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */ 586 587 } ETH_DMADescTypeDef; 588 589 /** 590 * @brief Received Frame Informations structure definition 591 */ 592 typedef struct 593 { 594 ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */ 595 596 ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */ 597 598 uint32_t SegCount; /*!< Segment count */ 599 600 uint32_t length; /*!< Frame length */ 601 602 uint32_t buffer; /*!< Frame buffer */ 603 604 } ETH_DMARxFrameInfos; 605 606 /** 607 * @brief ETH Handle Structure definition 608 */ 609 610 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 611 typedef struct __ETH_HandleTypeDef 612 #else 613 typedef struct 614 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 615 { 616 ETH_TypeDef *Instance; /*!< Register base address */ 617 618 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */ 619 620 uint32_t LinkStatus; /*!< Ethernet link status */ 621 622 ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */ 623 624 ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */ 625 626 ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */ 627 628 __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */ 629 630 HAL_LockTypeDef Lock; /*!< ETH Lock */ 631 632 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 633 634 void (* TxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Tx Complete Callback */ 635 void (* RxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Rx Complete Callback */ 636 void (* DMAErrorCallback) ( struct __ETH_HandleTypeDef * heth); /*!< DMA Error Callback */ 637 void (* MspInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp Init callback */ 638 void (* MspDeInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp DeInit callback */ 639 640 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 641 642 } ETH_HandleTypeDef; 643 644 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 645 /** 646 * @brief HAL ETH Callback ID enumeration definition 647 */ 648 typedef enum 649 { 650 HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */ 651 HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */ 652 HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */ 653 HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */ 654 HAL_ETH_DMA_ERROR_CB_ID = 0x04U, /*!< ETH DMA Error Callback ID */ 655 656 }HAL_ETH_CallbackIDTypeDef; 657 658 /** 659 * @brief HAL ETH Callback pointer definition 660 */ 661 typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef * heth); /*!< pointer to an ETH callback function */ 662 663 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 664 665 /** 666 * @} 667 */ 668 669 /* Exported constants --------------------------------------------------------*/ 670 /** @defgroup ETH_Exported_Constants ETH Exported Constants 671 * @{ 672 */ 673 674 /** @defgroup ETH_Buffers_setting ETH Buffers setting 675 * @{ 676 */ 677 #define ETH_MAX_PACKET_SIZE 1524U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */ 678 #define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ 679 #define ETH_CRC 4U /*!< Ethernet CRC */ 680 #define ETH_EXTRA 2U /*!< Extra bytes in some cases */ 681 #define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */ 682 #define ETH_MIN_ETH_PAYLOAD 46U /*!< Minimum Ethernet payload size */ 683 #define ETH_MAX_ETH_PAYLOAD 1500U /*!< Maximum Ethernet payload size */ 684 #define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */ 685 686 /* Ethernet driver receive buffers are organized in a chained linked-list, when 687 an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO 688 to the driver receive buffers memory. 689 690 Depending on the size of the received ethernet packet and the size of 691 each ethernet driver receive buffer, the received packet can take one or more 692 ethernet driver receive buffer. 693 694 In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE 695 and the total count of the driver receive buffers ETH_RXBUFNB. 696 697 The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as 698 example, they can be reconfigured in the application layer to fit the application 699 needs */ 700 701 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet 702 packet */ 703 #ifndef ETH_RX_BUF_SIZE 704 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE 705 #endif 706 707 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ 708 #ifndef ETH_RXBUFNB 709 #define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ 710 #endif 711 712 713 /* Ethernet driver transmit buffers are organized in a chained linked-list, when 714 an ethernet packet is transmitted, Tx-DMA will transfer the packet from the 715 driver transmit buffers memory to the TxFIFO. 716 717 Depending on the size of the Ethernet packet to be transmitted and the size of 718 each ethernet driver transmit buffer, the packet to be transmitted can take 719 one or more ethernet driver transmit buffer. 720 721 In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE 722 and the total count of the driver transmit buffers ETH_TXBUFNB. 723 724 The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as 725 example, they can be reconfigured in the application layer to fit the application 726 needs */ 727 728 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet 729 packet */ 730 #ifndef ETH_TX_BUF_SIZE 731 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE 732 #endif 733 734 /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/ 735 #ifndef ETH_TXBUFNB 736 #define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ 737 #endif 738 739 /** 740 * @} 741 */ 742 743 /** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor 744 * @{ 745 */ 746 747 /* 748 DMA Tx Descriptor 749 ----------------------------------------------------------------------------------------------- 750 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | 751 ----------------------------------------------------------------------------------------------- 752 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | 753 ----------------------------------------------------------------------------------------------- 754 TDES2 | Buffer1 Address [31:0] | 755 ----------------------------------------------------------------------------------------------- 756 TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | 757 ----------------------------------------------------------------------------------------------- 758 */ 759 760 /** 761 * @brief Bit definition of TDES0 register: DMA Tx descriptor status register 762 */ 763 #define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ 764 #define ETH_DMATXDESC_IC 0x40000000U /*!< Interrupt on Completion */ 765 #define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */ 766 #define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */ 767 #define ETH_DMATXDESC_DC 0x08000000U /*!< Disable CRC */ 768 #define ETH_DMATXDESC_DP 0x04000000U /*!< Disable Padding */ 769 #define ETH_DMATXDESC_TTSE 0x02000000U /*!< Transmit Time Stamp Enable */ 770 #define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */ 771 #define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */ 772 #define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */ 773 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ 774 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ 775 #define ETH_DMATXDESC_TER 0x00200000U /*!< Transmit End of Ring */ 776 #define ETH_DMATXDESC_TCH 0x00100000U /*!< Second Address Chained */ 777 #define ETH_DMATXDESC_TTSS 0x00020000U /*!< Tx Time Stamp Status */ 778 #define ETH_DMATXDESC_IHE 0x00010000U /*!< IP Header Error */ 779 #define ETH_DMATXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ 780 #define ETH_DMATXDESC_JT 0x00004000U /*!< Jabber Timeout */ 781 #define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ 782 #define ETH_DMATXDESC_PCE 0x00001000U /*!< Payload Checksum Error */ 783 #define ETH_DMATXDESC_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */ 784 #define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */ 785 #define ETH_DMATXDESC_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */ 786 #define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */ 787 #define ETH_DMATXDESC_VF 0x00000080U /*!< VLAN Frame */ 788 #define ETH_DMATXDESC_CC 0x00000078U /*!< Collision Count */ 789 #define ETH_DMATXDESC_ED 0x00000004U /*!< Excessive Deferral */ 790 #define ETH_DMATXDESC_UF 0x00000002U /*!< Underflow Error: late data arrival from the memory */ 791 #define ETH_DMATXDESC_DB 0x00000001U /*!< Deferred Bit */ 792 793 /** 794 * @brief Bit definition of TDES1 register 795 */ 796 #define ETH_DMATXDESC_TBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */ 797 #define ETH_DMATXDESC_TBS1 0x00001FFFU /*!< Transmit Buffer1 Size */ 798 799 /** 800 * @brief Bit definition of TDES2 register 801 */ 802 #define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ 803 804 /** 805 * @brief Bit definition of TDES3 register 806 */ 807 #define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ 808 809 /*--------------------------------------------------------------------------------------------- 810 TDES6 | Transmit Time Stamp Low [31:0] | 811 ----------------------------------------------------------------------------------------------- 812 TDES7 | Transmit Time Stamp High [31:0] | 813 ----------------------------------------------------------------------------------------------*/ 814 815 /* Bit definition of TDES6 register */ 816 #define ETH_DMAPTPTXDESC_TTSL 0xFFFFFFFFU /* Transmit Time Stamp Low */ 817 818 /* Bit definition of TDES7 register */ 819 #define ETH_DMAPTPTXDESC_TTSH 0xFFFFFFFFU /* Transmit Time Stamp High */ 820 821 /** 822 * @} 823 */ 824 /** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor 825 * @{ 826 */ 827 828 /* 829 DMA Rx Descriptor 830 -------------------------------------------------------------------------------------------------------------------- 831 RDES0 | OWN(31) | Status [30:0] | 832 --------------------------------------------------------------------------------------------------------------------- 833 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | 834 --------------------------------------------------------------------------------------------------------------------- 835 RDES2 | Buffer1 Address [31:0] | 836 --------------------------------------------------------------------------------------------------------------------- 837 RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | 838 --------------------------------------------------------------------------------------------------------------------- 839 */ 840 841 /** 842 * @brief Bit definition of RDES0 register: DMA Rx descriptor status register 843 */ 844 #define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ 845 #define ETH_DMARXDESC_AFM 0x40000000U /*!< DA Filter Fail for the rx frame */ 846 #define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */ 847 #define ETH_DMARXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ 848 #define ETH_DMARXDESC_DE 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */ 849 #define ETH_DMARXDESC_SAF 0x00002000U /*!< SA Filter Fail for the received frame */ 850 #define ETH_DMARXDESC_LE 0x00001000U /*!< Frame size not matching with length field */ 851 #define ETH_DMARXDESC_OE 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */ 852 #define ETH_DMARXDESC_VLAN 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */ 853 #define ETH_DMARXDESC_FS 0x00000200U /*!< First descriptor of the frame */ 854 #define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */ 855 #define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ 856 #define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */ 857 #define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */ 858 #define ETH_DMARXDESC_RWT 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ 859 #define ETH_DMARXDESC_RE 0x00000008U /*!< Receive error: error reported by MII interface */ 860 #define ETH_DMARXDESC_DBE 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */ 861 #define ETH_DMARXDESC_CE 0x00000002U /*!< CRC error */ 862 #define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ 863 864 /** 865 * @brief Bit definition of RDES1 register 866 */ 867 #define ETH_DMARXDESC_DIC 0x80000000U /*!< Disable Interrupt on Completion */ 868 #define ETH_DMARXDESC_RBS2 0x1FFF0000U /*!< Receive Buffer2 Size */ 869 #define ETH_DMARXDESC_RER 0x00008000U /*!< Receive End of Ring */ 870 #define ETH_DMARXDESC_RCH 0x00004000U /*!< Second Address Chained */ 871 #define ETH_DMARXDESC_RBS1 0x00001FFFU /*!< Receive Buffer1 Size */ 872 873 /** 874 * @brief Bit definition of RDES2 register 875 */ 876 #define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ 877 878 /** 879 * @brief Bit definition of RDES3 register 880 */ 881 #define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ 882 883 /*--------------------------------------------------------------------------------------------------------------------- 884 RDES4 | Reserved[31:15] | Extended Status [14:0] | 885 --------------------------------------------------------------------------------------------------------------------- 886 RDES5 | Reserved[31:0] | 887 --------------------------------------------------------------------------------------------------------------------- 888 RDES6 | Receive Time Stamp Low [31:0] | 889 --------------------------------------------------------------------------------------------------------------------- 890 RDES7 | Receive Time Stamp High [31:0] | 891 --------------------------------------------------------------------------------------------------------------------*/ 892 893 /* Bit definition of RDES4 register */ 894 #define ETH_DMAPTPRXDESC_PTPV 0x00002000U /* PTP Version */ 895 #define ETH_DMAPTPRXDESC_PTPFT 0x00001000U /* PTP Frame Type */ 896 #define ETH_DMAPTPRXDESC_PTPMT 0x00000F00U /* PTP Message Type */ 897 #define ETH_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message (all clock types) */ 898 #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message (all clock types) */ 899 #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message (all clock types) */ 900 #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message (all clock types) */ 901 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ 902 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */ 903 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */ 904 #define ETH_DMAPTPRXDESC_IPV6PR 0x00000080U /* IPv6 Packet Received */ 905 #define ETH_DMAPTPRXDESC_IPV4PR 0x00000040U /* IPv4 Packet Received */ 906 #define ETH_DMAPTPRXDESC_IPCB 0x00000020U /* IP Checksum Bypassed */ 907 #define ETH_DMAPTPRXDESC_IPPE 0x00000010U /* IP Payload Error */ 908 #define ETH_DMAPTPRXDESC_IPHE 0x00000008U /* IP Header Error */ 909 #define ETH_DMAPTPRXDESC_IPPT 0x00000007U /* IP Payload Type */ 910 #define ETH_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in the IP datagram */ 911 #define ETH_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in the IP datagram */ 912 #define ETH_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in the IP datagram */ 913 914 /* Bit definition of RDES6 register */ 915 #define ETH_DMAPTPRXDESC_RTSL 0xFFFFFFFFU /* Receive Time Stamp Low */ 916 917 /* Bit definition of RDES7 register */ 918 #define ETH_DMAPTPRXDESC_RTSH 0xFFFFFFFFU /* Receive Time Stamp High */ 919 /** 920 * @} 921 */ 922 /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation 923 * @{ 924 */ 925 #define ETH_AUTONEGOTIATION_ENABLE 0x00000001U 926 #define ETH_AUTONEGOTIATION_DISABLE 0x00000000U 927 928 /** 929 * @} 930 */ 931 /** @defgroup ETH_Speed ETH Speed 932 * @{ 933 */ 934 #define ETH_SPEED_10M 0x00000000U 935 #define ETH_SPEED_100M 0x00004000U 936 937 /** 938 * @} 939 */ 940 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode 941 * @{ 942 */ 943 #define ETH_MODE_FULLDUPLEX 0x00000800U 944 #define ETH_MODE_HALFDUPLEX 0x00000000U 945 /** 946 * @} 947 */ 948 /** @defgroup ETH_Rx_Mode ETH Rx Mode 949 * @{ 950 */ 951 #define ETH_RXPOLLING_MODE 0x00000000U 952 #define ETH_RXINTERRUPT_MODE 0x00000001U 953 /** 954 * @} 955 */ 956 957 /** @defgroup ETH_Checksum_Mode ETH Checksum Mode 958 * @{ 959 */ 960 #define ETH_CHECKSUM_BY_HARDWARE 0x00000000U 961 #define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U 962 /** 963 * @} 964 */ 965 966 /** @defgroup ETH_Media_Interface ETH Media Interface 967 * @{ 968 */ 969 #define ETH_MEDIA_INTERFACE_MII 0x00000000U 970 #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL) 971 /** 972 * @} 973 */ 974 975 /** @defgroup ETH_Watchdog ETH Watchdog 976 * @{ 977 */ 978 #define ETH_WATCHDOG_ENABLE 0x00000000U 979 #define ETH_WATCHDOG_DISABLE 0x00800000U 980 /** 981 * @} 982 */ 983 984 /** @defgroup ETH_Jabber ETH Jabber 985 * @{ 986 */ 987 #define ETH_JABBER_ENABLE 0x00000000U 988 #define ETH_JABBER_DISABLE 0x00400000U 989 /** 990 * @} 991 */ 992 993 /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap 994 * @{ 995 */ 996 #define ETH_INTERFRAMEGAP_96BIT 0x00000000U /*!< minimum IFG between frames during transmission is 96Bit */ 997 #define ETH_INTERFRAMEGAP_88BIT 0x00020000U /*!< minimum IFG between frames during transmission is 88Bit */ 998 #define ETH_INTERFRAMEGAP_80BIT 0x00040000U /*!< minimum IFG between frames during transmission is 80Bit */ 999 #define ETH_INTERFRAMEGAP_72BIT 0x00060000U /*!< minimum IFG between frames during transmission is 72Bit */ 1000 #define ETH_INTERFRAMEGAP_64BIT 0x00080000U /*!< minimum IFG between frames during transmission is 64Bit */ 1001 #define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /*!< minimum IFG between frames during transmission is 56Bit */ 1002 #define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /*!< minimum IFG between frames during transmission is 48Bit */ 1003 #define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /*!< minimum IFG between frames during transmission is 40Bit */ 1004 /** 1005 * @} 1006 */ 1007 1008 /** @defgroup ETH_Carrier_Sense ETH Carrier Sense 1009 * @{ 1010 */ 1011 #define ETH_CARRIERSENCE_ENABLE 0x00000000U 1012 #define ETH_CARRIERSENCE_DISABLE 0x00010000U 1013 /** 1014 * @} 1015 */ 1016 1017 /** @defgroup ETH_Receive_Own ETH Receive Own 1018 * @{ 1019 */ 1020 #define ETH_RECEIVEOWN_ENABLE 0x00000000U 1021 #define ETH_RECEIVEOWN_DISABLE 0x00002000U 1022 /** 1023 * @} 1024 */ 1025 1026 /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode 1027 * @{ 1028 */ 1029 #define ETH_LOOPBACKMODE_ENABLE 0x00001000U 1030 #define ETH_LOOPBACKMODE_DISABLE 0x00000000U 1031 /** 1032 * @} 1033 */ 1034 1035 /** @defgroup ETH_Checksum_Offload ETH Checksum Offload 1036 * @{ 1037 */ 1038 #define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U 1039 #define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U 1040 /** 1041 * @} 1042 */ 1043 1044 /** @defgroup ETH_Retry_Transmission ETH Retry Transmission 1045 * @{ 1046 */ 1047 #define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U 1048 #define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U 1049 /** 1050 * @} 1051 */ 1052 1053 /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip 1054 * @{ 1055 */ 1056 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U 1057 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U 1058 /** 1059 * @} 1060 */ 1061 1062 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit 1063 * @{ 1064 */ 1065 #define ETH_BACKOFFLIMIT_10 0x00000000U 1066 #define ETH_BACKOFFLIMIT_8 0x00000020U 1067 #define ETH_BACKOFFLIMIT_4 0x00000040U 1068 #define ETH_BACKOFFLIMIT_1 0x00000060U 1069 /** 1070 * @} 1071 */ 1072 1073 /** @defgroup ETH_Deferral_Check ETH Deferral Check 1074 * @{ 1075 */ 1076 #define ETH_DEFFERRALCHECK_ENABLE 0x00000010U 1077 #define ETH_DEFFERRALCHECK_DISABLE 0x00000000U 1078 /** 1079 * @} 1080 */ 1081 1082 /** @defgroup ETH_Receive_All ETH Receive All 1083 * @{ 1084 */ 1085 #define ETH_RECEIVEALL_ENABLE 0x80000000U 1086 #define ETH_RECEIVEAll_DISABLE 0x00000000U 1087 /** 1088 * @} 1089 */ 1090 1091 /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter 1092 * @{ 1093 */ 1094 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U 1095 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U 1096 #define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U 1097 /** 1098 * @} 1099 */ 1100 1101 /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames 1102 * @{ 1103 */ 1104 #define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /*!< MAC filters all control frames from reaching the application */ 1105 #define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /*!< MAC forwards all control frames to application even if they fail the Address Filter */ 1106 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /*!< MAC forwards control frames that pass the Address Filter. */ 1107 /** 1108 * @} 1109 */ 1110 1111 /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception 1112 * @{ 1113 */ 1114 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U 1115 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U 1116 /** 1117 * @} 1118 */ 1119 1120 /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter 1121 * @{ 1122 */ 1123 #define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U 1124 #define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U 1125 /** 1126 * @} 1127 */ 1128 1129 /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode 1130 * @{ 1131 */ 1132 #define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U 1133 #define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U 1134 /** 1135 * @} 1136 */ 1137 1138 /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter 1139 * @{ 1140 */ 1141 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U 1142 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U 1143 #define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U 1144 #define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U 1145 /** 1146 * @} 1147 */ 1148 1149 /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter 1150 * @{ 1151 */ 1152 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U 1153 #define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U 1154 #define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U 1155 /** 1156 * @} 1157 */ 1158 1159 /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause 1160 * @{ 1161 */ 1162 #define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U 1163 #define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U 1164 /** 1165 * @} 1166 */ 1167 1168 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold 1169 * @{ 1170 */ 1171 #define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /*!< Pause time minus 4 slot times */ 1172 #define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /*!< Pause time minus 28 slot times */ 1173 #define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /*!< Pause time minus 144 slot times */ 1174 #define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /*!< Pause time minus 256 slot times */ 1175 /** 1176 * @} 1177 */ 1178 1179 /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect 1180 * @{ 1181 */ 1182 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U 1183 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U 1184 /** 1185 * @} 1186 */ 1187 1188 /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control 1189 * @{ 1190 */ 1191 #define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U 1192 #define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U 1193 /** 1194 * @} 1195 */ 1196 1197 /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control 1198 * @{ 1199 */ 1200 #define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U 1201 #define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U 1202 /** 1203 * @} 1204 */ 1205 1206 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison 1207 * @{ 1208 */ 1209 #define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U 1210 #define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U 1211 /** 1212 * @} 1213 */ 1214 1215 /** @defgroup ETH_MAC_addresses ETH MAC addresses 1216 * @{ 1217 */ 1218 #define ETH_MAC_ADDRESS0 0x00000000U 1219 #define ETH_MAC_ADDRESS1 0x00000008U 1220 #define ETH_MAC_ADDRESS2 0x00000010U 1221 #define ETH_MAC_ADDRESS3 0x00000018U 1222 /** 1223 * @} 1224 */ 1225 1226 /** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA 1227 * @{ 1228 */ 1229 #define ETH_MAC_ADDRESSFILTER_SA 0x00000000U 1230 #define ETH_MAC_ADDRESSFILTER_DA 0x00000008U 1231 /** 1232 * @} 1233 */ 1234 1235 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes 1236 * @{ 1237 */ 1238 #define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /*!< Mask MAC Address high reg bits [15:8] */ 1239 #define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /*!< Mask MAC Address high reg bits [7:0] */ 1240 #define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /*!< Mask MAC Address low reg bits [31:24] */ 1241 #define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /*!< Mask MAC Address low reg bits [23:16] */ 1242 #define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /*!< Mask MAC Address low reg bits [15:8] */ 1243 #define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /*!< Mask MAC Address low reg bits [70] */ 1244 /** 1245 * @} 1246 */ 1247 1248 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame 1249 * @{ 1250 */ 1251 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U 1252 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U 1253 /** 1254 * @} 1255 */ 1256 1257 /** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward 1258 * @{ 1259 */ 1260 #define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U 1261 #define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U 1262 /** 1263 * @} 1264 */ 1265 1266 /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame 1267 * @{ 1268 */ 1269 #define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U 1270 #define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U 1271 /** 1272 * @} 1273 */ 1274 1275 /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward 1276 * @{ 1277 */ 1278 #define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U 1279 #define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U 1280 /** 1281 * @} 1282 */ 1283 1284 /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control 1285 * @{ 1286 */ 1287 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ 1288 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ 1289 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ 1290 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ 1291 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ 1292 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ 1293 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ 1294 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ 1295 /** 1296 * @} 1297 */ 1298 1299 /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames 1300 * @{ 1301 */ 1302 #define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U 1303 #define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U 1304 /** 1305 * @} 1306 */ 1307 1308 /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames 1309 * @{ 1310 */ 1311 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U 1312 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U 1313 /** 1314 * @} 1315 */ 1316 1317 /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control 1318 * @{ 1319 */ 1320 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ 1321 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ 1322 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ 1323 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ 1324 /** 1325 * @} 1326 */ 1327 1328 /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate 1329 * @{ 1330 */ 1331 #define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U 1332 #define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U 1333 /** 1334 * @} 1335 */ 1336 1337 /** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats 1338 * @{ 1339 */ 1340 #define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U 1341 #define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U 1342 /** 1343 * @} 1344 */ 1345 1346 /** @defgroup ETH_Fixed_Burst ETH Fixed Burst 1347 * @{ 1348 */ 1349 #define ETH_FIXEDBURST_ENABLE 0x00010000U 1350 #define ETH_FIXEDBURST_DISABLE 0x00000000U 1351 /** 1352 * @} 1353 */ 1354 1355 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length 1356 * @{ 1357 */ 1358 #define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ 1359 #define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ 1360 #define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ 1361 #define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ 1362 #define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ 1363 #define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ 1364 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ 1365 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ 1366 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ 1367 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ 1368 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ 1369 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ 1370 /** 1371 * @} 1372 */ 1373 1374 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length 1375 * @{ 1376 */ 1377 #define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ 1378 #define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ 1379 #define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 1380 #define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 1381 #define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 1382 #define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 1383 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 1384 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 1385 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 1386 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 1387 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ 1388 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ 1389 /** 1390 * @} 1391 */ 1392 1393 /** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format 1394 * @{ 1395 */ 1396 #define ETH_DMAENHANCEDDESCRIPTOR_ENABLE 0x00000080U 1397 #define ETH_DMAENHANCEDDESCRIPTOR_DISABLE 0x00000000U 1398 /** 1399 * @} 1400 */ 1401 1402 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration 1403 * @{ 1404 */ 1405 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U 1406 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U 1407 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U 1408 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U 1409 #define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U 1410 /** 1411 * @} 1412 */ 1413 1414 /** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment 1415 * @{ 1416 */ 1417 #define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /*!< Last Segment */ 1418 #define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /*!< First Segment */ 1419 /** 1420 * @} 1421 */ 1422 1423 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control 1424 * @{ 1425 */ 1426 #define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /*!< Checksum engine bypass */ 1427 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /*!< IPv4 header checksum insertion */ 1428 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ 1429 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ 1430 /** 1431 * @} 1432 */ 1433 1434 /** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers 1435 * @{ 1436 */ 1437 #define ETH_DMARXDESC_BUFFER1 0x00000000U /*!< DMA Rx Desc Buffer1 */ 1438 #define ETH_DMARXDESC_BUFFER2 0x00000001U /*!< DMA Rx Desc Buffer2 */ 1439 /** 1440 * @} 1441 */ 1442 1443 /** @defgroup ETH_PMT_Flags ETH PMT Flags 1444 * @{ 1445 */ 1446 #define ETH_PMT_FLAG_WUFFRPR 0x80000000U /*!< Wake-Up Frame Filter Register Pointer Reset */ 1447 #define ETH_PMT_FLAG_WUFR 0x00000040U /*!< Wake-Up Frame Received */ 1448 #define ETH_PMT_FLAG_MPR 0x00000020U /*!< Magic Packet Received */ 1449 /** 1450 * @} 1451 */ 1452 1453 /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts 1454 * @{ 1455 */ 1456 #define ETH_MMC_IT_TGF 0x00200000U /*!< When Tx good frame counter reaches half the maximum value */ 1457 #define ETH_MMC_IT_TGFMSC 0x00008000U /*!< When Tx good multi col counter reaches half the maximum value */ 1458 #define ETH_MMC_IT_TGFSC 0x00004000U /*!< When Tx good single col counter reaches half the maximum value */ 1459 /** 1460 * @} 1461 */ 1462 1463 /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts 1464 * @{ 1465 */ 1466 #define ETH_MMC_IT_RGUF 0x10020000U /*!< When Rx good unicast frames counter reaches half the maximum value */ 1467 #define ETH_MMC_IT_RFAE 0x10000040U /*!< When Rx alignment error counter reaches half the maximum value */ 1468 #define ETH_MMC_IT_RFCE 0x10000020U /*!< When Rx crc error counter reaches half the maximum value */ 1469 /** 1470 * @} 1471 */ 1472 1473 /** @defgroup ETH_MAC_Flags ETH MAC Flags 1474 * @{ 1475 */ 1476 #define ETH_MAC_FLAG_TST 0x00000200U /*!< Time stamp trigger flag (on MAC) */ 1477 #define ETH_MAC_FLAG_MMCT 0x00000040U /*!< MMC transmit flag */ 1478 #define ETH_MAC_FLAG_MMCR 0x00000020U /*!< MMC receive flag */ 1479 #define ETH_MAC_FLAG_MMC 0x00000010U /*!< MMC flag (on MAC) */ 1480 #define ETH_MAC_FLAG_PMT 0x00000008U /*!< PMT flag (on MAC) */ 1481 /** 1482 * @} 1483 */ 1484 1485 /** @defgroup ETH_DMA_Flags ETH DMA Flags 1486 * @{ 1487 */ 1488 #define ETH_DMA_FLAG_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */ 1489 #define ETH_DMA_FLAG_PMT 0x10000000U /*!< PMT interrupt (on DMA) */ 1490 #define ETH_DMA_FLAG_MMC 0x08000000U /*!< MMC interrupt (on DMA) */ 1491 #define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U /*!< Error bits 0-Rx DMA, 1-Tx DMA */ 1492 #define ETH_DMA_FLAG_READWRITEERROR 0x01000000U /*!< Error bits 0-write transfer, 1-read transfer */ 1493 #define ETH_DMA_FLAG_ACCESSERROR 0x02000000U /*!< Error bits 0-data buffer, 1-desc. access */ 1494 #define ETH_DMA_FLAG_NIS 0x00010000U /*!< Normal interrupt summary flag */ 1495 #define ETH_DMA_FLAG_AIS 0x00008000U /*!< Abnormal interrupt summary flag */ 1496 #define ETH_DMA_FLAG_ER 0x00004000U /*!< Early receive flag */ 1497 #define ETH_DMA_FLAG_FBE 0x00002000U /*!< Fatal bus error flag */ 1498 #define ETH_DMA_FLAG_ET 0x00000400U /*!< Early transmit flag */ 1499 #define ETH_DMA_FLAG_RWT 0x00000200U /*!< Receive watchdog timeout flag */ 1500 #define ETH_DMA_FLAG_RPS 0x00000100U /*!< Receive process stopped flag */ 1501 #define ETH_DMA_FLAG_RBU 0x00000080U /*!< Receive buffer unavailable flag */ 1502 #define ETH_DMA_FLAG_R 0x00000040U /*!< Receive flag */ 1503 #define ETH_DMA_FLAG_TU 0x00000020U /*!< Underflow flag */ 1504 #define ETH_DMA_FLAG_RO 0x00000010U /*!< Overflow flag */ 1505 #define ETH_DMA_FLAG_TJT 0x00000008U /*!< Transmit jabber timeout flag */ 1506 #define ETH_DMA_FLAG_TBU 0x00000004U /*!< Transmit buffer unavailable flag */ 1507 #define ETH_DMA_FLAG_TPS 0x00000002U /*!< Transmit process stopped flag */ 1508 #define ETH_DMA_FLAG_T 0x00000001U /*!< Transmit flag */ 1509 /** 1510 * @} 1511 */ 1512 1513 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts 1514 * @{ 1515 */ 1516 #define ETH_MAC_IT_TST 0x00000200U /*!< Time stamp trigger interrupt (on MAC) */ 1517 #define ETH_MAC_IT_MMCT 0x00000040U /*!< MMC transmit interrupt */ 1518 #define ETH_MAC_IT_MMCR 0x00000020U /*!< MMC receive interrupt */ 1519 #define ETH_MAC_IT_MMC 0x00000010U /*!< MMC interrupt (on MAC) */ 1520 #define ETH_MAC_IT_PMT 0x00000008U /*!< PMT interrupt (on MAC) */ 1521 /** 1522 * @} 1523 */ 1524 1525 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts 1526 * @{ 1527 */ 1528 #define ETH_DMA_IT_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */ 1529 #define ETH_DMA_IT_PMT 0x10000000U /*!< PMT interrupt (on DMA) */ 1530 #define ETH_DMA_IT_MMC 0x08000000U /*!< MMC interrupt (on DMA) */ 1531 #define ETH_DMA_IT_NIS 0x00010000U /*!< Normal interrupt summary */ 1532 #define ETH_DMA_IT_AIS 0x00008000U /*!< Abnormal interrupt summary */ 1533 #define ETH_DMA_IT_ER 0x00004000U /*!< Early receive interrupt */ 1534 #define ETH_DMA_IT_FBE 0x00002000U /*!< Fatal bus error interrupt */ 1535 #define ETH_DMA_IT_ET 0x00000400U /*!< Early transmit interrupt */ 1536 #define ETH_DMA_IT_RWT 0x00000200U /*!< Receive watchdog timeout interrupt */ 1537 #define ETH_DMA_IT_RPS 0x00000100U /*!< Receive process stopped interrupt */ 1538 #define ETH_DMA_IT_RBU 0x00000080U /*!< Receive buffer unavailable interrupt */ 1539 #define ETH_DMA_IT_R 0x00000040U /*!< Receive interrupt */ 1540 #define ETH_DMA_IT_TU 0x00000020U /*!< Underflow interrupt */ 1541 #define ETH_DMA_IT_RO 0x00000010U /*!< Overflow interrupt */ 1542 #define ETH_DMA_IT_TJT 0x00000008U /*!< Transmit jabber timeout interrupt */ 1543 #define ETH_DMA_IT_TBU 0x00000004U /*!< Transmit buffer unavailable interrupt */ 1544 #define ETH_DMA_IT_TPS 0x00000002U /*!< Transmit process stopped interrupt */ 1545 #define ETH_DMA_IT_T 0x00000001U /*!< Transmit interrupt */ 1546 /** 1547 * @} 1548 */ 1549 1550 /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state 1551 * @{ 1552 */ 1553 #define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Tx Command issued */ 1554 #define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /*!< Running - fetching the Tx descriptor */ 1555 #define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /*!< Running - waiting for status */ 1556 #define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U /*!< Running - reading the data from host memory */ 1557 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U /*!< Suspended - Tx Descriptor unavailable */ 1558 #define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U /*!< Running - closing Rx descriptor */ 1559 1560 /** 1561 * @} 1562 */ 1563 1564 1565 /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state 1566 * @{ 1567 */ 1568 #define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Rx Command issued */ 1569 #define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /*!< Running - fetching the Rx descriptor */ 1570 #define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /*!< Running - waiting for packet */ 1571 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U /*!< Suspended - Rx Descriptor unavailable */ 1572 #define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U /*!< Running - closing descriptor */ 1573 #define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U /*!< Running - queuing the receive frame into host memory */ 1574 1575 /** 1576 * @} 1577 */ 1578 1579 /** @defgroup ETH_DMA_overflow ETH DMA overflow 1580 * @{ 1581 */ 1582 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /*!< Overflow bit for FIFO overflow counter */ 1583 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /*!< Overflow bit for missed frame counter */ 1584 /** 1585 * @} 1586 */ 1587 1588 /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP 1589 * @{ 1590 */ 1591 #define ETH_EXTI_LINE_WAKEUP 0x00080000U /*!< External interrupt line 19 Connected to the ETH EXTI Line */ 1592 1593 /** 1594 * @} 1595 */ 1596 1597 /** 1598 * @} 1599 */ 1600 1601 /* Exported macro ------------------------------------------------------------*/ 1602 /** @defgroup ETH_Exported_Macros ETH Exported Macros 1603 * @brief macros to handle interrupts and specific clock configurations 1604 * @{ 1605 */ 1606 1607 /** @brief Reset ETH handle state 1608 * @param __HANDLE__ specifies the ETH handle. 1609 * @retval None 1610 */ 1611 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 1612 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ 1613 (__HANDLE__)->State = HAL_ETH_STATE_RESET; \ 1614 (__HANDLE__)->MspInitCallback = NULL; \ 1615 (__HANDLE__)->MspDeInitCallback = NULL; \ 1616 } while(0) 1617 #else 1618 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET) 1619 #endif /*USE_HAL_ETH_REGISTER_CALLBACKS */ 1620 1621 /** 1622 * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. 1623 * @param __HANDLE__ ETH Handle 1624 * @param __FLAG__ specifies the flag of TDES0 to check. 1625 * @retval the ETH_DMATxDescFlag (SET or RESET). 1626 */ 1627 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__)) 1628 1629 /** 1630 * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not. 1631 * @param __HANDLE__ ETH Handle 1632 * @param __FLAG__ specifies the flag of RDES0 to check. 1633 * @retval the ETH_DMATxDescFlag (SET or RESET). 1634 */ 1635 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__)) 1636 1637 /** 1638 * @brief Enables the specified DMA Rx Desc receive interrupt. 1639 * @param __HANDLE__ ETH Handle 1640 * @retval None 1641 */ 1642 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC)) 1643 1644 /** 1645 * @brief Disables the specified DMA Rx Desc receive interrupt. 1646 * @param __HANDLE__ ETH Handle 1647 * @retval None 1648 */ 1649 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC) 1650 1651 /** 1652 * @brief Set the specified DMA Rx Desc Own bit. 1653 * @param __HANDLE__ ETH Handle 1654 * @retval None 1655 */ 1656 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN) 1657 1658 /** 1659 * @brief Returns the specified ETHERNET DMA Tx Desc collision count. 1660 * @param __HANDLE__ ETH Handle 1661 * @retval The Transmit descriptor collision counter value. 1662 */ 1663 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT) 1664 1665 /** 1666 * @brief Set the specified DMA Tx Desc Own bit. 1667 * @param __HANDLE__ ETH Handle 1668 * @retval None 1669 */ 1670 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN) 1671 1672 /** 1673 * @brief Enables the specified DMA Tx Desc Transmit interrupt. 1674 * @param __HANDLE__ ETH Handle 1675 * @retval None 1676 */ 1677 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC) 1678 1679 /** 1680 * @brief Disables the specified DMA Tx Desc Transmit interrupt. 1681 * @param __HANDLE__ ETH Handle 1682 * @retval None 1683 */ 1684 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC) 1685 1686 /** 1687 * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. 1688 * @param __HANDLE__ ETH Handle 1689 * @param __CHECKSUM__ specifies is the DMA Tx desc checksum insertion. 1690 * This parameter can be one of the following values: 1691 * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass 1692 * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum 1693 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present 1694 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header 1695 * @retval None 1696 */ 1697 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__)) 1698 1699 /** 1700 * @brief Enables the DMA Tx Desc CRC. 1701 * @param __HANDLE__ ETH Handle 1702 * @retval None 1703 */ 1704 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC) 1705 1706 /** 1707 * @brief Disables the DMA Tx Desc CRC. 1708 * @param __HANDLE__ ETH Handle 1709 * @retval None 1710 */ 1711 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC) 1712 1713 /** 1714 * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes. 1715 * @param __HANDLE__ ETH Handle 1716 * @retval None 1717 */ 1718 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP) 1719 1720 /** 1721 * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes. 1722 * @param __HANDLE__ ETH Handle 1723 * @retval None 1724 */ 1725 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP) 1726 1727 /** 1728 * @brief Enables the specified ETHERNET MAC interrupts. 1729 * @param __HANDLE__ ETH Handle 1730 * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be 1731 * enabled or disabled. 1732 * This parameter can be any combination of the following values: 1733 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt 1734 * @arg ETH_MAC_IT_PMT : PMT interrupt 1735 * @retval None 1736 */ 1737 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__)) 1738 1739 /** 1740 * @brief Disables the specified ETHERNET MAC interrupts. 1741 * @param __HANDLE__ ETH Handle 1742 * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be 1743 * enabled or disabled. 1744 * This parameter can be any combination of the following values: 1745 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt 1746 * @arg ETH_MAC_IT_PMT : PMT interrupt 1747 * @retval None 1748 */ 1749 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__)) 1750 1751 /** 1752 * @brief Initiate a Pause Control Frame (Full-duplex only). 1753 * @param __HANDLE__ ETH Handle 1754 * @retval None 1755 */ 1756 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) 1757 1758 /** 1759 * @brief Checks whether the ETHERNET flow control busy bit is set or not. 1760 * @param __HANDLE__ ETH Handle 1761 * @retval The new state of flow control busy status bit (SET or RESET). 1762 */ 1763 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA) 1764 1765 /** 1766 * @brief Enables the MAC Back Pressure operation activation (Half-duplex only). 1767 * @param __HANDLE__ ETH Handle 1768 * @retval None 1769 */ 1770 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) 1771 1772 /** 1773 * @brief Disables the MAC BackPressure operation activation (Half-duplex only). 1774 * @param __HANDLE__ ETH Handle 1775 * @retval None 1776 */ 1777 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA) 1778 1779 /** 1780 * @brief Checks whether the specified ETHERNET MAC flag is set or not. 1781 * @param __HANDLE__ ETH Handle 1782 * @param __FLAG__ specifies the flag to check. 1783 * This parameter can be one of the following values: 1784 * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag 1785 * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag 1786 * @arg ETH_MAC_FLAG_MMCR : MMC receive flag 1787 * @arg ETH_MAC_FLAG_MMC : MMC flag 1788 * @arg ETH_MAC_FLAG_PMT : PMT flag 1789 * @retval The state of ETHERNET MAC flag. 1790 */ 1791 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__)) 1792 1793 /** 1794 * @brief Enables the specified ETHERNET DMA interrupts. 1795 * @param __HANDLE__ ETH Handle 1796 * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be 1797 * enabled @ref ETH_DMA_Interrupts 1798 * @retval None 1799 */ 1800 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__)) 1801 1802 /** 1803 * @brief Disables the specified ETHERNET DMA interrupts. 1804 * @param __HANDLE__ ETH Handle 1805 * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be 1806 * disabled. @ref ETH_DMA_Interrupts 1807 * @retval None 1808 */ 1809 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__)) 1810 1811 /** 1812 * @brief Clears the ETHERNET DMA IT pending bit. 1813 * @param __HANDLE__ ETH Handle 1814 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts 1815 * @retval None 1816 */ 1817 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__)) 1818 1819 /** 1820 * @brief Checks whether the specified ETHERNET DMA flag is set or not. 1821 * @param __HANDLE__ ETH Handle 1822 * @param __FLAG__ specifies the flag to check. @ref ETH_DMA_Flags 1823 * @retval The new state of ETH_DMA_FLAG (SET or RESET). 1824 */ 1825 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__)) 1826 1827 /** 1828 * @brief Checks whether the specified ETHERNET DMA flag is set or not. 1829 * @param __HANDLE__ ETH Handle 1830 * @param __FLAG__ specifies the flag to clear. @ref ETH_DMA_Flags 1831 * @retval The new state of ETH_DMA_FLAG (SET or RESET). 1832 */ 1833 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__)) 1834 1835 /** 1836 * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. 1837 * @param __HANDLE__ ETH Handle 1838 * @param __OVERFLOW__ specifies the DMA overflow flag to check. 1839 * This parameter can be one of the following values: 1840 * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter 1841 * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter 1842 * @retval The state of ETHERNET DMA overflow Flag (SET or RESET). 1843 */ 1844 #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__)) 1845 1846 /** 1847 * @brief Set the DMA Receive status watchdog timer register value 1848 * @param __HANDLE__ ETH Handle 1849 * @param __VALUE__ DMA Receive status watchdog timer register value 1850 * @retval None 1851 */ 1852 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__)) 1853 1854 /** 1855 * @brief Enables any unicast packet filtered by the MAC address 1856 * recognition to be a wake-up frame. 1857 * @param __HANDLE__ ETH Handle. 1858 * @retval None 1859 */ 1860 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU) 1861 1862 /** 1863 * @brief Disables any unicast packet filtered by the MAC address 1864 * recognition to be a wake-up frame. 1865 * @param __HANDLE__ ETH Handle. 1866 * @retval None 1867 */ 1868 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU) 1869 1870 /** 1871 * @brief Enables the MAC Wake-Up Frame Detection. 1872 * @param __HANDLE__ ETH Handle. 1873 * @retval None 1874 */ 1875 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE) 1876 1877 /** 1878 * @brief Disables the MAC Wake-Up Frame Detection. 1879 * @param __HANDLE__ ETH Handle. 1880 * @retval None 1881 */ 1882 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) 1883 1884 /** 1885 * @brief Enables the MAC Magic Packet Detection. 1886 * @param __HANDLE__ ETH Handle. 1887 * @retval None 1888 */ 1889 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE) 1890 1891 /** 1892 * @brief Disables the MAC Magic Packet Detection. 1893 * @param __HANDLE__ ETH Handle. 1894 * @retval None 1895 */ 1896 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) 1897 1898 /** 1899 * @brief Enables the MAC Power Down. 1900 * @param __HANDLE__ ETH Handle 1901 * @retval None 1902 */ 1903 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD) 1904 1905 /** 1906 * @brief Disables the MAC Power Down. 1907 * @param __HANDLE__ ETH Handle 1908 * @retval None 1909 */ 1910 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD) 1911 1912 /** 1913 * @brief Checks whether the specified ETHERNET PMT flag is set or not. 1914 * @param __HANDLE__ ETH Handle. 1915 * @param __FLAG__ specifies the flag to check. 1916 * This parameter can be one of the following values: 1917 * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset 1918 * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received 1919 * @arg ETH_PMT_FLAG_MPR : Magic Packet Received 1920 * @retval The new state of ETHERNET PMT Flag (SET or RESET). 1921 */ 1922 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__)) 1923 1924 /** 1925 * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16) 1926 * @param __HANDLE__ ETH Handle. 1927 * @retval None 1928 */ 1929 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP)) 1930 1931 /** 1932 * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16) 1933 * @param __HANDLE__ ETH Handle. 1934 * @retval None 1935 */ 1936 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\ 1937 (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0) 1938 1939 /** 1940 * @brief Enables the MMC Counter Freeze. 1941 * @param __HANDLE__ ETH Handle. 1942 * @retval None 1943 */ 1944 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF) 1945 1946 /** 1947 * @brief Disables the MMC Counter Freeze. 1948 * @param __HANDLE__ ETH Handle. 1949 * @retval None 1950 */ 1951 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF) 1952 1953 /** 1954 * @brief Enables the MMC Reset On Read. 1955 * @param __HANDLE__ ETH Handle. 1956 * @retval None 1957 */ 1958 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR) 1959 1960 /** 1961 * @brief Disables the MMC Reset On Read. 1962 * @param __HANDLE__ ETH Handle. 1963 * @retval None 1964 */ 1965 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR) 1966 1967 /** 1968 * @brief Enables the MMC Counter Stop Rollover. 1969 * @param __HANDLE__ ETH Handle. 1970 * @retval None 1971 */ 1972 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR) 1973 1974 /** 1975 * @brief Disables the MMC Counter Stop Rollover. 1976 * @param __HANDLE__ ETH Handle. 1977 * @retval None 1978 */ 1979 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR) 1980 1981 /** 1982 * @brief Resets the MMC Counters. 1983 * @param __HANDLE__ ETH Handle. 1984 * @retval None 1985 */ 1986 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR) 1987 1988 /** 1989 * @brief Enables the specified ETHERNET MMC Rx interrupts. 1990 * @param __HANDLE__ ETH Handle. 1991 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. 1992 * This parameter can be one of the following values: 1993 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value 1994 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value 1995 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value 1996 * @retval None 1997 */ 1998 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU) 1999 /** 2000 * @brief Disables the specified ETHERNET MMC Rx interrupts. 2001 * @param __HANDLE__ ETH Handle. 2002 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. 2003 * This parameter can be one of the following values: 2004 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value 2005 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value 2006 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value 2007 * @retval None 2008 */ 2009 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU) 2010 /** 2011 * @brief Enables the specified ETHERNET MMC Tx interrupts. 2012 * @param __HANDLE__ ETH Handle. 2013 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. 2014 * This parameter can be one of the following values: 2015 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value 2016 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value 2017 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value 2018 * @retval None 2019 */ 2020 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__)) 2021 2022 /** 2023 * @brief Disables the specified ETHERNET MMC Tx interrupts. 2024 * @param __HANDLE__ ETH Handle. 2025 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. 2026 * This parameter can be one of the following values: 2027 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value 2028 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value 2029 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value 2030 * @retval None 2031 */ 2032 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__)) 2033 2034 /** 2035 * @brief Enables the ETH External interrupt line. 2036 * @retval None 2037 */ 2038 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP) 2039 2040 /** 2041 * @brief Disables the ETH External interrupt line. 2042 * @retval None 2043 */ 2044 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP) 2045 2046 /** 2047 * @brief Enable event on ETH External event line. 2048 * @retval None. 2049 */ 2050 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP) 2051 2052 /** 2053 * @brief Disable event on ETH External event line 2054 * @retval None. 2055 */ 2056 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP) 2057 2058 /** 2059 * @brief Get flag of the ETH External interrupt line. 2060 * @retval None 2061 */ 2062 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP) 2063 2064 /** 2065 * @brief Clear flag of the ETH External interrupt line. 2066 * @retval None 2067 */ 2068 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP) 2069 2070 /** 2071 * @brief Enables rising edge trigger to the ETH External interrupt line. 2072 * @retval None 2073 */ 2074 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP 2075 2076 /** 2077 * @brief Disables the rising edge trigger to the ETH External interrupt line. 2078 * @retval None 2079 */ 2080 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP) 2081 2082 /** 2083 * @brief Enables falling edge trigger to the ETH External interrupt line. 2084 * @retval None 2085 */ 2086 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP) 2087 2088 /** 2089 * @brief Disables falling edge trigger to the ETH External interrupt line. 2090 * @retval None 2091 */ 2092 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP) 2093 2094 /** 2095 * @brief Enables rising/falling edge trigger to the ETH External interrupt line. 2096 * @retval None 2097 */ 2098 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\ 2099 EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\ 2100 }while(0U) 2101 2102 /** 2103 * @brief Disables rising/falling edge trigger to the ETH External interrupt line. 2104 * @retval None 2105 */ 2106 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ 2107 EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ 2108 }while(0U) 2109 2110 /** 2111 * @brief Generate a Software interrupt on selected EXTI line. 2112 * @retval None. 2113 */ 2114 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP 2115 2116 /** 2117 * @} 2118 */ 2119 /* Exported functions --------------------------------------------------------*/ 2120 2121 /** @addtogroup ETH_Exported_Functions 2122 * @{ 2123 */ 2124 2125 /* Initialization and de-initialization functions ****************************/ 2126 2127 /** @addtogroup ETH_Exported_Functions_Group1 2128 * @{ 2129 */ 2130 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); 2131 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); 2132 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); 2133 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); 2134 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount); 2135 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); 2136 /* Callbacks Register/UnRegister functions ***********************************/ 2137 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 2138 HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback); 2139 HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID); 2140 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 2141 2142 /** 2143 * @} 2144 */ 2145 /* IO operation functions ****************************************************/ 2146 2147 /** @addtogroup ETH_Exported_Functions_Group2 2148 * @{ 2149 */ 2150 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength); 2151 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth); 2152 /* Communication with PHY functions*/ 2153 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue); 2154 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue); 2155 /* Non-Blocking mode: Interrupt */ 2156 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth); 2157 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); 2158 /* Callback in non blocking modes (Interrupt) */ 2159 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); 2160 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); 2161 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); 2162 /** 2163 * @} 2164 */ 2165 2166 /* Peripheral Control functions **********************************************/ 2167 2168 /** @addtogroup ETH_Exported_Functions_Group3 2169 * @{ 2170 */ 2171 2172 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); 2173 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); 2174 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf); 2175 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf); 2176 /** 2177 * @} 2178 */ 2179 2180 /* Peripheral State functions ************************************************/ 2181 2182 /** @addtogroup ETH_Exported_Functions_Group4 2183 * @{ 2184 */ 2185 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); 2186 /** 2187 * @} 2188 */ 2189 2190 /** 2191 * @} 2192 */ 2193 2194 /** 2195 * @} 2196 */ 2197 2198 /** 2199 * @} 2200 */ 2201 2202 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\ 2203 STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 2204 2205 #ifdef __cplusplus 2206 } 2207 #endif 2208 2209 #endif /* __STM32F4xx_HAL_ETH_LEGACY_H */ 2210
