1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_hal_can_legacy.h 4 * @author MCD Application Team 5 * @brief Header file of CAN HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32F4xx_HAL_CAN_LEGACY_H 21 #define __STM32F4xx_HAL_CAN_LEGACY_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ 28 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 29 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ 30 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ 31 defined(STM32F423xx) 32 /* Includes ------------------------------------------------------------------*/ 33 #include "stm32f4xx_hal_def.h" 34 35 /** @addtogroup STM32F4xx_HAL_Driver 36 * @{ 37 */ 38 39 /** @addtogroup CAN 40 * @{ 41 */ 42 43 /* Exported types ------------------------------------------------------------*/ 44 /** @defgroup CAN_Exported_Types CAN Exported Types 45 * @{ 46 */ 47 48 /** 49 * @brief HAL State structures definition 50 */ 51 typedef enum 52 { 53 HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ 54 HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ 55 HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */ 56 HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */ 57 HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */ 58 HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */ 59 HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */ 60 HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */ 61 HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */ 62 HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */ 63 HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */ 64 HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */ 65 66 }HAL_CAN_StateTypeDef; 67 68 /** 69 * @brief CAN init structure definition 70 */ 71 typedef struct 72 { 73 uint32_t Prescaler; /*!< Specifies the length of a time quantum. 74 This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ 75 76 uint32_t Mode; /*!< Specifies the CAN operating mode. 77 This parameter can be a value of @ref CAN_operating_mode */ 78 79 uint32_t SJW; /*!< Specifies the maximum number of time quanta 80 the CAN hardware is allowed to lengthen or 81 shorten a bit to perform resynchronization. 82 This parameter can be a value of @ref CAN_synchronisation_jump_width */ 83 84 uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1. 85 This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ 86 87 uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2. 88 This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ 89 90 uint32_t TTCM; /*!< Enable or disable the time triggered communication mode. 91 This parameter can be set to ENABLE or DISABLE. */ 92 93 uint32_t ABOM; /*!< Enable or disable the automatic bus-off management. 94 This parameter can be set to ENABLE or DISABLE */ 95 96 uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode. 97 This parameter can be set to ENABLE or DISABLE */ 98 99 uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode. 100 This parameter can be set to ENABLE or DISABLE */ 101 102 uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode. 103 This parameter can be set to ENABLE or DISABLE */ 104 105 uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority. 106 This parameter can be set to ENABLE or DISABLE */ 107 }CAN_InitTypeDef; 108 109 /** 110 * @brief CAN filter configuration structure definition 111 */ 112 typedef struct 113 { 114 uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit 115 configuration, first one for a 16-bit configuration). 116 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 117 118 uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit 119 configuration, second one for a 16-bit configuration). 120 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 121 122 uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, 123 according to the mode (MSBs for a 32-bit configuration, 124 first one for a 16-bit configuration). 125 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 126 127 uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, 128 according to the mode (LSBs for a 32-bit configuration, 129 second one for a 16-bit configuration). 130 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 131 132 uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. 133 This parameter can be a value of @ref CAN_filter_FIFO */ 134 135 uint32_t FilterNumber; /*!< Specifies the filter which will be initialized. 136 This parameter must be a number between Min_Data = 0 and Max_Data = 27 */ 137 138 uint32_t FilterMode; /*!< Specifies the filter mode to be initialized. 139 This parameter can be a value of @ref CAN_filter_mode */ 140 141 uint32_t FilterScale; /*!< Specifies the filter scale. 142 This parameter can be a value of @ref CAN_filter_scale */ 143 144 uint32_t FilterActivation; /*!< Enable or disable the filter. 145 This parameter can be set to ENABLE or DISABLE. */ 146 147 uint32_t BankNumber; /*!< Select the start slave bank filter. 148 This parameter must be a number between Min_Data = 0 and Max_Data = 28 */ 149 150 }CAN_FilterConfTypeDef; 151 152 /** 153 * @brief CAN Tx message structure definition 154 */ 155 typedef struct 156 { 157 uint32_t StdId; /*!< Specifies the standard identifier. 158 This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ 159 160 uint32_t ExtId; /*!< Specifies the extended identifier. 161 This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ 162 163 uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. 164 This parameter can be a value of @ref CAN_Identifier_Type */ 165 166 uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. 167 This parameter can be a value of @ref CAN_remote_transmission_request */ 168 169 uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. 170 This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ 171 172 uint8_t Data[8]; /*!< Contains the data to be transmitted. 173 This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ 174 175 }CanTxMsgTypeDef; 176 177 /** 178 * @brief CAN Rx message structure definition 179 */ 180 typedef struct 181 { 182 uint32_t StdId; /*!< Specifies the standard identifier. 183 This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ 184 185 uint32_t ExtId; /*!< Specifies the extended identifier. 186 This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ 187 188 uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received. 189 This parameter can be a value of @ref CAN_Identifier_Type */ 190 191 uint32_t RTR; /*!< Specifies the type of frame for the received message. 192 This parameter can be a value of @ref CAN_remote_transmission_request */ 193 194 uint32_t DLC; /*!< Specifies the length of the frame that will be received. 195 This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ 196 197 uint8_t Data[8]; /*!< Contains the data to be received. 198 This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ 199 200 uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. 201 This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ 202 203 uint32_t FIFONumber; /*!< Specifies the receive FIFO number. 204 This parameter can be CAN_FIFO0 or CAN_FIFO1 */ 205 206 }CanRxMsgTypeDef; 207 208 /** 209 * @brief CAN handle Structure definition 210 */ 211 typedef struct 212 { 213 CAN_TypeDef *Instance; /*!< Register base address */ 214 215 CAN_InitTypeDef Init; /*!< CAN required parameters */ 216 217 CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */ 218 219 CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */ 220 221 CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */ 222 223 __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ 224 225 HAL_LockTypeDef Lock; /*!< CAN locking object */ 226 227 __IO uint32_t ErrorCode; /*!< CAN Error code */ 228 229 }CAN_HandleTypeDef; 230 231 /** 232 * @} 233 */ 234 235 /* Exported constants --------------------------------------------------------*/ 236 /** @defgroup CAN_Exported_Constants CAN Exported Constants 237 * @{ 238 */ 239 240 /** @defgroup CAN_Error_Code CAN Error Code 241 * @{ 242 */ 243 #define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */ 244 #define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */ 245 #define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */ 246 #define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */ 247 #define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */ 248 #define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */ 249 #define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */ 250 #define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */ 251 #define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */ 252 #define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */ 253 #define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */ 254 #define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */ 255 #define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */ 256 /** 257 * @} 258 */ 259 260 /** @defgroup CAN_InitStatus CAN InitStatus 261 * @{ 262 */ 263 #define CAN_INITSTATUS_FAILED ((uint8_t)0x00) /*!< CAN initialization failed */ 264 #define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01) /*!< CAN initialization OK */ 265 /** 266 * @} 267 */ 268 269 /** @defgroup CAN_operating_mode CAN Operating Mode 270 * @{ 271 */ 272 #define CAN_MODE_NORMAL 0x00000000U /*!< Normal mode */ 273 #define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ 274 #define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ 275 #define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ 276 /** 277 * @} 278 */ 279 280 /** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width 281 * @{ 282 */ 283 #define CAN_SJW_1TQ 0x00000000U /*!< 1 time quantum */ 284 #define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ 285 #define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ 286 #define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ 287 /** 288 * @} 289 */ 290 291 /** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1 292 * @{ 293 */ 294 #define CAN_BS1_1TQ 0x00000000U /*!< 1 time quantum */ 295 #define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ 296 #define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ 297 #define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ 298 #define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */ 299 #define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */ 300 #define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */ 301 #define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */ 302 #define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */ 303 #define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */ 304 #define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */ 305 #define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */ 306 #define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */ 307 #define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */ 308 #define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */ 309 #define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */ 310 /** 311 * @} 312 */ 313 314 /** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2 315 * @{ 316 */ 317 #define CAN_BS2_1TQ 0x00000000U /*!< 1 time quantum */ 318 #define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ 319 #define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ 320 #define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ 321 #define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */ 322 #define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */ 323 #define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */ 324 #define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */ 325 /** 326 * @} 327 */ 328 329 /** @defgroup CAN_filter_mode CAN Filter Mode 330 * @{ 331 */ 332 #define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */ 333 #define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */ 334 /** 335 * @} 336 */ 337 338 /** @defgroup CAN_filter_scale CAN Filter Scale 339 * @{ 340 */ 341 #define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */ 342 #define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */ 343 /** 344 * @} 345 */ 346 347 /** @defgroup CAN_filter_FIFO CAN Filter FIFO 348 * @{ 349 */ 350 #define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ 351 #define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ 352 /** 353 * @} 354 */ 355 356 /** @defgroup CAN_Identifier_Type CAN Identifier Type 357 * @{ 358 */ 359 #define CAN_ID_STD 0x00000000U /*!< Standard Id */ 360 #define CAN_ID_EXT 0x00000004U /*!< Extended Id */ 361 /** 362 * @} 363 */ 364 365 /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request 366 * @{ 367 */ 368 #define CAN_RTR_DATA 0x00000000U /*!< Data frame */ 369 #define CAN_RTR_REMOTE 0x00000002U /*!< Remote frame */ 370 /** 371 * @} 372 */ 373 374 /** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants 375 * @{ 376 */ 377 #define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ 378 #define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ 379 /** 380 * @} 381 */ 382 383 /** @defgroup CAN_flags CAN Flags 384 * @{ 385 */ 386 /* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() 387 and CAN_ClearFlag() functions. */ 388 /* If the flag is 0x1XXXXXXX, it means that it can only be used with 389 CAN_GetFlagStatus() function. */ 390 391 /* Transmit Flags */ 392 #define CAN_FLAG_RQCP0 0x00000500U /*!< Request MailBox0 flag */ 393 #define CAN_FLAG_RQCP1 0x00000508U /*!< Request MailBox1 flag */ 394 #define CAN_FLAG_RQCP2 0x00000510U /*!< Request MailBox2 flag */ 395 #define CAN_FLAG_TXOK0 0x00000501U /*!< Transmission OK MailBox0 flag */ 396 #define CAN_FLAG_TXOK1 0x00000509U /*!< Transmission OK MailBox1 flag */ 397 #define CAN_FLAG_TXOK2 0x00000511U /*!< Transmission OK MailBox2 flag */ 398 #define CAN_FLAG_TME0 0x0000051AU /*!< Transmit mailbox 0 empty flag */ 399 #define CAN_FLAG_TME1 0x0000051BU /*!< Transmit mailbox 0 empty flag */ 400 #define CAN_FLAG_TME2 0x0000051CU /*!< Transmit mailbox 0 empty flag */ 401 402 /* Receive Flags */ 403 #define CAN_FLAG_FF0 0x00000203U /*!< FIFO 0 Full flag */ 404 #define CAN_FLAG_FOV0 0x00000204U /*!< FIFO 0 Overrun flag */ 405 406 #define CAN_FLAG_FF1 0x00000403U /*!< FIFO 1 Full flag */ 407 #define CAN_FLAG_FOV1 0x00000404U /*!< FIFO 1 Overrun flag */ 408 409 /* Operating Mode Flags */ 410 #define CAN_FLAG_INAK 0x00000100U /*!< Initialization acknowledge flag */ 411 #define CAN_FLAG_SLAK 0x00000101U /*!< Sleep acknowledge flag */ 412 #define CAN_FLAG_ERRI 0x00000102U /*!< Error flag */ 413 #define CAN_FLAG_WKU 0x00000103U /*!< Wake up flag */ 414 #define CAN_FLAG_SLAKI 0x00000104U /*!< Sleep acknowledge flag */ 415 416 /* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. 417 In this case the SLAK bit can be polled.*/ 418 419 /* Error Flags */ 420 #define CAN_FLAG_EWG 0x00000300U /*!< Error warning flag */ 421 #define CAN_FLAG_EPV 0x00000301U /*!< Error passive flag */ 422 #define CAN_FLAG_BOF 0x00000302U /*!< Bus-Off flag */ 423 /** 424 * @} 425 */ 426 427 /** @defgroup CAN_Interrupts CAN Interrupts 428 * @{ 429 */ 430 #define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ 431 432 /* Receive Interrupts */ 433 #define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ 434 #define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ 435 #define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ 436 #define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ 437 #define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ 438 #define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ 439 440 /* Operating Mode Interrupts */ 441 #define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ 442 #define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ 443 444 /* Error Interrupts */ 445 #define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ 446 #define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ 447 #define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ 448 #define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ 449 #define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ 450 /** 451 * @} 452 */ 453 454 /** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition 455 * @{ 456 */ 457 #define CAN_TXMAILBOX_0 ((uint8_t)0x00) 458 #define CAN_TXMAILBOX_1 ((uint8_t)0x01) 459 #define CAN_TXMAILBOX_2 ((uint8_t)0x02) 460 /** 461 * @} 462 */ 463 464 /** 465 * @} 466 */ 467 468 /* Exported macro ------------------------------------------------------------*/ 469 /** @defgroup CAN_Exported_Macros CAN Exported Macros 470 * @{ 471 */ 472 473 /** @brief Reset CAN handle state 474 * @param __HANDLE__ specifies the CAN Handle. 475 * @retval None 476 */ 477 #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) 478 479 /** 480 * @brief Enable the specified CAN interrupts. 481 * @param __HANDLE__ CAN handle 482 * @param __INTERRUPT__ CAN Interrupt 483 * @retval None 484 */ 485 #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) 486 487 /** 488 * @brief Disable the specified CAN interrupts. 489 * @param __HANDLE__ CAN handle 490 * @param __INTERRUPT__ CAN Interrupt 491 * @retval None 492 */ 493 #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) 494 495 /** 496 * @brief Return the number of pending received messages. 497 * @param __HANDLE__ CAN handle 498 * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. 499 * @retval The number of pending message. 500 */ 501 #define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ 502 ((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & 0x03U))) 503 504 /** @brief Check whether the specified CAN flag is set or not. 505 * @param __HANDLE__ CAN Handle 506 * @param __FLAG__ specifies the flag to check. 507 * This parameter can be one of the following values: 508 * @arg CAN_TSR_RQCP0: Request MailBox0 Flag 509 * @arg CAN_TSR_RQCP1: Request MailBox1 Flag 510 * @arg CAN_TSR_RQCP2: Request MailBox2 Flag 511 * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag 512 * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag 513 * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag 514 * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag 515 * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag 516 * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag 517 * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag 518 * @arg CAN_FLAG_FF0: FIFO 0 Full Flag 519 * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag 520 * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag 521 * @arg CAN_FLAG_FF1: FIFO 1 Full Flag 522 * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag 523 * @arg CAN_FLAG_WKU: Wake up Flag 524 * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag 525 * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag 526 * @arg CAN_FLAG_EWG: Error Warning Flag 527 * @arg CAN_FLAG_EPV: Error Passive Flag 528 * @arg CAN_FLAG_BOF: Bus-Off Flag 529 * @retval The new state of __FLAG__ (TRUE or FALSE). 530 */ 531 #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ 532 ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ 533 (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ 534 (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ 535 (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ 536 ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK)))) 537 538 /** @brief Clear the specified CAN pending flag. 539 * @param __HANDLE__ CAN Handle. 540 * @param __FLAG__ specifies the flag to check. 541 * This parameter can be one of the following values: 542 * @arg CAN_TSR_RQCP0: Request MailBox0 Flag 543 * @arg CAN_TSR_RQCP1: Request MailBox1 Flag 544 * @arg CAN_TSR_RQCP2: Request MailBox2 Flag 545 * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag 546 * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag 547 * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag 548 * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag 549 * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag 550 * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag 551 * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag 552 * @arg CAN_FLAG_FF0: FIFO 0 Full Flag 553 * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag 554 * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag 555 * @arg CAN_FLAG_FF1: FIFO 1 Full Flag 556 * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag 557 * @arg CAN_FLAG_WKU: Wake up Flag 558 * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag 559 * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag 560 * @retval The new state of __FLAG__ (TRUE or FALSE). 561 */ 562 #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 563 ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ 564 (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ 565 (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ 566 (((__HANDLE__)->Instance->MSR) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK)))) 567 568 /** @brief Check if the specified CAN interrupt source is enabled or disabled. 569 * @param __HANDLE__ CAN Handle 570 * @param __INTERRUPT__ specifies the CAN interrupt source to check. 571 * This parameter can be one of the following values: 572 * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable 573 * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable 574 * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable 575 * @retval The new state of __IT__ (TRUE or FALSE). 576 */ 577 #define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 578 579 /** 580 * @brief Check the transmission status of a CAN Frame. 581 * @param __HANDLE__ CAN Handle 582 * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission. 583 * @retval The new status of transmission (TRUE or FALSE). 584 */ 585 #define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\ 586 (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\ 587 ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\ 588 ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2))) 589 590 /** 591 * @brief Release the specified receive FIFO. 592 * @param __HANDLE__ CAN handle 593 * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. 594 * @retval None 595 */ 596 #define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ 597 ((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1)) 598 599 /** 600 * @brief Cancel a transmit request. 601 * @param __HANDLE__ CAN Handle 602 * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission. 603 * @retval None 604 */ 605 #define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\ 606 (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\ 607 ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\ 608 ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2)) 609 610 /** 611 * @brief Enable or disable the DBG Freeze for CAN. 612 * @param __HANDLE__ CAN Handle 613 * @param __NEWSTATE__ new state of the CAN peripheral. 614 * This parameter can be: ENABLE (CAN reception/transmission is frozen 615 * during debug. Reception FIFOs can still be accessed/controlled normally) 616 * or DISABLE (CAN is working during debug). 617 * @retval None 618 */ 619 #define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \ 620 ((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) 621 622 /** 623 * @} 624 */ 625 626 /* Exported functions --------------------------------------------------------*/ 627 /** @addtogroup CAN_Exported_Functions 628 * @{ 629 */ 630 631 /** @addtogroup CAN_Exported_Functions_Group1 632 * @{ 633 */ 634 /* Initialization/de-initialization functions ***********************************/ 635 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan); 636 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig); 637 HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan); 638 void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan); 639 void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan); 640 /** 641 * @} 642 */ 643 644 /** @addtogroup CAN_Exported_Functions_Group2 645 * @{ 646 */ 647 /* I/O operation functions ******************************************************/ 648 HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout); 649 HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan); 650 HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout); 651 HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber); 652 HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan); 653 HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); 654 void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan); 655 void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan); 656 void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan); 657 void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); 658 /** 659 * @} 660 */ 661 662 /** @addtogroup CAN_Exported_Functions_Group3 663 * @{ 664 */ 665 /* Peripheral State functions ***************************************************/ 666 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); 667 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); 668 /** 669 * @} 670 */ 671 672 /** 673 * @} 674 */ 675 676 /* Private types -------------------------------------------------------------*/ 677 /** @defgroup CAN_Private_Types CAN Private Types 678 * @{ 679 */ 680 681 /** 682 * @} 683 */ 684 685 /* Private variables ---------------------------------------------------------*/ 686 /** @defgroup CAN_Private_Variables CAN Private Variables 687 * @{ 688 */ 689 690 /** 691 * @} 692 */ 693 694 /* Private constants ---------------------------------------------------------*/ 695 /** @defgroup CAN_Private_Constants CAN Private Constants 696 * @{ 697 */ 698 #define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ 699 #define CAN_FLAG_MASK 0x000000FFU 700 /** 701 * @} 702 */ 703 704 /* Private macros ------------------------------------------------------------*/ 705 /** @defgroup CAN_Private_Macros CAN Private Macros 706 * @{ 707 */ 708 #define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ 709 ((MODE) == CAN_MODE_LOOPBACK)|| \ 710 ((MODE) == CAN_MODE_SILENT) || \ 711 ((MODE) == CAN_MODE_SILENT_LOOPBACK)) 712 #define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \ 713 ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) 714 #define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) 715 #define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) 716 #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) 717 #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U) 718 #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ 719 ((MODE) == CAN_FILTERMODE_IDLIST)) 720 #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ 721 ((SCALE) == CAN_FILTERSCALE_32BIT)) 722 #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ 723 ((FIFO) == CAN_FILTER_FIFO1)) 724 #define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U) 725 726 #define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) 727 #define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FFU)) 728 #define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) 729 #define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) 730 731 #define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ 732 ((IDTYPE) == CAN_ID_EXT)) 733 #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) 734 #define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) 735 736 /** 737 * @} 738 */ 739 740 /* Private functions ---------------------------------------------------------*/ 741 /** @defgroup CAN_Private_Functions CAN Private Functions 742 * @{ 743 */ 744 745 /** 746 * @} 747 */ 748 749 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ 750 STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ 751 STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 752 753 /** 754 * @} 755 */ 756 757 /** 758 * @} 759 */ 760 761 #ifdef __cplusplus 762 } 763 #endif 764 765 #endif /* __STM32F4xx_HAL_CAN_LEGACY_H */ 766
