1 /** 2 ****************************************************************************** 3 * @file stm32_hal_legacy.h 4 * @author MCD Application Team 5 * @brief This file contains aliases definition for the STM32Cube HAL constants 6 * macros and functions maintained for legacy purpose. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32_HAL_LEGACY 22 #define STM32_HAL_LEGACY 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 /* Exported types ------------------------------------------------------------*/ 30 /* Exported constants --------------------------------------------------------*/ 31 32 /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose 33 * @{ 34 */ 35 #define AES_FLAG_RDERR CRYP_FLAG_RDERR 36 #define AES_FLAG_WRERR CRYP_FLAG_WRERR 37 #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF 38 #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR 39 #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR 40 #if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1) 41 #define CRYP_DATATYPE_32B CRYP_NO_SWAP 42 #define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP 43 #define CRYP_DATATYPE_8B CRYP_BYTE_SWAP 44 #define CRYP_DATATYPE_1B CRYP_BIT_SWAP 45 #if defined(STM32U5) 46 #define CRYP_CCF_CLEAR CRYP_CLEAR_CCF 47 #define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF 48 #endif /* STM32U5 */ 49 #endif /* STM32U5 || STM32H7 || STM32MP1 */ 50 /** 51 * @} 52 */ 53 54 /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose 55 * @{ 56 */ 57 #define ADC_RESOLUTION12b ADC_RESOLUTION_12B 58 #define ADC_RESOLUTION10b ADC_RESOLUTION_10B 59 #define ADC_RESOLUTION8b ADC_RESOLUTION_8B 60 #define ADC_RESOLUTION6b ADC_RESOLUTION_6B 61 #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN 62 #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED 63 #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV 64 #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV 65 #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV 66 #define REGULAR_GROUP ADC_REGULAR_GROUP 67 #define INJECTED_GROUP ADC_INJECTED_GROUP 68 #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP 69 #define AWD_EVENT ADC_AWD_EVENT 70 #define AWD1_EVENT ADC_AWD1_EVENT 71 #define AWD2_EVENT ADC_AWD2_EVENT 72 #define AWD3_EVENT ADC_AWD3_EVENT 73 #define OVR_EVENT ADC_OVR_EVENT 74 #define JQOVF_EVENT ADC_JQOVF_EVENT 75 #define ALL_CHANNELS ADC_ALL_CHANNELS 76 #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS 77 #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS 78 #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR 79 #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT 80 #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 81 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 82 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 83 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 84 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 85 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO 86 #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 87 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO 88 #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 89 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO 90 #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 91 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 92 #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE 93 #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING 94 #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING 95 #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING 96 #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 97 98 #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY 99 #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY 100 #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC 101 #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC 102 #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL 103 #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL 104 #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 105 106 #if defined(STM32H7) 107 #define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT 108 #endif /* STM32H7 */ 109 110 #if defined(STM32U5) 111 #define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES 112 #define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES 113 #define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 114 #endif /* STM32U5 */ 115 116 /** 117 * @} 118 */ 119 120 /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose 121 * @{ 122 */ 123 124 #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG 125 126 /** 127 * @} 128 */ 129 130 /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose 131 * @{ 132 */ 133 #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE 134 #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE 135 #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 136 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 137 #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 138 #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 139 #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 140 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 141 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 142 #if defined(STM32L0) 143 #define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ 144 #endif 145 #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR 146 #if defined(STM32F373xC) || defined(STM32F378xx) 147 #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 148 #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR 149 #endif /* STM32F373xC || STM32F378xx */ 150 151 #if defined(STM32L0) || defined(STM32L4) 152 #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON 153 154 #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 155 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 156 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 157 #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 158 #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 159 #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 160 161 #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT 162 #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT 163 #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT 164 #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT 165 #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 166 #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 167 #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 168 #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 169 #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 170 #if defined(STM32L0) 171 /* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ 172 /* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ 173 /* to the second dedicated IO (only for COMP2). */ 174 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 175 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 176 #else 177 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 178 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 179 #endif 180 #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 181 #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 182 183 #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW 184 #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH 185 186 /* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ 187 /* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ 188 #if defined(COMP_CSR_LOCK) 189 #define COMP_FLAG_LOCK COMP_CSR_LOCK 190 #elif defined(COMP_CSR_COMP1LOCK) 191 #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK 192 #elif defined(COMP_CSR_COMPxLOCK) 193 #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK 194 #endif 195 196 #if defined(STM32L4) 197 #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 198 #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 199 #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 200 #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 201 #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 202 #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 203 #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE 204 #endif 205 206 #if defined(STM32L0) 207 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED 208 #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER 209 #else 210 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED 211 #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED 212 #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER 213 #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER 214 #endif 215 216 #endif 217 /** 218 * @} 219 */ 220 221 /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose 222 * @{ 223 */ 224 #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig 225 #if defined(STM32U5) 226 #define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE 227 #define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE 228 #define MPU_DEVICE_nGRE MPU_DEVICE_NGRE 229 #endif /* STM32U5 */ 230 /** 231 * @} 232 */ 233 234 /** @defgroup CRC_Aliases CRC API aliases 235 * @{ 236 */ 237 #if defined(STM32C0) 238 #else 239 #define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ 240 #define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ 241 #endif 242 /** 243 * @} 244 */ 245 246 /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose 247 * @{ 248 */ 249 250 #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE 251 #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE 252 253 /** 254 * @} 255 */ 256 257 /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose 258 * @{ 259 */ 260 261 #define DAC1_CHANNEL_1 DAC_CHANNEL_1 262 #define DAC1_CHANNEL_2 DAC_CHANNEL_2 263 #define DAC2_CHANNEL_1 DAC_CHANNEL_1 264 #define DAC_WAVE_NONE 0x00000000U 265 #define DAC_WAVE_NOISE DAC_CR_WAVE1_0 266 #define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 267 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE 268 #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE 269 #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE 270 271 #if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) 272 #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL 273 #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL 274 #endif 275 276 #if defined(STM32U5) 277 #define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 278 #define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 279 #define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 280 #define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 281 #endif 282 283 #if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) 284 #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID 285 #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID 286 #endif 287 288 /** 289 * @} 290 */ 291 292 /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose 293 * @{ 294 */ 295 #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 296 #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 297 #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 298 #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 299 #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 300 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 301 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 302 #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 303 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 304 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 305 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 306 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 307 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 308 #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 309 310 #define IS_HAL_REMAPDMA IS_DMA_REMAP 311 #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE 312 #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE 313 314 #if defined(STM32L4) 315 316 #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 317 #define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 318 #define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 319 #define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 320 #define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 321 #define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 322 #define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 323 #define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 324 #define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 325 #define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 326 #define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 327 #define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 328 #define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 329 #define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 330 #define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 331 #define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 332 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 333 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 334 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 335 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 336 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 337 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 338 #define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE 339 #define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT 340 #define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT 341 #define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT 342 343 #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT 344 #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING 345 #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING 346 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING 347 348 #if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 349 #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI 350 #endif 351 352 #endif /* STM32L4 */ 353 354 #if defined(STM32G0) 355 #define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 356 #define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 357 #define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM 358 #define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM 359 360 #define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM 361 #define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM 362 #endif 363 364 #if defined(STM32H7) 365 366 #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 367 #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 368 369 #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX 370 #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX 371 372 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 373 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 374 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 375 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 376 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 377 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT 378 #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 379 #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO 380 381 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 382 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 383 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 384 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 385 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 386 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 387 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 388 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 389 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 390 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 391 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT 392 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 393 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT 394 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 395 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 396 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP 397 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP 398 #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT 399 #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT 400 #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP 401 #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 402 #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 403 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 404 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT 405 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 406 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 407 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT 408 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 409 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 410 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 411 412 #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT 413 #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING 414 #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING 415 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING 416 417 #define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT 418 #define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT 419 #define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT 420 421 #define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT 422 #define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT 423 424 #endif /* STM32H7 */ 425 426 #if defined(STM32U5) 427 #define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI 428 #endif /* STM32U5 */ 429 /** 430 * @} 431 */ 432 433 /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose 434 * @{ 435 */ 436 437 #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE 438 #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD 439 #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD 440 #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD 441 #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS 442 #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES 443 #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES 444 #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE 445 #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE 446 #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE 447 #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE 448 #define OBEX_PCROP OPTIONBYTE_PCROP 449 #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG 450 #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE 451 #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE 452 #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE 453 #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD 454 #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD 455 #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE 456 #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD 457 #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD 458 #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE 459 #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD 460 #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD 461 #define PAGESIZE FLASH_PAGE_SIZE 462 #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE 463 #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD 464 #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD 465 #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 466 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 467 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 468 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 469 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST 470 #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST 471 #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA 472 #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB 473 #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA 474 #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB 475 #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE 476 #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN 477 #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE 478 #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN 479 #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE 480 #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD 481 #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG 482 #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS 483 #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP 484 #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV 485 #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR 486 #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG 487 #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION 488 #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA 489 #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE 490 #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE 491 #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS 492 #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS 493 #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST 494 #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR 495 #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO 496 #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION 497 #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS 498 #define OB_WDG_SW OB_IWDG_SW 499 #define OB_WDG_HW OB_IWDG_HW 500 #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET 501 #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET 502 #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET 503 #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET 504 #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR 505 #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 506 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 507 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 508 #if defined(STM32G0) || defined(STM32C0) 509 #define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE 510 #define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH 511 #else 512 #define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE 513 #define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE 514 #endif 515 #if defined(STM32H7) 516 #define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 517 #define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 518 #define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 519 #define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 520 #define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 521 #define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 522 #define FLASH_FLAG_WDW FLASH_FLAG_WBNE 523 #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL 524 #endif /* STM32H7 */ 525 #if defined(STM32U5) 526 #define OB_USER_nRST_STOP OB_USER_NRST_STOP 527 #define OB_USER_nRST_STDBY OB_USER_NRST_STDBY 528 #define OB_USER_nRST_SHDW OB_USER_NRST_SHDW 529 #define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 530 #define OB_USER_nBOOT0 OB_USER_NBOOT0 531 #define OB_nBOOT0_RESET OB_NBOOT0_RESET 532 #define OB_nBOOT0_SET OB_NBOOT0_SET 533 #endif /* STM32U5 */ 534 535 /** 536 * @} 537 */ 538 539 /** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose 540 * @{ 541 */ 542 543 #if defined(STM32H7) 544 #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE 545 #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE 546 #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET 547 #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET 548 #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE 549 #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE 550 #endif /* STM32H7 */ 551 552 /** 553 * @} 554 */ 555 556 /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose 557 * @{ 558 */ 559 560 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 561 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 562 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 563 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 564 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 565 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 566 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 567 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 568 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 569 #if defined(STM32G4) 570 571 #define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster 572 #define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster 573 #define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD 574 #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD 575 #endif /* STM32G4 */ 576 577 /** 578 * @} 579 */ 580 581 582 /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose 583 * @{ 584 */ 585 #if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) 586 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE 587 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE 588 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 589 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 590 #elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) 591 #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE 592 #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE 593 #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 594 #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 595 #endif 596 /** 597 * @} 598 */ 599 600 /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose 601 * @{ 602 */ 603 604 #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef 605 #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef 606 /** 607 * @} 608 */ 609 610 /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose 611 * @{ 612 */ 613 #define GET_GPIO_SOURCE GPIO_GET_INDEX 614 #define GET_GPIO_INDEX GPIO_GET_INDEX 615 616 #if defined(STM32F4) 617 #define GPIO_AF12_SDMMC GPIO_AF12_SDIO 618 #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO 619 #endif 620 621 #if defined(STM32F7) 622 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 623 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 624 #endif 625 626 #if defined(STM32L4) 627 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 628 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 629 #endif 630 631 #if defined(STM32H7) 632 #define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 633 #define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 634 #define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 635 #define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 636 #define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 637 #define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 638 639 #if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ 640 defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) 641 #define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS 642 #define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS 643 #define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS 644 #endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ 645 #endif /* STM32H7 */ 646 647 #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 648 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 649 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 650 651 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) 652 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW 653 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM 654 #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH 655 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH 656 #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ 657 658 #if defined(STM32L1) 659 #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW 660 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM 661 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH 662 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH 663 #endif /* STM32L1 */ 664 665 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) 666 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW 667 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM 668 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH 669 #endif /* STM32F0 || STM32F3 || STM32F1 */ 670 671 #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 672 673 #if defined(STM32U5) 674 #define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ 675 #endif /* STM32U5 */ 676 #if defined(STM32U5) 677 #define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP 678 #define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 679 #endif /* STM32U5 */ 680 /** 681 * @} 682 */ 683 684 /** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose 685 * @{ 686 */ 687 #if defined(STM32U5) 688 #define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI 689 #endif /* STM32U5 */ 690 /** 691 * @} 692 */ 693 694 /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose 695 * @{ 696 */ 697 #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED 698 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 699 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 700 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 701 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 702 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 703 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 704 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 705 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 706 707 #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER 708 #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER 709 #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD 710 #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD 711 #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER 712 #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER 713 #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE 714 #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE 715 716 #if defined(STM32G4) 717 #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig 718 #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable 719 #define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable 720 #define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset 721 #define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A 722 #define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B 723 #define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL 724 #define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL 725 #endif /* STM32G4 */ 726 727 #if defined(STM32H7) 728 #define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 729 #define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 730 #define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 731 #define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 732 #define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 733 #define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 734 #define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 735 #define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 736 #define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 737 #define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 738 #define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 739 #define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 740 #define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 741 #define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 742 #define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 743 #define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 744 #define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 745 #define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 746 #define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 747 #define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 748 #define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 749 #define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 750 #define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 751 #define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 752 #define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 753 #define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 754 #define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 755 #define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 756 #define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 757 #define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 758 #define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 759 #define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 760 #define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 761 #define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 762 #define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 763 #define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 764 #define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 765 #define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 766 #define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 767 #define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 768 #define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 769 #define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 770 #define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 771 #define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 772 #define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 773 #define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 774 #define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 775 #define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 776 #define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 777 #define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 778 #define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 779 #define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 780 #define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 781 #define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 782 783 #define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 784 #define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 785 #define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 786 #define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 787 #define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 788 #define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 789 #define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 790 #define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 791 #define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 792 #define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 793 #define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 794 #define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 795 #define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 796 #define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 797 #define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 798 #define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 799 #define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 800 #define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 801 #define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 802 #define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 803 #define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 804 #define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 805 #define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 806 #define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 807 #define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 808 #define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 809 #define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 810 #define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 811 #define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 812 #define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 813 #define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 814 #define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 815 #define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 816 #define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 817 #define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 818 #define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 819 #define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 820 #define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 821 #define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 822 #define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 823 #define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 824 #define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 825 #define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 826 #define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 827 #define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 828 #define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 829 #define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 830 #define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 831 #define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 832 #define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 833 #define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 834 #define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 835 #define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 836 #define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 837 #endif /* STM32H7 */ 838 839 #if defined(STM32F3) 840 /** @brief Constants defining available sources associated to external events. 841 */ 842 #define HRTIM_EVENTSRC_1 (0x00000000U) 843 #define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) 844 #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) 845 #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) 846 847 /** @brief Constants defining the DLL calibration periods (in micro seconds) 848 */ 849 #define HRTIM_CALIBRATIONRATE_7300 0x00000000U 850 #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) 851 #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) 852 #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) 853 854 #endif /* STM32F3 */ 855 /** 856 * @} 857 */ 858 859 /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose 860 * @{ 861 */ 862 #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE 863 #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE 864 #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE 865 #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE 866 #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE 867 #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE 868 #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE 869 #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE 870 #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) 871 #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX 872 #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX 873 #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX 874 #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX 875 #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX 876 #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX 877 #endif 878 /** 879 * @} 880 */ 881 882 /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose 883 * @{ 884 */ 885 #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE 886 #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE 887 888 /** 889 * @} 890 */ 891 892 /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose 893 * @{ 894 */ 895 #define KR_KEY_RELOAD IWDG_KEY_RELOAD 896 #define KR_KEY_ENABLE IWDG_KEY_ENABLE 897 #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE 898 #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE 899 /** 900 * @} 901 */ 902 903 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose 904 * @{ 905 */ 906 907 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 908 #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS 909 #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS 910 #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS 911 912 #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING 913 #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING 914 #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING 915 916 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 917 #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS 918 #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS 919 #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS 920 921 /* The following 3 definition have also been present in a temporary version of lptim.h */ 922 /* They need to be renamed also to the right name, just in case */ 923 #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS 924 #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS 925 #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS 926 927 928 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose 929 * @{ 930 */ 931 #define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue 932 /** 933 * @} 934 */ 935 936 #if defined(STM32U5) 937 #define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF 938 #define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF 939 #define LPTIM_CHANNEL_ALL 0x00000000U 940 #endif /* STM32U5 */ 941 /** 942 * @} 943 */ 944 945 /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose 946 * @{ 947 */ 948 #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b 949 #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b 950 #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b 951 #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b 952 953 #define NAND_AddressTypedef NAND_AddressTypeDef 954 955 #define __ARRAY_ADDRESS ARRAY_ADDRESS 956 #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE 957 #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE 958 #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE 959 #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE 960 /** 961 * @} 962 */ 963 964 /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose 965 * @{ 966 */ 967 #define NOR_StatusTypedef HAL_NOR_StatusTypeDef 968 #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS 969 #define NOR_ONGOING HAL_NOR_STATUS_ONGOING 970 #define NOR_ERROR HAL_NOR_STATUS_ERROR 971 #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT 972 973 #define __NOR_WRITE NOR_WRITE 974 #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT 975 /** 976 * @} 977 */ 978 979 /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose 980 * @{ 981 */ 982 983 #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 984 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 985 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 986 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 987 988 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 989 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 990 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 991 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 992 993 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 994 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 995 996 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 997 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 998 999 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 1000 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 1001 1002 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 1003 1004 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO 1005 #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 1006 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 1007 1008 #if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) 1009 #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID 1010 #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID 1011 #endif 1012 1013 #if defined(STM32L4) || defined(STM32L5) 1014 #define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER 1015 #elif defined(STM32G4) 1016 #define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED 1017 #endif 1018 1019 /** 1020 * @} 1021 */ 1022 1023 /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose 1024 * @{ 1025 */ 1026 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS 1027 1028 #if defined(STM32H7) 1029 #define I2S_IT_TXE I2S_IT_TXP 1030 #define I2S_IT_RXNE I2S_IT_RXP 1031 1032 #define I2S_FLAG_TXE I2S_FLAG_TXP 1033 #define I2S_FLAG_RXNE I2S_FLAG_RXP 1034 #endif 1035 1036 #if defined(STM32F7) 1037 #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL 1038 #endif 1039 /** 1040 * @} 1041 */ 1042 1043 /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose 1044 * @{ 1045 */ 1046 1047 /* Compact Flash-ATA registers description */ 1048 #define CF_DATA ATA_DATA 1049 #define CF_SECTOR_COUNT ATA_SECTOR_COUNT 1050 #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER 1051 #define CF_CYLINDER_LOW ATA_CYLINDER_LOW 1052 #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH 1053 #define CF_CARD_HEAD ATA_CARD_HEAD 1054 #define CF_STATUS_CMD ATA_STATUS_CMD 1055 #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE 1056 #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA 1057 1058 /* Compact Flash-ATA commands */ 1059 #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD 1060 #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD 1061 #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD 1062 #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD 1063 1064 #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef 1065 #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS 1066 #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING 1067 #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR 1068 #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT 1069 /** 1070 * @} 1071 */ 1072 1073 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose 1074 * @{ 1075 */ 1076 1077 #define FORMAT_BIN RTC_FORMAT_BIN 1078 #define FORMAT_BCD RTC_FORMAT_BCD 1079 1080 #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE 1081 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE 1082 #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 1083 #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 1084 1085 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 1086 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 1087 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE 1088 #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT 1089 #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT 1090 1091 #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT 1092 #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 1093 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 1094 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 1095 1096 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE 1097 #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 1098 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 1099 1100 #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT 1101 #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 1102 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 1103 1104 #if defined(STM32F7) 1105 #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK 1106 #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK 1107 #endif /* STM32F7 */ 1108 1109 #if defined(STM32H7) 1110 #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X 1111 #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT 1112 #endif /* STM32H7 */ 1113 1114 #if defined(STM32F7) || defined(STM32H7) 1115 #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 1116 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 1117 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 1118 #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP 1119 #endif /* STM32F7 || STM32H7 */ 1120 1121 /** 1122 * @} 1123 */ 1124 1125 1126 /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose 1127 * @{ 1128 */ 1129 #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE 1130 #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE 1131 1132 #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE 1133 #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE 1134 #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE 1135 #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE 1136 1137 #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE 1138 #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE 1139 1140 #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE 1141 #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE 1142 /** 1143 * @} 1144 */ 1145 1146 1147 /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose 1148 * @{ 1149 */ 1150 #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE 1151 #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE 1152 #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE 1153 #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE 1154 #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE 1155 #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE 1156 #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE 1157 #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE 1158 #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE 1159 #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE 1160 #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN 1161 /** 1162 * @} 1163 */ 1164 1165 /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose 1166 * @{ 1167 */ 1168 #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE 1169 #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE 1170 1171 #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE 1172 #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE 1173 1174 #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE 1175 #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE 1176 1177 #if defined(STM32H7) 1178 1179 #define SPI_FLAG_TXE SPI_FLAG_TXP 1180 #define SPI_FLAG_RXNE SPI_FLAG_RXP 1181 1182 #define SPI_IT_TXE SPI_IT_TXP 1183 #define SPI_IT_RXNE SPI_IT_RXP 1184 1185 #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET 1186 #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET 1187 #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET 1188 #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET 1189 1190 #endif /* STM32H7 */ 1191 1192 /** 1193 * @} 1194 */ 1195 1196 /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose 1197 * @{ 1198 */ 1199 #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK 1200 #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK 1201 1202 #define TIM_DMABase_CR1 TIM_DMABASE_CR1 1203 #define TIM_DMABase_CR2 TIM_DMABASE_CR2 1204 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR 1205 #define TIM_DMABase_DIER TIM_DMABASE_DIER 1206 #define TIM_DMABase_SR TIM_DMABASE_SR 1207 #define TIM_DMABase_EGR TIM_DMABASE_EGR 1208 #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 1209 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 1210 #define TIM_DMABase_CCER TIM_DMABASE_CCER 1211 #define TIM_DMABase_CNT TIM_DMABASE_CNT 1212 #define TIM_DMABase_PSC TIM_DMABASE_PSC 1213 #define TIM_DMABase_ARR TIM_DMABASE_ARR 1214 #define TIM_DMABase_RCR TIM_DMABASE_RCR 1215 #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 1216 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 1217 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 1218 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 1219 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR 1220 #define TIM_DMABase_DCR TIM_DMABASE_DCR 1221 #define TIM_DMABase_DMAR TIM_DMABASE_DMAR 1222 #define TIM_DMABase_OR1 TIM_DMABASE_OR1 1223 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 1224 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 1225 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 1226 #define TIM_DMABase_OR2 TIM_DMABASE_OR2 1227 #define TIM_DMABase_OR3 TIM_DMABASE_OR3 1228 #define TIM_DMABase_OR TIM_DMABASE_OR 1229 1230 #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE 1231 #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 1232 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 1233 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 1234 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 1235 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM 1236 #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER 1237 #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK 1238 #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 1239 1240 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER 1241 #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS 1242 #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS 1243 #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS 1244 #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS 1245 #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS 1246 #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS 1247 #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS 1248 #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS 1249 #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS 1250 #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS 1251 #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS 1252 #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS 1253 #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS 1254 #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS 1255 #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS 1256 #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS 1257 #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS 1258 1259 #if defined(STM32L0) 1260 #define TIM22_TI1_GPIO1 TIM22_TI1_GPIO 1261 #define TIM22_TI1_GPIO2 TIM22_TI1_GPIO 1262 #endif 1263 1264 #if defined(STM32F3) 1265 #define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE 1266 #endif 1267 1268 #if defined(STM32H7) 1269 #define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 1270 #define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 1271 #define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 1272 #define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 1273 #define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 1274 #define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 1275 #define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 1276 #define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 1277 #define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 1278 #define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 1279 #define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 1280 #define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 1281 #define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 1282 #define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 1283 #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 1284 #endif 1285 1286 #if defined(STM32U5) || defined(STM32MP2) 1287 #define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS 1288 #define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK 1289 #endif 1290 /** 1291 * @} 1292 */ 1293 1294 /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose 1295 * @{ 1296 */ 1297 #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING 1298 #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING 1299 /** 1300 * @} 1301 */ 1302 1303 /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose 1304 * @{ 1305 */ 1306 #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE 1307 #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE 1308 #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE 1309 #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE 1310 1311 #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE 1312 #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE 1313 1314 #define __DIV_SAMPLING16 UART_DIV_SAMPLING16 1315 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 1316 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 1317 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 1318 1319 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8 1320 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 1321 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 1322 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 1323 1324 #define __DIV_LPUART UART_DIV_LPUART 1325 1326 #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE 1327 #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK 1328 1329 /** 1330 * @} 1331 */ 1332 1333 1334 /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose 1335 * @{ 1336 */ 1337 1338 #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE 1339 #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE 1340 1341 #define USARTNACK_ENABLED USART_NACK_ENABLE 1342 #define USARTNACK_DISABLED USART_NACK_DISABLE 1343 /** 1344 * @} 1345 */ 1346 1347 /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose 1348 * @{ 1349 */ 1350 #define CFR_BASE WWDG_CFR_BASE 1351 1352 /** 1353 * @} 1354 */ 1355 1356 /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose 1357 * @{ 1358 */ 1359 #define CAN_FilterFIFO0 CAN_FILTER_FIFO0 1360 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1 1361 #define CAN_IT_RQCP0 CAN_IT_TME 1362 #define CAN_IT_RQCP1 CAN_IT_TME 1363 #define CAN_IT_RQCP2 CAN_IT_TME 1364 #define INAK_TIMEOUT CAN_TIMEOUT_VALUE 1365 #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE 1366 #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) 1367 #define CAN_TXSTATUS_OK ((uint8_t)0x01U) 1368 #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) 1369 1370 /** 1371 * @} 1372 */ 1373 1374 /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose 1375 * @{ 1376 */ 1377 1378 #define VLAN_TAG ETH_VLAN_TAG 1379 #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD 1380 #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD 1381 #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD 1382 #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK 1383 #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK 1384 #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK 1385 #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK 1386 1387 #define ETH_MMCCR 0x00000100U 1388 #define ETH_MMCRIR 0x00000104U 1389 #define ETH_MMCTIR 0x00000108U 1390 #define ETH_MMCRIMR 0x0000010CU 1391 #define ETH_MMCTIMR 0x00000110U 1392 #define ETH_MMCTGFSCCR 0x0000014CU 1393 #define ETH_MMCTGFMSCCR 0x00000150U 1394 #define ETH_MMCTGFCR 0x00000168U 1395 #define ETH_MMCRFCECR 0x00000194U 1396 #define ETH_MMCRFAECR 0x00000198U 1397 #define ETH_MMCRGUFCR 0x000001C4U 1398 1399 #define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ 1400 #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ 1401 #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ 1402 #define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ 1403 #define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ 1404 #define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ 1405 #define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ 1406 #define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ 1407 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ 1408 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ 1409 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ 1410 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ 1411 #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ 1412 #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ 1413 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ 1414 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ 1415 #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ 1416 #if defined(STM32F1) 1417 #else 1418 #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ 1419 #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ 1420 #define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ 1421 #endif 1422 #define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ 1423 #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ 1424 #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ 1425 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ 1426 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ 1427 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ 1428 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ 1429 1430 /** 1431 * @} 1432 */ 1433 1434 /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose 1435 * @{ 1436 */ 1437 #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR 1438 #define DCMI_IT_OVF DCMI_IT_OVR 1439 #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI 1440 #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI 1441 1442 #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop 1443 #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop 1444 #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop 1445 1446 /** 1447 * @} 1448 */ 1449 1450 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ 1451 || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ 1452 || defined(STM32H7) 1453 /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose 1454 * @{ 1455 */ 1456 #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 1457 #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 1458 #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 1459 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 1460 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 1461 1462 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888 1463 #define CM_RGB888 DMA2D_INPUT_RGB888 1464 #define CM_RGB565 DMA2D_INPUT_RGB565 1465 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555 1466 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444 1467 #define CM_L8 DMA2D_INPUT_L8 1468 #define CM_AL44 DMA2D_INPUT_AL44 1469 #define CM_AL88 DMA2D_INPUT_AL88 1470 #define CM_L4 DMA2D_INPUT_L4 1471 #define CM_A8 DMA2D_INPUT_A8 1472 #define CM_A4 DMA2D_INPUT_A4 1473 /** 1474 * @} 1475 */ 1476 #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ 1477 1478 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ 1479 || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ 1480 || defined(STM32H7) || defined(STM32U5) 1481 /** @defgroup DMA2D_Aliases DMA2D API Aliases 1482 * @{ 1483 */ 1484 #define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort 1485 for compatibility with legacy code */ 1486 /** 1487 * @} 1488 */ 1489 1490 #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ 1491 1492 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose 1493 * @{ 1494 */ 1495 1496 /** 1497 * @} 1498 */ 1499 1500 /* Exported functions --------------------------------------------------------*/ 1501 1502 /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose 1503 * @{ 1504 */ 1505 #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback 1506 /** 1507 * @} 1508 */ 1509 1510 /** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose 1511 * @{ 1512 */ 1513 1514 #if defined(STM32U5) 1515 #define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr 1516 #define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT 1517 #endif /* STM32U5 */ 1518 1519 /** 1520 * @} 1521 */ 1522 1523 #if !defined(STM32F2) 1524 /** @defgroup HASH_alias HASH API alias 1525 * @{ 1526 */ 1527 #define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ 1528 /** 1529 * 1530 * @} 1531 */ 1532 #endif /* STM32F2 */ 1533 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose 1534 * @{ 1535 */ 1536 #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef 1537 #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef 1538 #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish 1539 #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish 1540 #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish 1541 #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish 1542 1543 /*HASH Algorithm Selection*/ 1544 1545 #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 1546 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 1547 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 1548 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 1549 1550 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH 1551 #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC 1552 1553 #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY 1554 #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY 1555 1556 #if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) 1557 1558 #define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt 1559 #define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End 1560 #define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT 1561 #define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT 1562 1563 #define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt 1564 #define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End 1565 #define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT 1566 #define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT 1567 1568 #define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt 1569 #define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End 1570 #define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT 1571 #define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT 1572 1573 #define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt 1574 #define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End 1575 #define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT 1576 #define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT 1577 1578 #endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ 1579 /** 1580 * @} 1581 */ 1582 1583 /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose 1584 * @{ 1585 */ 1586 #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode 1587 #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode 1588 #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode 1589 #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode 1590 #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode 1591 #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode 1592 #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ 1593 )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) 1594 #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect 1595 #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) 1596 #if defined(STM32L0) 1597 #else 1598 #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) 1599 #endif 1600 #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) 1601 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ 1602 )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) 1603 #if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) 1604 #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode 1605 #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode 1606 #define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode 1607 #define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode 1608 #endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ 1609 1610 /** 1611 * @} 1612 */ 1613 1614 /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose 1615 * @{ 1616 */ 1617 #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram 1618 #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown 1619 #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown 1620 #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock 1621 #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock 1622 #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase 1623 #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program 1624 1625 /** 1626 * @} 1627 */ 1628 1629 /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose 1630 * @{ 1631 */ 1632 #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter 1633 #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter 1634 #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter 1635 #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter 1636 1637 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\ 1638 )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) 1639 1640 #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) 1641 #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT 1642 #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT 1643 #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT 1644 #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT 1645 #endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ 1646 #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) 1647 #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA 1648 #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA 1649 #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA 1650 #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA 1651 #endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ 1652 1653 #if defined(STM32F4) 1654 #define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT 1655 #define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT 1656 #define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT 1657 #define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT 1658 #define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA 1659 #define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA 1660 #define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA 1661 #define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA 1662 #endif /* STM32F4 */ 1663 /** 1664 * @} 1665 */ 1666 1667 /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose 1668 * @{ 1669 */ 1670 1671 #if defined(STM32G0) 1672 #define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD 1673 #define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD 1674 #define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD 1675 #define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler 1676 #endif 1677 #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD 1678 #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg 1679 #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown 1680 #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor 1681 #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg 1682 #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown 1683 #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor 1684 #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler 1685 #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD 1686 #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler 1687 #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback 1688 #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive 1689 #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive 1690 #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC 1691 #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC 1692 #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM 1693 1694 #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL 1695 #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING 1696 #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING 1697 #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING 1698 #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING 1699 #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING 1700 #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING 1701 1702 #define CR_OFFSET_BB PWR_CR_OFFSET_BB 1703 #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB 1704 #define PMODE_BIT_NUMBER VOS_BIT_NUMBER 1705 #define CR_PMODE_BB CR_VOS_BB 1706 1707 #define DBP_BitNumber DBP_BIT_NUMBER 1708 #define PVDE_BitNumber PVDE_BIT_NUMBER 1709 #define PMODE_BitNumber PMODE_BIT_NUMBER 1710 #define EWUP_BitNumber EWUP_BIT_NUMBER 1711 #define FPDS_BitNumber FPDS_BIT_NUMBER 1712 #define ODEN_BitNumber ODEN_BIT_NUMBER 1713 #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER 1714 #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER 1715 #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER 1716 #define BRE_BitNumber BRE_BIT_NUMBER 1717 1718 #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL 1719 1720 #if defined (STM32U5) 1721 #define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP 1722 #define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP 1723 #define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP 1724 #define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP 1725 #define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP 1726 #define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP 1727 #define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP 1728 #define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP 1729 #define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP 1730 #define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP 1731 #define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP 1732 #define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP 1733 #define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP 1734 1735 #define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP 1736 #define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP 1737 #define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP 1738 1739 #define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP 1740 #define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP 1741 #define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP 1742 #define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP 1743 #define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP 1744 #define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP 1745 #define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP 1746 #define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP 1747 #define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP 1748 #define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP 1749 #define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP 1750 #define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP 1751 #define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP 1752 #define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP 1753 1754 #define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP 1755 1756 #define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP 1757 #define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP 1758 #define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP 1759 #define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP 1760 #define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP 1761 #define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP 1762 #define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP 1763 #define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP 1764 #define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP 1765 #define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP 1766 #define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP 1767 #define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP 1768 #define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP 1769 #define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP 1770 1771 #define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP 1772 #define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP 1773 #define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP 1774 #define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP 1775 #define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP 1776 #define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP 1777 #define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP 1778 #define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP 1779 1780 #define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY 1781 #define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY 1782 #define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY 1783 1784 #define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN 1785 #define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN 1786 #define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN 1787 #define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN 1788 #define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN 1789 1790 #define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK 1791 #endif 1792 1793 /** 1794 * @} 1795 */ 1796 1797 /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose 1798 * @{ 1799 */ 1800 #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT 1801 #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback 1802 #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback 1803 /** 1804 * @} 1805 */ 1806 1807 /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose 1808 * @{ 1809 */ 1810 #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo 1811 /** 1812 * @} 1813 */ 1814 1815 /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose 1816 * @{ 1817 */ 1818 #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt 1819 #define HAL_TIM_DMAError TIM_DMAError 1820 #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt 1821 #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt 1822 #if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) 1823 #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro 1824 #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT 1825 #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback 1826 #define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent 1827 #define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT 1828 #define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA 1829 #endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ 1830 /** 1831 * @} 1832 */ 1833 1834 /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose 1835 * @{ 1836 */ 1837 #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback 1838 /** 1839 * @} 1840 */ 1841 1842 /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose 1843 * @{ 1844 */ 1845 #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback 1846 #define HAL_LTDC_Relaod HAL_LTDC_Reload 1847 #define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig 1848 #define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig 1849 /** 1850 * @} 1851 */ 1852 1853 1854 /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose 1855 * @{ 1856 */ 1857 1858 /** 1859 * @} 1860 */ 1861 1862 /* Exported macros ------------------------------------------------------------*/ 1863 1864 /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose 1865 * @{ 1866 */ 1867 #define AES_IT_CC CRYP_IT_CC 1868 #define AES_IT_ERR CRYP_IT_ERR 1869 #define AES_FLAG_CCF CRYP_FLAG_CCF 1870 /** 1871 * @} 1872 */ 1873 1874 /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose 1875 * @{ 1876 */ 1877 #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE 1878 #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH 1879 #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH 1880 #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM 1881 #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC 1882 #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM 1883 #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC 1884 #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI 1885 #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK 1886 #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG 1887 #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG 1888 #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE 1889 #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE 1890 #define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE 1891 1892 #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY 1893 #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 1894 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS 1895 #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER 1896 #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER 1897 1898 /** 1899 * @} 1900 */ 1901 1902 1903 /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose 1904 * @{ 1905 */ 1906 #define __ADC_ENABLE __HAL_ADC_ENABLE 1907 #define __ADC_DISABLE __HAL_ADC_DISABLE 1908 #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS 1909 #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS 1910 #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE 1911 #define __ADC_IS_ENABLED ADC_IS_ENABLE 1912 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR 1913 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED 1914 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED 1915 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR 1916 #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED 1917 #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING 1918 #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE 1919 1920 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION 1921 #define __HAL_ADC_JSQR_RK ADC_JSQR_RK 1922 #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT 1923 #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR 1924 #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION 1925 #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE 1926 #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS 1927 #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS 1928 #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM 1929 #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT 1930 #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS 1931 #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN 1932 #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ 1933 #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET 1934 #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET 1935 #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL 1936 #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL 1937 #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET 1938 #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET 1939 #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD 1940 1941 #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION 1942 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION 1943 #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION 1944 #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER 1945 #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI 1946 #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE 1947 #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE 1948 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER 1949 #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER 1950 #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE 1951 1952 #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT 1953 #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT 1954 #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL 1955 #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM 1956 #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET 1957 #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE 1958 #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE 1959 #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER 1960 1961 #define __HAL_ADC_SQR1 ADC_SQR1 1962 #define __HAL_ADC_SMPR1 ADC_SMPR1 1963 #define __HAL_ADC_SMPR2 ADC_SMPR2 1964 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK 1965 #define __HAL_ADC_SQR2_RK ADC_SQR2_RK 1966 #define __HAL_ADC_SQR1_RK ADC_SQR1_RK 1967 #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS 1968 #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS 1969 #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV 1970 #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection 1971 #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq 1972 #define __HAL_ADC_JSQR ADC_JSQR 1973 1974 #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL 1975 #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS 1976 #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF 1977 #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT 1978 #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS 1979 #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN 1980 #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR 1981 #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ 1982 1983 /** 1984 * @} 1985 */ 1986 1987 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose 1988 * @{ 1989 */ 1990 #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT 1991 #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT 1992 #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT 1993 #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE 1994 1995 /** 1996 * @} 1997 */ 1998 1999 /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose 2000 * @{ 2001 */ 2002 #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 2003 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 2004 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 2005 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 2006 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 2007 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 2008 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 2009 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 2010 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 2011 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 2012 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 2013 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 2014 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 2015 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 2016 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 2017 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 2018 2019 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 2020 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 2021 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 2022 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 2023 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 2024 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 2025 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 2026 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 2027 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 2028 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 2029 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 2030 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 2031 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 2032 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 2033 2034 2035 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 2036 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 2037 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 2038 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 2039 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 2040 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 2041 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC 2042 #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC 2043 #if defined(STM32H7) 2044 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 2045 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 2046 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 2047 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 2048 #else 2049 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG 2050 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG 2051 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG 2052 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG 2053 #endif /* STM32H7 */ 2054 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT 2055 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT 2056 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT 2057 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT 2058 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT 2059 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT 2060 #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 2061 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 2062 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 2063 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 2064 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 2065 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 2066 2067 /** 2068 * @} 2069 */ 2070 2071 /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose 2072 * @{ 2073 */ 2074 #if defined(STM32F3) 2075 #define COMP_START __HAL_COMP_ENABLE 2076 #define COMP_STOP __HAL_COMP_DISABLE 2077 #define COMP_LOCK __HAL_COMP_LOCK 2078 2079 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 2080 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 2081 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 2082 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) 2083 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 2084 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 2085 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) 2086 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 2087 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 2088 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) 2089 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 2090 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 2091 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) 2092 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 2093 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 2094 __HAL_COMP_COMP6_EXTI_ENABLE_IT()) 2095 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 2096 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 2097 __HAL_COMP_COMP6_EXTI_DISABLE_IT()) 2098 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 2099 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 2100 __HAL_COMP_COMP6_EXTI_GET_FLAG()) 2101 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 2102 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 2103 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) 2104 # endif 2105 # if defined(STM32F302xE) || defined(STM32F302xC) 2106 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2107 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 2108 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 2109 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) 2110 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2111 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 2112 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 2113 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) 2114 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2115 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 2116 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 2117 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) 2118 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2119 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 2120 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 2121 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) 2122 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2123 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 2124 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 2125 __HAL_COMP_COMP6_EXTI_ENABLE_IT()) 2126 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2127 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 2128 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 2129 __HAL_COMP_COMP6_EXTI_DISABLE_IT()) 2130 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2131 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 2132 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 2133 __HAL_COMP_COMP6_EXTI_GET_FLAG()) 2134 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2135 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 2136 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 2137 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) 2138 # endif 2139 # if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) 2140 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2141 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 2142 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ 2143 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 2144 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ 2145 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ 2146 __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) 2147 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2148 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 2149 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ 2150 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 2151 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ 2152 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ 2153 __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) 2154 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2155 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 2156 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ 2157 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 2158 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ 2159 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ 2160 __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) 2161 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2162 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 2163 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ 2164 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 2165 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ 2166 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ 2167 __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) 2168 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2169 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 2170 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ 2171 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 2172 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ 2173 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ 2174 __HAL_COMP_COMP7_EXTI_ENABLE_IT()) 2175 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2176 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 2177 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ 2178 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 2179 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ 2180 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ 2181 __HAL_COMP_COMP7_EXTI_DISABLE_IT()) 2182 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2183 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 2184 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ 2185 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 2186 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ 2187 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ 2188 __HAL_COMP_COMP7_EXTI_GET_FLAG()) 2189 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2190 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 2191 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ 2192 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 2193 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ 2194 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ 2195 __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) 2196 # endif 2197 # if defined(STM32F373xC) ||defined(STM32F378xx) 2198 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2199 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) 2200 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2201 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) 2202 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2203 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) 2204 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2205 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) 2206 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2207 __HAL_COMP_COMP2_EXTI_ENABLE_IT()) 2208 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2209 __HAL_COMP_COMP2_EXTI_DISABLE_IT()) 2210 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2211 __HAL_COMP_COMP2_EXTI_GET_FLAG()) 2212 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2213 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) 2214 # endif 2215 #else 2216 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2217 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) 2218 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2219 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) 2220 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2221 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) 2222 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2223 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) 2224 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2225 __HAL_COMP_COMP2_EXTI_ENABLE_IT()) 2226 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2227 __HAL_COMP_COMP2_EXTI_DISABLE_IT()) 2228 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2229 __HAL_COMP_COMP2_EXTI_GET_FLAG()) 2230 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2231 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) 2232 #endif 2233 2234 #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE 2235 2236 #if defined(STM32L0) || defined(STM32L4) 2237 /* Note: On these STM32 families, the only argument of this macro */ 2238 /* is COMP_FLAG_LOCK. */ 2239 /* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ 2240 /* argument. */ 2241 #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) 2242 #endif 2243 /** 2244 * @} 2245 */ 2246 2247 #if defined(STM32L0) || defined(STM32L4) 2248 /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose 2249 * @{ 2250 */ 2251 #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ 2252 #define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ 2253 /** 2254 * @} 2255 */ 2256 #endif 2257 2258 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose 2259 * @{ 2260 */ 2261 2262 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ 2263 ((WAVE) == DAC_WAVE_NOISE)|| \ 2264 ((WAVE) == DAC_WAVE_TRIANGLE)) 2265 2266 /** 2267 * @} 2268 */ 2269 2270 /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose 2271 * @{ 2272 */ 2273 2274 #define IS_WRPAREA IS_OB_WRPAREA 2275 #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM 2276 #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM 2277 #define IS_TYPEERASE IS_FLASH_TYPEERASE 2278 #define IS_NBSECTORS IS_FLASH_NBSECTORS 2279 #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE 2280 2281 /** 2282 * @} 2283 */ 2284 2285 /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose 2286 * @{ 2287 */ 2288 2289 #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 2290 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START 2291 #if defined(STM32F1) 2292 #define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE 2293 #else 2294 #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE 2295 #endif /* STM32F1 */ 2296 #define __HAL_I2C_RISE_TIME I2C_RISE_TIME 2297 #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD 2298 #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST 2299 #define __HAL_I2C_SPEED I2C_SPEED 2300 #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE 2301 #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ 2302 #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS 2303 #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE 2304 #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ 2305 #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB 2306 #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB 2307 #define __HAL_I2C_FREQRANGE I2C_FREQRANGE 2308 /** 2309 * @} 2310 */ 2311 2312 /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose 2313 * @{ 2314 */ 2315 2316 #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE 2317 #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT 2318 2319 #if defined(STM32H7) 2320 #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG 2321 #endif 2322 2323 /** 2324 * @} 2325 */ 2326 2327 /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose 2328 * @{ 2329 */ 2330 2331 #define __IRDA_DISABLE __HAL_IRDA_DISABLE 2332 #define __IRDA_ENABLE __HAL_IRDA_ENABLE 2333 2334 #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE 2335 #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION 2336 #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE 2337 #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION 2338 2339 #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE 2340 2341 2342 /** 2343 * @} 2344 */ 2345 2346 2347 /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose 2348 * @{ 2349 */ 2350 #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS 2351 #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS 2352 /** 2353 * @} 2354 */ 2355 2356 2357 /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose 2358 * @{ 2359 */ 2360 2361 #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT 2362 #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT 2363 #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE 2364 2365 /** 2366 * @} 2367 */ 2368 2369 2370 /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose 2371 * @{ 2372 */ 2373 #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD 2374 #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX 2375 #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX 2376 #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX 2377 #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX 2378 #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L 2379 #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H 2380 #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM 2381 #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES 2382 #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX 2383 #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT 2384 #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION 2385 #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET 2386 2387 /** 2388 * @} 2389 */ 2390 2391 2392 /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose 2393 * @{ 2394 */ 2395 #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT 2396 #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT 2397 #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE 2398 #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2399 #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE 2400 #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2401 #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE 2402 #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE 2403 #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE 2404 #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE 2405 #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE 2406 #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE 2407 #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine 2408 #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine 2409 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig 2410 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig 2411 #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) 2412 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT 2413 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT 2414 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE 2415 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2416 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE 2417 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2418 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2419 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2420 #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) 2421 #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) 2422 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention 2423 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention 2424 #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 2425 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 2426 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE 2427 #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE 2428 #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB 2429 #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB 2430 2431 #if defined (STM32F4) 2432 #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() 2433 #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() 2434 #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() 2435 #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() 2436 #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() 2437 #else 2438 #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG 2439 #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT 2440 #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT 2441 #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT 2442 #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG 2443 #endif /* STM32F4 */ 2444 /** 2445 * @} 2446 */ 2447 2448 2449 /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose 2450 * @{ 2451 */ 2452 2453 #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI 2454 #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI 2455 2456 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback 2457 #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\ 2458 )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) 2459 2460 #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE 2461 #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE 2462 #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE 2463 #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE 2464 #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET 2465 #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET 2466 #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE 2467 #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE 2468 #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET 2469 #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET 2470 #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE 2471 #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE 2472 #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE 2473 #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE 2474 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET 2475 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET 2476 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE 2477 #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE 2478 #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET 2479 #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET 2480 #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE 2481 #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE 2482 #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE 2483 #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE 2484 #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET 2485 #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET 2486 #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE 2487 #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE 2488 #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE 2489 #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE 2490 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET 2491 #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET 2492 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE 2493 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE 2494 #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET 2495 #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET 2496 #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET 2497 #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET 2498 #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET 2499 #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET 2500 #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET 2501 #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET 2502 #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET 2503 #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET 2504 #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET 2505 #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET 2506 #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET 2507 #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET 2508 #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE 2509 #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE 2510 #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET 2511 #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET 2512 #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE 2513 #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE 2514 #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE 2515 #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE 2516 #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET 2517 #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET 2518 #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE 2519 #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE 2520 #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET 2521 #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET 2522 #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE 2523 #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE 2524 #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET 2525 #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET 2526 #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE 2527 #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE 2528 #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE 2529 #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE 2530 #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET 2531 #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET 2532 #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE 2533 #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE 2534 #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET 2535 #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET 2536 #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE 2537 #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE 2538 #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE 2539 #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE 2540 #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET 2541 #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET 2542 #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE 2543 #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE 2544 #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET 2545 #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET 2546 #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE 2547 #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE 2548 #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE 2549 #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE 2550 #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET 2551 #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET 2552 #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE 2553 #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE 2554 #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET 2555 #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET 2556 #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE 2557 #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE 2558 #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE 2559 #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE 2560 #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET 2561 #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET 2562 #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE 2563 #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE 2564 #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE 2565 #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE 2566 #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET 2567 #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET 2568 #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE 2569 #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE 2570 #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE 2571 #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE 2572 #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET 2573 #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET 2574 #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE 2575 #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE 2576 #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET 2577 #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET 2578 #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE 2579 #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE 2580 #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE 2581 #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE 2582 #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE 2583 #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE 2584 #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE 2585 #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE 2586 #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE 2587 #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE 2588 #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET 2589 #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET 2590 #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE 2591 #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE 2592 #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET 2593 #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET 2594 #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE 2595 #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE 2596 #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE 2597 #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE 2598 #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE 2599 #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE 2600 #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET 2601 #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET 2602 #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE 2603 #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE 2604 #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE 2605 #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE 2606 #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE 2607 #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE 2608 #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET 2609 #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET 2610 #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE 2611 #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE 2612 #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE 2613 #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE 2614 #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET 2615 #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET 2616 #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE 2617 #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE 2618 #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE 2619 #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE 2620 #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET 2621 #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET 2622 #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE 2623 #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE 2624 #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE 2625 #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE 2626 #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET 2627 #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET 2628 #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE 2629 #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE 2630 #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE 2631 #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE 2632 #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET 2633 #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET 2634 #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE 2635 #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE 2636 #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE 2637 #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE 2638 #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET 2639 #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET 2640 #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE 2641 #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE 2642 #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE 2643 #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE 2644 #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET 2645 #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET 2646 #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE 2647 #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE 2648 #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE 2649 #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE 2650 #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET 2651 #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET 2652 #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE 2653 #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE 2654 #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE 2655 #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE 2656 #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET 2657 #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET 2658 #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE 2659 #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE 2660 #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE 2661 #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE 2662 #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET 2663 #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET 2664 #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE 2665 #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE 2666 #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE 2667 #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE 2668 #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET 2669 #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET 2670 #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE 2671 #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE 2672 #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE 2673 #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE 2674 #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET 2675 #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET 2676 #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE 2677 #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE 2678 #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE 2679 #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE 2680 #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET 2681 #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET 2682 #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE 2683 #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE 2684 #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE 2685 #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE 2686 #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET 2687 #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET 2688 #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE 2689 #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE 2690 #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE 2691 #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE 2692 #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET 2693 #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET 2694 #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE 2695 #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE 2696 #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE 2697 #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE 2698 #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET 2699 #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET 2700 #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE 2701 #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE 2702 #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE 2703 #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE 2704 #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET 2705 #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET 2706 #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE 2707 #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE 2708 #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE 2709 #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE 2710 #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET 2711 #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET 2712 #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE 2713 #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE 2714 #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE 2715 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE 2716 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET 2717 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET 2718 2719 #if defined(STM32WB) 2720 #define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE 2721 #define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE 2722 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE 2723 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE 2724 #define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET 2725 #define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET 2726 #define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED 2727 #define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED 2728 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED 2729 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED 2730 #define QSPI_IRQHandler QUADSPI_IRQHandler 2731 #endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ 2732 2733 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE 2734 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE 2735 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE 2736 #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE 2737 #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET 2738 #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET 2739 #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE 2740 #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE 2741 #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE 2742 #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE 2743 #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET 2744 #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET 2745 #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE 2746 #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE 2747 #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE 2748 #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE 2749 #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET 2750 #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET 2751 #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE 2752 #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE 2753 #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE 2754 #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE 2755 #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE 2756 #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE 2757 #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET 2758 #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET 2759 #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE 2760 #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE 2761 #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE 2762 #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE 2763 #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET 2764 #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET 2765 #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE 2766 #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE 2767 #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE 2768 #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE 2769 #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET 2770 #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET 2771 #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE 2772 #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE 2773 #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE 2774 #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE 2775 #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET 2776 #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET 2777 #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE 2778 #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE 2779 #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE 2780 #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE 2781 #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE 2782 #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE 2783 #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE 2784 #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE 2785 #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE 2786 #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE 2787 #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET 2788 #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET 2789 #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE 2790 #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE 2791 #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE 2792 #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE 2793 #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET 2794 #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET 2795 #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE 2796 #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE 2797 #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE 2798 #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE 2799 #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET 2800 #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET 2801 #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE 2802 #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE 2803 #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET 2804 #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET 2805 #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE 2806 #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE 2807 #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET 2808 #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET 2809 #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE 2810 #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE 2811 #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET 2812 #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET 2813 #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE 2814 #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE 2815 #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET 2816 #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET 2817 #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE 2818 #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE 2819 #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET 2820 #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET 2821 #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE 2822 #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE 2823 #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE 2824 #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE 2825 #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET 2826 #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET 2827 #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE 2828 #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE 2829 #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE 2830 #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE 2831 #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET 2832 #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET 2833 #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE 2834 #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE 2835 #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE 2836 #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE 2837 #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET 2838 #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET 2839 #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE 2840 #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE 2841 #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE 2842 #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE 2843 #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET 2844 #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET 2845 #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE 2846 #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE 2847 #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE 2848 #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE 2849 #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET 2850 #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET 2851 #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE 2852 #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE 2853 #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE 2854 #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE 2855 #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET 2856 #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET 2857 #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE 2858 #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE 2859 #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE 2860 #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE 2861 #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET 2862 #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET 2863 #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE 2864 #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE 2865 #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE 2866 #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE 2867 #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET 2868 #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET 2869 #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE 2870 #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE 2871 #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE 2872 #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE 2873 #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET 2874 #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET 2875 #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE 2876 #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE 2877 #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE 2878 #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE 2879 #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET 2880 #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET 2881 #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE 2882 #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE 2883 #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET 2884 #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET 2885 #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE 2886 #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE 2887 #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE 2888 #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE 2889 #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET 2890 #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET 2891 #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE 2892 #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE 2893 #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE 2894 #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE 2895 #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET 2896 #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET 2897 #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE 2898 #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE 2899 #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE 2900 #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE 2901 #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET 2902 #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET 2903 #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE 2904 #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE 2905 #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE 2906 #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE 2907 #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET 2908 #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET 2909 #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE 2910 #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE 2911 #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE 2912 #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE 2913 #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET 2914 #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET 2915 #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE 2916 #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE 2917 #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE 2918 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE 2919 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET 2920 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET 2921 #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE 2922 #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE 2923 #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE 2924 #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE 2925 #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET 2926 #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET 2927 #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE 2928 #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE 2929 #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE 2930 #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE 2931 #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET 2932 #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET 2933 #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE 2934 #define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE 2935 #define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET 2936 #define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET 2937 #define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE 2938 #define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE 2939 #define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET 2940 #define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET 2941 #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE 2942 #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE 2943 #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET 2944 #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE 2945 #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE 2946 #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE 2947 #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE 2948 #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET 2949 2950 #if defined(STM32H7) 2951 #define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE 2952 #define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE 2953 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE 2954 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE 2955 2956 #define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ 2957 #define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ 2958 2959 2960 #define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED 2961 #define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED 2962 #endif 2963 2964 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE 2965 #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE 2966 #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE 2967 #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE 2968 #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET 2969 #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET 2970 2971 #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE 2972 #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE 2973 #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET 2974 #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET 2975 #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE 2976 #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE 2977 #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE 2978 #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE 2979 #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET 2980 #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET 2981 #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE 2982 #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE 2983 #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE 2984 #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE 2985 #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE 2986 #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE 2987 #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET 2988 #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET 2989 #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE 2990 #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE 2991 2992 #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET 2993 #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET 2994 #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE 2995 #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE 2996 #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE 2997 #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE 2998 #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE 2999 #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE 3000 #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE 3001 #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE 3002 #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE 3003 #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE 3004 #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE 3005 #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE 3006 #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE 3007 #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE 3008 #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE 3009 #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE 3010 #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE 3011 #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET 3012 #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET 3013 #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE 3014 #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE 3015 #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE 3016 #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE 3017 #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE 3018 #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET 3019 #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET 3020 #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE 3021 #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE 3022 #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE 3023 #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE 3024 #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET 3025 #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET 3026 #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE 3027 #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE 3028 #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE 3029 #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE 3030 #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET 3031 #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET 3032 #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE 3033 #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE 3034 #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE 3035 #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE 3036 #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE 3037 #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE 3038 #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE 3039 #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE 3040 #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE 3041 #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE 3042 #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE 3043 #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE 3044 #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE 3045 #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE 3046 #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE 3047 #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE 3048 #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE 3049 #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE 3050 #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE 3051 #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE 3052 #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE 3053 #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET 3054 #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET 3055 #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE 3056 #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE 3057 #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE 3058 #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE 3059 #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET 3060 #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET 3061 #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE 3062 #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE 3063 #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE 3064 #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE 3065 #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET 3066 #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET 3067 #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE 3068 #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE 3069 #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE 3070 #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE 3071 #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET 3072 #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET 3073 #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE 3074 #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE 3075 #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE 3076 #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE 3077 #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET 3078 #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE 3079 #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE 3080 #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE 3081 #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE 3082 #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE 3083 #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE 3084 #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET 3085 #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET 3086 #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE 3087 #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE 3088 #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE 3089 #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE 3090 #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET 3091 #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET 3092 #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE 3093 #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE 3094 #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE 3095 #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE 3096 #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET 3097 #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET 3098 #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE 3099 #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE 3100 #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE 3101 #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE 3102 #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET 3103 #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET 3104 #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE 3105 #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 3106 #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE 3107 #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE 3108 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED 3109 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED 3110 #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET 3111 #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET 3112 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE 3113 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 3114 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED 3115 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED 3116 #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE 3117 #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE 3118 #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE 3119 #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE 3120 #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE 3121 #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE 3122 #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE 3123 #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE 3124 #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE 3125 #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET 3126 #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET 3127 #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE 3128 #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE 3129 #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET 3130 #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET 3131 #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE 3132 #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE 3133 #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE 3134 #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE 3135 #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET 3136 #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET 3137 #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE 3138 #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE 3139 3140 /* alias define maintained for legacy */ 3141 #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET 3142 #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET 3143 3144 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE 3145 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE 3146 #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE 3147 #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE 3148 #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE 3149 #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE 3150 #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE 3151 #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE 3152 #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE 3153 #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE 3154 #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE 3155 #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE 3156 #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE 3157 #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE 3158 #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE 3159 #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE 3160 #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE 3161 #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE 3162 #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE 3163 #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE 3164 3165 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET 3166 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET 3167 #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET 3168 #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET 3169 #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET 3170 #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET 3171 #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET 3172 #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET 3173 #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET 3174 #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET 3175 #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET 3176 #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET 3177 #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET 3178 #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET 3179 #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET 3180 #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET 3181 #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET 3182 #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET 3183 #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET 3184 #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET 3185 3186 #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED 3187 #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED 3188 #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED 3189 #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED 3190 #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED 3191 #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED 3192 #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED 3193 #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED 3194 #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED 3195 #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED 3196 #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED 3197 #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED 3198 #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED 3199 #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED 3200 #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED 3201 #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED 3202 #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED 3203 #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED 3204 #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED 3205 #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED 3206 #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED 3207 #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED 3208 #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED 3209 #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED 3210 #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED 3211 #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED 3212 #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED 3213 #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED 3214 #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED 3215 #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED 3216 #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED 3217 #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED 3218 #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED 3219 #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED 3220 #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED 3221 #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED 3222 #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED 3223 #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED 3224 #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED 3225 #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED 3226 #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED 3227 #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED 3228 #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED 3229 #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED 3230 #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED 3231 #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED 3232 #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED 3233 #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED 3234 #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED 3235 #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED 3236 #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED 3237 #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED 3238 #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED 3239 #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED 3240 #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED 3241 #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED 3242 #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED 3243 #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED 3244 #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED 3245 #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED 3246 #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED 3247 #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED 3248 #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED 3249 #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED 3250 #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED 3251 #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED 3252 #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED 3253 #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED 3254 #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED 3255 #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED 3256 #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED 3257 #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED 3258 #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED 3259 #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED 3260 #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED 3261 #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED 3262 #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED 3263 #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED 3264 #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED 3265 #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED 3266 #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED 3267 #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED 3268 #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED 3269 #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED 3270 #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED 3271 #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED 3272 #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED 3273 #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED 3274 #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED 3275 #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED 3276 #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED 3277 #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED 3278 #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED 3279 #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED 3280 #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED 3281 #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED 3282 #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED 3283 #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED 3284 #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED 3285 #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED 3286 #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED 3287 #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED 3288 #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED 3289 #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED 3290 #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED 3291 #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED 3292 #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED 3293 #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED 3294 #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED 3295 #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED 3296 #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED 3297 #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED 3298 #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED 3299 #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED 3300 #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED 3301 #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED 3302 3303 #if defined(STM32L1) 3304 #define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE 3305 #define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE 3306 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE 3307 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE 3308 #define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET 3309 #define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET 3310 #endif /* STM32L1 */ 3311 3312 #if defined(STM32F4) 3313 #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET 3314 #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET 3315 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE 3316 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE 3317 #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE 3318 #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE 3319 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED 3320 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED 3321 #define Sdmmc1ClockSelection SdioClockSelection 3322 #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO 3323 #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 3324 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK 3325 #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG 3326 #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE 3327 #endif 3328 3329 #if defined(STM32F7) || defined(STM32L4) 3330 #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET 3331 #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET 3332 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE 3333 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE 3334 #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE 3335 #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE 3336 #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED 3337 #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED 3338 #define SdioClockSelection Sdmmc1ClockSelection 3339 #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 3340 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG 3341 #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE 3342 #endif 3343 3344 #if defined(STM32F7) 3345 #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 3346 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK 3347 #endif 3348 3349 #if defined(STM32H7) 3350 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() 3351 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() 3352 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() 3353 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() 3354 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() 3355 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() 3356 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() 3357 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() 3358 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() 3359 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() 3360 3361 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() 3362 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() 3363 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() 3364 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() 3365 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() 3366 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() 3367 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() 3368 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() 3369 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() 3370 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() 3371 #endif 3372 3373 #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG 3374 #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG 3375 3376 #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE 3377 3378 #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE 3379 #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE 3380 #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK 3381 #define IS_RCC_HCLK_DIV IS_RCC_PCLK 3382 #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK 3383 3384 #define RCC_IT_HSI14 RCC_IT_HSI14RDY 3385 3386 #define RCC_IT_CSSLSE RCC_IT_LSECSS 3387 #define RCC_IT_CSSHSE RCC_IT_CSS 3388 3389 #define RCC_PLLMUL_3 RCC_PLL_MUL3 3390 #define RCC_PLLMUL_4 RCC_PLL_MUL4 3391 #define RCC_PLLMUL_6 RCC_PLL_MUL6 3392 #define RCC_PLLMUL_8 RCC_PLL_MUL8 3393 #define RCC_PLLMUL_12 RCC_PLL_MUL12 3394 #define RCC_PLLMUL_16 RCC_PLL_MUL16 3395 #define RCC_PLLMUL_24 RCC_PLL_MUL24 3396 #define RCC_PLLMUL_32 RCC_PLL_MUL32 3397 #define RCC_PLLMUL_48 RCC_PLL_MUL48 3398 3399 #define RCC_PLLDIV_2 RCC_PLL_DIV2 3400 #define RCC_PLLDIV_3 RCC_PLL_DIV3 3401 #define RCC_PLLDIV_4 RCC_PLL_DIV4 3402 3403 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE 3404 #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG 3405 #define RCC_MCO_NODIV RCC_MCODIV_1 3406 #define RCC_MCO_DIV1 RCC_MCODIV_1 3407 #define RCC_MCO_DIV2 RCC_MCODIV_2 3408 #define RCC_MCO_DIV4 RCC_MCODIV_4 3409 #define RCC_MCO_DIV8 RCC_MCODIV_8 3410 #define RCC_MCO_DIV16 RCC_MCODIV_16 3411 #define RCC_MCO_DIV32 RCC_MCODIV_32 3412 #define RCC_MCO_DIV64 RCC_MCODIV_64 3413 #define RCC_MCO_DIV128 RCC_MCODIV_128 3414 #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK 3415 #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI 3416 #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE 3417 #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK 3418 #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI 3419 #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 3420 #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 3421 #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE 3422 #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK 3423 #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK 3424 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 3425 3426 #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0) 3427 #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE 3428 #else 3429 #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK 3430 #endif 3431 3432 #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 3433 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL 3434 #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI 3435 #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL 3436 #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL 3437 #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 3438 #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 3439 #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 3440 3441 #define HSION_BitNumber RCC_HSION_BIT_NUMBER 3442 #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER 3443 #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER 3444 #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER 3445 #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER 3446 #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER 3447 #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER 3448 #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER 3449 #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER 3450 #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER 3451 #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER 3452 #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER 3453 #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER 3454 #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER 3455 #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER 3456 #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER 3457 #define LSION_BitNumber RCC_LSION_BIT_NUMBER 3458 #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER 3459 #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER 3460 #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER 3461 #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER 3462 #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER 3463 #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER 3464 #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER 3465 #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER 3466 #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER 3467 #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS 3468 #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS 3469 #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS 3470 #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS 3471 #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE 3472 #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE 3473 3474 #define CR_HSION_BB RCC_CR_HSION_BB 3475 #define CR_CSSON_BB RCC_CR_CSSON_BB 3476 #define CR_PLLON_BB RCC_CR_PLLON_BB 3477 #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB 3478 #define CR_MSION_BB RCC_CR_MSION_BB 3479 #define CSR_LSION_BB RCC_CSR_LSION_BB 3480 #define CSR_LSEON_BB RCC_CSR_LSEON_BB 3481 #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB 3482 #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB 3483 #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB 3484 #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB 3485 #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB 3486 #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB 3487 #define CR_HSEON_BB RCC_CR_HSEON_BB 3488 #define CSR_RMVF_BB RCC_CSR_RMVF_BB 3489 #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB 3490 #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB 3491 3492 #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE 3493 #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE 3494 #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE 3495 #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE 3496 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE 3497 3498 #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT 3499 3500 #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN 3501 #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF 3502 3503 #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 3504 #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ 3505 #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP 3506 #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ 3507 #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE 3508 #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 3509 3510 #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE 3511 #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE 3512 #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED 3513 #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED 3514 #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET 3515 #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET 3516 #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE 3517 #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE 3518 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED 3519 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED 3520 #define DfsdmClockSelection Dfsdm1ClockSelection 3521 #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 3522 #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 3523 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK 3524 #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG 3525 #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE 3526 #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 3527 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 3528 #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 3529 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 3530 3531 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 3532 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 3533 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 3534 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 3535 #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 3536 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 3537 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 3538 #if defined(STM32U5) 3539 #define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL 3540 #define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL 3541 #define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE 3542 #define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE 3543 #define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE 3544 #define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE 3545 #define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE 3546 #define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE 3547 #define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE 3548 #define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE 3549 #define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE 3550 #define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT 3551 #define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK 3552 #define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 3553 #define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 3554 #define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 3555 #define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK 3556 #define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE 3557 #define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE 3558 #define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED 3559 #define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED 3560 #define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET 3561 #define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET 3562 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE 3563 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE 3564 #define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE 3565 #define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE 3566 #define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE 3567 #define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG 3568 #define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE 3569 #endif /* STM32U5 */ 3570 3571 /** 3572 * @} 3573 */ 3574 3575 /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose 3576 * @{ 3577 */ 3578 #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) 3579 3580 /** 3581 * @} 3582 */ 3583 3584 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose 3585 * @{ 3586 */ 3587 #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \ 3588 defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ 3589 defined (STM32C0) 3590 #else 3591 #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG 3592 #endif 3593 #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT 3594 #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT 3595 3596 #if defined (STM32F1) 3597 #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() 3598 3599 #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() 3600 3601 #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() 3602 3603 #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() 3604 3605 #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() 3606 #else 3607 #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ 3608 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ 3609 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) 3610 #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ 3611 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ 3612 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) 3613 #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ 3614 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ 3615 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) 3616 #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ 3617 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ 3618 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) 3619 #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ 3620 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ 3621 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) 3622 #endif /* STM32F1 */ 3623 3624 #define IS_ALARM IS_RTC_ALARM 3625 #define IS_ALARM_MASK IS_RTC_ALARM_MASK 3626 #define IS_TAMPER IS_RTC_TAMPER 3627 #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE 3628 #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER 3629 #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT 3630 #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE 3631 #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION 3632 #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE 3633 #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ 3634 #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION 3635 #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER 3636 #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK 3637 #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER 3638 3639 #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE 3640 #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE 3641 3642 /** 3643 * @} 3644 */ 3645 3646 /** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose 3647 * @{ 3648 */ 3649 3650 #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE 3651 #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS 3652 3653 #if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) 3654 #define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE 3655 #define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE 3656 #define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE 3657 3658 #define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV 3659 #define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV 3660 #endif 3661 3662 #if defined(STM32F4) || defined(STM32F2) 3663 #define SD_SDMMC_DISABLED SD_SDIO_DISABLED 3664 #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY 3665 #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED 3666 #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION 3667 #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND 3668 #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT 3669 #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED 3670 #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE 3671 #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE 3672 #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE 3673 #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL 3674 #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT 3675 #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT 3676 #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG 3677 #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG 3678 #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT 3679 #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT 3680 #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS 3681 #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT 3682 #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND 3683 /* alias CMSIS */ 3684 #define SDMMC1_IRQn SDIO_IRQn 3685 #define SDMMC1_IRQHandler SDIO_IRQHandler 3686 #endif 3687 3688 #if defined(STM32F7) || defined(STM32L4) 3689 #define SD_SDIO_DISABLED SD_SDMMC_DISABLED 3690 #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY 3691 #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED 3692 #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION 3693 #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND 3694 #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT 3695 #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED 3696 #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE 3697 #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE 3698 #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE 3699 #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE 3700 #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT 3701 #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT 3702 #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG 3703 #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG 3704 #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT 3705 #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT 3706 #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS 3707 #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT 3708 #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND 3709 /* alias CMSIS for compatibilities */ 3710 #define SDIO_IRQn SDMMC1_IRQn 3711 #define SDIO_IRQHandler SDMMC1_IRQHandler 3712 #endif 3713 3714 #if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) 3715 #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef 3716 #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef 3717 #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef 3718 #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef 3719 #endif 3720 3721 #if defined(STM32H7) || defined(STM32L5) 3722 #define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback 3723 #define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback 3724 #define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback 3725 #define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback 3726 #define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback 3727 #define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback 3728 #define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback 3729 #define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback 3730 #define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback 3731 #endif 3732 /** 3733 * @} 3734 */ 3735 3736 /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose 3737 * @{ 3738 */ 3739 3740 #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT 3741 #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT 3742 #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE 3743 #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE 3744 #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE 3745 #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE 3746 3747 #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE 3748 #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE 3749 3750 #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE 3751 3752 /** 3753 * @} 3754 */ 3755 3756 /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose 3757 * @{ 3758 */ 3759 #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 3760 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 3761 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START 3762 #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH 3763 #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR 3764 #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE 3765 #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE 3766 #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED 3767 /** 3768 * @} 3769 */ 3770 3771 /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose 3772 * @{ 3773 */ 3774 3775 #define __HAL_SPI_1LINE_TX SPI_1LINE_TX 3776 #define __HAL_SPI_1LINE_RX SPI_1LINE_RX 3777 #define __HAL_SPI_RESET_CRC SPI_RESET_CRC 3778 3779 /** 3780 * @} 3781 */ 3782 3783 /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose 3784 * @{ 3785 */ 3786 3787 #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE 3788 #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION 3789 #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE 3790 #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION 3791 3792 #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD 3793 3794 #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE 3795 #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE 3796 3797 /** 3798 * @} 3799 */ 3800 3801 3802 /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose 3803 * @{ 3804 */ 3805 3806 #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT 3807 #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT 3808 #define __USART_ENABLE __HAL_USART_ENABLE 3809 #define __USART_DISABLE __HAL_USART_DISABLE 3810 3811 #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE 3812 #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE 3813 3814 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) 3815 #define USART_OVERSAMPLING_16 0x00000000U 3816 #define USART_OVERSAMPLING_8 USART_CR1_OVER8 3817 3818 #define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ 3819 ((__SAMPLING__) == USART_OVERSAMPLING_8)) 3820 #endif /* STM32F0 || STM32F3 || STM32F7 */ 3821 /** 3822 * @} 3823 */ 3824 3825 /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose 3826 * @{ 3827 */ 3828 #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE 3829 3830 #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 3831 #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 3832 #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 3833 #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE 3834 3835 #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 3836 #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 3837 #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 3838 #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE 3839 3840 #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT 3841 #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT 3842 #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG 3843 #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG 3844 #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE 3845 #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE 3846 #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 3847 3848 #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT 3849 #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT 3850 #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG 3851 #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG 3852 #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE 3853 #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE 3854 #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 3855 #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT 3856 3857 #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT 3858 #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT 3859 #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG 3860 #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG 3861 #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE 3862 #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE 3863 #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 3864 #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT 3865 3866 #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup 3867 #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup 3868 3869 #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo 3870 #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo 3871 /** 3872 * @} 3873 */ 3874 3875 /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose 3876 * @{ 3877 */ 3878 #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE 3879 #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE 3880 3881 #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE 3882 #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT 3883 3884 #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE 3885 3886 #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN 3887 #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER 3888 #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER 3889 #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER 3890 #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD 3891 #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD 3892 #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION 3893 #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION 3894 #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER 3895 #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER 3896 #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE 3897 #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE 3898 3899 #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 3900 /** 3901 * @} 3902 */ 3903 3904 /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose 3905 * @{ 3906 */ 3907 3908 #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT 3909 #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT 3910 #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG 3911 #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG 3912 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER 3913 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER 3914 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER 3915 3916 #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE 3917 #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE 3918 #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE 3919 /** 3920 * @} 3921 */ 3922 3923 /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose 3924 * @{ 3925 */ 3926 #define __HAL_LTDC_LAYER LTDC_LAYER 3927 #define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG 3928 /** 3929 * @} 3930 */ 3931 3932 /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose 3933 * @{ 3934 */ 3935 #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE 3936 #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE 3937 #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE 3938 #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE 3939 #define SAI_STREOMODE SAI_STEREOMODE 3940 #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY 3941 #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL 3942 #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL 3943 #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL 3944 #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL 3945 #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL 3946 #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE 3947 #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 3948 #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE 3949 /** 3950 * @} 3951 */ 3952 3953 /** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose 3954 * @{ 3955 */ 3956 #if defined(STM32H7) 3957 #define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow 3958 #define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT 3959 #define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA 3960 #endif 3961 /** 3962 * @} 3963 */ 3964 3965 /** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose 3966 * @{ 3967 */ 3968 #if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) 3969 #define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT 3970 #define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA 3971 #define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart 3972 #define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT 3973 #define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA 3974 #define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop 3975 #endif 3976 /** 3977 * @} 3978 */ 3979 3980 /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose 3981 * @{ 3982 */ 3983 #if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) 3984 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE 3985 #endif /* STM32L4 || STM32F4 || STM32F7 */ 3986 /** 3987 * @} 3988 */ 3989 3990 /** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose 3991 * @{ 3992 */ 3993 #if defined (STM32F7) 3994 #define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE 3995 #endif /* STM32F7 */ 3996 /** 3997 * @} 3998 */ 3999 4000 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose 4001 * @{ 4002 */ 4003 4004 /** 4005 * @} 4006 */ 4007 4008 #ifdef __cplusplus 4009 } 4010 #endif 4011 4012 #endif /* STM32_HAL_LEGACY */ 4013 4014 4015
